1 /* 2 * linux/include/linux/clk-provider.h 3 * 4 * Copyright (c) 2010-2011 Jeremy Kerr <[email protected]> 5 * Copyright (C) 2011-2012 Linaro Ltd <[email protected]> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #ifndef __LINUX_CLK_PROVIDER_H 12 #define __LINUX_CLK_PROVIDER_H 13 14 #include <linux/clk.h> 15 #include <linux/io.h> 16 #include <linux/of.h> 17 18 #ifdef CONFIG_COMMON_CLK 19 20 /* 21 * flags used across common struct clk. these flags should only affect the 22 * top-level framework. custom flags for dealing with hardware specifics 23 * belong in struct clk_foo 24 */ 25 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ 26 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ 27 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ 28 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ 29 #define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ 30 #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ 31 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ 32 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ 33 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ 34 35 struct clk_hw; 36 struct dentry; 37 38 /** 39 * struct clk_ops - Callback operations for hardware clocks; these are to 40 * be provided by the clock implementation, and will be called by drivers 41 * through the clk_* api. 42 * 43 * @prepare: Prepare the clock for enabling. This must not return until 44 * the clock is fully prepared, and it's safe to call clk_enable. 45 * This callback is intended to allow clock implementations to 46 * do any initialisation that may sleep. Called with 47 * prepare_lock held. 48 * 49 * @unprepare: Release the clock from its prepared state. This will typically 50 * undo any work done in the @prepare callback. Called with 51 * prepare_lock held. 52 * 53 * @is_prepared: Queries the hardware to determine if the clock is prepared. 54 * This function is allowed to sleep. Optional, if this op is not 55 * set then the prepare count will be used. 56 * 57 * @unprepare_unused: Unprepare the clock atomically. Only called from 58 * clk_disable_unused for prepare clocks with special needs. 59 * Called with prepare mutex held. This function may sleep. 60 * 61 * @enable: Enable the clock atomically. This must not return until the 62 * clock is generating a valid clock signal, usable by consumer 63 * devices. Called with enable_lock held. This function must not 64 * sleep. 65 * 66 * @disable: Disable the clock atomically. Called with enable_lock held. 67 * This function must not sleep. 68 * 69 * @is_enabled: Queries the hardware to determine if the clock is enabled. 70 * This function must not sleep. Optional, if this op is not 71 * set then the enable count will be used. 72 * 73 * @disable_unused: Disable the clock atomically. Only called from 74 * clk_disable_unused for gate clocks with special needs. 75 * Called with enable_lock held. This function must not 76 * sleep. 77 * 78 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The 79 * parent rate is an input parameter. It is up to the caller to 80 * ensure that the prepare_mutex is held across this call. 81 * Returns the calculated rate. Optional, but recommended - if 82 * this op is not set then clock rate will be initialized to 0. 83 * 84 * @round_rate: Given a target rate as input, returns the closest rate actually 85 * supported by the clock. The parent rate is an input/output 86 * parameter. 87 * 88 * @determine_rate: Given a target rate as input, returns the closest rate 89 * actually supported by the clock, and optionally the parent clock 90 * that should be used to provide the clock rate. 91 * 92 * @set_parent: Change the input source of this clock; for clocks with multiple 93 * possible parents specify a new parent by passing in the index 94 * as a u8 corresponding to the parent in either the .parent_names 95 * or .parents arrays. This function in affect translates an 96 * array index into the value programmed into the hardware. 97 * Returns 0 on success, -EERROR otherwise. 98 * 99 * @get_parent: Queries the hardware to determine the parent of a clock. The 100 * return value is a u8 which specifies the index corresponding to 101 * the parent clock. This index can be applied to either the 102 * .parent_names or .parents arrays. In short, this function 103 * translates the parent value read from hardware into an array 104 * index. Currently only called when the clock is initialized by 105 * __clk_init. This callback is mandatory for clocks with 106 * multiple parents. It is optional (and unnecessary) for clocks 107 * with 0 or 1 parents. 108 * 109 * @set_rate: Change the rate of this clock. The requested rate is specified 110 * by the second argument, which should typically be the return 111 * of .round_rate call. The third argument gives the parent rate 112 * which is likely helpful for most .set_rate implementation. 113 * Returns 0 on success, -EERROR otherwise. 114 * 115 * @set_rate_and_parent: Change the rate and the parent of this clock. The 116 * requested rate is specified by the second argument, which 117 * should typically be the return of .round_rate call. The 118 * third argument gives the parent rate which is likely helpful 119 * for most .set_rate_and_parent implementation. The fourth 120 * argument gives the parent index. This callback is optional (and 121 * unnecessary) for clocks with 0 or 1 parents as well as 122 * for clocks that can tolerate switching the rate and the parent 123 * separately via calls to .set_parent and .set_rate. 124 * Returns 0 on success, -EERROR otherwise. 125 * 126 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy 127 * is expressed in ppb (parts per billion). The parent accuracy is 128 * an input parameter. 129 * Returns the calculated accuracy. Optional - if this op is not 130 * set then clock accuracy will be initialized to parent accuracy 131 * or 0 (perfect clock) if clock has no parent. 132 * 133 * @get_phase: Queries the hardware to get the current phase of a clock. 134 * Returned values are 0-359 degrees on success, negative 135 * error codes on failure. 136 * 137 * @set_phase: Shift the phase this clock signal in degrees specified 138 * by the second argument. Valid values for degrees are 139 * 0-359. Return 0 on success, otherwise -EERROR. 140 * 141 * @init: Perform platform-specific initialization magic. 142 * This is not not used by any of the basic clock types. 143 * Please consider other ways of solving initialization problems 144 * before using this callback, as its use is discouraged. 145 * 146 * @debug_init: Set up type-specific debugfs entries for this clock. This 147 * is called once, after the debugfs directory entry for this 148 * clock has been created. The dentry pointer representing that 149 * directory is provided as an argument. Called with 150 * prepare_lock held. Returns 0 on success, -EERROR otherwise. 151 * 152 * 153 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow 154 * implementations to split any work between atomic (enable) and sleepable 155 * (prepare) contexts. If enabling a clock requires code that might sleep, 156 * this must be done in clk_prepare. Clock enable code that will never be 157 * called in a sleepable context may be implemented in clk_enable. 158 * 159 * Typically, drivers will call clk_prepare when a clock may be needed later 160 * (eg. when a device is opened), and clk_enable when the clock is actually 161 * required (eg. from an interrupt). Note that clk_prepare MUST have been 162 * called before clk_enable. 163 */ 164 struct clk_ops { 165 int (*prepare)(struct clk_hw *hw); 166 void (*unprepare)(struct clk_hw *hw); 167 int (*is_prepared)(struct clk_hw *hw); 168 void (*unprepare_unused)(struct clk_hw *hw); 169 int (*enable)(struct clk_hw *hw); 170 void (*disable)(struct clk_hw *hw); 171 int (*is_enabled)(struct clk_hw *hw); 172 void (*disable_unused)(struct clk_hw *hw); 173 unsigned long (*recalc_rate)(struct clk_hw *hw, 174 unsigned long parent_rate); 175 long (*round_rate)(struct clk_hw *hw, unsigned long rate, 176 unsigned long *parent_rate); 177 long (*determine_rate)(struct clk_hw *hw, unsigned long rate, 178 unsigned long *best_parent_rate, 179 struct clk **best_parent_clk); 180 int (*set_parent)(struct clk_hw *hw, u8 index); 181 u8 (*get_parent)(struct clk_hw *hw); 182 int (*set_rate)(struct clk_hw *hw, unsigned long rate, 183 unsigned long parent_rate); 184 int (*set_rate_and_parent)(struct clk_hw *hw, 185 unsigned long rate, 186 unsigned long parent_rate, u8 index); 187 unsigned long (*recalc_accuracy)(struct clk_hw *hw, 188 unsigned long parent_accuracy); 189 int (*get_phase)(struct clk_hw *hw); 190 int (*set_phase)(struct clk_hw *hw, int degrees); 191 void (*init)(struct clk_hw *hw); 192 int (*debug_init)(struct clk_hw *hw, struct dentry *dentry); 193 }; 194 195 /** 196 * struct clk_init_data - holds init data that's common to all clocks and is 197 * shared between the clock provider and the common clock framework. 198 * 199 * @name: clock name 200 * @ops: operations this clock supports 201 * @parent_names: array of string names for all possible parents 202 * @num_parents: number of possible parents 203 * @flags: framework-level hints and quirks 204 */ 205 struct clk_init_data { 206 const char *name; 207 const struct clk_ops *ops; 208 const char **parent_names; 209 u8 num_parents; 210 unsigned long flags; 211 }; 212 213 /** 214 * struct clk_hw - handle for traversing from a struct clk to its corresponding 215 * hardware-specific structure. struct clk_hw should be declared within struct 216 * clk_foo and then referenced by the struct clk instance that uses struct 217 * clk_foo's clk_ops 218 * 219 * @clk: pointer to the struct clk instance that points back to this struct 220 * clk_hw instance 221 * 222 * @init: pointer to struct clk_init_data that contains the init data shared 223 * with the common clock framework. 224 */ 225 struct clk_hw { 226 struct clk *clk; 227 const struct clk_init_data *init; 228 }; 229 230 /* 231 * DOC: Basic clock implementations common to many platforms 232 * 233 * Each basic clock hardware type is comprised of a structure describing the 234 * clock hardware, implementations of the relevant callbacks in struct clk_ops, 235 * unique flags for that hardware type, a registration function and an 236 * alternative macro for static initialization 237 */ 238 239 /** 240 * struct clk_fixed_rate - fixed-rate clock 241 * @hw: handle between common and hardware-specific interfaces 242 * @fixed_rate: constant frequency of clock 243 */ 244 struct clk_fixed_rate { 245 struct clk_hw hw; 246 unsigned long fixed_rate; 247 unsigned long fixed_accuracy; 248 u8 flags; 249 }; 250 251 extern const struct clk_ops clk_fixed_rate_ops; 252 struct clk *clk_register_fixed_rate(struct device *dev, const char *name, 253 const char *parent_name, unsigned long flags, 254 unsigned long fixed_rate); 255 struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, 256 const char *name, const char *parent_name, unsigned long flags, 257 unsigned long fixed_rate, unsigned long fixed_accuracy); 258 259 void of_fixed_clk_setup(struct device_node *np); 260 261 /** 262 * struct clk_gate - gating clock 263 * 264 * @hw: handle between common and hardware-specific interfaces 265 * @reg: register controlling gate 266 * @bit_idx: single bit controlling gate 267 * @flags: hardware-specific flags 268 * @lock: register lock 269 * 270 * Clock which can gate its output. Implements .enable & .disable 271 * 272 * Flags: 273 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to 274 * enable the clock. Setting this flag does the opposite: setting the bit 275 * disable the clock and clearing it enables the clock 276 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit 277 * of this register, and mask of gate bits are in higher 16-bit of this 278 * register. While setting the gate bits, higher 16-bit should also be 279 * updated to indicate changing gate bits. 280 */ 281 struct clk_gate { 282 struct clk_hw hw; 283 void __iomem *reg; 284 u8 bit_idx; 285 u8 flags; 286 spinlock_t *lock; 287 }; 288 289 #define CLK_GATE_SET_TO_DISABLE BIT(0) 290 #define CLK_GATE_HIWORD_MASK BIT(1) 291 292 extern const struct clk_ops clk_gate_ops; 293 struct clk *clk_register_gate(struct device *dev, const char *name, 294 const char *parent_name, unsigned long flags, 295 void __iomem *reg, u8 bit_idx, 296 u8 clk_gate_flags, spinlock_t *lock); 297 298 struct clk_div_table { 299 unsigned int val; 300 unsigned int div; 301 }; 302 303 /** 304 * struct clk_divider - adjustable divider clock 305 * 306 * @hw: handle between common and hardware-specific interfaces 307 * @reg: register containing the divider 308 * @shift: shift to the divider bit field 309 * @width: width of the divider bit field 310 * @table: array of value/divider pairs, last entry should have div = 0 311 * @lock: register lock 312 * 313 * Clock with an adjustable divider affecting its output frequency. Implements 314 * .recalc_rate, .set_rate and .round_rate 315 * 316 * Flags: 317 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the 318 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is 319 * the raw value read from the register, with the value of zero considered 320 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. 321 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from 322 * the hardware register 323 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have 324 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. 325 * Some hardware implementations gracefully handle this case and allow a 326 * zero divisor by not modifying their input clock 327 * (divide by one / bypass). 328 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit 329 * of this register, and mask of divider bits are in higher 16-bit of this 330 * register. While setting the divider bits, higher 16-bit should also be 331 * updated to indicate changing divider bits. 332 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded 333 * to the closest integer instead of the up one. 334 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should 335 * not be changed by the clock framework. 336 */ 337 struct clk_divider { 338 struct clk_hw hw; 339 void __iomem *reg; 340 u8 shift; 341 u8 width; 342 u8 flags; 343 const struct clk_div_table *table; 344 spinlock_t *lock; 345 }; 346 347 #define CLK_DIVIDER_ONE_BASED BIT(0) 348 #define CLK_DIVIDER_POWER_OF_TWO BIT(1) 349 #define CLK_DIVIDER_ALLOW_ZERO BIT(2) 350 #define CLK_DIVIDER_HIWORD_MASK BIT(3) 351 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) 352 #define CLK_DIVIDER_READ_ONLY BIT(5) 353 354 extern const struct clk_ops clk_divider_ops; 355 extern const struct clk_ops clk_divider_ro_ops; 356 struct clk *clk_register_divider(struct device *dev, const char *name, 357 const char *parent_name, unsigned long flags, 358 void __iomem *reg, u8 shift, u8 width, 359 u8 clk_divider_flags, spinlock_t *lock); 360 struct clk *clk_register_divider_table(struct device *dev, const char *name, 361 const char *parent_name, unsigned long flags, 362 void __iomem *reg, u8 shift, u8 width, 363 u8 clk_divider_flags, const struct clk_div_table *table, 364 spinlock_t *lock); 365 366 /** 367 * struct clk_mux - multiplexer clock 368 * 369 * @hw: handle between common and hardware-specific interfaces 370 * @reg: register controlling multiplexer 371 * @shift: shift to multiplexer bit field 372 * @width: width of mutliplexer bit field 373 * @flags: hardware-specific flags 374 * @lock: register lock 375 * 376 * Clock with multiple selectable parents. Implements .get_parent, .set_parent 377 * and .recalc_rate 378 * 379 * Flags: 380 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 381 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) 382 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this 383 * register, and mask of mux bits are in higher 16-bit of this register. 384 * While setting the mux bits, higher 16-bit should also be updated to 385 * indicate changing mux bits. 386 */ 387 struct clk_mux { 388 struct clk_hw hw; 389 void __iomem *reg; 390 u32 *table; 391 u32 mask; 392 u8 shift; 393 u8 flags; 394 spinlock_t *lock; 395 }; 396 397 #define CLK_MUX_INDEX_ONE BIT(0) 398 #define CLK_MUX_INDEX_BIT BIT(1) 399 #define CLK_MUX_HIWORD_MASK BIT(2) 400 #define CLK_MUX_READ_ONLY BIT(3) /* mux setting cannot be changed */ 401 402 extern const struct clk_ops clk_mux_ops; 403 extern const struct clk_ops clk_mux_ro_ops; 404 405 struct clk *clk_register_mux(struct device *dev, const char *name, 406 const char **parent_names, u8 num_parents, unsigned long flags, 407 void __iomem *reg, u8 shift, u8 width, 408 u8 clk_mux_flags, spinlock_t *lock); 409 410 struct clk *clk_register_mux_table(struct device *dev, const char *name, 411 const char **parent_names, u8 num_parents, unsigned long flags, 412 void __iomem *reg, u8 shift, u32 mask, 413 u8 clk_mux_flags, u32 *table, spinlock_t *lock); 414 415 void of_fixed_factor_clk_setup(struct device_node *node); 416 417 /** 418 * struct clk_fixed_factor - fixed multiplier and divider clock 419 * 420 * @hw: handle between common and hardware-specific interfaces 421 * @mult: multiplier 422 * @div: divider 423 * 424 * Clock with a fixed multiplier and divider. The output frequency is the 425 * parent clock rate divided by div and multiplied by mult. 426 * Implements .recalc_rate, .set_rate and .round_rate 427 */ 428 429 struct clk_fixed_factor { 430 struct clk_hw hw; 431 unsigned int mult; 432 unsigned int div; 433 }; 434 435 extern struct clk_ops clk_fixed_factor_ops; 436 struct clk *clk_register_fixed_factor(struct device *dev, const char *name, 437 const char *parent_name, unsigned long flags, 438 unsigned int mult, unsigned int div); 439 440 /** 441 * struct clk_fractional_divider - adjustable fractional divider clock 442 * 443 * @hw: handle between common and hardware-specific interfaces 444 * @reg: register containing the divider 445 * @mshift: shift to the numerator bit field 446 * @mwidth: width of the numerator bit field 447 * @nshift: shift to the denominator bit field 448 * @nwidth: width of the denominator bit field 449 * @lock: register lock 450 * 451 * Clock with adjustable fractional divider affecting its output frequency. 452 */ 453 454 struct clk_fractional_divider { 455 struct clk_hw hw; 456 void __iomem *reg; 457 u8 mshift; 458 u32 mmask; 459 u8 nshift; 460 u32 nmask; 461 u8 flags; 462 spinlock_t *lock; 463 }; 464 465 extern const struct clk_ops clk_fractional_divider_ops; 466 struct clk *clk_register_fractional_divider(struct device *dev, 467 const char *name, const char *parent_name, unsigned long flags, 468 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, 469 u8 clk_divider_flags, spinlock_t *lock); 470 471 /*** 472 * struct clk_composite - aggregate clock of mux, divider and gate clocks 473 * 474 * @hw: handle between common and hardware-specific interfaces 475 * @mux_hw: handle between composite and hardware-specific mux clock 476 * @rate_hw: handle between composite and hardware-specific rate clock 477 * @gate_hw: handle between composite and hardware-specific gate clock 478 * @mux_ops: clock ops for mux 479 * @rate_ops: clock ops for rate 480 * @gate_ops: clock ops for gate 481 */ 482 struct clk_composite { 483 struct clk_hw hw; 484 struct clk_ops ops; 485 486 struct clk_hw *mux_hw; 487 struct clk_hw *rate_hw; 488 struct clk_hw *gate_hw; 489 490 const struct clk_ops *mux_ops; 491 const struct clk_ops *rate_ops; 492 const struct clk_ops *gate_ops; 493 }; 494 495 struct clk *clk_register_composite(struct device *dev, const char *name, 496 const char **parent_names, int num_parents, 497 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 498 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 499 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 500 unsigned long flags); 501 502 /*** 503 * struct clk_gpio_gate - gpio gated clock 504 * 505 * @hw: handle between common and hardware-specific interfaces 506 * @gpiod: gpio descriptor 507 * 508 * Clock with a gpio control for enabling and disabling the parent clock. 509 * Implements .enable, .disable and .is_enabled 510 */ 511 512 struct clk_gpio { 513 struct clk_hw hw; 514 struct gpio_desc *gpiod; 515 }; 516 517 extern const struct clk_ops clk_gpio_gate_ops; 518 struct clk *clk_register_gpio_gate(struct device *dev, const char *name, 519 const char *parent_name, struct gpio_desc *gpio, 520 unsigned long flags); 521 522 void of_gpio_clk_gate_setup(struct device_node *node); 523 524 /** 525 * clk_register - allocate a new clock, register it and return an opaque cookie 526 * @dev: device that is registering this clock 527 * @hw: link to hardware-specific clock data 528 * 529 * clk_register is the primary interface for populating the clock tree with new 530 * clock nodes. It returns a pointer to the newly allocated struct clk which 531 * cannot be dereferenced by driver code but may be used in conjuction with the 532 * rest of the clock API. In the event of an error clk_register will return an 533 * error code; drivers must test for an error code after calling clk_register. 534 */ 535 struct clk *clk_register(struct device *dev, struct clk_hw *hw); 536 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); 537 538 void clk_unregister(struct clk *clk); 539 void devm_clk_unregister(struct device *dev, struct clk *clk); 540 541 /* helper functions */ 542 const char *__clk_get_name(struct clk *clk); 543 struct clk_hw *__clk_get_hw(struct clk *clk); 544 u8 __clk_get_num_parents(struct clk *clk); 545 struct clk *__clk_get_parent(struct clk *clk); 546 struct clk *clk_get_parent_by_index(struct clk *clk, u8 index); 547 unsigned int __clk_get_enable_count(struct clk *clk); 548 unsigned int __clk_get_prepare_count(struct clk *clk); 549 unsigned long __clk_get_rate(struct clk *clk); 550 unsigned long __clk_get_accuracy(struct clk *clk); 551 unsigned long __clk_get_flags(struct clk *clk); 552 bool __clk_is_prepared(struct clk *clk); 553 bool __clk_is_enabled(struct clk *clk); 554 struct clk *__clk_lookup(const char *name); 555 long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate, 556 unsigned long *best_parent_rate, 557 struct clk **best_parent_p); 558 559 /* 560 * FIXME clock api without lock protection 561 */ 562 int __clk_prepare(struct clk *clk); 563 void __clk_unprepare(struct clk *clk); 564 void __clk_reparent(struct clk *clk, struct clk *new_parent); 565 unsigned long __clk_round_rate(struct clk *clk, unsigned long rate); 566 567 struct of_device_id; 568 569 typedef void (*of_clk_init_cb_t)(struct device_node *); 570 571 struct clk_onecell_data { 572 struct clk **clks; 573 unsigned int clk_num; 574 }; 575 576 extern struct of_device_id __clk_of_table; 577 578 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn) 579 580 #ifdef CONFIG_OF 581 int of_clk_add_provider(struct device_node *np, 582 struct clk *(*clk_src_get)(struct of_phandle_args *args, 583 void *data), 584 void *data); 585 void of_clk_del_provider(struct device_node *np); 586 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, 587 void *data); 588 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); 589 int of_clk_get_parent_count(struct device_node *np); 590 const char *of_clk_get_parent_name(struct device_node *np, int index); 591 592 void of_clk_init(const struct of_device_id *matches); 593 594 #else /* !CONFIG_OF */ 595 596 static inline int of_clk_add_provider(struct device_node *np, 597 struct clk *(*clk_src_get)(struct of_phandle_args *args, 598 void *data), 599 void *data) 600 { 601 return 0; 602 } 603 #define of_clk_del_provider(np) \ 604 { while (0); } 605 static inline struct clk *of_clk_src_simple_get( 606 struct of_phandle_args *clkspec, void *data) 607 { 608 return ERR_PTR(-ENOENT); 609 } 610 static inline struct clk *of_clk_src_onecell_get( 611 struct of_phandle_args *clkspec, void *data) 612 { 613 return ERR_PTR(-ENOENT); 614 } 615 static inline const char *of_clk_get_parent_name(struct device_node *np, 616 int index) 617 { 618 return NULL; 619 } 620 #define of_clk_init(matches) \ 621 { while (0); } 622 #endif /* CONFIG_OF */ 623 624 /* 625 * wrap access to peripherals in accessor routines 626 * for improved portability across platforms 627 */ 628 629 #if IS_ENABLED(CONFIG_PPC) 630 631 static inline u32 clk_readl(u32 __iomem *reg) 632 { 633 return ioread32be(reg); 634 } 635 636 static inline void clk_writel(u32 val, u32 __iomem *reg) 637 { 638 iowrite32be(val, reg); 639 } 640 641 #else /* platform dependent I/O accessors */ 642 643 static inline u32 clk_readl(u32 __iomem *reg) 644 { 645 return readl(reg); 646 } 647 648 static inline void clk_writel(u32 val, u32 __iomem *reg) 649 { 650 writel(val, reg); 651 } 652 653 #endif /* platform dependent I/O accessors */ 654 655 #ifdef CONFIG_DEBUG_FS 656 struct dentry *clk_debugfs_add_file(struct clk *clk, char *name, umode_t mode, 657 void *data, const struct file_operations *fops); 658 #endif 659 660 #endif /* CONFIG_COMMON_CLK */ 661 #endif /* CLK_PROVIDER_H */ 662