1 /* 2 * linux/include/linux/clk-provider.h 3 * 4 * Copyright (c) 2010-2011 Jeremy Kerr <[email protected]> 5 * Copyright (C) 2011-2012 Linaro Ltd <[email protected]> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #ifndef __LINUX_CLK_PROVIDER_H 12 #define __LINUX_CLK_PROVIDER_H 13 14 #include <linux/io.h> 15 #include <linux/of.h> 16 #include <linux/of_clk.h> 17 18 #ifdef CONFIG_COMMON_CLK 19 20 /* 21 * flags used across common struct clk. these flags should only affect the 22 * top-level framework. custom flags for dealing with hardware specifics 23 * belong in struct clk_foo 24 * 25 * Please update clk_flags[] in drivers/clk/clk.c when making changes here! 26 */ 27 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ 28 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ 29 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ 30 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ 31 /* unused */ 32 #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ 33 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ 34 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ 35 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ 36 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ 37 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */ 38 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ 39 /* parents need enable during gate/ungate, set rate and re-parent */ 40 #define CLK_OPS_PARENT_ENABLE BIT(12) 41 /* duty cycle call may be forwarded to the parent clock */ 42 #define CLK_DUTY_CYCLE_PARENT BIT(13) 43 44 struct clk; 45 struct clk_hw; 46 struct clk_core; 47 struct dentry; 48 49 /** 50 * struct clk_rate_request - Structure encoding the clk constraints that 51 * a clock user might require. 52 * 53 * @rate: Requested clock rate. This field will be adjusted by 54 * clock drivers according to hardware capabilities. 55 * @min_rate: Minimum rate imposed by clk users. 56 * @max_rate: Maximum rate imposed by clk users. 57 * @best_parent_rate: The best parent rate a parent can provide to fulfill the 58 * requested constraints. 59 * @best_parent_hw: The most appropriate parent clock that fulfills the 60 * requested constraints. 61 * 62 */ 63 struct clk_rate_request { 64 unsigned long rate; 65 unsigned long min_rate; 66 unsigned long max_rate; 67 unsigned long best_parent_rate; 68 struct clk_hw *best_parent_hw; 69 }; 70 71 /** 72 * struct clk_duty - Struture encoding the duty cycle ratio of a clock 73 * 74 * @num: Numerator of the duty cycle ratio 75 * @den: Denominator of the duty cycle ratio 76 */ 77 struct clk_duty { 78 unsigned int num; 79 unsigned int den; 80 }; 81 82 /** 83 * struct clk_ops - Callback operations for hardware clocks; these are to 84 * be provided by the clock implementation, and will be called by drivers 85 * through the clk_* api. 86 * 87 * @prepare: Prepare the clock for enabling. This must not return until 88 * the clock is fully prepared, and it's safe to call clk_enable. 89 * This callback is intended to allow clock implementations to 90 * do any initialisation that may sleep. Called with 91 * prepare_lock held. 92 * 93 * @unprepare: Release the clock from its prepared state. This will typically 94 * undo any work done in the @prepare callback. Called with 95 * prepare_lock held. 96 * 97 * @is_prepared: Queries the hardware to determine if the clock is prepared. 98 * This function is allowed to sleep. Optional, if this op is not 99 * set then the prepare count will be used. 100 * 101 * @unprepare_unused: Unprepare the clock atomically. Only called from 102 * clk_disable_unused for prepare clocks with special needs. 103 * Called with prepare mutex held. This function may sleep. 104 * 105 * @enable: Enable the clock atomically. This must not return until the 106 * clock is generating a valid clock signal, usable by consumer 107 * devices. Called with enable_lock held. This function must not 108 * sleep. 109 * 110 * @disable: Disable the clock atomically. Called with enable_lock held. 111 * This function must not sleep. 112 * 113 * @is_enabled: Queries the hardware to determine if the clock is enabled. 114 * This function must not sleep. Optional, if this op is not 115 * set then the enable count will be used. 116 * 117 * @disable_unused: Disable the clock atomically. Only called from 118 * clk_disable_unused for gate clocks with special needs. 119 * Called with enable_lock held. This function must not 120 * sleep. 121 * 122 * @save_context: Save the context of the clock in prepration for poweroff. 123 * 124 * @restore_context: Restore the context of the clock after a restoration 125 * of power. 126 * 127 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The 128 * parent rate is an input parameter. It is up to the caller to 129 * ensure that the prepare_mutex is held across this call. 130 * Returns the calculated rate. Optional, but recommended - if 131 * this op is not set then clock rate will be initialized to 0. 132 * 133 * @round_rate: Given a target rate as input, returns the closest rate actually 134 * supported by the clock. The parent rate is an input/output 135 * parameter. 136 * 137 * @determine_rate: Given a target rate as input, returns the closest rate 138 * actually supported by the clock, and optionally the parent clock 139 * that should be used to provide the clock rate. 140 * 141 * @set_parent: Change the input source of this clock; for clocks with multiple 142 * possible parents specify a new parent by passing in the index 143 * as a u8 corresponding to the parent in either the .parent_names 144 * or .parents arrays. This function in affect translates an 145 * array index into the value programmed into the hardware. 146 * Returns 0 on success, -EERROR otherwise. 147 * 148 * @get_parent: Queries the hardware to determine the parent of a clock. The 149 * return value is a u8 which specifies the index corresponding to 150 * the parent clock. This index can be applied to either the 151 * .parent_names or .parents arrays. In short, this function 152 * translates the parent value read from hardware into an array 153 * index. Currently only called when the clock is initialized by 154 * __clk_init. This callback is mandatory for clocks with 155 * multiple parents. It is optional (and unnecessary) for clocks 156 * with 0 or 1 parents. 157 * 158 * @set_rate: Change the rate of this clock. The requested rate is specified 159 * by the second argument, which should typically be the return 160 * of .round_rate call. The third argument gives the parent rate 161 * which is likely helpful for most .set_rate implementation. 162 * Returns 0 on success, -EERROR otherwise. 163 * 164 * @set_rate_and_parent: Change the rate and the parent of this clock. The 165 * requested rate is specified by the second argument, which 166 * should typically be the return of .round_rate call. The 167 * third argument gives the parent rate which is likely helpful 168 * for most .set_rate_and_parent implementation. The fourth 169 * argument gives the parent index. This callback is optional (and 170 * unnecessary) for clocks with 0 or 1 parents as well as 171 * for clocks that can tolerate switching the rate and the parent 172 * separately via calls to .set_parent and .set_rate. 173 * Returns 0 on success, -EERROR otherwise. 174 * 175 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy 176 * is expressed in ppb (parts per billion). The parent accuracy is 177 * an input parameter. 178 * Returns the calculated accuracy. Optional - if this op is not 179 * set then clock accuracy will be initialized to parent accuracy 180 * or 0 (perfect clock) if clock has no parent. 181 * 182 * @get_phase: Queries the hardware to get the current phase of a clock. 183 * Returned values are 0-359 degrees on success, negative 184 * error codes on failure. 185 * 186 * @set_phase: Shift the phase this clock signal in degrees specified 187 * by the second argument. Valid values for degrees are 188 * 0-359. Return 0 on success, otherwise -EERROR. 189 * 190 * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio 191 * of a clock. Returned values denominator cannot be 0 and must be 192 * superior or equal to the numerator. 193 * 194 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by 195 * the numerator (2nd argurment) and denominator (3rd argument). 196 * Argument must be a valid ratio (denominator > 0 197 * and >= numerator) Return 0 on success, otherwise -EERROR. 198 * 199 * @init: Perform platform-specific initialization magic. 200 * This is not not used by any of the basic clock types. 201 * Please consider other ways of solving initialization problems 202 * before using this callback, as its use is discouraged. 203 * 204 * @debug_init: Set up type-specific debugfs entries for this clock. This 205 * is called once, after the debugfs directory entry for this 206 * clock has been created. The dentry pointer representing that 207 * directory is provided as an argument. Called with 208 * prepare_lock held. Returns 0 on success, -EERROR otherwise. 209 * 210 * 211 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow 212 * implementations to split any work between atomic (enable) and sleepable 213 * (prepare) contexts. If enabling a clock requires code that might sleep, 214 * this must be done in clk_prepare. Clock enable code that will never be 215 * called in a sleepable context may be implemented in clk_enable. 216 * 217 * Typically, drivers will call clk_prepare when a clock may be needed later 218 * (eg. when a device is opened), and clk_enable when the clock is actually 219 * required (eg. from an interrupt). Note that clk_prepare MUST have been 220 * called before clk_enable. 221 */ 222 struct clk_ops { 223 int (*prepare)(struct clk_hw *hw); 224 void (*unprepare)(struct clk_hw *hw); 225 int (*is_prepared)(struct clk_hw *hw); 226 void (*unprepare_unused)(struct clk_hw *hw); 227 int (*enable)(struct clk_hw *hw); 228 void (*disable)(struct clk_hw *hw); 229 int (*is_enabled)(struct clk_hw *hw); 230 void (*disable_unused)(struct clk_hw *hw); 231 int (*save_context)(struct clk_hw *hw); 232 void (*restore_context)(struct clk_hw *hw); 233 unsigned long (*recalc_rate)(struct clk_hw *hw, 234 unsigned long parent_rate); 235 long (*round_rate)(struct clk_hw *hw, unsigned long rate, 236 unsigned long *parent_rate); 237 int (*determine_rate)(struct clk_hw *hw, 238 struct clk_rate_request *req); 239 int (*set_parent)(struct clk_hw *hw, u8 index); 240 u8 (*get_parent)(struct clk_hw *hw); 241 int (*set_rate)(struct clk_hw *hw, unsigned long rate, 242 unsigned long parent_rate); 243 int (*set_rate_and_parent)(struct clk_hw *hw, 244 unsigned long rate, 245 unsigned long parent_rate, u8 index); 246 unsigned long (*recalc_accuracy)(struct clk_hw *hw, 247 unsigned long parent_accuracy); 248 int (*get_phase)(struct clk_hw *hw); 249 int (*set_phase)(struct clk_hw *hw, int degrees); 250 int (*get_duty_cycle)(struct clk_hw *hw, 251 struct clk_duty *duty); 252 int (*set_duty_cycle)(struct clk_hw *hw, 253 struct clk_duty *duty); 254 void (*init)(struct clk_hw *hw); 255 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry); 256 }; 257 258 /** 259 * struct clk_init_data - holds init data that's common to all clocks and is 260 * shared between the clock provider and the common clock framework. 261 * 262 * @name: clock name 263 * @ops: operations this clock supports 264 * @parent_names: array of string names for all possible parents 265 * @num_parents: number of possible parents 266 * @flags: framework-level hints and quirks 267 */ 268 struct clk_init_data { 269 const char *name; 270 const struct clk_ops *ops; 271 const char * const *parent_names; 272 u8 num_parents; 273 unsigned long flags; 274 }; 275 276 /** 277 * struct clk_hw - handle for traversing from a struct clk to its corresponding 278 * hardware-specific structure. struct clk_hw should be declared within struct 279 * clk_foo and then referenced by the struct clk instance that uses struct 280 * clk_foo's clk_ops 281 * 282 * @core: pointer to the struct clk_core instance that points back to this 283 * struct clk_hw instance 284 * 285 * @clk: pointer to the per-user struct clk instance that can be used to call 286 * into the clk API 287 * 288 * @init: pointer to struct clk_init_data that contains the init data shared 289 * with the common clock framework. 290 */ 291 struct clk_hw { 292 struct clk_core *core; 293 struct clk *clk; 294 const struct clk_init_data *init; 295 }; 296 297 /* 298 * DOC: Basic clock implementations common to many platforms 299 * 300 * Each basic clock hardware type is comprised of a structure describing the 301 * clock hardware, implementations of the relevant callbacks in struct clk_ops, 302 * unique flags for that hardware type, a registration function and an 303 * alternative macro for static initialization 304 */ 305 306 /** 307 * struct clk_fixed_rate - fixed-rate clock 308 * @hw: handle between common and hardware-specific interfaces 309 * @fixed_rate: constant frequency of clock 310 */ 311 struct clk_fixed_rate { 312 struct clk_hw hw; 313 unsigned long fixed_rate; 314 unsigned long fixed_accuracy; 315 u8 flags; 316 }; 317 318 #define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw) 319 320 extern const struct clk_ops clk_fixed_rate_ops; 321 struct clk *clk_register_fixed_rate(struct device *dev, const char *name, 322 const char *parent_name, unsigned long flags, 323 unsigned long fixed_rate); 324 struct clk_hw *clk_hw_register_fixed_rate(struct device *dev, const char *name, 325 const char *parent_name, unsigned long flags, 326 unsigned long fixed_rate); 327 struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, 328 const char *name, const char *parent_name, unsigned long flags, 329 unsigned long fixed_rate, unsigned long fixed_accuracy); 330 void clk_unregister_fixed_rate(struct clk *clk); 331 struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev, 332 const char *name, const char *parent_name, unsigned long flags, 333 unsigned long fixed_rate, unsigned long fixed_accuracy); 334 void clk_hw_unregister_fixed_rate(struct clk_hw *hw); 335 336 void of_fixed_clk_setup(struct device_node *np); 337 338 /** 339 * struct clk_gate - gating clock 340 * 341 * @hw: handle between common and hardware-specific interfaces 342 * @reg: register controlling gate 343 * @bit_idx: single bit controlling gate 344 * @flags: hardware-specific flags 345 * @lock: register lock 346 * 347 * Clock which can gate its output. Implements .enable & .disable 348 * 349 * Flags: 350 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to 351 * enable the clock. Setting this flag does the opposite: setting the bit 352 * disable the clock and clearing it enables the clock 353 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit 354 * of this register, and mask of gate bits are in higher 16-bit of this 355 * register. While setting the gate bits, higher 16-bit should also be 356 * updated to indicate changing gate bits. 357 */ 358 struct clk_gate { 359 struct clk_hw hw; 360 void __iomem *reg; 361 u8 bit_idx; 362 u8 flags; 363 spinlock_t *lock; 364 }; 365 366 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) 367 368 #define CLK_GATE_SET_TO_DISABLE BIT(0) 369 #define CLK_GATE_HIWORD_MASK BIT(1) 370 371 extern const struct clk_ops clk_gate_ops; 372 struct clk *clk_register_gate(struct device *dev, const char *name, 373 const char *parent_name, unsigned long flags, 374 void __iomem *reg, u8 bit_idx, 375 u8 clk_gate_flags, spinlock_t *lock); 376 struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name, 377 const char *parent_name, unsigned long flags, 378 void __iomem *reg, u8 bit_idx, 379 u8 clk_gate_flags, spinlock_t *lock); 380 void clk_unregister_gate(struct clk *clk); 381 void clk_hw_unregister_gate(struct clk_hw *hw); 382 int clk_gate_is_enabled(struct clk_hw *hw); 383 384 struct clk_div_table { 385 unsigned int val; 386 unsigned int div; 387 }; 388 389 /** 390 * struct clk_divider - adjustable divider clock 391 * 392 * @hw: handle between common and hardware-specific interfaces 393 * @reg: register containing the divider 394 * @shift: shift to the divider bit field 395 * @width: width of the divider bit field 396 * @table: array of value/divider pairs, last entry should have div = 0 397 * @lock: register lock 398 * 399 * Clock with an adjustable divider affecting its output frequency. Implements 400 * .recalc_rate, .set_rate and .round_rate 401 * 402 * Flags: 403 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the 404 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is 405 * the raw value read from the register, with the value of zero considered 406 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. 407 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from 408 * the hardware register 409 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have 410 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. 411 * Some hardware implementations gracefully handle this case and allow a 412 * zero divisor by not modifying their input clock 413 * (divide by one / bypass). 414 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit 415 * of this register, and mask of divider bits are in higher 16-bit of this 416 * register. While setting the divider bits, higher 16-bit should also be 417 * updated to indicate changing divider bits. 418 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded 419 * to the closest integer instead of the up one. 420 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should 421 * not be changed by the clock framework. 422 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED 423 * except when the value read from the register is zero, the divisor is 424 * 2^width of the field. 425 */ 426 struct clk_divider { 427 struct clk_hw hw; 428 void __iomem *reg; 429 u8 shift; 430 u8 width; 431 u8 flags; 432 const struct clk_div_table *table; 433 spinlock_t *lock; 434 }; 435 436 #define clk_div_mask(width) ((1 << (width)) - 1) 437 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) 438 439 #define CLK_DIVIDER_ONE_BASED BIT(0) 440 #define CLK_DIVIDER_POWER_OF_TWO BIT(1) 441 #define CLK_DIVIDER_ALLOW_ZERO BIT(2) 442 #define CLK_DIVIDER_HIWORD_MASK BIT(3) 443 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) 444 #define CLK_DIVIDER_READ_ONLY BIT(5) 445 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) 446 447 extern const struct clk_ops clk_divider_ops; 448 extern const struct clk_ops clk_divider_ro_ops; 449 450 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, 451 unsigned int val, const struct clk_div_table *table, 452 unsigned long flags, unsigned long width); 453 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, 454 unsigned long rate, unsigned long *prate, 455 const struct clk_div_table *table, 456 u8 width, unsigned long flags); 457 long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, 458 unsigned long rate, unsigned long *prate, 459 const struct clk_div_table *table, u8 width, 460 unsigned long flags, unsigned int val); 461 int divider_get_val(unsigned long rate, unsigned long parent_rate, 462 const struct clk_div_table *table, u8 width, 463 unsigned long flags); 464 465 struct clk *clk_register_divider(struct device *dev, const char *name, 466 const char *parent_name, unsigned long flags, 467 void __iomem *reg, u8 shift, u8 width, 468 u8 clk_divider_flags, spinlock_t *lock); 469 struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name, 470 const char *parent_name, unsigned long flags, 471 void __iomem *reg, u8 shift, u8 width, 472 u8 clk_divider_flags, spinlock_t *lock); 473 struct clk *clk_register_divider_table(struct device *dev, const char *name, 474 const char *parent_name, unsigned long flags, 475 void __iomem *reg, u8 shift, u8 width, 476 u8 clk_divider_flags, const struct clk_div_table *table, 477 spinlock_t *lock); 478 struct clk_hw *clk_hw_register_divider_table(struct device *dev, 479 const char *name, const char *parent_name, unsigned long flags, 480 void __iomem *reg, u8 shift, u8 width, 481 u8 clk_divider_flags, const struct clk_div_table *table, 482 spinlock_t *lock); 483 void clk_unregister_divider(struct clk *clk); 484 void clk_hw_unregister_divider(struct clk_hw *hw); 485 486 /** 487 * struct clk_mux - multiplexer clock 488 * 489 * @hw: handle between common and hardware-specific interfaces 490 * @reg: register controlling multiplexer 491 * @table: array of register values corresponding to the parent index 492 * @shift: shift to multiplexer bit field 493 * @mask: mask of mutliplexer bit field 494 * @flags: hardware-specific flags 495 * @lock: register lock 496 * 497 * Clock with multiple selectable parents. Implements .get_parent, .set_parent 498 * and .recalc_rate 499 * 500 * Flags: 501 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 502 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) 503 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this 504 * register, and mask of mux bits are in higher 16-bit of this register. 505 * While setting the mux bits, higher 16-bit should also be updated to 506 * indicate changing mux bits. 507 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired 508 * frequency. 509 */ 510 struct clk_mux { 511 struct clk_hw hw; 512 void __iomem *reg; 513 u32 *table; 514 u32 mask; 515 u8 shift; 516 u8 flags; 517 spinlock_t *lock; 518 }; 519 520 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) 521 522 #define CLK_MUX_INDEX_ONE BIT(0) 523 #define CLK_MUX_INDEX_BIT BIT(1) 524 #define CLK_MUX_HIWORD_MASK BIT(2) 525 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ 526 #define CLK_MUX_ROUND_CLOSEST BIT(4) 527 528 extern const struct clk_ops clk_mux_ops; 529 extern const struct clk_ops clk_mux_ro_ops; 530 531 struct clk *clk_register_mux(struct device *dev, const char *name, 532 const char * const *parent_names, u8 num_parents, 533 unsigned long flags, 534 void __iomem *reg, u8 shift, u8 width, 535 u8 clk_mux_flags, spinlock_t *lock); 536 struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name, 537 const char * const *parent_names, u8 num_parents, 538 unsigned long flags, 539 void __iomem *reg, u8 shift, u8 width, 540 u8 clk_mux_flags, spinlock_t *lock); 541 542 struct clk *clk_register_mux_table(struct device *dev, const char *name, 543 const char * const *parent_names, u8 num_parents, 544 unsigned long flags, 545 void __iomem *reg, u8 shift, u32 mask, 546 u8 clk_mux_flags, u32 *table, spinlock_t *lock); 547 struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name, 548 const char * const *parent_names, u8 num_parents, 549 unsigned long flags, 550 void __iomem *reg, u8 shift, u32 mask, 551 u8 clk_mux_flags, u32 *table, spinlock_t *lock); 552 553 int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, 554 unsigned int val); 555 unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index); 556 557 void clk_unregister_mux(struct clk *clk); 558 void clk_hw_unregister_mux(struct clk_hw *hw); 559 560 void of_fixed_factor_clk_setup(struct device_node *node); 561 562 /** 563 * struct clk_fixed_factor - fixed multiplier and divider clock 564 * 565 * @hw: handle between common and hardware-specific interfaces 566 * @mult: multiplier 567 * @div: divider 568 * 569 * Clock with a fixed multiplier and divider. The output frequency is the 570 * parent clock rate divided by div and multiplied by mult. 571 * Implements .recalc_rate, .set_rate and .round_rate 572 */ 573 574 struct clk_fixed_factor { 575 struct clk_hw hw; 576 unsigned int mult; 577 unsigned int div; 578 }; 579 580 #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw) 581 582 extern const struct clk_ops clk_fixed_factor_ops; 583 struct clk *clk_register_fixed_factor(struct device *dev, const char *name, 584 const char *parent_name, unsigned long flags, 585 unsigned int mult, unsigned int div); 586 void clk_unregister_fixed_factor(struct clk *clk); 587 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, 588 const char *name, const char *parent_name, unsigned long flags, 589 unsigned int mult, unsigned int div); 590 void clk_hw_unregister_fixed_factor(struct clk_hw *hw); 591 592 /** 593 * struct clk_fractional_divider - adjustable fractional divider clock 594 * 595 * @hw: handle between common and hardware-specific interfaces 596 * @reg: register containing the divider 597 * @mshift: shift to the numerator bit field 598 * @mwidth: width of the numerator bit field 599 * @nshift: shift to the denominator bit field 600 * @nwidth: width of the denominator bit field 601 * @lock: register lock 602 * 603 * Clock with adjustable fractional divider affecting its output frequency. 604 */ 605 struct clk_fractional_divider { 606 struct clk_hw hw; 607 void __iomem *reg; 608 u8 mshift; 609 u8 mwidth; 610 u32 mmask; 611 u8 nshift; 612 u8 nwidth; 613 u32 nmask; 614 u8 flags; 615 void (*approximation)(struct clk_hw *hw, 616 unsigned long rate, unsigned long *parent_rate, 617 unsigned long *m, unsigned long *n); 618 spinlock_t *lock; 619 }; 620 621 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) 622 623 extern const struct clk_ops clk_fractional_divider_ops; 624 struct clk *clk_register_fractional_divider(struct device *dev, 625 const char *name, const char *parent_name, unsigned long flags, 626 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, 627 u8 clk_divider_flags, spinlock_t *lock); 628 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, 629 const char *name, const char *parent_name, unsigned long flags, 630 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, 631 u8 clk_divider_flags, spinlock_t *lock); 632 void clk_hw_unregister_fractional_divider(struct clk_hw *hw); 633 634 /** 635 * struct clk_multiplier - adjustable multiplier clock 636 * 637 * @hw: handle between common and hardware-specific interfaces 638 * @reg: register containing the multiplier 639 * @shift: shift to the multiplier bit field 640 * @width: width of the multiplier bit field 641 * @lock: register lock 642 * 643 * Clock with an adjustable multiplier affecting its output frequency. 644 * Implements .recalc_rate, .set_rate and .round_rate 645 * 646 * Flags: 647 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read 648 * from the register, with 0 being a valid value effectively 649 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is 650 * set, then a null multiplier will be considered as a bypass, 651 * leaving the parent rate unmodified. 652 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be 653 * rounded to the closest integer instead of the down one. 654 */ 655 struct clk_multiplier { 656 struct clk_hw hw; 657 void __iomem *reg; 658 u8 shift; 659 u8 width; 660 u8 flags; 661 spinlock_t *lock; 662 }; 663 664 #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw) 665 666 #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0) 667 #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1) 668 669 extern const struct clk_ops clk_multiplier_ops; 670 671 /*** 672 * struct clk_composite - aggregate clock of mux, divider and gate clocks 673 * 674 * @hw: handle between common and hardware-specific interfaces 675 * @mux_hw: handle between composite and hardware-specific mux clock 676 * @rate_hw: handle between composite and hardware-specific rate clock 677 * @gate_hw: handle between composite and hardware-specific gate clock 678 * @mux_ops: clock ops for mux 679 * @rate_ops: clock ops for rate 680 * @gate_ops: clock ops for gate 681 */ 682 struct clk_composite { 683 struct clk_hw hw; 684 struct clk_ops ops; 685 686 struct clk_hw *mux_hw; 687 struct clk_hw *rate_hw; 688 struct clk_hw *gate_hw; 689 690 const struct clk_ops *mux_ops; 691 const struct clk_ops *rate_ops; 692 const struct clk_ops *gate_ops; 693 }; 694 695 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) 696 697 struct clk *clk_register_composite(struct device *dev, const char *name, 698 const char * const *parent_names, int num_parents, 699 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 700 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 701 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 702 unsigned long flags); 703 void clk_unregister_composite(struct clk *clk); 704 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name, 705 const char * const *parent_names, int num_parents, 706 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 707 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 708 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 709 unsigned long flags); 710 void clk_hw_unregister_composite(struct clk_hw *hw); 711 712 /*** 713 * struct clk_gpio_gate - gpio gated clock 714 * 715 * @hw: handle between common and hardware-specific interfaces 716 * @gpiod: gpio descriptor 717 * 718 * Clock with a gpio control for enabling and disabling the parent clock. 719 * Implements .enable, .disable and .is_enabled 720 */ 721 722 struct clk_gpio { 723 struct clk_hw hw; 724 struct gpio_desc *gpiod; 725 }; 726 727 #define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw) 728 729 extern const struct clk_ops clk_gpio_gate_ops; 730 struct clk *clk_register_gpio_gate(struct device *dev, const char *name, 731 const char *parent_name, struct gpio_desc *gpiod, 732 unsigned long flags); 733 struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name, 734 const char *parent_name, struct gpio_desc *gpiod, 735 unsigned long flags); 736 void clk_hw_unregister_gpio_gate(struct clk_hw *hw); 737 738 /** 739 * struct clk_gpio_mux - gpio controlled clock multiplexer 740 * 741 * @hw: see struct clk_gpio 742 * @gpiod: gpio descriptor to select the parent of this clock multiplexer 743 * 744 * Clock with a gpio control for selecting the parent clock. 745 * Implements .get_parent, .set_parent and .determine_rate 746 */ 747 748 extern const struct clk_ops clk_gpio_mux_ops; 749 struct clk *clk_register_gpio_mux(struct device *dev, const char *name, 750 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod, 751 unsigned long flags); 752 struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name, 753 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod, 754 unsigned long flags); 755 void clk_hw_unregister_gpio_mux(struct clk_hw *hw); 756 757 /** 758 * clk_register - allocate a new clock, register it and return an opaque cookie 759 * @dev: device that is registering this clock 760 * @hw: link to hardware-specific clock data 761 * 762 * clk_register is the primary interface for populating the clock tree with new 763 * clock nodes. It returns a pointer to the newly allocated struct clk which 764 * cannot be dereferenced by driver code but may be used in conjuction with the 765 * rest of the clock API. In the event of an error clk_register will return an 766 * error code; drivers must test for an error code after calling clk_register. 767 */ 768 struct clk *clk_register(struct device *dev, struct clk_hw *hw); 769 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); 770 771 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw); 772 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw); 773 774 void clk_unregister(struct clk *clk); 775 void devm_clk_unregister(struct device *dev, struct clk *clk); 776 777 void clk_hw_unregister(struct clk_hw *hw); 778 void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw); 779 780 /* helper functions */ 781 const char *__clk_get_name(const struct clk *clk); 782 const char *clk_hw_get_name(const struct clk_hw *hw); 783 struct clk_hw *__clk_get_hw(struct clk *clk); 784 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); 785 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); 786 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, 787 unsigned int index); 788 unsigned int __clk_get_enable_count(struct clk *clk); 789 unsigned long clk_hw_get_rate(const struct clk_hw *hw); 790 unsigned long __clk_get_flags(struct clk *clk); 791 unsigned long clk_hw_get_flags(const struct clk_hw *hw); 792 bool clk_hw_is_prepared(const struct clk_hw *hw); 793 bool clk_hw_rate_is_protected(const struct clk_hw *hw); 794 bool clk_hw_is_enabled(const struct clk_hw *hw); 795 bool __clk_is_enabled(struct clk *clk); 796 struct clk *__clk_lookup(const char *name); 797 int __clk_mux_determine_rate(struct clk_hw *hw, 798 struct clk_rate_request *req); 799 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req); 800 int __clk_mux_determine_rate_closest(struct clk_hw *hw, 801 struct clk_rate_request *req); 802 int clk_mux_determine_rate_flags(struct clk_hw *hw, 803 struct clk_rate_request *req, 804 unsigned long flags); 805 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent); 806 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, 807 unsigned long max_rate); 808 809 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src) 810 { 811 dst->clk = src->clk; 812 dst->core = src->core; 813 } 814 815 static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate, 816 unsigned long *prate, 817 const struct clk_div_table *table, 818 u8 width, unsigned long flags) 819 { 820 return divider_round_rate_parent(hw, clk_hw_get_parent(hw), 821 rate, prate, table, width, flags); 822 } 823 824 static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate, 825 unsigned long *prate, 826 const struct clk_div_table *table, 827 u8 width, unsigned long flags, 828 unsigned int val) 829 { 830 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw), 831 rate, prate, table, width, flags, 832 val); 833 } 834 835 /* 836 * FIXME clock api without lock protection 837 */ 838 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate); 839 840 struct of_device_id; 841 842 struct clk_onecell_data { 843 struct clk **clks; 844 unsigned int clk_num; 845 }; 846 847 struct clk_hw_onecell_data { 848 unsigned int num; 849 struct clk_hw *hws[]; 850 }; 851 852 extern struct of_device_id __clk_of_table; 853 854 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn) 855 856 /* 857 * Use this macro when you have a driver that requires two initialization 858 * routines, one at of_clk_init(), and one at platform device probe 859 */ 860 #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \ 861 static void __init name##_of_clk_init_driver(struct device_node *np) \ 862 { \ 863 of_node_clear_flag(np, OF_POPULATED); \ 864 fn(np); \ 865 } \ 866 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver) 867 868 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ 869 (&(struct clk_init_data) { \ 870 .flags = _flags, \ 871 .name = _name, \ 872 .parent_names = (const char *[]) { _parent }, \ 873 .num_parents = 1, \ 874 .ops = _ops, \ 875 }) 876 877 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ 878 (&(struct clk_init_data) { \ 879 .flags = _flags, \ 880 .name = _name, \ 881 .parent_names = _parents, \ 882 .num_parents = ARRAY_SIZE(_parents), \ 883 .ops = _ops, \ 884 }) 885 886 #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \ 887 (&(struct clk_init_data) { \ 888 .flags = _flags, \ 889 .name = _name, \ 890 .parent_names = NULL, \ 891 .num_parents = 0, \ 892 .ops = _ops, \ 893 }) 894 895 #define CLK_FIXED_FACTOR(_struct, _name, _parent, \ 896 _div, _mult, _flags) \ 897 struct clk_fixed_factor _struct = { \ 898 .div = _div, \ 899 .mult = _mult, \ 900 .hw.init = CLK_HW_INIT(_name, \ 901 _parent, \ 902 &clk_fixed_factor_ops, \ 903 _flags), \ 904 } 905 906 #ifdef CONFIG_OF 907 int of_clk_add_provider(struct device_node *np, 908 struct clk *(*clk_src_get)(struct of_phandle_args *args, 909 void *data), 910 void *data); 911 int of_clk_add_hw_provider(struct device_node *np, 912 struct clk_hw *(*get)(struct of_phandle_args *clkspec, 913 void *data), 914 void *data); 915 int devm_of_clk_add_hw_provider(struct device *dev, 916 struct clk_hw *(*get)(struct of_phandle_args *clkspec, 917 void *data), 918 void *data); 919 void of_clk_del_provider(struct device_node *np); 920 void devm_of_clk_del_provider(struct device *dev); 921 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, 922 void *data); 923 struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, 924 void *data); 925 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); 926 struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec, 927 void *data); 928 int of_clk_parent_fill(struct device_node *np, const char **parents, 929 unsigned int size); 930 int of_clk_detect_critical(struct device_node *np, int index, 931 unsigned long *flags); 932 933 #else /* !CONFIG_OF */ 934 935 static inline int of_clk_add_provider(struct device_node *np, 936 struct clk *(*clk_src_get)(struct of_phandle_args *args, 937 void *data), 938 void *data) 939 { 940 return 0; 941 } 942 static inline int of_clk_add_hw_provider(struct device_node *np, 943 struct clk_hw *(*get)(struct of_phandle_args *clkspec, 944 void *data), 945 void *data) 946 { 947 return 0; 948 } 949 static inline int devm_of_clk_add_hw_provider(struct device *dev, 950 struct clk_hw *(*get)(struct of_phandle_args *clkspec, 951 void *data), 952 void *data) 953 { 954 return 0; 955 } 956 static inline void of_clk_del_provider(struct device_node *np) {} 957 static inline void devm_of_clk_del_provider(struct device *dev) {} 958 static inline struct clk *of_clk_src_simple_get( 959 struct of_phandle_args *clkspec, void *data) 960 { 961 return ERR_PTR(-ENOENT); 962 } 963 static inline struct clk_hw * 964 of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data) 965 { 966 return ERR_PTR(-ENOENT); 967 } 968 static inline struct clk *of_clk_src_onecell_get( 969 struct of_phandle_args *clkspec, void *data) 970 { 971 return ERR_PTR(-ENOENT); 972 } 973 static inline struct clk_hw * 974 of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data) 975 { 976 return ERR_PTR(-ENOENT); 977 } 978 static inline int of_clk_parent_fill(struct device_node *np, 979 const char **parents, unsigned int size) 980 { 981 return 0; 982 } 983 static inline int of_clk_detect_critical(struct device_node *np, int index, 984 unsigned long *flags) 985 { 986 return 0; 987 } 988 #endif /* CONFIG_OF */ 989 990 /* 991 * wrap access to peripherals in accessor routines 992 * for improved portability across platforms 993 */ 994 995 #if IS_ENABLED(CONFIG_PPC) 996 997 static inline u32 clk_readl(u32 __iomem *reg) 998 { 999 return ioread32be(reg); 1000 } 1001 1002 static inline void clk_writel(u32 val, u32 __iomem *reg) 1003 { 1004 iowrite32be(val, reg); 1005 } 1006 1007 #else /* platform dependent I/O accessors */ 1008 1009 static inline u32 clk_readl(u32 __iomem *reg) 1010 { 1011 return readl(reg); 1012 } 1013 1014 static inline void clk_writel(u32 val, u32 __iomem *reg) 1015 { 1016 writel(val, reg); 1017 } 1018 1019 #endif /* platform dependent I/O accessors */ 1020 1021 void clk_gate_restore_context(struct clk_hw *hw); 1022 1023 #endif /* CONFIG_COMMON_CLK */ 1024 #endif /* CLK_PROVIDER_H */ 1025