1 /* 2 * linux/include/linux/clk-provider.h 3 * 4 * Copyright (c) 2010-2011 Jeremy Kerr <[email protected]> 5 * Copyright (C) 2011-2012 Linaro Ltd <[email protected]> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #ifndef __LINUX_CLK_PROVIDER_H 12 #define __LINUX_CLK_PROVIDER_H 13 14 #include <linux/io.h> 15 #include <linux/of.h> 16 17 #ifdef CONFIG_COMMON_CLK 18 19 /* 20 * flags used across common struct clk. these flags should only affect the 21 * top-level framework. custom flags for dealing with hardware specifics 22 * belong in struct clk_foo 23 */ 24 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ 25 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ 26 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ 27 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ 28 /* unused */ 29 #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ 30 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ 31 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ 32 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ 33 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ 34 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */ 35 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ 36 /* parents need enable during gate/ungate, set rate and re-parent */ 37 #define CLK_OPS_PARENT_ENABLE BIT(12) 38 39 struct clk; 40 struct clk_hw; 41 struct clk_core; 42 struct dentry; 43 44 /** 45 * struct clk_rate_request - Structure encoding the clk constraints that 46 * a clock user might require. 47 * 48 * @rate: Requested clock rate. This field will be adjusted by 49 * clock drivers according to hardware capabilities. 50 * @min_rate: Minimum rate imposed by clk users. 51 * @max_rate: Maximum rate imposed by clk users. 52 * @best_parent_rate: The best parent rate a parent can provide to fulfill the 53 * requested constraints. 54 * @best_parent_hw: The most appropriate parent clock that fulfills the 55 * requested constraints. 56 * 57 */ 58 struct clk_rate_request { 59 unsigned long rate; 60 unsigned long min_rate; 61 unsigned long max_rate; 62 unsigned long best_parent_rate; 63 struct clk_hw *best_parent_hw; 64 }; 65 66 /** 67 * struct clk_ops - Callback operations for hardware clocks; these are to 68 * be provided by the clock implementation, and will be called by drivers 69 * through the clk_* api. 70 * 71 * @prepare: Prepare the clock for enabling. This must not return until 72 * the clock is fully prepared, and it's safe to call clk_enable. 73 * This callback is intended to allow clock implementations to 74 * do any initialisation that may sleep. Called with 75 * prepare_lock held. 76 * 77 * @unprepare: Release the clock from its prepared state. This will typically 78 * undo any work done in the @prepare callback. Called with 79 * prepare_lock held. 80 * 81 * @is_prepared: Queries the hardware to determine if the clock is prepared. 82 * This function is allowed to sleep. Optional, if this op is not 83 * set then the prepare count will be used. 84 * 85 * @unprepare_unused: Unprepare the clock atomically. Only called from 86 * clk_disable_unused for prepare clocks with special needs. 87 * Called with prepare mutex held. This function may sleep. 88 * 89 * @enable: Enable the clock atomically. This must not return until the 90 * clock is generating a valid clock signal, usable by consumer 91 * devices. Called with enable_lock held. This function must not 92 * sleep. 93 * 94 * @disable: Disable the clock atomically. Called with enable_lock held. 95 * This function must not sleep. 96 * 97 * @is_enabled: Queries the hardware to determine if the clock is enabled. 98 * This function must not sleep. Optional, if this op is not 99 * set then the enable count will be used. 100 * 101 * @disable_unused: Disable the clock atomically. Only called from 102 * clk_disable_unused for gate clocks with special needs. 103 * Called with enable_lock held. This function must not 104 * sleep. 105 * 106 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The 107 * parent rate is an input parameter. It is up to the caller to 108 * ensure that the prepare_mutex is held across this call. 109 * Returns the calculated rate. Optional, but recommended - if 110 * this op is not set then clock rate will be initialized to 0. 111 * 112 * @round_rate: Given a target rate as input, returns the closest rate actually 113 * supported by the clock. The parent rate is an input/output 114 * parameter. 115 * 116 * @determine_rate: Given a target rate as input, returns the closest rate 117 * actually supported by the clock, and optionally the parent clock 118 * that should be used to provide the clock rate. 119 * 120 * @set_parent: Change the input source of this clock; for clocks with multiple 121 * possible parents specify a new parent by passing in the index 122 * as a u8 corresponding to the parent in either the .parent_names 123 * or .parents arrays. This function in affect translates an 124 * array index into the value programmed into the hardware. 125 * Returns 0 on success, -EERROR otherwise. 126 * 127 * @get_parent: Queries the hardware to determine the parent of a clock. The 128 * return value is a u8 which specifies the index corresponding to 129 * the parent clock. This index can be applied to either the 130 * .parent_names or .parents arrays. In short, this function 131 * translates the parent value read from hardware into an array 132 * index. Currently only called when the clock is initialized by 133 * __clk_init. This callback is mandatory for clocks with 134 * multiple parents. It is optional (and unnecessary) for clocks 135 * with 0 or 1 parents. 136 * 137 * @set_rate: Change the rate of this clock. The requested rate is specified 138 * by the second argument, which should typically be the return 139 * of .round_rate call. The third argument gives the parent rate 140 * which is likely helpful for most .set_rate implementation. 141 * Returns 0 on success, -EERROR otherwise. 142 * 143 * @set_rate_and_parent: Change the rate and the parent of this clock. The 144 * requested rate is specified by the second argument, which 145 * should typically be the return of .round_rate call. The 146 * third argument gives the parent rate which is likely helpful 147 * for most .set_rate_and_parent implementation. The fourth 148 * argument gives the parent index. This callback is optional (and 149 * unnecessary) for clocks with 0 or 1 parents as well as 150 * for clocks that can tolerate switching the rate and the parent 151 * separately via calls to .set_parent and .set_rate. 152 * Returns 0 on success, -EERROR otherwise. 153 * 154 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy 155 * is expressed in ppb (parts per billion). The parent accuracy is 156 * an input parameter. 157 * Returns the calculated accuracy. Optional - if this op is not 158 * set then clock accuracy will be initialized to parent accuracy 159 * or 0 (perfect clock) if clock has no parent. 160 * 161 * @get_phase: Queries the hardware to get the current phase of a clock. 162 * Returned values are 0-359 degrees on success, negative 163 * error codes on failure. 164 * 165 * @set_phase: Shift the phase this clock signal in degrees specified 166 * by the second argument. Valid values for degrees are 167 * 0-359. Return 0 on success, otherwise -EERROR. 168 * 169 * @init: Perform platform-specific initialization magic. 170 * This is not not used by any of the basic clock types. 171 * Please consider other ways of solving initialization problems 172 * before using this callback, as its use is discouraged. 173 * 174 * @debug_init: Set up type-specific debugfs entries for this clock. This 175 * is called once, after the debugfs directory entry for this 176 * clock has been created. The dentry pointer representing that 177 * directory is provided as an argument. Called with 178 * prepare_lock held. Returns 0 on success, -EERROR otherwise. 179 * 180 * 181 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow 182 * implementations to split any work between atomic (enable) and sleepable 183 * (prepare) contexts. If enabling a clock requires code that might sleep, 184 * this must be done in clk_prepare. Clock enable code that will never be 185 * called in a sleepable context may be implemented in clk_enable. 186 * 187 * Typically, drivers will call clk_prepare when a clock may be needed later 188 * (eg. when a device is opened), and clk_enable when the clock is actually 189 * required (eg. from an interrupt). Note that clk_prepare MUST have been 190 * called before clk_enable. 191 */ 192 struct clk_ops { 193 int (*prepare)(struct clk_hw *hw); 194 void (*unprepare)(struct clk_hw *hw); 195 int (*is_prepared)(struct clk_hw *hw); 196 void (*unprepare_unused)(struct clk_hw *hw); 197 int (*enable)(struct clk_hw *hw); 198 void (*disable)(struct clk_hw *hw); 199 int (*is_enabled)(struct clk_hw *hw); 200 void (*disable_unused)(struct clk_hw *hw); 201 unsigned long (*recalc_rate)(struct clk_hw *hw, 202 unsigned long parent_rate); 203 long (*round_rate)(struct clk_hw *hw, unsigned long rate, 204 unsigned long *parent_rate); 205 int (*determine_rate)(struct clk_hw *hw, 206 struct clk_rate_request *req); 207 int (*set_parent)(struct clk_hw *hw, u8 index); 208 u8 (*get_parent)(struct clk_hw *hw); 209 int (*set_rate)(struct clk_hw *hw, unsigned long rate, 210 unsigned long parent_rate); 211 int (*set_rate_and_parent)(struct clk_hw *hw, 212 unsigned long rate, 213 unsigned long parent_rate, u8 index); 214 unsigned long (*recalc_accuracy)(struct clk_hw *hw, 215 unsigned long parent_accuracy); 216 int (*get_phase)(struct clk_hw *hw); 217 int (*set_phase)(struct clk_hw *hw, int degrees); 218 void (*init)(struct clk_hw *hw); 219 int (*debug_init)(struct clk_hw *hw, struct dentry *dentry); 220 }; 221 222 /** 223 * struct clk_init_data - holds init data that's common to all clocks and is 224 * shared between the clock provider and the common clock framework. 225 * 226 * @name: clock name 227 * @ops: operations this clock supports 228 * @parent_names: array of string names for all possible parents 229 * @num_parents: number of possible parents 230 * @flags: framework-level hints and quirks 231 */ 232 struct clk_init_data { 233 const char *name; 234 const struct clk_ops *ops; 235 const char * const *parent_names; 236 u8 num_parents; 237 unsigned long flags; 238 }; 239 240 /** 241 * struct clk_hw - handle for traversing from a struct clk to its corresponding 242 * hardware-specific structure. struct clk_hw should be declared within struct 243 * clk_foo and then referenced by the struct clk instance that uses struct 244 * clk_foo's clk_ops 245 * 246 * @core: pointer to the struct clk_core instance that points back to this 247 * struct clk_hw instance 248 * 249 * @clk: pointer to the per-user struct clk instance that can be used to call 250 * into the clk API 251 * 252 * @init: pointer to struct clk_init_data that contains the init data shared 253 * with the common clock framework. 254 */ 255 struct clk_hw { 256 struct clk_core *core; 257 struct clk *clk; 258 const struct clk_init_data *init; 259 }; 260 261 /* 262 * DOC: Basic clock implementations common to many platforms 263 * 264 * Each basic clock hardware type is comprised of a structure describing the 265 * clock hardware, implementations of the relevant callbacks in struct clk_ops, 266 * unique flags for that hardware type, a registration function and an 267 * alternative macro for static initialization 268 */ 269 270 /** 271 * struct clk_fixed_rate - fixed-rate clock 272 * @hw: handle between common and hardware-specific interfaces 273 * @fixed_rate: constant frequency of clock 274 */ 275 struct clk_fixed_rate { 276 struct clk_hw hw; 277 unsigned long fixed_rate; 278 unsigned long fixed_accuracy; 279 u8 flags; 280 }; 281 282 #define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw) 283 284 extern const struct clk_ops clk_fixed_rate_ops; 285 struct clk *clk_register_fixed_rate(struct device *dev, const char *name, 286 const char *parent_name, unsigned long flags, 287 unsigned long fixed_rate); 288 struct clk_hw *clk_hw_register_fixed_rate(struct device *dev, const char *name, 289 const char *parent_name, unsigned long flags, 290 unsigned long fixed_rate); 291 struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, 292 const char *name, const char *parent_name, unsigned long flags, 293 unsigned long fixed_rate, unsigned long fixed_accuracy); 294 void clk_unregister_fixed_rate(struct clk *clk); 295 struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev, 296 const char *name, const char *parent_name, unsigned long flags, 297 unsigned long fixed_rate, unsigned long fixed_accuracy); 298 void clk_hw_unregister_fixed_rate(struct clk_hw *hw); 299 300 void of_fixed_clk_setup(struct device_node *np); 301 302 /** 303 * struct clk_gate - gating clock 304 * 305 * @hw: handle between common and hardware-specific interfaces 306 * @reg: register controlling gate 307 * @bit_idx: single bit controlling gate 308 * @flags: hardware-specific flags 309 * @lock: register lock 310 * 311 * Clock which can gate its output. Implements .enable & .disable 312 * 313 * Flags: 314 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to 315 * enable the clock. Setting this flag does the opposite: setting the bit 316 * disable the clock and clearing it enables the clock 317 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit 318 * of this register, and mask of gate bits are in higher 16-bit of this 319 * register. While setting the gate bits, higher 16-bit should also be 320 * updated to indicate changing gate bits. 321 */ 322 struct clk_gate { 323 struct clk_hw hw; 324 void __iomem *reg; 325 u8 bit_idx; 326 u8 flags; 327 spinlock_t *lock; 328 }; 329 330 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) 331 332 #define CLK_GATE_SET_TO_DISABLE BIT(0) 333 #define CLK_GATE_HIWORD_MASK BIT(1) 334 335 extern const struct clk_ops clk_gate_ops; 336 struct clk *clk_register_gate(struct device *dev, const char *name, 337 const char *parent_name, unsigned long flags, 338 void __iomem *reg, u8 bit_idx, 339 u8 clk_gate_flags, spinlock_t *lock); 340 struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name, 341 const char *parent_name, unsigned long flags, 342 void __iomem *reg, u8 bit_idx, 343 u8 clk_gate_flags, spinlock_t *lock); 344 void clk_unregister_gate(struct clk *clk); 345 void clk_hw_unregister_gate(struct clk_hw *hw); 346 347 struct clk_div_table { 348 unsigned int val; 349 unsigned int div; 350 }; 351 352 /** 353 * struct clk_divider - adjustable divider clock 354 * 355 * @hw: handle between common and hardware-specific interfaces 356 * @reg: register containing the divider 357 * @shift: shift to the divider bit field 358 * @width: width of the divider bit field 359 * @table: array of value/divider pairs, last entry should have div = 0 360 * @lock: register lock 361 * 362 * Clock with an adjustable divider affecting its output frequency. Implements 363 * .recalc_rate, .set_rate and .round_rate 364 * 365 * Flags: 366 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the 367 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is 368 * the raw value read from the register, with the value of zero considered 369 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. 370 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from 371 * the hardware register 372 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have 373 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. 374 * Some hardware implementations gracefully handle this case and allow a 375 * zero divisor by not modifying their input clock 376 * (divide by one / bypass). 377 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit 378 * of this register, and mask of divider bits are in higher 16-bit of this 379 * register. While setting the divider bits, higher 16-bit should also be 380 * updated to indicate changing divider bits. 381 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded 382 * to the closest integer instead of the up one. 383 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should 384 * not be changed by the clock framework. 385 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED 386 * except when the value read from the register is zero, the divisor is 387 * 2^width of the field. 388 */ 389 struct clk_divider { 390 struct clk_hw hw; 391 void __iomem *reg; 392 u8 shift; 393 u8 width; 394 u8 flags; 395 const struct clk_div_table *table; 396 spinlock_t *lock; 397 }; 398 399 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) 400 401 #define CLK_DIVIDER_ONE_BASED BIT(0) 402 #define CLK_DIVIDER_POWER_OF_TWO BIT(1) 403 #define CLK_DIVIDER_ALLOW_ZERO BIT(2) 404 #define CLK_DIVIDER_HIWORD_MASK BIT(3) 405 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) 406 #define CLK_DIVIDER_READ_ONLY BIT(5) 407 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) 408 409 extern const struct clk_ops clk_divider_ops; 410 extern const struct clk_ops clk_divider_ro_ops; 411 412 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, 413 unsigned int val, const struct clk_div_table *table, 414 unsigned long flags); 415 long divider_round_rate(struct clk_hw *hw, unsigned long rate, 416 unsigned long *prate, const struct clk_div_table *table, 417 u8 width, unsigned long flags); 418 int divider_get_val(unsigned long rate, unsigned long parent_rate, 419 const struct clk_div_table *table, u8 width, 420 unsigned long flags); 421 422 struct clk *clk_register_divider(struct device *dev, const char *name, 423 const char *parent_name, unsigned long flags, 424 void __iomem *reg, u8 shift, u8 width, 425 u8 clk_divider_flags, spinlock_t *lock); 426 struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name, 427 const char *parent_name, unsigned long flags, 428 void __iomem *reg, u8 shift, u8 width, 429 u8 clk_divider_flags, spinlock_t *lock); 430 struct clk *clk_register_divider_table(struct device *dev, const char *name, 431 const char *parent_name, unsigned long flags, 432 void __iomem *reg, u8 shift, u8 width, 433 u8 clk_divider_flags, const struct clk_div_table *table, 434 spinlock_t *lock); 435 struct clk_hw *clk_hw_register_divider_table(struct device *dev, 436 const char *name, const char *parent_name, unsigned long flags, 437 void __iomem *reg, u8 shift, u8 width, 438 u8 clk_divider_flags, const struct clk_div_table *table, 439 spinlock_t *lock); 440 void clk_unregister_divider(struct clk *clk); 441 void clk_hw_unregister_divider(struct clk_hw *hw); 442 443 /** 444 * struct clk_mux - multiplexer clock 445 * 446 * @hw: handle between common and hardware-specific interfaces 447 * @reg: register controlling multiplexer 448 * @shift: shift to multiplexer bit field 449 * @width: width of mutliplexer bit field 450 * @flags: hardware-specific flags 451 * @lock: register lock 452 * 453 * Clock with multiple selectable parents. Implements .get_parent, .set_parent 454 * and .recalc_rate 455 * 456 * Flags: 457 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 458 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) 459 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this 460 * register, and mask of mux bits are in higher 16-bit of this register. 461 * While setting the mux bits, higher 16-bit should also be updated to 462 * indicate changing mux bits. 463 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired 464 * frequency. 465 */ 466 struct clk_mux { 467 struct clk_hw hw; 468 void __iomem *reg; 469 u32 *table; 470 u32 mask; 471 u8 shift; 472 u8 flags; 473 spinlock_t *lock; 474 }; 475 476 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) 477 478 #define CLK_MUX_INDEX_ONE BIT(0) 479 #define CLK_MUX_INDEX_BIT BIT(1) 480 #define CLK_MUX_HIWORD_MASK BIT(2) 481 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ 482 #define CLK_MUX_ROUND_CLOSEST BIT(4) 483 484 extern const struct clk_ops clk_mux_ops; 485 extern const struct clk_ops clk_mux_ro_ops; 486 487 struct clk *clk_register_mux(struct device *dev, const char *name, 488 const char * const *parent_names, u8 num_parents, 489 unsigned long flags, 490 void __iomem *reg, u8 shift, u8 width, 491 u8 clk_mux_flags, spinlock_t *lock); 492 struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name, 493 const char * const *parent_names, u8 num_parents, 494 unsigned long flags, 495 void __iomem *reg, u8 shift, u8 width, 496 u8 clk_mux_flags, spinlock_t *lock); 497 498 struct clk *clk_register_mux_table(struct device *dev, const char *name, 499 const char * const *parent_names, u8 num_parents, 500 unsigned long flags, 501 void __iomem *reg, u8 shift, u32 mask, 502 u8 clk_mux_flags, u32 *table, spinlock_t *lock); 503 struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name, 504 const char * const *parent_names, u8 num_parents, 505 unsigned long flags, 506 void __iomem *reg, u8 shift, u32 mask, 507 u8 clk_mux_flags, u32 *table, spinlock_t *lock); 508 509 void clk_unregister_mux(struct clk *clk); 510 void clk_hw_unregister_mux(struct clk_hw *hw); 511 512 void of_fixed_factor_clk_setup(struct device_node *node); 513 514 /** 515 * struct clk_fixed_factor - fixed multiplier and divider clock 516 * 517 * @hw: handle between common and hardware-specific interfaces 518 * @mult: multiplier 519 * @div: divider 520 * 521 * Clock with a fixed multiplier and divider. The output frequency is the 522 * parent clock rate divided by div and multiplied by mult. 523 * Implements .recalc_rate, .set_rate and .round_rate 524 */ 525 526 struct clk_fixed_factor { 527 struct clk_hw hw; 528 unsigned int mult; 529 unsigned int div; 530 }; 531 532 #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw) 533 534 extern const struct clk_ops clk_fixed_factor_ops; 535 struct clk *clk_register_fixed_factor(struct device *dev, const char *name, 536 const char *parent_name, unsigned long flags, 537 unsigned int mult, unsigned int div); 538 void clk_unregister_fixed_factor(struct clk *clk); 539 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, 540 const char *name, const char *parent_name, unsigned long flags, 541 unsigned int mult, unsigned int div); 542 void clk_hw_unregister_fixed_factor(struct clk_hw *hw); 543 544 /** 545 * struct clk_fractional_divider - adjustable fractional divider clock 546 * 547 * @hw: handle between common and hardware-specific interfaces 548 * @reg: register containing the divider 549 * @mshift: shift to the numerator bit field 550 * @mwidth: width of the numerator bit field 551 * @nshift: shift to the denominator bit field 552 * @nwidth: width of the denominator bit field 553 * @lock: register lock 554 * 555 * Clock with adjustable fractional divider affecting its output frequency. 556 */ 557 struct clk_fractional_divider { 558 struct clk_hw hw; 559 void __iomem *reg; 560 u8 mshift; 561 u8 mwidth; 562 u32 mmask; 563 u8 nshift; 564 u8 nwidth; 565 u32 nmask; 566 u8 flags; 567 spinlock_t *lock; 568 }; 569 570 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) 571 572 extern const struct clk_ops clk_fractional_divider_ops; 573 struct clk *clk_register_fractional_divider(struct device *dev, 574 const char *name, const char *parent_name, unsigned long flags, 575 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, 576 u8 clk_divider_flags, spinlock_t *lock); 577 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, 578 const char *name, const char *parent_name, unsigned long flags, 579 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, 580 u8 clk_divider_flags, spinlock_t *lock); 581 void clk_hw_unregister_fractional_divider(struct clk_hw *hw); 582 583 /** 584 * struct clk_multiplier - adjustable multiplier clock 585 * 586 * @hw: handle between common and hardware-specific interfaces 587 * @reg: register containing the multiplier 588 * @shift: shift to the multiplier bit field 589 * @width: width of the multiplier bit field 590 * @lock: register lock 591 * 592 * Clock with an adjustable multiplier affecting its output frequency. 593 * Implements .recalc_rate, .set_rate and .round_rate 594 * 595 * Flags: 596 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read 597 * from the register, with 0 being a valid value effectively 598 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is 599 * set, then a null multiplier will be considered as a bypass, 600 * leaving the parent rate unmodified. 601 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be 602 * rounded to the closest integer instead of the down one. 603 */ 604 struct clk_multiplier { 605 struct clk_hw hw; 606 void __iomem *reg; 607 u8 shift; 608 u8 width; 609 u8 flags; 610 spinlock_t *lock; 611 }; 612 613 #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw) 614 615 #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0) 616 #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1) 617 618 extern const struct clk_ops clk_multiplier_ops; 619 620 /*** 621 * struct clk_composite - aggregate clock of mux, divider and gate clocks 622 * 623 * @hw: handle between common and hardware-specific interfaces 624 * @mux_hw: handle between composite and hardware-specific mux clock 625 * @rate_hw: handle between composite and hardware-specific rate clock 626 * @gate_hw: handle between composite and hardware-specific gate clock 627 * @mux_ops: clock ops for mux 628 * @rate_ops: clock ops for rate 629 * @gate_ops: clock ops for gate 630 */ 631 struct clk_composite { 632 struct clk_hw hw; 633 struct clk_ops ops; 634 635 struct clk_hw *mux_hw; 636 struct clk_hw *rate_hw; 637 struct clk_hw *gate_hw; 638 639 const struct clk_ops *mux_ops; 640 const struct clk_ops *rate_ops; 641 const struct clk_ops *gate_ops; 642 }; 643 644 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) 645 646 struct clk *clk_register_composite(struct device *dev, const char *name, 647 const char * const *parent_names, int num_parents, 648 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 649 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 650 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 651 unsigned long flags); 652 void clk_unregister_composite(struct clk *clk); 653 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name, 654 const char * const *parent_names, int num_parents, 655 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 656 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 657 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 658 unsigned long flags); 659 void clk_hw_unregister_composite(struct clk_hw *hw); 660 661 /*** 662 * struct clk_gpio_gate - gpio gated clock 663 * 664 * @hw: handle between common and hardware-specific interfaces 665 * @gpiod: gpio descriptor 666 * 667 * Clock with a gpio control for enabling and disabling the parent clock. 668 * Implements .enable, .disable and .is_enabled 669 */ 670 671 struct clk_gpio { 672 struct clk_hw hw; 673 struct gpio_desc *gpiod; 674 }; 675 676 #define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw) 677 678 extern const struct clk_ops clk_gpio_gate_ops; 679 struct clk *clk_register_gpio_gate(struct device *dev, const char *name, 680 const char *parent_name, unsigned gpio, bool active_low, 681 unsigned long flags); 682 struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name, 683 const char *parent_name, unsigned gpio, bool active_low, 684 unsigned long flags); 685 void clk_hw_unregister_gpio_gate(struct clk_hw *hw); 686 687 /** 688 * struct clk_gpio_mux - gpio controlled clock multiplexer 689 * 690 * @hw: see struct clk_gpio 691 * @gpiod: gpio descriptor to select the parent of this clock multiplexer 692 * 693 * Clock with a gpio control for selecting the parent clock. 694 * Implements .get_parent, .set_parent and .determine_rate 695 */ 696 697 extern const struct clk_ops clk_gpio_mux_ops; 698 struct clk *clk_register_gpio_mux(struct device *dev, const char *name, 699 const char * const *parent_names, u8 num_parents, unsigned gpio, 700 bool active_low, unsigned long flags); 701 struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name, 702 const char * const *parent_names, u8 num_parents, unsigned gpio, 703 bool active_low, unsigned long flags); 704 void clk_hw_unregister_gpio_mux(struct clk_hw *hw); 705 706 /** 707 * clk_register - allocate a new clock, register it and return an opaque cookie 708 * @dev: device that is registering this clock 709 * @hw: link to hardware-specific clock data 710 * 711 * clk_register is the primary interface for populating the clock tree with new 712 * clock nodes. It returns a pointer to the newly allocated struct clk which 713 * cannot be dereferenced by driver code but may be used in conjuction with the 714 * rest of the clock API. In the event of an error clk_register will return an 715 * error code; drivers must test for an error code after calling clk_register. 716 */ 717 struct clk *clk_register(struct device *dev, struct clk_hw *hw); 718 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); 719 720 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw); 721 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw); 722 723 void clk_unregister(struct clk *clk); 724 void devm_clk_unregister(struct device *dev, struct clk *clk); 725 726 void clk_hw_unregister(struct clk_hw *hw); 727 void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw); 728 729 /* helper functions */ 730 const char *__clk_get_name(const struct clk *clk); 731 const char *clk_hw_get_name(const struct clk_hw *hw); 732 struct clk_hw *__clk_get_hw(struct clk *clk); 733 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); 734 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); 735 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, 736 unsigned int index); 737 unsigned int __clk_get_enable_count(struct clk *clk); 738 unsigned long clk_hw_get_rate(const struct clk_hw *hw); 739 unsigned long __clk_get_flags(struct clk *clk); 740 unsigned long clk_hw_get_flags(const struct clk_hw *hw); 741 bool clk_hw_is_prepared(const struct clk_hw *hw); 742 bool clk_hw_is_enabled(const struct clk_hw *hw); 743 bool __clk_is_enabled(struct clk *clk); 744 struct clk *__clk_lookup(const char *name); 745 int __clk_mux_determine_rate(struct clk_hw *hw, 746 struct clk_rate_request *req); 747 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req); 748 int __clk_mux_determine_rate_closest(struct clk_hw *hw, 749 struct clk_rate_request *req); 750 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent); 751 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, 752 unsigned long max_rate); 753 754 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src) 755 { 756 dst->clk = src->clk; 757 dst->core = src->core; 758 } 759 760 /* 761 * FIXME clock api without lock protection 762 */ 763 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate); 764 765 struct of_device_id; 766 767 typedef void (*of_clk_init_cb_t)(struct device_node *); 768 769 struct clk_onecell_data { 770 struct clk **clks; 771 unsigned int clk_num; 772 }; 773 774 struct clk_hw_onecell_data { 775 unsigned int num; 776 struct clk_hw *hws[]; 777 }; 778 779 extern struct of_device_id __clk_of_table; 780 781 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn) 782 783 /* 784 * Use this macro when you have a driver that requires two initialization 785 * routines, one at of_clk_init(), and one at platform device probe 786 */ 787 #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \ 788 static void __init name##_of_clk_init_driver(struct device_node *np) \ 789 { \ 790 of_node_clear_flag(np, OF_POPULATED); \ 791 fn(np); \ 792 } \ 793 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver) 794 795 #ifdef CONFIG_OF 796 int of_clk_add_provider(struct device_node *np, 797 struct clk *(*clk_src_get)(struct of_phandle_args *args, 798 void *data), 799 void *data); 800 int of_clk_add_hw_provider(struct device_node *np, 801 struct clk_hw *(*get)(struct of_phandle_args *clkspec, 802 void *data), 803 void *data); 804 void of_clk_del_provider(struct device_node *np); 805 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, 806 void *data); 807 struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, 808 void *data); 809 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); 810 struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec, 811 void *data); 812 unsigned int of_clk_get_parent_count(struct device_node *np); 813 int of_clk_parent_fill(struct device_node *np, const char **parents, 814 unsigned int size); 815 const char *of_clk_get_parent_name(struct device_node *np, int index); 816 int of_clk_detect_critical(struct device_node *np, int index, 817 unsigned long *flags); 818 void of_clk_init(const struct of_device_id *matches); 819 820 #else /* !CONFIG_OF */ 821 822 static inline int of_clk_add_provider(struct device_node *np, 823 struct clk *(*clk_src_get)(struct of_phandle_args *args, 824 void *data), 825 void *data) 826 { 827 return 0; 828 } 829 static inline int of_clk_add_hw_provider(struct device_node *np, 830 struct clk_hw *(*get)(struct of_phandle_args *clkspec, 831 void *data), 832 void *data) 833 { 834 return 0; 835 } 836 static inline void of_clk_del_provider(struct device_node *np) {} 837 static inline struct clk *of_clk_src_simple_get( 838 struct of_phandle_args *clkspec, void *data) 839 { 840 return ERR_PTR(-ENOENT); 841 } 842 static inline struct clk_hw * 843 of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data) 844 { 845 return ERR_PTR(-ENOENT); 846 } 847 static inline struct clk *of_clk_src_onecell_get( 848 struct of_phandle_args *clkspec, void *data) 849 { 850 return ERR_PTR(-ENOENT); 851 } 852 static inline struct clk_hw * 853 of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data) 854 { 855 return ERR_PTR(-ENOENT); 856 } 857 static inline unsigned int of_clk_get_parent_count(struct device_node *np) 858 { 859 return 0; 860 } 861 static inline int of_clk_parent_fill(struct device_node *np, 862 const char **parents, unsigned int size) 863 { 864 return 0; 865 } 866 static inline const char *of_clk_get_parent_name(struct device_node *np, 867 int index) 868 { 869 return NULL; 870 } 871 static inline int of_clk_detect_critical(struct device_node *np, int index, 872 unsigned long *flags) 873 { 874 return 0; 875 } 876 static inline void of_clk_init(const struct of_device_id *matches) {} 877 #endif /* CONFIG_OF */ 878 879 /* 880 * wrap access to peripherals in accessor routines 881 * for improved portability across platforms 882 */ 883 884 #if IS_ENABLED(CONFIG_PPC) 885 886 static inline u32 clk_readl(u32 __iomem *reg) 887 { 888 return ioread32be(reg); 889 } 890 891 static inline void clk_writel(u32 val, u32 __iomem *reg) 892 { 893 iowrite32be(val, reg); 894 } 895 896 #else /* platform dependent I/O accessors */ 897 898 static inline u32 clk_readl(u32 __iomem *reg) 899 { 900 return readl(reg); 901 } 902 903 static inline void clk_writel(u32 val, u32 __iomem *reg) 904 { 905 writel(val, reg); 906 } 907 908 #endif /* platform dependent I/O accessors */ 909 910 #ifdef CONFIG_DEBUG_FS 911 struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode, 912 void *data, const struct file_operations *fops); 913 #endif 914 915 #endif /* CONFIG_COMMON_CLK */ 916 #endif /* CLK_PROVIDER_H */ 917