1# SPDX-License-Identifier: GPL-2.0-only 2config ARCH_HAS_RESET_CONTROLLER 3 bool 4 5menuconfig RESET_CONTROLLER 6 bool "Reset Controller Support" 7 default y if ARCH_HAS_RESET_CONTROLLER 8 help 9 Generic Reset Controller support. 10 11 This framework is designed to abstract reset handling of devices 12 via GPIOs or SoC-internal reset controller modules. 13 14 If unsure, say no. 15 16if RESET_CONTROLLER 17 18config RESET_A10SR 19 tristate "Altera Arria10 System Resource Reset" 20 depends on MFD_ALTERA_A10SR || COMPILE_TEST 21 help 22 This option enables support for the external reset functions for 23 peripheral PHYs on the Altera Arria10 System Resource Chip. 24 25config RESET_ATH79 26 bool "AR71xx Reset Driver" if COMPILE_TEST 27 default ATH79 28 help 29 This enables the ATH79 reset controller driver that supports the 30 AR71xx SoC reset controller. 31 32config RESET_AXS10X 33 bool "AXS10x Reset Driver" if COMPILE_TEST 34 default ARC_PLAT_AXS10X 35 help 36 This enables the reset controller driver for AXS10x. 37 38config RESET_BCM6345 39 bool "BCM6345 Reset Controller" 40 depends on BMIPS_GENERIC || COMPILE_TEST 41 default BMIPS_GENERIC 42 help 43 This enables the reset controller driver for BCM6345 SoCs. 44 45config RESET_BERLIN 46 tristate "Berlin Reset Driver" 47 depends on ARCH_BERLIN || COMPILE_TEST 48 default m if ARCH_BERLIN 49 help 50 This enables the reset controller driver for Marvell Berlin SoCs. 51 52config RESET_BRCMSTB 53 tristate "Broadcom STB reset controller" 54 depends on ARCH_BRCMSTB || COMPILE_TEST 55 default ARCH_BRCMSTB 56 help 57 This enables the reset controller driver for Broadcom STB SoCs using 58 a SUN_TOP_CTRL_SW_INIT style controller. 59 60config RESET_BRCMSTB_RESCAL 61 tristate "Broadcom STB RESCAL reset controller" 62 depends on HAS_IOMEM 63 depends on ARCH_BRCMSTB || COMPILE_TEST 64 default ARCH_BRCMSTB 65 help 66 This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on 67 BCM7216. 68 69config RESET_GPIO 70 tristate "GPIO reset controller" 71 help 72 This enables a generic reset controller for resets attached via 73 GPIOs. Typically for OF platforms this driver expects "reset-gpios" 74 property. 75 76 If compiled as module, it will be called reset-gpio. 77 78config RESET_HSDK 79 bool "Synopsys HSDK Reset Driver" 80 depends on HAS_IOMEM 81 depends on ARC_SOC_HSDK || COMPILE_TEST 82 help 83 This enables the reset controller driver for HSDK board. 84 85config RESET_IMX7 86 tristate "i.MX7/8 Reset Driver" 87 depends on HAS_IOMEM 88 depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST 89 default y if SOC_IMX7D 90 select MFD_SYSCON 91 help 92 This enables the reset controller driver for i.MX7 SoCs. 93 94config RESET_IMX8MP_AUDIOMIX 95 tristate "i.MX8MP AudioMix Reset Driver" 96 select AUXILIARY_BUS 97 default CLK_IMX8MP 98 help 99 This enables the reset controller driver for i.MX8MP AudioMix 100 101config RESET_INTEL_GW 102 bool "Intel Reset Controller Driver" 103 depends on X86 || COMPILE_TEST 104 depends on OF && HAS_IOMEM 105 select REGMAP_MMIO 106 help 107 This enables the reset controller driver for Intel Gateway SoCs. 108 Say Y to control the reset signals provided by reset controller. 109 Otherwise, say N. 110 111config RESET_K210 112 bool "Reset controller driver for Canaan Kendryte K210 SoC" 113 depends on (SOC_CANAAN_K210 || COMPILE_TEST) && OF 114 select MFD_SYSCON 115 default SOC_CANAAN_K210 116 help 117 Support for the Canaan Kendryte K210 RISC-V SoC reset controller. 118 Say Y if you want to control reset signals provided by this 119 controller. 120 121config RESET_LANTIQ 122 bool "Lantiq XWAY Reset Driver" if COMPILE_TEST 123 default SOC_TYPE_XWAY 124 help 125 This enables the reset controller driver for Lantiq / Intel XWAY SoCs. 126 127config RESET_LPC18XX 128 bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST 129 default ARCH_LPC18XX 130 help 131 This enables the reset controller driver for NXP LPC18xx/43xx SoCs. 132 133config RESET_MCHP_SPARX5 134 bool "Microchip Sparx5 reset driver" 135 depends on ARCH_SPARX5 || SOC_LAN966 || COMPILE_TEST 136 default y if SPARX5_SWITCH 137 select MFD_SYSCON 138 help 139 This driver supports switch core reset for the Microchip Sparx5 SoC. 140 141config RESET_MESON 142 tristate "Meson Reset Driver" 143 depends on ARCH_MESON || COMPILE_TEST 144 default ARCH_MESON 145 help 146 This enables the reset driver for Amlogic Meson SoCs. 147 148config RESET_MESON_AUDIO_ARB 149 tristate "Meson Audio Memory Arbiter Reset Driver" 150 depends on ARCH_MESON || COMPILE_TEST 151 help 152 This enables the reset driver for Audio Memory Arbiter of 153 Amlogic's A113 based SoCs 154 155config RESET_NPCM 156 bool "NPCM BMC Reset Driver" if COMPILE_TEST 157 default ARCH_NPCM 158 help 159 This enables the reset controller driver for Nuvoton NPCM 160 BMC SoCs. 161 162config RESET_NUVOTON_MA35D1 163 bool "Nuvoton MA35D1 Reset Driver" 164 depends on ARCH_MA35 || COMPILE_TEST 165 default ARCH_MA35 166 help 167 This enables the reset controller driver for Nuvoton MA35D1 SoC. 168 169config RESET_PISTACHIO 170 bool "Pistachio Reset Driver" 171 depends on MIPS || COMPILE_TEST 172 help 173 This enables the reset driver for ImgTec Pistachio SoCs. 174 175config RESET_POLARFIRE_SOC 176 bool "Microchip PolarFire SoC (MPFS) Reset Driver" 177 depends on MCHP_CLK_MPFS 178 select AUXILIARY_BUS 179 default MCHP_CLK_MPFS 180 help 181 This driver supports peripheral reset for the Microchip PolarFire SoC 182 183config RESET_QCOM_AOSS 184 tristate "Qcom AOSS Reset Driver" 185 depends on ARCH_QCOM || COMPILE_TEST 186 help 187 This enables the AOSS (always on subsystem) reset driver 188 for Qualcomm SDM845 SoCs. Say Y if you want to control 189 reset signals provided by AOSS for Modem, Venus, ADSP, 190 GPU, Camera, Wireless, Display subsystem. Otherwise, say N. 191 192config RESET_QCOM_PDC 193 tristate "Qualcomm PDC Reset Driver" 194 depends on ARCH_QCOM || COMPILE_TEST 195 help 196 This enables the PDC (Power Domain Controller) reset driver 197 for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want 198 to control reset signals provided by PDC for Modem, Compute, 199 Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS. 200 201config RESET_RASPBERRYPI 202 tristate "Raspberry Pi 4 Firmware Reset Driver" 203 depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST) 204 default USB_XHCI_PCI 205 help 206 Raspberry Pi 4's co-processor controls some of the board's HW 207 initialization process, but it's up to Linux to trigger it when 208 relevant. This driver provides a reset controller capable of 209 interfacing with RPi4's co-processor and model these firmware 210 initialization routines as reset lines. 211 212config RESET_RZG2L_USBPHY_CTRL 213 tristate "Renesas RZ/G2L USBPHY control driver" 214 depends on ARCH_RZG2L || COMPILE_TEST 215 help 216 Support for USBPHY Control found on RZ/G2L family. It mainly 217 controls reset and power down of the USB/PHY. 218 219config RESET_SCMI 220 tristate "Reset driver controlled via ARM SCMI interface" 221 depends on ARM_SCMI_PROTOCOL || COMPILE_TEST 222 default ARM_SCMI_PROTOCOL 223 help 224 This driver provides support for reset signal/domains that are 225 controlled by firmware that implements the SCMI interface. 226 227 This driver uses SCMI Message Protocol to interact with the 228 firmware controlling all the reset signals. 229 230config RESET_SIMPLE 231 bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT 232 default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC 233 depends on HAS_IOMEM 234 help 235 This enables a simple reset controller driver for reset lines that 236 that can be asserted and deasserted by toggling bits in a contiguous, 237 exclusive register space. 238 239 Currently this driver supports: 240 - Altera SoCFPGAs 241 - ASPEED BMC SoCs 242 - Bitmain BM1880 SoC 243 - Realtek SoCs 244 - RCC reset controller in STM32 MCUs 245 - Allwinner SoCs 246 - SiFive FU740 SoCs 247 - Sophgo SoCs 248 249config RESET_SOCFPGA 250 bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) 251 default ARM && ARCH_INTEL_SOCFPGA 252 select RESET_SIMPLE 253 help 254 This enables the reset driver for the SoCFPGA ARMv7 platforms. This 255 driver gets initialized early during platform init calls. 256 257config RESET_SUNPLUS 258 bool "Sunplus SoCs Reset Driver" if COMPILE_TEST 259 default ARCH_SUNPLUS 260 help 261 This enables the reset driver support for Sunplus SoCs. 262 The reset lines that can be asserted and deasserted by toggling bits 263 in a contiguous, exclusive register space. The register is HIWORD_MASKED, 264 which means each register holds 16 reset lines. 265 266config RESET_SUNXI 267 bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI 268 default ARCH_SUNXI 269 select RESET_SIMPLE 270 help 271 This enables the reset driver for Allwinner SoCs. 272 273config RESET_TI_SCI 274 tristate "TI System Control Interface (TI-SCI) reset driver" 275 depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n) 276 help 277 This enables the reset driver support over TI System Control Interface 278 available on some new TI's SoCs. If you wish to use reset resources 279 managed by the TI System Controller, say Y here. Otherwise, say N. 280 281config RESET_TI_SYSCON 282 tristate "TI SYSCON Reset Driver" 283 depends on HAS_IOMEM 284 select MFD_SYSCON 285 help 286 This enables the reset driver support for TI devices with 287 memory-mapped reset registers as part of a syscon device node. If 288 you wish to use the reset framework for such memory-mapped devices, 289 say Y here. Otherwise, say N. 290 291config RESET_TI_TPS380X 292 tristate "TI TPS380x Reset Driver" 293 select GPIOLIB 294 help 295 This enables the reset driver support for TI TPS380x devices. If 296 you wish to use the reset framework for such devices, say Y here. 297 Otherwise, say N. 298 299config RESET_TN48M_CPLD 300 tristate "Delta Networks TN48M switch CPLD reset controller" 301 depends on MFD_TN48M_CPLD || COMPILE_TEST 302 default MFD_TN48M_CPLD 303 help 304 This enables the reset controller driver for the Delta TN48M CPLD. 305 It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X 306 switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and 307 Microchip PD69200 PoE PSE controller. 308 309 This driver can also be built as a module. If so, the module will be 310 called reset-tn48m. 311 312config RESET_UNIPHIER 313 tristate "Reset controller driver for UniPhier SoCs" 314 depends on ARCH_UNIPHIER || COMPILE_TEST 315 depends on OF && MFD_SYSCON 316 default ARCH_UNIPHIER 317 help 318 Support for reset controllers on UniPhier SoCs. 319 Say Y if you want to control reset signals provided by System Control 320 block, Media I/O block, Peripheral Block. 321 322config RESET_UNIPHIER_GLUE 323 tristate "Reset driver in glue layer for UniPhier SoCs" 324 depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF 325 default ARCH_UNIPHIER 326 select RESET_SIMPLE 327 help 328 Support for peripheral core reset included in its own glue layer 329 on UniPhier SoCs. Say Y if you want to control reset signals 330 provided by the glue layer. 331 332config RESET_ZYNQ 333 bool "ZYNQ Reset Driver" if COMPILE_TEST 334 default ARCH_ZYNQ 335 help 336 This enables the reset controller driver for Xilinx Zynq SoCs. 337 338source "drivers/reset/starfive/Kconfig" 339source "drivers/reset/sti/Kconfig" 340source "drivers/reset/hisilicon/Kconfig" 341source "drivers/reset/tegra/Kconfig" 342 343endif 344