xref: /linux-6.15/drivers/reset/Kconfig (revision 6b64fde5)
1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only
261fc4131SPhilipp Zabelconfig ARCH_HAS_RESET_CONTROLLER
361fc4131SPhilipp Zabel	bool
461fc4131SPhilipp Zabel
561fc4131SPhilipp Zabelmenuconfig RESET_CONTROLLER
661fc4131SPhilipp Zabel	bool "Reset Controller Support"
761fc4131SPhilipp Zabel	default y if ARCH_HAS_RESET_CONTROLLER
861fc4131SPhilipp Zabel	help
961fc4131SPhilipp Zabel	  Generic Reset Controller support.
1061fc4131SPhilipp Zabel
1161fc4131SPhilipp Zabel	  This framework is designed to abstract reset handling of devices
1261fc4131SPhilipp Zabel	  via GPIOs or SoC-internal reset controller modules.
1361fc4131SPhilipp Zabel
1461fc4131SPhilipp Zabel	  If unsure, say no.
15e5d76075SStephen Gallimore
16998cd463SMasahiro Yamadaif RESET_CONTROLLER
17998cd463SMasahiro Yamada
1862700682SThor Thayerconfig RESET_A10SR
1962700682SThor Thayer	tristate "Altera Arria10 System Resource Reset"
20af19f193SPhilipp Zabel	depends on MFD_ALTERA_A10SR || COMPILE_TEST
2162700682SThor Thayer	help
2262700682SThor Thayer	  This option enables support for the external reset functions for
2362700682SThor Thayer	  peripheral PHYs on the Altera Arria10 System Resource Chip.
2462700682SThor Thayer
25e27b4a6eSPhilipp Zabelconfig RESET_ATH79
26e27b4a6eSPhilipp Zabel	bool "AR71xx Reset Driver" if COMPILE_TEST
27e27b4a6eSPhilipp Zabel	default ATH79
28e27b4a6eSPhilipp Zabel	help
29e27b4a6eSPhilipp Zabel	  This enables the ATH79 reset controller driver that supports the
30e27b4a6eSPhilipp Zabel	  AR71xx SoC reset controller.
31e27b4a6eSPhilipp Zabel
3237634923SEugeniy Paltsevconfig RESET_AXS10X
3337634923SEugeniy Paltsev	bool "AXS10x Reset Driver" if COMPILE_TEST
3437634923SEugeniy Paltsev	default ARC_PLAT_AXS10X
3537634923SEugeniy Paltsev	help
3637634923SEugeniy Paltsev	  This enables the reset controller driver for AXS10x.
3737634923SEugeniy Paltsev
38aac02543SÁlvaro Fernández Rojasconfig RESET_BCM6345
39aac02543SÁlvaro Fernández Rojas	bool "BCM6345 Reset Controller"
40aac02543SÁlvaro Fernández Rojas	depends on BMIPS_GENERIC || COMPILE_TEST
41aac02543SÁlvaro Fernández Rojas	default BMIPS_GENERIC
42aac02543SÁlvaro Fernández Rojas	help
43aac02543SÁlvaro Fernández Rojas	  This enables the reset controller driver for BCM6345 SoCs.
44aac02543SÁlvaro Fernández Rojas
4570d467eaSPhilipp Zabelconfig RESET_BERLIN
465e787cdfSJisheng Zhang	tristate "Berlin Reset Driver"
475e787cdfSJisheng Zhang	depends on ARCH_BERLIN || COMPILE_TEST
485e787cdfSJisheng Zhang	default m if ARCH_BERLIN
4970d467eaSPhilipp Zabel	help
5070d467eaSPhilipp Zabel	  This enables the reset controller driver for Marvell Berlin SoCs.
5170d467eaSPhilipp Zabel
5277750bc0SFlorian Fainelliconfig RESET_BRCMSTB
5377750bc0SFlorian Fainelli	tristate "Broadcom STB reset controller"
5477750bc0SFlorian Fainelli	depends on ARCH_BRCMSTB || COMPILE_TEST
5577750bc0SFlorian Fainelli	default ARCH_BRCMSTB
5677750bc0SFlorian Fainelli	help
5777750bc0SFlorian Fainelli	  This enables the reset controller driver for Broadcom STB SoCs using
5877750bc0SFlorian Fainelli	  a SUN_TOP_CTRL_SW_INIT style controller.
5977750bc0SFlorian Fainelli
604cf176e5SJim Quinlanconfig RESET_BRCMSTB_RESCAL
615694ca29SFlorian Fainelli	tristate "Broadcom STB RESCAL reset controller"
627fbcc535SBrendan Higgins	depends on HAS_IOMEM
6342f6a76fSGeert Uytterhoeven	depends on ARCH_BRCMSTB || COMPILE_TEST
6442f6a76fSGeert Uytterhoeven	default ARCH_BRCMSTB
654cf176e5SJim Quinlan	help
664cf176e5SJim Quinlan	  This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
674cf176e5SJim Quinlan	  BCM7216.
684cf176e5SJim Quinlan
69487b1b32SThéo Lebrunconfig RESET_EYEQ
70487b1b32SThéo Lebrun	bool "Mobileye EyeQ reset controller"
71487b1b32SThéo Lebrun	depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST
72487b1b32SThéo Lebrun	select AUXILIARY_BUS
73487b1b32SThéo Lebrun	default MACH_EYEQ5 || MACH_EYEQ6H
74487b1b32SThéo Lebrun	help
75487b1b32SThéo Lebrun	  This enables the Mobileye EyeQ reset controller, used in EyeQ5, EyeQ6L
76487b1b32SThéo Lebrun	  and EyeQ6H SoCs.
77487b1b32SThéo Lebrun
78487b1b32SThéo Lebrun	  It has one or more domains, with a varying number of resets in each.
79487b1b32SThéo Lebrun	  Registers are located in a shared register region called OLB. EyeQ6H
80487b1b32SThéo Lebrun	  has multiple reset instances.
81487b1b32SThéo Lebrun
82cee544a4SKrzysztof Kozlowskiconfig RESET_GPIO
83cee544a4SKrzysztof Kozlowski	tristate "GPIO reset controller"
8401f6a84cSMark Brown	depends on GPIOLIB
85cee544a4SKrzysztof Kozlowski	help
86cee544a4SKrzysztof Kozlowski	  This enables a generic reset controller for resets attached via
87cee544a4SKrzysztof Kozlowski	  GPIOs.  Typically for OF platforms this driver expects "reset-gpios"
88cee544a4SKrzysztof Kozlowski	  property.
89cee544a4SKrzysztof Kozlowski
90cee544a4SKrzysztof Kozlowski	  If compiled as module, it will be called reset-gpio.
91cee544a4SKrzysztof Kozlowski
9213541226SVineet Guptaconfig RESET_HSDK
9313541226SVineet Gupta	bool "Synopsys HSDK Reset Driver"
942d48a237SThomas Meyer	depends on HAS_IOMEM
95544e3bf4SGeert Uytterhoeven	depends on ARC_SOC_HSDK || COMPILE_TEST
96e0be864fSEugeniy Paltsev	help
9713541226SVineet Gupta	  This enables the reset controller driver for HSDK board.
98e0be864fSEugeniy Paltsev
99*6b64fde5SFrank Liconfig RESET_IMX_SCU
100*6b64fde5SFrank Li	tristate "i.MX8Q Reset Driver"
101*6b64fde5SFrank Li	depends on IMX_SCU && HAVE_ARM_SMCCC
102*6b64fde5SFrank Li	depends on (ARM64 && ARCH_MXC) || COMPILE_TEST
103*6b64fde5SFrank Li	help
104*6b64fde5SFrank Li          This enables the reset controller driver for i.MX8QM/i.MX8QXP
105*6b64fde5SFrank Li
106abf97755SAndrey Smirnovconfig RESET_IMX7
107a442abbbSAnson Huang	tristate "i.MX7/8 Reset Driver"
1088fa56620SMasahiro Yamada	depends on HAS_IOMEM
109a442abbbSAnson Huang	depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST
110a442abbbSAnson Huang	default y if SOC_IMX7D
111abf97755SAndrey Smirnov	select MFD_SYSCON
112abf97755SAndrey Smirnov	help
113abf97755SAndrey Smirnov	  This enables the reset controller driver for i.MX7 SoCs.
114abf97755SAndrey Smirnov
115fe125601SShengjiu Wangconfig RESET_IMX8MP_AUDIOMIX
116fe125601SShengjiu Wang	tristate "i.MX8MP AudioMix Reset Driver"
117eb5d88b1SGeert Uytterhoeven	depends on ARCH_MXC || COMPILE_TEST
118fe125601SShengjiu Wang	select AUXILIARY_BUS
119fe125601SShengjiu Wang	default CLK_IMX8MP
120fe125601SShengjiu Wang	help
121fe125601SShengjiu Wang	  This enables the reset controller driver for i.MX8MP AudioMix
122fe125601SShengjiu Wang
123c9aef213SDilip Kotaconfig RESET_INTEL_GW
124c9aef213SDilip Kota	bool "Intel Reset Controller Driver"
1256ab9d621SGeert Uytterhoeven	depends on X86 || COMPILE_TEST
126b460e0a9SBrendan Higgins	depends on OF && HAS_IOMEM
127c9aef213SDilip Kota	select REGMAP_MMIO
128c9aef213SDilip Kota	help
129c9aef213SDilip Kota	  This enables the reset controller driver for Intel Gateway SoCs.
130c9aef213SDilip Kota	  Say Y to control the reset signals provided by reset controller.
131c9aef213SDilip Kota	  Otherwise, say N.
132c9aef213SDilip Kota
1335a2308daSDamien Le Moalconfig RESET_K210
1345a2308daSDamien Le Moal	bool "Reset controller driver for Canaan Kendryte K210 SoC"
13568f41105SYangyu Chen	depends on (SOC_CANAAN_K210 || COMPILE_TEST) && OF
1365a2308daSDamien Le Moal	select MFD_SYSCON
13768f41105SYangyu Chen	default SOC_CANAAN_K210
1385a2308daSDamien Le Moal	help
1395a2308daSDamien Le Moal	  Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
1405a2308daSDamien Le Moal	  Say Y if you want to control reset signals provided by this
1415a2308daSDamien Le Moal	  controller.
1425a2308daSDamien Le Moal
14379797b6fSMartin Blumenstinglconfig RESET_LANTIQ
14479797b6fSMartin Blumenstingl	bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
14579797b6fSMartin Blumenstingl	default SOC_TYPE_XWAY
14679797b6fSMartin Blumenstingl	help
14779797b6fSMartin Blumenstingl	  This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
14879797b6fSMartin Blumenstingl
149cd7f4b81SPhilipp Zabelconfig RESET_LPC18XX
150cd7f4b81SPhilipp Zabel	bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
151cd7f4b81SPhilipp Zabel	default ARCH_LPC18XX
152cd7f4b81SPhilipp Zabel	help
153cd7f4b81SPhilipp Zabel	  This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
154cd7f4b81SPhilipp Zabel
155453ed428SSteen Hegelundconfig RESET_MCHP_SPARX5
156996737efSClément Léger	tristate "Microchip Sparx5 reset driver"
157eba0deddSHerve Codina	depends on ARCH_SPARX5 || SOC_LAN966 || MCHP_LAN966X_PCI || COMPILE_TEST
158453ed428SSteen Hegelund	default y if SPARX5_SWITCH
159453ed428SSteen Hegelund	select MFD_SYSCON
160453ed428SSteen Hegelund	help
161453ed428SSteen Hegelund	  This driver supports switch core reset for the Microchip Sparx5 SoC.
162453ed428SSteen Hegelund
1639c81b2ccSTomer Maimonconfig RESET_NPCM
1649c81b2ccSTomer Maimon	bool "NPCM BMC Reset Driver" if COMPILE_TEST
1659c81b2ccSTomer Maimon	default ARCH_NPCM
16622823157STomer Maimon	select AUXILIARY_BUS
1679c81b2ccSTomer Maimon	help
1689c81b2ccSTomer Maimon	  This enables the reset controller driver for Nuvoton NPCM
1699c81b2ccSTomer Maimon	  BMC SoCs.
1709c81b2ccSTomer Maimon
171e4bb55d6SJacky Huangconfig RESET_NUVOTON_MA35D1
172aead1076SGeert Uytterhoeven	bool "Nuvoton MA35D1 Reset Driver"
173aead1076SGeert Uytterhoeven	depends on ARCH_MA35 || COMPILE_TEST
174aead1076SGeert Uytterhoeven	default ARCH_MA35
175e4bb55d6SJacky Huang	help
176e4bb55d6SJacky Huang	  This enables the reset controller driver for Nuvoton MA35D1 SoC.
177e4bb55d6SJacky Huang
178fab3f730SPhilipp Zabelconfig RESET_PISTACHIO
1794af16070SGeert Uytterhoeven	bool "Pistachio Reset Driver"
1804af16070SGeert Uytterhoeven	depends on MIPS || COMPILE_TEST
181fab3f730SPhilipp Zabel	help
182fab3f730SPhilipp Zabel	  This enables the reset driver for ImgTec Pistachio SoCs.
183fab3f730SPhilipp Zabel
18405f9e363SConor Dooleyconfig RESET_POLARFIRE_SOC
18505f9e363SConor Dooley	bool "Microchip PolarFire SoC (MPFS) Reset Driver"
186afb39e2bSPhilipp Zabel	depends on MCHP_CLK_MPFS
187afb39e2bSPhilipp Zabel	select AUXILIARY_BUS
18805f9e363SConor Dooley	default MCHP_CLK_MPFS
18905f9e363SConor Dooley	help
19005f9e363SConor Dooley	  This driver supports peripheral reset for the Microchip PolarFire SoC
19105f9e363SConor Dooley
1925ecb0651SSibi Sankarconfig RESET_QCOM_AOSS
193e2d5e833SJohn Stultz	tristate "Qcom AOSS Reset Driver"
1945ecb0651SSibi Sankar	depends on ARCH_QCOM || COMPILE_TEST
1955ecb0651SSibi Sankar	help
1965ecb0651SSibi Sankar	  This enables the AOSS (always on subsystem) reset driver
1975ecb0651SSibi Sankar	  for Qualcomm SDM845 SoCs. Say Y if you want to control
1985ecb0651SSibi Sankar	  reset signals provided by AOSS for Modem, Venus, ADSP,
1995ecb0651SSibi Sankar	  GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
2005ecb0651SSibi Sankar
201eea2926bSSibi Sankarconfig RESET_QCOM_PDC
202eea2926bSSibi Sankar	tristate "Qualcomm PDC Reset Driver"
203eea2926bSSibi Sankar	depends on ARCH_QCOM || COMPILE_TEST
204eea2926bSSibi Sankar	help
205eea2926bSSibi Sankar	  This enables the PDC (Power Domain Controller) reset driver
206eea2926bSSibi Sankar	  for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
207eea2926bSSibi Sankar	  to control reset signals provided by PDC for Modem, Compute,
208eea2926bSSibi Sankar	  Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
209eea2926bSSibi Sankar
210abffc82aSNicolas Saenz Julienneconfig RESET_RASPBERRYPI
211abffc82aSNicolas Saenz Julienne	tristate "Raspberry Pi 4 Firmware Reset Driver"
212abffc82aSNicolas Saenz Julienne	depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST)
213abffc82aSNicolas Saenz Julienne	default USB_XHCI_PCI
214abffc82aSNicolas Saenz Julienne	help
215abffc82aSNicolas Saenz Julienne	  Raspberry Pi 4's co-processor controls some of the board's HW
216abffc82aSNicolas Saenz Julienne	  initialization process, but it's up to Linux to trigger it when
217abffc82aSNicolas Saenz Julienne	  relevant. This driver provides a reset controller capable of
218abffc82aSNicolas Saenz Julienne	  interfacing with RPi4's co-processor and model these firmware
219abffc82aSNicolas Saenz Julienne	  initialization routines as reset lines.
220abffc82aSNicolas Saenz Julienne
221bee08559SBiju Dasconfig RESET_RZG2L_USBPHY_CTRL
222bee08559SBiju Das	tristate "Renesas RZ/G2L USBPHY control driver"
2239fe7dd4eSLad Prabhakar	depends on ARCH_RZG2L || COMPILE_TEST
224bee08559SBiju Das	help
225bee08559SBiju Das	  Support for USBPHY Control found on RZ/G2L family. It mainly
226bee08559SBiju Das	  controls reset and power down of the USB/PHY.
227bee08559SBiju Das
228c8ae9c2dSSudeep Hollaconfig RESET_SCMI
229c8ae9c2dSSudeep Holla	tristate "Reset driver controlled via ARM SCMI interface"
230c8ae9c2dSSudeep Holla	depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
231c8ae9c2dSSudeep Holla	default ARM_SCMI_PROTOCOL
232c8ae9c2dSSudeep Holla	help
233c8ae9c2dSSudeep Holla	  This driver provides support for reset signal/domains that are
234c8ae9c2dSSudeep Holla	  controlled by firmware that implements the SCMI interface.
235c8ae9c2dSSudeep Holla
236c8ae9c2dSSudeep Holla	  This driver uses SCMI Message Protocol to interact with the
237c8ae9c2dSSudeep Holla	  firmware controlling all the reset signals.
238c8ae9c2dSSudeep Holla
23981c22ad0SPhilipp Zabelconfig RESET_SIMPLE
24018d1909bSBen Dooks	bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT
241a6166a4dSChen Wang	default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
242c4ada3caSBen Dooks	depends on HAS_IOMEM
24381c22ad0SPhilipp Zabel	help
24481c22ad0SPhilipp Zabel	  This enables a simple reset controller driver for reset lines that
24581c22ad0SPhilipp Zabel	  that can be asserted and deasserted by toggling bits in a contiguous,
24681c22ad0SPhilipp Zabel	  exclusive register space.
24781c22ad0SPhilipp Zabel
2481d7592f8SJoel Stanley	  Currently this driver supports:
2491d7592f8SJoel Stanley	   - Altera SoCFPGAs
2501d7592f8SJoel Stanley	   - ASPEED BMC SoCs
2515ac33eebSAndreas Färber	   - Bitmain BM1880 SoC
2523ab831e5SAndreas Färber	   - Realtek SoCs
2531d7592f8SJoel Stanley	   - RCC reset controller in STM32 MCUs
2541d7592f8SJoel Stanley	   - Allwinner SoCs
255e4d368e0SGreentime Hu	   - SiFive FU740 SoCs
256a6166a4dSChen Wang	   - Sophgo SoCs
2577e0e901dSPhilipp Zabel
258b3ca9888SDinh Nguyenconfig RESET_SOCFPGA
259225c13f0SKrzysztof Kozlowski	bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)
260225c13f0SKrzysztof Kozlowski	default ARM && ARCH_INTEL_SOCFPGA
261b3ca9888SDinh Nguyen	select RESET_SIMPLE
262b3ca9888SDinh Nguyen	help
263b3ca9888SDinh Nguyen	  This enables the reset driver for the SoCFPGA ARMv7 platforms. This
264b3ca9888SDinh Nguyen	  driver gets initialized early during platform init calls.
265b3ca9888SDinh Nguyen
266dbf018beSQin Jianconfig RESET_SUNPLUS
267dbf018beSQin Jian	bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
268dbf018beSQin Jian	default ARCH_SUNPLUS
269dbf018beSQin Jian	help
270dbf018beSQin Jian	  This enables the reset driver support for Sunplus SoCs.
271dbf018beSQin Jian	  The reset lines that can be asserted and deasserted by toggling bits
272dbf018beSQin Jian	  in a contiguous, exclusive register space. The register is HIWORD_MASKED,
273dbf018beSQin Jian	  which means each register holds 16 reset lines.
274dbf018beSQin Jian
2750ae08419SPhilipp Zabelconfig RESET_SUNXI
2760ae08419SPhilipp Zabel	bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
2770ae08419SPhilipp Zabel	default ARCH_SUNXI
278e13c205aSPhilipp Zabel	select RESET_SIMPLE
2790ae08419SPhilipp Zabel	help
2800ae08419SPhilipp Zabel	  This enables the reset driver for Allwinner SoCs.
2810ae08419SPhilipp Zabel
28228df169bSAndrew F. Davisconfig RESET_TI_SCI
28328df169bSAndrew F. Davis	tristate "TI System Control Interface (TI-SCI) reset driver"
28413678f3fSRandy Dunlap	depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n)
28528df169bSAndrew F. Davis	help
28628df169bSAndrew F. Davis	  This enables the reset driver support over TI System Control Interface
28728df169bSAndrew F. Davis	  available on some new TI's SoCs. If you wish to use reset resources
28828df169bSAndrew F. Davis	  managed by the TI System Controller, say Y here. Otherwise, say N.
28928df169bSAndrew F. Davis
290dd9bf863SSuman Annaconfig RESET_TI_SYSCON
291cc7c2bb1SAndrew F. Davis	tristate "TI SYSCON Reset Driver"
292cc7c2bb1SAndrew F. Davis	depends on HAS_IOMEM
293cc7c2bb1SAndrew F. Davis	select MFD_SYSCON
294cc7c2bb1SAndrew F. Davis	help
295cc7c2bb1SAndrew F. Davis	  This enables the reset driver support for TI devices with
296cc7c2bb1SAndrew F. Davis	  memory-mapped reset registers as part of a syscon device node. If
297cc7c2bb1SAndrew F. Davis	  you wish to use the reset framework for such memory-mapped devices,
298cc7c2bb1SAndrew F. Davis	  say Y here. Otherwise, say N.
299cc7c2bb1SAndrew F. Davis
3008a4e6154SMarco Felschconfig RESET_TI_TPS380X
3018a4e6154SMarco Felsch	tristate "TI TPS380x Reset Driver"
3028a4e6154SMarco Felsch	select GPIOLIB
3038a4e6154SMarco Felsch	help
3048a4e6154SMarco Felsch	  This enables the reset driver support for TI TPS380x devices. If
3058a4e6154SMarco Felsch	  you wish to use the reset framework for such devices, say Y here.
3068a4e6154SMarco Felsch	  Otherwise, say N.
3078a4e6154SMarco Felsch
3085cd3921dSRobert Markoconfig RESET_TN48M_CPLD
3095cd3921dSRobert Marko	tristate "Delta Networks TN48M switch CPLD reset controller"
3105cd3921dSRobert Marko	depends on MFD_TN48M_CPLD || COMPILE_TEST
3115cd3921dSRobert Marko	default MFD_TN48M_CPLD
3125cd3921dSRobert Marko	help
3135cd3921dSRobert Marko	  This enables the reset controller driver for the Delta TN48M CPLD.
3145cd3921dSRobert Marko	  It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X
3155cd3921dSRobert Marko	  switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and
3165cd3921dSRobert Marko	  Microchip PD69200 PoE PSE controller.
3175cd3921dSRobert Marko
3185cd3921dSRobert Marko	  This driver can also be built as a module. If so, the module will be
3195cd3921dSRobert Marko	  called reset-tn48m.
3205cd3921dSRobert Marko
32154e991b5SMasahiro Yamadaconfig RESET_UNIPHIER
32254e991b5SMasahiro Yamada	tristate "Reset controller driver for UniPhier SoCs"
32354e991b5SMasahiro Yamada	depends on ARCH_UNIPHIER || COMPILE_TEST
32454e991b5SMasahiro Yamada	depends on OF && MFD_SYSCON
32554e991b5SMasahiro Yamada	default ARCH_UNIPHIER
32654e991b5SMasahiro Yamada	help
32754e991b5SMasahiro Yamada	  Support for reset controllers on UniPhier SoCs.
32854e991b5SMasahiro Yamada	  Say Y if you want to control reset signals provided by System Control
32954e991b5SMasahiro Yamada	  block, Media I/O block, Peripheral Block.
33054e991b5SMasahiro Yamada
3313eb8f765SKunihiko Hayashiconfig RESET_UNIPHIER_GLUE
3323eb8f765SKunihiko Hayashi	tristate "Reset driver in glue layer for UniPhier SoCs"
333499fef09SKunihiko Hayashi	depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
334499fef09SKunihiko Hayashi	default ARCH_UNIPHIER
335499fef09SKunihiko Hayashi	select RESET_SIMPLE
336499fef09SKunihiko Hayashi	help
3373eb8f765SKunihiko Hayashi	  Support for peripheral core reset included in its own glue layer
3383eb8f765SKunihiko Hayashi	  on UniPhier SoCs. Say Y if you want to control reset signals
3393eb8f765SKunihiko Hayashi	  provided by the glue layer.
340499fef09SKunihiko Hayashi
3416f51b860SPhilipp Zabelconfig RESET_ZYNQ
3426f51b860SPhilipp Zabel	bool "ZYNQ Reset Driver" if COMPILE_TEST
3436f51b860SPhilipp Zabel	default ARCH_ZYNQ
3446f51b860SPhilipp Zabel	help
3456f51b860SPhilipp Zabel	  This enables the reset controller driver for Xilinx Zynq SoCs.
3466f51b860SPhilipp Zabel
3474f6a43adSPhilipp Zabelconfig RESET_ZYNQMP
3484f6a43adSPhilipp Zabel	bool "ZYNQMP Reset Driver" if COMPILE_TEST
3494f6a43adSPhilipp Zabel	default ARCH_ZYNQMP
3504f6a43adSPhilipp Zabel	help
3514f6a43adSPhilipp Zabel	  This enables the reset controller driver for Xilinx ZynqMP SoCs.
3524f6a43adSPhilipp Zabel
3532c138ee3SJerome Brunetsource "drivers/reset/amlogic/Kconfig"
35469bfec75SEmil Renner Berthingsource "drivers/reset/starfive/Kconfig"
355e5d76075SStephen Gallimoresource "drivers/reset/sti/Kconfig"
356f59d23c2SChen Fengsource "drivers/reset/hisilicon/Kconfig"
357dc606c52SThierry Redingsource "drivers/reset/tegra/Kconfig"
358998cd463SMasahiro Yamada
359998cd463SMasahiro Yamadaendif
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