xref: /linux-6.15/drivers/perf/Kconfig (revision f5bfa23f) 
1# SPDX-License-Identifier: GPL-2.0-only
2#
3# Performance Monitor Drivers
4#
5
6menu "Performance monitor support"
7	depends on PERF_EVENTS
8
9config ARM_CCI_PMU
10	tristate "ARM CCI PMU driver"
11	depends on (ARM && CPU_V7) || ARM64
12	select ARM_CCI
13	help
14	  Support for PMU events monitoring on the ARM CCI (Cache Coherent
15	  Interconnect) family of products.
16
17	  If compiled as a module, it will be called arm-cci.
18
19config ARM_CCI400_PMU
20	bool "support CCI-400"
21	default y
22	depends on ARM_CCI_PMU
23	select ARM_CCI400_COMMON
24	help
25	  CCI-400 provides 4 independent event counters counting events related
26	  to the connected slave/master interfaces, plus a cycle counter.
27
28config ARM_CCI5xx_PMU
29	bool "support CCI-500/CCI-550"
30	default y
31	depends on ARM_CCI_PMU
32	help
33	  CCI-500/CCI-550 both provide 8 independent event counters, which can
34	  count events pertaining to the slave/master interfaces as well as the
35	  internal events to the CCI.
36
37config ARM_CCN
38	tristate "ARM CCN driver support"
39	depends on ARM || ARM64 || COMPILE_TEST
40	help
41	  PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
42	  interconnect.
43
44config ARM_CMN
45	tristate "Arm CMN-600 PMU support"
46	depends on ARM64 || COMPILE_TEST
47	help
48	  Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
49	  Network interconnect.
50
51config ARM_PMU
52	depends on ARM || ARM64
53	bool "ARM PMU framework"
54	default y
55	help
56	  Say y if you want to use CPU performance monitors on ARM-based
57	  systems.
58
59config RISCV_PMU
60	depends on RISCV
61	bool "RISC-V PMU framework"
62	default y
63	help
64	  Say y if you want to use CPU performance monitors on RISCV-based
65	  systems. This provides the core PMU framework that abstracts common
66	  PMU functionalities in a core library so that different PMU drivers
67	  can reuse it.
68
69config ARM_PMU_ACPI
70	depends on ARM_PMU && ACPI
71	def_bool y
72
73config ARM_SMMU_V3_PMU
74	 tristate "ARM SMMUv3 Performance Monitors Extension"
75	 depends on (ARM64 && ACPI) || (COMPILE_TEST && 64BIT)
76	 depends on GENERIC_MSI_IRQ_DOMAIN
77	   help
78	   Provides support for the ARM SMMUv3 Performance Monitor Counter
79	   Groups (PMCG), which provide monitoring of transactions passing
80	   through the SMMU and allow the resulting information to be filtered
81	   based on the Stream ID of the corresponding master.
82
83config ARM_DSU_PMU
84	tristate "ARM DynamIQ Shared Unit (DSU) PMU"
85	depends on ARM64
86	  help
87	  Provides support for performance monitor unit in ARM DynamIQ Shared
88	  Unit (DSU). The DSU integrates one or more cores with an L3 memory
89	  system, control logic. The PMU allows counting various events related
90	  to DSU.
91
92config FSL_IMX8_DDR_PMU
93	tristate "Freescale i.MX8 DDR perf monitor"
94	depends on ARCH_MXC || COMPILE_TEST
95	  help
96	  Provides support for the DDR performance monitor in i.MX8, which
97	  can give information about memory throughput and other related
98	  events.
99
100config QCOM_L2_PMU
101	bool "Qualcomm Technologies L2-cache PMU"
102	depends on ARCH_QCOM && ARM64 && ACPI
103	select QCOM_KRYO_L2_ACCESSORS
104	  help
105	  Provides support for the L2 cache performance monitor unit (PMU)
106	  in Qualcomm Technologies processors.
107	  Adds the L2 cache PMU into the perf events subsystem for
108	  monitoring L2 cache events.
109
110config QCOM_L3_PMU
111	bool "Qualcomm Technologies L3-cache PMU"
112	depends on ARCH_QCOM && ARM64 && ACPI
113	select QCOM_IRQ_COMBINER
114	help
115	   Provides support for the L3 cache performance monitor unit (PMU)
116	   in Qualcomm Technologies processors.
117	   Adds the L3 cache PMU into the perf events subsystem for
118	   monitoring L3 cache events.
119
120config THUNDERX2_PMU
121	tristate "Cavium ThunderX2 SoC PMU UNCORE"
122	depends on ARCH_THUNDER2 || COMPILE_TEST
123	depends on NUMA && ACPI
124	default m
125	help
126	   Provides support for ThunderX2 UNCORE events.
127	   The SoC has PMU support in its L3 cache controller (L3C) and
128	   in the DDR4 Memory Controller (DMC).
129
130config XGENE_PMU
131        depends on ARCH_XGENE || (COMPILE_TEST && 64BIT)
132        bool "APM X-Gene SoC PMU"
133        default n
134        help
135          Say y if you want to use APM X-Gene SoC performance monitors.
136
137config ARM_SPE_PMU
138	tristate "Enable support for the ARMv8.2 Statistical Profiling Extension"
139	depends on ARM64
140	help
141	  Enable perf support for the ARMv8.2 Statistical Profiling
142	  Extension, which provides periodic sampling of operations in
143	  the CPU pipeline and reports this via the perf AUX interface.
144
145config ARM_DMC620_PMU
146	tristate "Enable PMU support for the ARM DMC-620 memory controller"
147	depends on (ARM64 && ACPI) || COMPILE_TEST
148	help
149	  Support for PMU events monitoring on the ARM DMC-620 memory
150	  controller.
151
152config MARVELL_CN10K_TAD_PMU
153	tristate "Marvell CN10K LLC-TAD PMU"
154	depends on ARM64 || (COMPILE_TEST && 64BIT)
155	help
156	  Provides support for Last-Level cache Tag-and-data Units (LLC-TAD)
157	  performance monitors on CN10K family silicons.
158
159source "drivers/perf/hisilicon/Kconfig"
160
161endmenu
162