xref: /linux-6.15/drivers/perf/Kconfig (revision 9b3e150e) 
1# SPDX-License-Identifier: GPL-2.0-only
2#
3# Performance Monitor Drivers
4#
5
6menu "Performance monitor support"
7	depends on PERF_EVENTS
8
9config ARM_CCI_PMU
10	tristate "ARM CCI PMU driver"
11	depends on (ARM && CPU_V7) || ARM64
12	select ARM_CCI
13	help
14	  Support for PMU events monitoring on the ARM CCI (Cache Coherent
15	  Interconnect) family of products.
16
17	  If compiled as a module, it will be called arm-cci.
18
19config ARM_CCI400_PMU
20	bool "support CCI-400"
21	default y
22	depends on ARM_CCI_PMU
23	select ARM_CCI400_COMMON
24	help
25	  CCI-400 provides 4 independent event counters counting events related
26	  to the connected slave/master interfaces, plus a cycle counter.
27
28config ARM_CCI5xx_PMU
29	bool "support CCI-500/CCI-550"
30	default y
31	depends on ARM_CCI_PMU
32	help
33	  CCI-500/CCI-550 both provide 8 independent event counters, which can
34	  count events pertaining to the slave/master interfaces as well as the
35	  internal events to the CCI.
36
37config ARM_CCN
38	tristate "ARM CCN driver support"
39	depends on ARM || ARM64 || COMPILE_TEST
40	help
41	  PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
42	  interconnect.
43
44config ARM_CMN
45	tristate "Arm CMN-600 PMU support"
46	depends on ARM64 || COMPILE_TEST
47	help
48	  Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
49	  Network interconnect.
50
51config ARM_PMU
52	depends on ARM || ARM64
53	bool "ARM PMU framework"
54	default y
55	help
56	  Say y if you want to use CPU performance monitors on ARM-based
57	  systems.
58
59config RISCV_PMU
60	depends on RISCV
61	bool "RISC-V PMU framework"
62	default y
63	help
64	  Say y if you want to use CPU performance monitors on RISCV-based
65	  systems. This provides the core PMU framework that abstracts common
66	  PMU functionalities in a core library so that different PMU drivers
67	  can reuse it.
68
69config RISCV_PMU_LEGACY
70	depends on RISCV_PMU
71	bool "RISC-V legacy PMU implementation"
72	default y
73	help
74	  Say y if you want to use the legacy CPU performance monitor
75	  implementation on RISC-V based systems. This only allows counting
76	  of cycle/instruction counter and doesn't support counter overflow,
77	  or programmable counters. It will be removed in future.
78
79config ARM_PMU_ACPI
80	depends on ARM_PMU && ACPI
81	def_bool y
82
83config ARM_SMMU_V3_PMU
84	 tristate "ARM SMMUv3 Performance Monitors Extension"
85	 depends on (ARM64 && ACPI) || (COMPILE_TEST && 64BIT)
86	 depends on GENERIC_MSI_IRQ_DOMAIN
87	   help
88	   Provides support for the ARM SMMUv3 Performance Monitor Counter
89	   Groups (PMCG), which provide monitoring of transactions passing
90	   through the SMMU and allow the resulting information to be filtered
91	   based on the Stream ID of the corresponding master.
92
93config ARM_DSU_PMU
94	tristate "ARM DynamIQ Shared Unit (DSU) PMU"
95	depends on ARM64
96	  help
97	  Provides support for performance monitor unit in ARM DynamIQ Shared
98	  Unit (DSU). The DSU integrates one or more cores with an L3 memory
99	  system, control logic. The PMU allows counting various events related
100	  to DSU.
101
102config FSL_IMX8_DDR_PMU
103	tristate "Freescale i.MX8 DDR perf monitor"
104	depends on ARCH_MXC || COMPILE_TEST
105	  help
106	  Provides support for the DDR performance monitor in i.MX8, which
107	  can give information about memory throughput and other related
108	  events.
109
110config QCOM_L2_PMU
111	bool "Qualcomm Technologies L2-cache PMU"
112	depends on ARCH_QCOM && ARM64 && ACPI
113	select QCOM_KRYO_L2_ACCESSORS
114	  help
115	  Provides support for the L2 cache performance monitor unit (PMU)
116	  in Qualcomm Technologies processors.
117	  Adds the L2 cache PMU into the perf events subsystem for
118	  monitoring L2 cache events.
119
120config QCOM_L3_PMU
121	bool "Qualcomm Technologies L3-cache PMU"
122	depends on ARCH_QCOM && ARM64 && ACPI
123	select QCOM_IRQ_COMBINER
124	help
125	   Provides support for the L3 cache performance monitor unit (PMU)
126	   in Qualcomm Technologies processors.
127	   Adds the L3 cache PMU into the perf events subsystem for
128	   monitoring L3 cache events.
129
130config THUNDERX2_PMU
131	tristate "Cavium ThunderX2 SoC PMU UNCORE"
132	depends on ARCH_THUNDER2 || COMPILE_TEST
133	depends on NUMA && ACPI
134	default m
135	help
136	   Provides support for ThunderX2 UNCORE events.
137	   The SoC has PMU support in its L3 cache controller (L3C) and
138	   in the DDR4 Memory Controller (DMC).
139
140config XGENE_PMU
141        depends on ARCH_XGENE || (COMPILE_TEST && 64BIT)
142        bool "APM X-Gene SoC PMU"
143        default n
144        help
145          Say y if you want to use APM X-Gene SoC performance monitors.
146
147config ARM_SPE_PMU
148	tristate "Enable support for the ARMv8.2 Statistical Profiling Extension"
149	depends on ARM64
150	help
151	  Enable perf support for the ARMv8.2 Statistical Profiling
152	  Extension, which provides periodic sampling of operations in
153	  the CPU pipeline and reports this via the perf AUX interface.
154
155config ARM_DMC620_PMU
156	tristate "Enable PMU support for the ARM DMC-620 memory controller"
157	depends on (ARM64 && ACPI) || COMPILE_TEST
158	help
159	  Support for PMU events monitoring on the ARM DMC-620 memory
160	  controller.
161
162config MARVELL_CN10K_TAD_PMU
163	tristate "Marvell CN10K LLC-TAD PMU"
164	depends on ARM64 || (COMPILE_TEST && 64BIT)
165	help
166	  Provides support for Last-Level cache Tag-and-data Units (LLC-TAD)
167	  performance monitors on CN10K family silicons.
168
169source "drivers/perf/hisilicon/Kconfig"
170
171endmenu
172