1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dc_bios_types.h" 27 #include "dce_stream_encoder.h" 28 #include "reg_helper.h" 29 #include "hw_shared.h" 30 31 #define DC_LOGGER \ 32 enc110->base.ctx->logger 33 34 35 #define REG(reg)\ 36 (enc110->regs->reg) 37 38 #undef FN 39 #define FN(reg_name, field_name) \ 40 enc110->se_shift->field_name, enc110->se_mask->field_name 41 42 #define VBI_LINE_0 0 43 #define DP_BLANK_MAX_RETRY 20 44 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 45 46 #ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 47 #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x00000010L 48 #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x00000300L 49 #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x00000004 50 #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x00000008 51 #endif 52 53 enum { 54 DP_MST_UPDATE_MAX_RETRY = 50 55 }; 56 57 #define DCE110_SE(audio)\ 58 container_of(audio, struct dce110_stream_encoder, base) 59 60 #define CTX \ 61 enc110->base.ctx 62 63 static void dce110_update_generic_info_packet( 64 struct dce110_stream_encoder *enc110, 65 uint32_t packet_index, 66 const struct dc_info_packet *info_packet) 67 { 68 uint32_t regval; 69 /* TODOFPGA Figure out a proper number for max_retries polling for lock 70 * use 50 for now. 71 */ 72 uint32_t max_retries = 50; 73 74 /*we need turn on clock before programming AFMT block*/ 75 if (REG(AFMT_CNTL)) 76 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 77 78 if (REG(AFMT_VBI_PACKET_CONTROL1)) { 79 if (packet_index >= 8) 80 ASSERT(0); 81 82 /* poll dig_update_lock is not locked -> asic internal signal 83 * assume otg master lock will unlock it 84 */ 85 /* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, 86 0, 10, max_retries);*/ 87 88 /* check if HW reading GSP memory */ 89 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, 90 0, 10, max_retries); 91 92 /* HW does is not reading GSP memory not reading too long -> 93 * something wrong. clear GPS memory access and notify? 94 * hw SW is writing to GSP memory 95 */ 96 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); 97 } 98 /* choose which generic packet to use */ 99 { 100 regval = REG_READ(AFMT_VBI_PACKET_CONTROL); 101 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, 102 AFMT_GENERIC_INDEX, packet_index); 103 } 104 105 /* write generic packet header 106 * (4th byte is for GENERIC0 only) */ 107 { 108 REG_SET_4(AFMT_GENERIC_HDR, 0, 109 AFMT_GENERIC_HB0, info_packet->hb0, 110 AFMT_GENERIC_HB1, info_packet->hb1, 111 AFMT_GENERIC_HB2, info_packet->hb2, 112 AFMT_GENERIC_HB3, info_packet->hb3); 113 } 114 115 /* write generic packet contents 116 * (we never use last 4 bytes) 117 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers */ 118 { 119 const uint32_t *content = 120 (const uint32_t *) &info_packet->sb[0]; 121 122 REG_WRITE(AFMT_GENERIC_0, *content++); 123 REG_WRITE(AFMT_GENERIC_1, *content++); 124 REG_WRITE(AFMT_GENERIC_2, *content++); 125 REG_WRITE(AFMT_GENERIC_3, *content++); 126 REG_WRITE(AFMT_GENERIC_4, *content++); 127 REG_WRITE(AFMT_GENERIC_5, *content++); 128 REG_WRITE(AFMT_GENERIC_6, *content++); 129 REG_WRITE(AFMT_GENERIC_7, *content); 130 } 131 132 if (!REG(AFMT_VBI_PACKET_CONTROL1)) { 133 /* force double-buffered packet update */ 134 REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL, 135 AFMT_GENERIC0_UPDATE, (packet_index == 0), 136 AFMT_GENERIC2_UPDATE, (packet_index == 2)); 137 } 138 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 139 if (REG(AFMT_VBI_PACKET_CONTROL1)) { 140 switch (packet_index) { 141 case 0: 142 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 143 AFMT_GENERIC0_FRAME_UPDATE, 1); 144 break; 145 case 1: 146 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 147 AFMT_GENERIC1_FRAME_UPDATE, 1); 148 break; 149 case 2: 150 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 151 AFMT_GENERIC2_FRAME_UPDATE, 1); 152 break; 153 case 3: 154 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 155 AFMT_GENERIC3_FRAME_UPDATE, 1); 156 break; 157 case 4: 158 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 159 AFMT_GENERIC4_FRAME_UPDATE, 1); 160 break; 161 case 5: 162 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 163 AFMT_GENERIC5_FRAME_UPDATE, 1); 164 break; 165 case 6: 166 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 167 AFMT_GENERIC6_FRAME_UPDATE, 1); 168 break; 169 case 7: 170 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 171 AFMT_GENERIC7_FRAME_UPDATE, 1); 172 break; 173 default: 174 break; 175 } 176 } 177 #endif 178 } 179 180 static void dce110_update_hdmi_info_packet( 181 struct dce110_stream_encoder *enc110, 182 uint32_t packet_index, 183 const struct dc_info_packet *info_packet) 184 { 185 uint32_t cont, send, line; 186 187 if (info_packet->valid) { 188 dce110_update_generic_info_packet( 189 enc110, 190 packet_index, 191 info_packet); 192 193 /* enable transmission of packet(s) - 194 * packet transmission begins on the next frame */ 195 cont = 1; 196 /* send packet(s) every frame */ 197 send = 1; 198 /* select line number to send packets on */ 199 line = 2; 200 } else { 201 cont = 0; 202 send = 0; 203 line = 0; 204 } 205 206 /* choose which generic packet control to use */ 207 switch (packet_index) { 208 case 0: 209 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 210 HDMI_GENERIC0_CONT, cont, 211 HDMI_GENERIC0_SEND, send, 212 HDMI_GENERIC0_LINE, line); 213 break; 214 case 1: 215 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 216 HDMI_GENERIC1_CONT, cont, 217 HDMI_GENERIC1_SEND, send, 218 HDMI_GENERIC1_LINE, line); 219 break; 220 case 2: 221 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 222 HDMI_GENERIC0_CONT, cont, 223 HDMI_GENERIC0_SEND, send, 224 HDMI_GENERIC0_LINE, line); 225 break; 226 case 3: 227 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 228 HDMI_GENERIC1_CONT, cont, 229 HDMI_GENERIC1_SEND, send, 230 HDMI_GENERIC1_LINE, line); 231 break; 232 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 233 case 4: 234 if (REG(HDMI_GENERIC_PACKET_CONTROL2)) 235 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 236 HDMI_GENERIC0_CONT, cont, 237 HDMI_GENERIC0_SEND, send, 238 HDMI_GENERIC0_LINE, line); 239 break; 240 case 5: 241 if (REG(HDMI_GENERIC_PACKET_CONTROL2)) 242 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 243 HDMI_GENERIC1_CONT, cont, 244 HDMI_GENERIC1_SEND, send, 245 HDMI_GENERIC1_LINE, line); 246 break; 247 case 6: 248 if (REG(HDMI_GENERIC_PACKET_CONTROL3)) 249 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 250 HDMI_GENERIC0_CONT, cont, 251 HDMI_GENERIC0_SEND, send, 252 HDMI_GENERIC0_LINE, line); 253 break; 254 case 7: 255 if (REG(HDMI_GENERIC_PACKET_CONTROL3)) 256 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 257 HDMI_GENERIC1_CONT, cont, 258 HDMI_GENERIC1_SEND, send, 259 HDMI_GENERIC1_LINE, line); 260 break; 261 #endif 262 default: 263 /* invalid HW packet index */ 264 DC_LOG_WARNING( 265 "Invalid HW packet index: %s()\n", 266 __func__); 267 return; 268 } 269 } 270 271 /* setup stream encoder in dp mode */ 272 static void dce110_stream_encoder_dp_set_stream_attribute( 273 struct stream_encoder *enc, 274 struct dc_crtc_timing *crtc_timing, 275 enum dc_color_space output_color_space, 276 uint32_t enable_sdp_splitting) 277 { 278 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 279 uint32_t h_active_start; 280 uint32_t v_active_start; 281 uint32_t misc0 = 0; 282 uint32_t misc1 = 0; 283 uint32_t h_blank; 284 uint32_t h_back_porch; 285 uint8_t synchronous_clock = 0; /* asynchronous mode */ 286 uint8_t colorimetry_bpc; 287 uint8_t dynamic_range_rgb = 0; /*full range*/ 288 uint8_t dynamic_range_ycbcr = 1; /*bt709*/ 289 #endif 290 291 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 292 struct dc_crtc_timing hw_crtc_timing = *crtc_timing; 293 if (hw_crtc_timing.flags.INTERLACE) { 294 /*the input timing is in VESA spec format with Interlace flag =1*/ 295 hw_crtc_timing.v_total /= 2; 296 hw_crtc_timing.v_border_top /= 2; 297 hw_crtc_timing.v_addressable /= 2; 298 hw_crtc_timing.v_border_bottom /= 2; 299 hw_crtc_timing.v_front_porch /= 2; 300 hw_crtc_timing.v_sync_width /= 2; 301 } 302 /* set pixel encoding */ 303 switch (hw_crtc_timing.pixel_encoding) { 304 case PIXEL_ENCODING_YCBCR422: 305 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 306 DP_PIXEL_ENCODING_TYPE_YCBCR422); 307 break; 308 case PIXEL_ENCODING_YCBCR444: 309 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 310 DP_PIXEL_ENCODING_TYPE_YCBCR444); 311 312 if (hw_crtc_timing.flags.Y_ONLY) 313 if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666) 314 /* HW testing only, no use case yet. 315 * Color depth of Y-only could be 316 * 8, 10, 12, 16 bits */ 317 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 318 DP_PIXEL_ENCODING_TYPE_Y_ONLY); 319 /* Note: DP_MSA_MISC1 bit 7 is the indicator 320 * of Y-only mode. 321 * This bit is set in HW if register 322 * DP_PIXEL_ENCODING is programmed to 0x4 */ 323 break; 324 case PIXEL_ENCODING_YCBCR420: 325 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 326 DP_PIXEL_ENCODING_TYPE_YCBCR420); 327 if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN) 328 REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1); 329 330 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 331 if (enc110->se_mask->DP_VID_N_MUL) 332 REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1); 333 #endif 334 break; 335 default: 336 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 337 DP_PIXEL_ENCODING_TYPE_RGB444); 338 break; 339 } 340 341 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 342 if (REG(DP_MSA_MISC)) 343 misc1 = REG_READ(DP_MSA_MISC); 344 #endif 345 346 /* set color depth */ 347 348 switch (hw_crtc_timing.display_color_depth) { 349 case COLOR_DEPTH_666: 350 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 351 0); 352 break; 353 case COLOR_DEPTH_888: 354 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 355 DP_COMPONENT_PIXEL_DEPTH_8BPC); 356 break; 357 case COLOR_DEPTH_101010: 358 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 359 DP_COMPONENT_PIXEL_DEPTH_10BPC); 360 361 break; 362 case COLOR_DEPTH_121212: 363 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 364 DP_COMPONENT_PIXEL_DEPTH_12BPC); 365 break; 366 default: 367 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 368 DP_COMPONENT_PIXEL_DEPTH_6BPC); 369 break; 370 } 371 372 /* set dynamic range and YCbCr range */ 373 374 375 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 376 switch (hw_crtc_timing.display_color_depth) { 377 case COLOR_DEPTH_666: 378 colorimetry_bpc = 0; 379 break; 380 case COLOR_DEPTH_888: 381 colorimetry_bpc = 1; 382 break; 383 case COLOR_DEPTH_101010: 384 colorimetry_bpc = 2; 385 break; 386 case COLOR_DEPTH_121212: 387 colorimetry_bpc = 3; 388 break; 389 default: 390 colorimetry_bpc = 0; 391 break; 392 } 393 394 misc0 = misc0 | synchronous_clock; 395 misc0 = colorimetry_bpc << 5; 396 397 if (REG(DP_MSA_TIMING_PARAM1)) { 398 switch (output_color_space) { 399 case COLOR_SPACE_SRGB: 400 misc0 = misc0 | 0x0; 401 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 402 dynamic_range_rgb = 0; /*full range*/ 403 break; 404 case COLOR_SPACE_SRGB_LIMITED: 405 misc0 = misc0 | 0x8; /* bit3=1 */ 406 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 407 dynamic_range_rgb = 1; /*limited range*/ 408 break; 409 case COLOR_SPACE_YCBCR601: 410 case COLOR_SPACE_YCBCR601_LIMITED: 411 misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */ 412 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 413 dynamic_range_ycbcr = 0; /*bt601*/ 414 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 415 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 416 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444) 417 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 418 break; 419 case COLOR_SPACE_YCBCR709: 420 case COLOR_SPACE_YCBCR709_LIMITED: 421 case COLOR_SPACE_YCBCR709_BLACK: 422 misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */ 423 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 424 dynamic_range_ycbcr = 1; /*bt709*/ 425 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 426 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 427 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444) 428 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 429 break; 430 case COLOR_SPACE_2020_RGB_LIMITEDRANGE: 431 dynamic_range_rgb = 1; /*limited range*/ 432 break; 433 case COLOR_SPACE_2020_RGB_FULLRANGE: 434 case COLOR_SPACE_2020_YCBCR: 435 case COLOR_SPACE_XR_RGB: 436 case COLOR_SPACE_MSREF_SCRGB: 437 case COLOR_SPACE_ADOBERGB: 438 case COLOR_SPACE_DCIP3: 439 case COLOR_SPACE_XV_YCC_709: 440 case COLOR_SPACE_XV_YCC_601: 441 case COLOR_SPACE_DISPLAYNATIVE: 442 case COLOR_SPACE_DOLBYVISION: 443 case COLOR_SPACE_APPCTRL: 444 case COLOR_SPACE_CUSTOMPOINTS: 445 case COLOR_SPACE_UNKNOWN: 446 /* do nothing */ 447 break; 448 } 449 if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE) 450 REG_UPDATE_2( 451 DP_PIXEL_FORMAT, 452 DP_DYN_RANGE, dynamic_range_rgb, 453 DP_YCBCR_RANGE, dynamic_range_ycbcr); 454 455 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 456 if (REG(DP_MSA_COLORIMETRY)) 457 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0); 458 459 if (REG(DP_MSA_MISC)) 460 REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */ 461 462 /* dcn new register 463 * dc_crtc_timing is vesa dmt struct. data from edid 464 */ 465 if (REG(DP_MSA_TIMING_PARAM1)) 466 REG_SET_2(DP_MSA_TIMING_PARAM1, 0, 467 DP_MSA_HTOTAL, hw_crtc_timing.h_total, 468 DP_MSA_VTOTAL, hw_crtc_timing.v_total); 469 #endif 470 471 /* calcuate from vesa timing parameters 472 * h_active_start related to leading edge of sync 473 */ 474 475 h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left - 476 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right; 477 478 h_back_porch = h_blank - hw_crtc_timing.h_front_porch - 479 hw_crtc_timing.h_sync_width; 480 481 /* start at begining of left border */ 482 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch; 483 484 485 v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top - 486 hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom - 487 hw_crtc_timing.v_front_porch; 488 489 490 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 491 /* start at begining of left border */ 492 if (REG(DP_MSA_TIMING_PARAM2)) 493 REG_SET_2(DP_MSA_TIMING_PARAM2, 0, 494 DP_MSA_HSTART, h_active_start, 495 DP_MSA_VSTART, v_active_start); 496 497 if (REG(DP_MSA_TIMING_PARAM3)) 498 REG_SET_4(DP_MSA_TIMING_PARAM3, 0, 499 DP_MSA_HSYNCWIDTH, 500 hw_crtc_timing.h_sync_width, 501 DP_MSA_HSYNCPOLARITY, 502 !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY, 503 DP_MSA_VSYNCWIDTH, 504 hw_crtc_timing.v_sync_width, 505 DP_MSA_VSYNCPOLARITY, 506 !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY); 507 508 /* HWDITH include border or overscan */ 509 if (REG(DP_MSA_TIMING_PARAM4)) 510 REG_SET_2(DP_MSA_TIMING_PARAM4, 0, 511 DP_MSA_HWIDTH, hw_crtc_timing.h_border_left + 512 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right, 513 DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top + 514 hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom); 515 #endif 516 } 517 #endif 518 } 519 520 static void dce110_stream_encoder_set_stream_attribute_helper( 521 struct dce110_stream_encoder *enc110, 522 struct dc_crtc_timing *crtc_timing) 523 { 524 if (enc110->regs->TMDS_CNTL) { 525 switch (crtc_timing->pixel_encoding) { 526 case PIXEL_ENCODING_YCBCR422: 527 REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 1); 528 break; 529 default: 530 REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 0); 531 break; 532 } 533 REG_UPDATE(TMDS_CNTL, TMDS_COLOR_FORMAT, 0); 534 } else if (enc110->regs->DIG_FE_CNTL) { 535 switch (crtc_timing->pixel_encoding) { 536 case PIXEL_ENCODING_YCBCR422: 537 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1); 538 break; 539 default: 540 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0); 541 break; 542 } 543 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0); 544 } 545 546 } 547 548 /* setup stream encoder in hdmi mode */ 549 static void dce110_stream_encoder_hdmi_set_stream_attribute( 550 struct stream_encoder *enc, 551 struct dc_crtc_timing *crtc_timing, 552 int actual_pix_clk_khz, 553 bool enable_audio) 554 { 555 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 556 struct bp_encoder_control cntl = {0}; 557 558 cntl.action = ENCODER_CONTROL_SETUP; 559 cntl.engine_id = enc110->base.id; 560 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; 561 cntl.enable_dp_audio = enable_audio; 562 cntl.pixel_clock = actual_pix_clk_khz; 563 cntl.lanes_number = LANE_COUNT_FOUR; 564 565 if (enc110->base.bp->funcs->encoder_control( 566 enc110->base.bp, &cntl) != BP_RESULT_OK) 567 return; 568 569 dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing); 570 571 /* setup HDMI engine */ 572 if (!enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) { 573 REG_UPDATE_3(HDMI_CONTROL, 574 HDMI_PACKET_GEN_VERSION, 1, 575 HDMI_KEEPOUT_MODE, 1, 576 HDMI_DEEP_COLOR_ENABLE, 0); 577 } else if (enc110->regs->DIG_FE_CNTL) { 578 REG_UPDATE_5(HDMI_CONTROL, 579 HDMI_PACKET_GEN_VERSION, 1, 580 HDMI_KEEPOUT_MODE, 1, 581 HDMI_DEEP_COLOR_ENABLE, 0, 582 HDMI_DATA_SCRAMBLE_EN, 0, 583 HDMI_CLOCK_CHANNEL_RATE, 0); 584 } 585 586 switch (crtc_timing->display_color_depth) { 587 case COLOR_DEPTH_888: 588 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 589 break; 590 case COLOR_DEPTH_101010: 591 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 592 REG_UPDATE_2(HDMI_CONTROL, 593 HDMI_DEEP_COLOR_DEPTH, 1, 594 HDMI_DEEP_COLOR_ENABLE, 0); 595 } else { 596 REG_UPDATE_2(HDMI_CONTROL, 597 HDMI_DEEP_COLOR_DEPTH, 1, 598 HDMI_DEEP_COLOR_ENABLE, 1); 599 } 600 break; 601 case COLOR_DEPTH_121212: 602 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 603 REG_UPDATE_2(HDMI_CONTROL, 604 HDMI_DEEP_COLOR_DEPTH, 2, 605 HDMI_DEEP_COLOR_ENABLE, 0); 606 } else { 607 REG_UPDATE_2(HDMI_CONTROL, 608 HDMI_DEEP_COLOR_DEPTH, 2, 609 HDMI_DEEP_COLOR_ENABLE, 1); 610 } 611 break; 612 case COLOR_DEPTH_161616: 613 REG_UPDATE_2(HDMI_CONTROL, 614 HDMI_DEEP_COLOR_DEPTH, 3, 615 HDMI_DEEP_COLOR_ENABLE, 1); 616 break; 617 default: 618 break; 619 } 620 621 if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) { 622 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) { 623 /* enable HDMI data scrambler 624 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M 625 * Clock channel frequency is 1/4 of character rate. 626 */ 627 REG_UPDATE_2(HDMI_CONTROL, 628 HDMI_DATA_SCRAMBLE_EN, 1, 629 HDMI_CLOCK_CHANNEL_RATE, 1); 630 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) { 631 632 /* TODO: New feature for DCE11, still need to implement */ 633 634 /* enable HDMI data scrambler 635 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE 636 * Clock channel frequency is the same 637 * as character rate 638 */ 639 REG_UPDATE_2(HDMI_CONTROL, 640 HDMI_DATA_SCRAMBLE_EN, 1, 641 HDMI_CLOCK_CHANNEL_RATE, 0); 642 } 643 } 644 645 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL, 646 HDMI_GC_CONT, 1, 647 HDMI_GC_SEND, 1, 648 HDMI_NULL_SEND, 1); 649 650 /* following belongs to audio */ 651 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 652 653 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 654 655 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 656 VBI_LINE_0 + 2); 657 658 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); 659 660 } 661 662 /* setup stream encoder in dvi mode */ 663 static void dce110_stream_encoder_dvi_set_stream_attribute( 664 struct stream_encoder *enc, 665 struct dc_crtc_timing *crtc_timing, 666 bool is_dual_link) 667 { 668 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 669 struct bp_encoder_control cntl = {0}; 670 671 cntl.action = ENCODER_CONTROL_SETUP; 672 cntl.engine_id = enc110->base.id; 673 cntl.signal = is_dual_link ? 674 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK; 675 cntl.enable_dp_audio = false; 676 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10; 677 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; 678 679 if (enc110->base.bp->funcs->encoder_control( 680 enc110->base.bp, &cntl) != BP_RESULT_OK) 681 return; 682 683 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); 684 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888); 685 dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing); 686 } 687 688 /* setup stream encoder in LVDS mode */ 689 static void dce110_stream_encoder_lvds_set_stream_attribute( 690 struct stream_encoder *enc, 691 struct dc_crtc_timing *crtc_timing) 692 { 693 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 694 struct bp_encoder_control cntl = {0}; 695 696 cntl.action = ENCODER_CONTROL_SETUP; 697 cntl.engine_id = enc110->base.id; 698 cntl.signal = SIGNAL_TYPE_LVDS; 699 cntl.enable_dp_audio = false; 700 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10; 701 cntl.lanes_number = LANE_COUNT_FOUR; 702 703 if (enc110->base.bp->funcs->encoder_control( 704 enc110->base.bp, &cntl) != BP_RESULT_OK) 705 return; 706 707 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); 708 } 709 710 static void dce110_stream_encoder_set_mst_bandwidth( 711 struct stream_encoder *enc, 712 struct fixed31_32 avg_time_slots_per_mtp) 713 { 714 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 715 uint32_t x = dc_fixpt_floor( 716 avg_time_slots_per_mtp); 717 uint32_t y = dc_fixpt_ceil( 718 dc_fixpt_shl( 719 dc_fixpt_sub_int( 720 avg_time_slots_per_mtp, 721 x), 722 26)); 723 724 { 725 REG_SET_2(DP_MSE_RATE_CNTL, 0, 726 DP_MSE_RATE_X, x, 727 DP_MSE_RATE_Y, y); 728 } 729 730 /* wait for update to be completed on the link */ 731 /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */ 732 /* is reset to 0 (not pending) */ 733 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, 734 0, 735 10, DP_MST_UPDATE_MAX_RETRY); 736 } 737 738 static void dce110_stream_encoder_update_hdmi_info_packets( 739 struct stream_encoder *enc, 740 const struct encoder_info_frame *info_frame) 741 { 742 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 743 744 if (enc110->se_mask->HDMI_AVI_INFO_CONT && 745 enc110->se_mask->HDMI_AVI_INFO_SEND) { 746 747 if (info_frame->avi.valid) { 748 const uint32_t *content = 749 (const uint32_t *) &info_frame->avi.sb[0]; 750 /*we need turn on clock before programming AFMT block*/ 751 if (REG(AFMT_CNTL)) 752 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 753 754 REG_WRITE(AFMT_AVI_INFO0, content[0]); 755 756 REG_WRITE(AFMT_AVI_INFO1, content[1]); 757 758 REG_WRITE(AFMT_AVI_INFO2, content[2]); 759 760 REG_WRITE(AFMT_AVI_INFO3, content[3]); 761 762 REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, 763 info_frame->avi.hb1); 764 765 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0, 766 HDMI_AVI_INFO_SEND, 1, 767 HDMI_AVI_INFO_CONT, 1); 768 769 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 770 VBI_LINE_0 + 2); 771 772 } else { 773 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0, 774 HDMI_AVI_INFO_SEND, 0, 775 HDMI_AVI_INFO_CONT, 0); 776 } 777 } 778 779 if (enc110->se_mask->HDMI_AVI_INFO_CONT && 780 enc110->se_mask->HDMI_AVI_INFO_SEND) { 781 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor); 782 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut); 783 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd); 784 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd); 785 } 786 787 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 788 if (enc110->se_mask->HDMI_DB_DISABLE) { 789 /* for bring up, disable dp double TODO */ 790 if (REG(HDMI_DB_CONTROL)) 791 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); 792 793 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->avi); 794 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->vendor); 795 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->gamut); 796 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->spd); 797 dce110_update_hdmi_info_packet(enc110, 4, &info_frame->hdrsmd); 798 } 799 #endif 800 } 801 802 static void dce110_stream_encoder_stop_hdmi_info_packets( 803 struct stream_encoder *enc) 804 { 805 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 806 807 /* stop generic packets 0 & 1 on HDMI */ 808 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0, 809 HDMI_GENERIC1_CONT, 0, 810 HDMI_GENERIC1_LINE, 0, 811 HDMI_GENERIC1_SEND, 0, 812 HDMI_GENERIC0_CONT, 0, 813 HDMI_GENERIC0_LINE, 0, 814 HDMI_GENERIC0_SEND, 0); 815 816 /* stop generic packets 2 & 3 on HDMI */ 817 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0, 818 HDMI_GENERIC0_CONT, 0, 819 HDMI_GENERIC0_LINE, 0, 820 HDMI_GENERIC0_SEND, 0, 821 HDMI_GENERIC1_CONT, 0, 822 HDMI_GENERIC1_LINE, 0, 823 HDMI_GENERIC1_SEND, 0); 824 825 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 826 /* stop generic packets 2 & 3 on HDMI */ 827 if (REG(HDMI_GENERIC_PACKET_CONTROL2)) 828 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0, 829 HDMI_GENERIC0_CONT, 0, 830 HDMI_GENERIC0_LINE, 0, 831 HDMI_GENERIC0_SEND, 0, 832 HDMI_GENERIC1_CONT, 0, 833 HDMI_GENERIC1_LINE, 0, 834 HDMI_GENERIC1_SEND, 0); 835 836 if (REG(HDMI_GENERIC_PACKET_CONTROL3)) 837 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0, 838 HDMI_GENERIC0_CONT, 0, 839 HDMI_GENERIC0_LINE, 0, 840 HDMI_GENERIC0_SEND, 0, 841 HDMI_GENERIC1_CONT, 0, 842 HDMI_GENERIC1_LINE, 0, 843 HDMI_GENERIC1_SEND, 0); 844 #endif 845 } 846 847 static void dce110_stream_encoder_update_dp_info_packets( 848 struct stream_encoder *enc, 849 const struct encoder_info_frame *info_frame) 850 { 851 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 852 uint32_t value = 0; 853 854 if (info_frame->vsc.valid) 855 dce110_update_generic_info_packet( 856 enc110, 857 0, /* packetIndex */ 858 &info_frame->vsc); 859 860 if (info_frame->spd.valid) 861 dce110_update_generic_info_packet( 862 enc110, 863 2, /* packetIndex */ 864 &info_frame->spd); 865 866 if (info_frame->hdrsmd.valid) 867 dce110_update_generic_info_packet( 868 enc110, 869 3, /* packetIndex */ 870 &info_frame->hdrsmd); 871 872 /* enable/disable transmission of packet(s). 873 * If enabled, packet transmission begins on the next frame 874 */ 875 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); 876 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); 877 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); 878 879 /* This bit is the master enable bit. 880 * When enabling secondary stream engine, 881 * this master bit must also be set. 882 * This register shared with audio info frame. 883 * Therefore we need to enable master bit 884 * if at least on of the fields is not 0 885 */ 886 value = REG_READ(DP_SEC_CNTL); 887 if (value) 888 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 889 } 890 891 static void dce110_stream_encoder_stop_dp_info_packets( 892 struct stream_encoder *enc) 893 { 894 /* stop generic packets on DP */ 895 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 896 uint32_t value = 0; 897 898 if (enc110->se_mask->DP_SEC_AVI_ENABLE) { 899 REG_SET_7(DP_SEC_CNTL, 0, 900 DP_SEC_GSP0_ENABLE, 0, 901 DP_SEC_GSP1_ENABLE, 0, 902 DP_SEC_GSP2_ENABLE, 0, 903 DP_SEC_GSP3_ENABLE, 0, 904 DP_SEC_AVI_ENABLE, 0, 905 DP_SEC_MPG_ENABLE, 0, 906 DP_SEC_STREAM_ENABLE, 0); 907 } 908 909 /* this register shared with audio info frame. 910 * therefore we need to keep master enabled 911 * if at least one of the fields is not 0 */ 912 value = REG_READ(DP_SEC_CNTL); 913 if (value) 914 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 915 916 } 917 918 static void dce110_stream_encoder_dp_blank( 919 struct stream_encoder *enc) 920 { 921 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 922 uint32_t reg1 = 0; 923 uint32_t max_retries = DP_BLANK_MAX_RETRY * 10; 924 925 /* Note: For CZ, we are changing driver default to disable 926 * stream deferred to next VBLANK. If results are positive, we 927 * will make the same change to all DCE versions. There are a 928 * handful of panels that cannot handle disable stream at 929 * HBLANK and will result in a white line flash across the 930 * screen on stream disable. */ 931 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1); 932 if ((reg1 & 0x1) == 0) 933 /*stream not enabled*/ 934 return; 935 /* Specify the video stream disable point 936 * (2 = start of the next vertical blank) */ 937 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2); 938 /* Larger delay to wait until VBLANK - use max retry of 939 * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode + 940 * a little more because we may not trust delay accuracy. 941 */ 942 max_retries = DP_BLANK_MAX_RETRY * 150; 943 944 /* disable DP stream */ 945 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); 946 947 /* the encoder stops sending the video stream 948 * at the start of the vertical blanking. 949 * Poll for DP_VID_STREAM_STATUS == 0 950 */ 951 952 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 953 0, 954 10, max_retries); 955 956 /* Tell the DP encoder to ignore timing from CRTC, must be done after 957 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is 958 * complete, stream status will be stuck in video stream enabled state, 959 * i.e. DP_VID_STREAM_STATUS stuck at 1. 960 */ 961 962 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true); 963 } 964 965 /* output video stream to link encoder */ 966 static void dce110_stream_encoder_dp_unblank( 967 struct stream_encoder *enc, 968 const struct encoder_unblank_param *param) 969 { 970 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 971 972 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) { 973 uint32_t n_vid = 0x8000; 974 uint32_t m_vid; 975 976 /* M / N = Fstream / Flink 977 * m_vid / n_vid = pixel rate / link rate 978 */ 979 980 uint64_t m_vid_l = n_vid; 981 982 m_vid_l *= param->timing.pix_clk_100hz / 10; 983 m_vid_l = div_u64(m_vid_l, 984 param->link_settings.link_rate 985 * LINK_RATE_REF_FREQ_IN_KHZ); 986 987 m_vid = (uint32_t) m_vid_l; 988 989 /* enable auto measurement */ 990 991 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0); 992 993 /* auto measurement need 1 full 0x8000 symbol cycle to kick in, 994 * therefore program initial value for Mvid and Nvid 995 */ 996 997 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid); 998 999 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid); 1000 1001 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1); 1002 } 1003 1004 /* set DIG_START to 0x1 to resync FIFO */ 1005 1006 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); 1007 1008 /* switch DP encoder to CRTC data */ 1009 1010 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); 1011 1012 /* wait 100us for DIG/DP logic to prime 1013 * (i.e. a few video lines) 1014 */ 1015 udelay(100); 1016 1017 /* the hardware would start sending video at the start of the next DP 1018 * frame (i.e. rising edge of the vblank). 1019 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this 1020 * register has no effect on enable transition! HW always guarantees 1021 * VID_STREAM enable at start of next frame, and this is not 1022 * programmable 1023 */ 1024 1025 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); 1026 } 1027 1028 static void dce110_stream_encoder_set_avmute( 1029 struct stream_encoder *enc, 1030 bool enable) 1031 { 1032 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1033 unsigned int value = enable ? 1 : 0; 1034 1035 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value); 1036 } 1037 1038 1039 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000 1040 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1 1041 1042 #include "include/audio_types.h" 1043 1044 /** 1045 * speakersToChannels 1046 * 1047 * @brief 1048 * translate speakers to channels 1049 * 1050 * FL - Front Left 1051 * FR - Front Right 1052 * RL - Rear Left 1053 * RR - Rear Right 1054 * RC - Rear Center 1055 * FC - Front Center 1056 * FLC - Front Left Center 1057 * FRC - Front Right Center 1058 * RLC - Rear Left Center 1059 * RRC - Rear Right Center 1060 * LFE - Low Freq Effect 1061 * 1062 * FC 1063 * FLC FRC 1064 * FL FR 1065 * 1066 * LFE 1067 * () 1068 * 1069 * 1070 * RL RR 1071 * RLC RRC 1072 * RC 1073 * 1074 * ch 8 7 6 5 4 3 2 1 1075 * 0b00000011 - - - - - - FR FL 1076 * 0b00000111 - - - - - LFE FR FL 1077 * 0b00001011 - - - - FC - FR FL 1078 * 0b00001111 - - - - FC LFE FR FL 1079 * 0b00010011 - - - RC - - FR FL 1080 * 0b00010111 - - - RC - LFE FR FL 1081 * 0b00011011 - - - RC FC - FR FL 1082 * 0b00011111 - - - RC FC LFE FR FL 1083 * 0b00110011 - - RR RL - - FR FL 1084 * 0b00110111 - - RR RL - LFE FR FL 1085 * 0b00111011 - - RR RL FC - FR FL 1086 * 0b00111111 - - RR RL FC LFE FR FL 1087 * 0b01110011 - RC RR RL - - FR FL 1088 * 0b01110111 - RC RR RL - LFE FR FL 1089 * 0b01111011 - RC RR RL FC - FR FL 1090 * 0b01111111 - RC RR RL FC LFE FR FL 1091 * 0b11110011 RRC RLC RR RL - - FR FL 1092 * 0b11110111 RRC RLC RR RL - LFE FR FL 1093 * 0b11111011 RRC RLC RR RL FC - FR FL 1094 * 0b11111111 RRC RLC RR RL FC LFE FR FL 1095 * 0b11000011 FRC FLC - - - - FR FL 1096 * 0b11000111 FRC FLC - - - LFE FR FL 1097 * 0b11001011 FRC FLC - - FC - FR FL 1098 * 0b11001111 FRC FLC - - FC LFE FR FL 1099 * 0b11010011 FRC FLC - RC - - FR FL 1100 * 0b11010111 FRC FLC - RC - LFE FR FL 1101 * 0b11011011 FRC FLC - RC FC - FR FL 1102 * 0b11011111 FRC FLC - RC FC LFE FR FL 1103 * 0b11110011 FRC FLC RR RL - - FR FL 1104 * 0b11110111 FRC FLC RR RL - LFE FR FL 1105 * 0b11111011 FRC FLC RR RL FC - FR FL 1106 * 0b11111111 FRC FLC RR RL FC LFE FR FL 1107 * 1108 * @param 1109 * speakers - speaker information as it comes from CEA audio block 1110 */ 1111 /* translate speakers to channels */ 1112 1113 union audio_cea_channels { 1114 uint8_t all; 1115 struct audio_cea_channels_bits { 1116 uint32_t FL:1; 1117 uint32_t FR:1; 1118 uint32_t LFE:1; 1119 uint32_t FC:1; 1120 uint32_t RL_RC:1; 1121 uint32_t RR:1; 1122 uint32_t RC_RLC_FLC:1; 1123 uint32_t RRC_FRC:1; 1124 } channels; 1125 }; 1126 1127 /* 25.2MHz/1.001*/ 1128 /* 25.2MHz/1.001*/ 1129 /* 25.2MHz*/ 1130 /* 27MHz */ 1131 /* 27MHz*1.001*/ 1132 /* 27MHz*1.001*/ 1133 /* 54MHz*/ 1134 /* 54MHz*1.001*/ 1135 /* 74.25MHz/1.001*/ 1136 /* 74.25MHz*/ 1137 /* 148.5MHz/1.001*/ 1138 /* 148.5MHz*/ 1139 1140 static const struct audio_clock_info audio_clock_info_table[16] = { 1141 {2517, 4576, 28125, 7007, 31250, 6864, 28125}, 1142 {2518, 4576, 28125, 7007, 31250, 6864, 28125}, 1143 {2520, 4096, 25200, 6272, 28000, 6144, 25200}, 1144 {2700, 4096, 27000, 6272, 30000, 6144, 27000}, 1145 {2702, 4096, 27027, 6272, 30030, 6144, 27027}, 1146 {2703, 4096, 27027, 6272, 30030, 6144, 27027}, 1147 {5400, 4096, 54000, 6272, 60000, 6144, 54000}, 1148 {5405, 4096, 54054, 6272, 60060, 6144, 54054}, 1149 {7417, 11648, 210937, 17836, 234375, 11648, 140625}, 1150 {7425, 4096, 74250, 6272, 82500, 6144, 74250}, 1151 {14835, 11648, 421875, 8918, 234375, 5824, 140625}, 1152 {14850, 4096, 148500, 6272, 165000, 6144, 148500}, 1153 {29670, 5824, 421875, 4459, 234375, 5824, 281250}, 1154 {29700, 3072, 222750, 4704, 247500, 5120, 247500}, 1155 {59340, 5824, 843750, 8918, 937500, 5824, 562500}, 1156 {59400, 3072, 445500, 9408, 990000, 6144, 594000} 1157 }; 1158 1159 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = { 1160 {2517, 9152, 84375, 7007, 48875, 9152, 56250}, 1161 {2518, 9152, 84375, 7007, 48875, 9152, 56250}, 1162 {2520, 4096, 37800, 6272, 42000, 6144, 37800}, 1163 {2700, 4096, 40500, 6272, 45000, 6144, 40500}, 1164 {2702, 8192, 81081, 6272, 45045, 8192, 54054}, 1165 {2703, 8192, 81081, 6272, 45045, 8192, 54054}, 1166 {5400, 4096, 81000, 6272, 90000, 6144, 81000}, 1167 {5405, 4096, 81081, 6272, 90090, 6144, 81081}, 1168 {7417, 11648, 316406, 17836, 351562, 11648, 210937}, 1169 {7425, 4096, 111375, 6272, 123750, 6144, 111375}, 1170 {14835, 11648, 632812, 17836, 703125, 11648, 421875}, 1171 {14850, 4096, 222750, 6272, 247500, 6144, 222750}, 1172 {29670, 5824, 632812, 8918, 703125, 5824, 421875}, 1173 {29700, 4096, 445500, 4704, 371250, 5120, 371250} 1174 }; 1175 1176 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = { 1177 {2517, 4576, 56250, 7007, 62500, 6864, 56250}, 1178 {2518, 4576, 56250, 7007, 62500, 6864, 56250}, 1179 {2520, 4096, 50400, 6272, 56000, 6144, 50400}, 1180 {2700, 4096, 54000, 6272, 60000, 6144, 54000}, 1181 {2702, 4096, 54054, 6267, 60060, 8192, 54054}, 1182 {2703, 4096, 54054, 6272, 60060, 8192, 54054}, 1183 {5400, 4096, 108000, 6272, 120000, 6144, 108000}, 1184 {5405, 4096, 108108, 6272, 120120, 6144, 108108}, 1185 {7417, 11648, 421875, 17836, 468750, 11648, 281250}, 1186 {7425, 4096, 148500, 6272, 165000, 6144, 148500}, 1187 {14835, 11648, 843750, 8918, 468750, 11648, 281250}, 1188 {14850, 4096, 297000, 6272, 330000, 6144, 297000}, 1189 {29670, 5824, 843750, 4459, 468750, 5824, 562500}, 1190 {29700, 3072, 445500, 4704, 495000, 5120, 495000} 1191 1192 1193 }; 1194 1195 static union audio_cea_channels speakers_to_channels( 1196 struct audio_speaker_flags speaker_flags) 1197 { 1198 union audio_cea_channels cea_channels = {0}; 1199 1200 /* these are one to one */ 1201 cea_channels.channels.FL = speaker_flags.FL_FR; 1202 cea_channels.channels.FR = speaker_flags.FL_FR; 1203 cea_channels.channels.LFE = speaker_flags.LFE; 1204 cea_channels.channels.FC = speaker_flags.FC; 1205 1206 /* if Rear Left and Right exist move RC speaker to channel 7 1207 * otherwise to channel 5 1208 */ 1209 if (speaker_flags.RL_RR) { 1210 cea_channels.channels.RL_RC = speaker_flags.RL_RR; 1211 cea_channels.channels.RR = speaker_flags.RL_RR; 1212 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC; 1213 } else { 1214 cea_channels.channels.RL_RC = speaker_flags.RC; 1215 } 1216 1217 /* FRONT Left Right Center and REAR Left Right Center are exclusive */ 1218 if (speaker_flags.FLC_FRC) { 1219 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC; 1220 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC; 1221 } else { 1222 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC; 1223 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC; 1224 } 1225 1226 return cea_channels; 1227 } 1228 1229 static uint32_t calc_max_audio_packets_per_line( 1230 const struct audio_crtc_info *crtc_info) 1231 { 1232 uint32_t max_packets_per_line; 1233 1234 max_packets_per_line = 1235 crtc_info->h_total - crtc_info->h_active; 1236 1237 if (crtc_info->pixel_repetition) 1238 max_packets_per_line *= crtc_info->pixel_repetition; 1239 1240 /* for other hdmi features */ 1241 max_packets_per_line -= 58; 1242 /* for Control Period */ 1243 max_packets_per_line -= 16; 1244 /* Number of Audio Packets per Line */ 1245 max_packets_per_line /= 32; 1246 1247 return max_packets_per_line; 1248 } 1249 1250 static void get_audio_clock_info( 1251 enum dc_color_depth color_depth, 1252 uint32_t crtc_pixel_clock_in_khz, 1253 uint32_t actual_pixel_clock_in_khz, 1254 struct audio_clock_info *audio_clock_info) 1255 { 1256 const struct audio_clock_info *clock_info; 1257 uint32_t index; 1258 uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10; 1259 uint32_t audio_array_size; 1260 1261 switch (color_depth) { 1262 case COLOR_DEPTH_161616: 1263 clock_info = audio_clock_info_table_48bpc; 1264 audio_array_size = ARRAY_SIZE( 1265 audio_clock_info_table_48bpc); 1266 break; 1267 case COLOR_DEPTH_121212: 1268 clock_info = audio_clock_info_table_36bpc; 1269 audio_array_size = ARRAY_SIZE( 1270 audio_clock_info_table_36bpc); 1271 break; 1272 default: 1273 clock_info = audio_clock_info_table; 1274 audio_array_size = ARRAY_SIZE( 1275 audio_clock_info_table); 1276 break; 1277 } 1278 1279 if (clock_info != NULL) { 1280 /* search for exact pixel clock in table */ 1281 for (index = 0; index < audio_array_size; index++) { 1282 if (clock_info[index].pixel_clock_in_10khz > 1283 crtc_pixel_clock_in_10khz) 1284 break; /* not match */ 1285 else if (clock_info[index].pixel_clock_in_10khz == 1286 crtc_pixel_clock_in_10khz) { 1287 /* match found */ 1288 *audio_clock_info = clock_info[index]; 1289 return; 1290 } 1291 } 1292 } 1293 1294 /* not found */ 1295 if (actual_pixel_clock_in_khz == 0) 1296 actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz; 1297 1298 /* See HDMI spec the table entry under 1299 * pixel clock of "Other". */ 1300 audio_clock_info->pixel_clock_in_10khz = 1301 actual_pixel_clock_in_khz / 10; 1302 audio_clock_info->cts_32khz = actual_pixel_clock_in_khz; 1303 audio_clock_info->cts_44khz = actual_pixel_clock_in_khz; 1304 audio_clock_info->cts_48khz = actual_pixel_clock_in_khz; 1305 1306 audio_clock_info->n_32khz = 4096; 1307 audio_clock_info->n_44khz = 6272; 1308 audio_clock_info->n_48khz = 6144; 1309 } 1310 1311 static void dce110_se_audio_setup( 1312 struct stream_encoder *enc, 1313 unsigned int az_inst, 1314 struct audio_info *audio_info) 1315 { 1316 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1317 1318 uint32_t speakers = 0; 1319 uint32_t channels = 0; 1320 1321 ASSERT(audio_info); 1322 if (audio_info == NULL) 1323 /* This should not happen.it does so we don't get BSOD*/ 1324 return; 1325 1326 speakers = audio_info->flags.info.ALLSPEAKERS; 1327 channels = speakers_to_channels(audio_info->flags.speaker_flags).all; 1328 1329 /* setup the audio stream source select (audio -> dig mapping) */ 1330 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst); 1331 1332 /* Channel allocation */ 1333 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels); 1334 } 1335 1336 static void dce110_se_setup_hdmi_audio( 1337 struct stream_encoder *enc, 1338 const struct audio_crtc_info *crtc_info) 1339 { 1340 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1341 1342 struct audio_clock_info audio_clock_info = {0}; 1343 uint32_t max_packets_per_line; 1344 1345 /* For now still do calculation, although this field is ignored when 1346 above HDMI_PACKET_GEN_VERSION set to 1 */ 1347 max_packets_per_line = calc_max_audio_packets_per_line(crtc_info); 1348 1349 /* HDMI_AUDIO_PACKET_CONTROL */ 1350 REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL, 1351 HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line, 1352 HDMI_AUDIO_DELAY_EN, 1); 1353 1354 /* AFMT_AUDIO_PACKET_CONTROL */ 1355 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1356 1357 /* AFMT_AUDIO_PACKET_CONTROL2 */ 1358 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 1359 AFMT_AUDIO_LAYOUT_OVRD, 0, 1360 AFMT_60958_OSF_OVRD, 0); 1361 1362 /* HDMI_ACR_PACKET_CONTROL */ 1363 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, 1364 HDMI_ACR_AUTO_SEND, 1, 1365 HDMI_ACR_SOURCE, 0, 1366 HDMI_ACR_AUDIO_PRIORITY, 0); 1367 1368 /* Program audio clock sample/regeneration parameters */ 1369 get_audio_clock_info(crtc_info->color_depth, 1370 crtc_info->requested_pixel_clock, 1371 crtc_info->calculated_pixel_clock, 1372 &audio_clock_info); 1373 DC_LOG_HW_AUDIO( 1374 "\n%s:Input::requested_pixel_clock = %d" \ 1375 "calculated_pixel_clock = %d \n", __func__, \ 1376 crtc_info->requested_pixel_clock, \ 1377 crtc_info->calculated_pixel_clock); 1378 1379 /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */ 1380 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); 1381 1382 /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */ 1383 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); 1384 1385 /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */ 1386 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz); 1387 1388 /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */ 1389 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); 1390 1391 /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */ 1392 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); 1393 1394 /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */ 1395 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz); 1396 1397 /* Video driver cannot know in advance which sample rate will 1398 be used by HD Audio driver 1399 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is 1400 programmed below in interruppt callback */ 1401 1402 /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK & 1403 AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */ 1404 REG_UPDATE_2(AFMT_60958_0, 1405 AFMT_60958_CS_CHANNEL_NUMBER_L, 1, 1406 AFMT_60958_CS_CLOCK_ACCURACY, 0); 1407 1408 /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */ 1409 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1410 1411 /*AFMT_60958_2 now keep this settings until 1412 * Programming guide comes out*/ 1413 REG_UPDATE_6(AFMT_60958_2, 1414 AFMT_60958_CS_CHANNEL_NUMBER_2, 3, 1415 AFMT_60958_CS_CHANNEL_NUMBER_3, 4, 1416 AFMT_60958_CS_CHANNEL_NUMBER_4, 5, 1417 AFMT_60958_CS_CHANNEL_NUMBER_5, 6, 1418 AFMT_60958_CS_CHANNEL_NUMBER_6, 7, 1419 AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1420 } 1421 1422 static void dce110_se_setup_dp_audio( 1423 struct stream_encoder *enc) 1424 { 1425 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1426 1427 /* --- DP Audio packet configurations --- */ 1428 1429 /* ATP Configuration */ 1430 REG_SET(DP_SEC_AUD_N, 0, 1431 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT); 1432 1433 /* Async/auto-calc timestamp mode */ 1434 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE, 1435 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC); 1436 1437 /* --- The following are the registers 1438 * copied from the SetupHDMI --- */ 1439 1440 /* AFMT_AUDIO_PACKET_CONTROL */ 1441 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1442 1443 /* AFMT_AUDIO_PACKET_CONTROL2 */ 1444 /* Program the ATP and AIP next */ 1445 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 1446 AFMT_AUDIO_LAYOUT_OVRD, 0, 1447 AFMT_60958_OSF_OVRD, 0); 1448 1449 /* AFMT_INFOFRAME_CONTROL0 */ 1450 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1451 1452 /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */ 1453 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0); 1454 } 1455 1456 static void dce110_se_enable_audio_clock( 1457 struct stream_encoder *enc, 1458 bool enable) 1459 { 1460 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1461 1462 if (REG(AFMT_CNTL) == 0) 1463 return; /* DCE8/10 does not have this register */ 1464 1465 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable); 1466 1467 /* wait for AFMT clock to turn on, 1468 * expectation: this should complete in 1-2 reads 1469 * 1470 * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10); 1471 * 1472 * TODO: wait for clock_on does not work well. May need HW 1473 * program sequence. But audio seems work normally even without wait 1474 * for clock_on status change 1475 */ 1476 } 1477 1478 static void dce110_se_enable_dp_audio( 1479 struct stream_encoder *enc) 1480 { 1481 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1482 1483 /* Enable Audio packets */ 1484 REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); 1485 1486 /* Program the ATP and AIP next */ 1487 REG_UPDATE_2(DP_SEC_CNTL, 1488 DP_SEC_ATP_ENABLE, 1, 1489 DP_SEC_AIP_ENABLE, 1); 1490 1491 /* Program STREAM_ENABLE after all the other enables. */ 1492 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1493 } 1494 1495 static void dce110_se_disable_dp_audio( 1496 struct stream_encoder *enc) 1497 { 1498 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1499 uint32_t value = 0; 1500 1501 /* Disable Audio packets */ 1502 REG_UPDATE_5(DP_SEC_CNTL, 1503 DP_SEC_ASP_ENABLE, 0, 1504 DP_SEC_ATP_ENABLE, 0, 1505 DP_SEC_AIP_ENABLE, 0, 1506 DP_SEC_ACM_ENABLE, 0, 1507 DP_SEC_STREAM_ENABLE, 0); 1508 1509 /* This register shared with encoder info frame. Therefore we need to 1510 keep master enabled if at least on of the fields is not 0 */ 1511 value = REG_READ(DP_SEC_CNTL); 1512 if (value != 0) 1513 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1514 1515 } 1516 1517 void dce110_se_audio_mute_control( 1518 struct stream_encoder *enc, 1519 bool mute) 1520 { 1521 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1522 1523 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute); 1524 } 1525 1526 void dce110_se_dp_audio_setup( 1527 struct stream_encoder *enc, 1528 unsigned int az_inst, 1529 struct audio_info *info) 1530 { 1531 dce110_se_audio_setup(enc, az_inst, info); 1532 } 1533 1534 void dce110_se_dp_audio_enable( 1535 struct stream_encoder *enc) 1536 { 1537 dce110_se_enable_audio_clock(enc, true); 1538 dce110_se_setup_dp_audio(enc); 1539 dce110_se_enable_dp_audio(enc); 1540 } 1541 1542 void dce110_se_dp_audio_disable( 1543 struct stream_encoder *enc) 1544 { 1545 dce110_se_disable_dp_audio(enc); 1546 dce110_se_enable_audio_clock(enc, false); 1547 } 1548 1549 void dce110_se_hdmi_audio_setup( 1550 struct stream_encoder *enc, 1551 unsigned int az_inst, 1552 struct audio_info *info, 1553 struct audio_crtc_info *audio_crtc_info) 1554 { 1555 dce110_se_enable_audio_clock(enc, true); 1556 dce110_se_setup_hdmi_audio(enc, audio_crtc_info); 1557 dce110_se_audio_setup(enc, az_inst, info); 1558 } 1559 1560 void dce110_se_hdmi_audio_disable( 1561 struct stream_encoder *enc) 1562 { 1563 dce110_se_enable_audio_clock(enc, false); 1564 } 1565 1566 1567 static void setup_stereo_sync( 1568 struct stream_encoder *enc, 1569 int tg_inst, bool enable) 1570 { 1571 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1572 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); 1573 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable); 1574 } 1575 1576 static void dig_connect_to_otg( 1577 struct stream_encoder *enc, 1578 int tg_inst) 1579 { 1580 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1581 1582 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); 1583 } 1584 1585 static const struct stream_encoder_funcs dce110_str_enc_funcs = { 1586 .dp_set_stream_attribute = 1587 dce110_stream_encoder_dp_set_stream_attribute, 1588 .hdmi_set_stream_attribute = 1589 dce110_stream_encoder_hdmi_set_stream_attribute, 1590 .dvi_set_stream_attribute = 1591 dce110_stream_encoder_dvi_set_stream_attribute, 1592 .lvds_set_stream_attribute = 1593 dce110_stream_encoder_lvds_set_stream_attribute, 1594 .set_mst_bandwidth = 1595 dce110_stream_encoder_set_mst_bandwidth, 1596 .update_hdmi_info_packets = 1597 dce110_stream_encoder_update_hdmi_info_packets, 1598 .stop_hdmi_info_packets = 1599 dce110_stream_encoder_stop_hdmi_info_packets, 1600 .update_dp_info_packets = 1601 dce110_stream_encoder_update_dp_info_packets, 1602 .stop_dp_info_packets = 1603 dce110_stream_encoder_stop_dp_info_packets, 1604 .dp_blank = 1605 dce110_stream_encoder_dp_blank, 1606 .dp_unblank = 1607 dce110_stream_encoder_dp_unblank, 1608 .audio_mute_control = dce110_se_audio_mute_control, 1609 1610 .dp_audio_setup = dce110_se_dp_audio_setup, 1611 .dp_audio_enable = dce110_se_dp_audio_enable, 1612 .dp_audio_disable = dce110_se_dp_audio_disable, 1613 1614 .hdmi_audio_setup = dce110_se_hdmi_audio_setup, 1615 .hdmi_audio_disable = dce110_se_hdmi_audio_disable, 1616 .setup_stereo_sync = setup_stereo_sync, 1617 .set_avmute = dce110_stream_encoder_set_avmute, 1618 .dig_connect_to_otg = dig_connect_to_otg, 1619 }; 1620 1621 void dce110_stream_encoder_construct( 1622 struct dce110_stream_encoder *enc110, 1623 struct dc_context *ctx, 1624 struct dc_bios *bp, 1625 enum engine_id eng_id, 1626 const struct dce110_stream_enc_registers *regs, 1627 const struct dce_stream_encoder_shift *se_shift, 1628 const struct dce_stream_encoder_mask *se_mask) 1629 { 1630 enc110->base.funcs = &dce110_str_enc_funcs; 1631 enc110->base.ctx = ctx; 1632 enc110->base.id = eng_id; 1633 enc110->base.bp = bp; 1634 enc110->regs = regs; 1635 enc110->se_shift = se_shift; 1636 enc110->se_mask = se_mask; 1637 } 1638