1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dc_bios_types.h" 27 #include "dce_stream_encoder.h" 28 #include "reg_helper.h" 29 30 enum DP_PIXEL_ENCODING { 31 DP_PIXEL_ENCODING_RGB444 = 0x00000000, 32 DP_PIXEL_ENCODING_YCBCR422 = 0x00000001, 33 DP_PIXEL_ENCODING_YCBCR444 = 0x00000002, 34 DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x00000003, 35 DP_PIXEL_ENCODING_Y_ONLY = 0x00000004, 36 DP_PIXEL_ENCODING_YCBCR420 = 0x00000005, 37 DP_PIXEL_ENCODING_RESERVED = 0x00000006, 38 }; 39 40 41 enum DP_COMPONENT_DEPTH { 42 DP_COMPONENT_DEPTH_6BPC = 0x00000000, 43 DP_COMPONENT_DEPTH_8BPC = 0x00000001, 44 DP_COMPONENT_DEPTH_10BPC = 0x00000002, 45 DP_COMPONENT_DEPTH_12BPC = 0x00000003, 46 DP_COMPONENT_DEPTH_16BPC = 0x00000004, 47 DP_COMPONENT_DEPTH_RESERVED = 0x00000005, 48 }; 49 50 51 #define REG(reg)\ 52 (enc110->regs->reg) 53 54 #undef FN 55 #define FN(reg_name, field_name) \ 56 enc110->se_shift->field_name, enc110->se_mask->field_name 57 58 #define VBI_LINE_0 0 59 #define DP_BLANK_MAX_RETRY 20 60 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 61 62 #ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 63 #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x00000010L 64 #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x00000300L 65 #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x00000004 66 #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x00000008 67 #endif 68 69 enum { 70 DP_MST_UPDATE_MAX_RETRY = 50 71 }; 72 73 #define DCE110_SE(audio)\ 74 container_of(audio, struct dce110_stream_encoder, base) 75 76 #define CTX \ 77 enc110->base.ctx 78 79 static void dce110_update_generic_info_packet( 80 struct dce110_stream_encoder *enc110, 81 uint32_t packet_index, 82 const struct encoder_info_packet *info_packet) 83 { 84 uint32_t regval; 85 /* TODOFPGA Figure out a proper number for max_retries polling for lock 86 * use 50 for now. 87 */ 88 uint32_t max_retries = 50; 89 90 /*we need turn on clock before programming AFMT block*/ 91 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 92 93 if (REG(AFMT_VBI_PACKET_CONTROL1)) { 94 if (packet_index >= 8) 95 ASSERT(0); 96 97 /* poll dig_update_lock is not locked -> asic internal signal 98 * assume otg master lock will unlock it 99 */ 100 /* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, 101 0, 10, max_retries);*/ 102 103 /* check if HW reading GSP memory */ 104 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, 105 0, 10, max_retries); 106 107 /* HW does is not reading GSP memory not reading too long -> 108 * something wrong. clear GPS memory access and notify? 109 * hw SW is writing to GSP memory 110 */ 111 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); 112 } 113 /* choose which generic packet to use */ 114 { 115 regval = REG_READ(AFMT_VBI_PACKET_CONTROL); 116 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, 117 AFMT_GENERIC_INDEX, packet_index); 118 } 119 120 /* write generic packet header 121 * (4th byte is for GENERIC0 only) */ 122 { 123 REG_SET_4(AFMT_GENERIC_HDR, 0, 124 AFMT_GENERIC_HB0, info_packet->hb0, 125 AFMT_GENERIC_HB1, info_packet->hb1, 126 AFMT_GENERIC_HB2, info_packet->hb2, 127 AFMT_GENERIC_HB3, info_packet->hb3); 128 } 129 130 /* write generic packet contents 131 * (we never use last 4 bytes) 132 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers */ 133 { 134 const uint32_t *content = 135 (const uint32_t *) &info_packet->sb[0]; 136 137 REG_WRITE(AFMT_GENERIC_0, *content++); 138 REG_WRITE(AFMT_GENERIC_1, *content++); 139 REG_WRITE(AFMT_GENERIC_2, *content++); 140 REG_WRITE(AFMT_GENERIC_3, *content++); 141 REG_WRITE(AFMT_GENERIC_4, *content++); 142 REG_WRITE(AFMT_GENERIC_5, *content++); 143 REG_WRITE(AFMT_GENERIC_6, *content++); 144 REG_WRITE(AFMT_GENERIC_7, *content); 145 } 146 147 if (!REG(AFMT_VBI_PACKET_CONTROL1)) { 148 /* force double-buffered packet update */ 149 REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL, 150 AFMT_GENERIC0_UPDATE, (packet_index == 0), 151 AFMT_GENERIC2_UPDATE, (packet_index == 2)); 152 } 153 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 154 if (REG(AFMT_VBI_PACKET_CONTROL1)) { 155 switch (packet_index) { 156 case 0: 157 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 158 AFMT_GENERIC0_FRAME_UPDATE, 1); 159 break; 160 case 1: 161 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 162 AFMT_GENERIC1_FRAME_UPDATE, 1); 163 break; 164 case 2: 165 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 166 AFMT_GENERIC2_FRAME_UPDATE, 1); 167 break; 168 case 3: 169 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 170 AFMT_GENERIC3_FRAME_UPDATE, 1); 171 break; 172 case 4: 173 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 174 AFMT_GENERIC4_FRAME_UPDATE, 1); 175 break; 176 case 5: 177 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 178 AFMT_GENERIC5_FRAME_UPDATE, 1); 179 break; 180 case 6: 181 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 182 AFMT_GENERIC6_FRAME_UPDATE, 1); 183 break; 184 case 7: 185 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 186 AFMT_GENERIC7_FRAME_UPDATE, 1); 187 break; 188 default: 189 break; 190 } 191 } 192 #endif 193 } 194 195 static void dce110_update_hdmi_info_packet( 196 struct dce110_stream_encoder *enc110, 197 uint32_t packet_index, 198 const struct encoder_info_packet *info_packet) 199 { 200 struct dc_context *ctx = enc110->base.ctx; 201 uint32_t cont, send, line; 202 203 if (info_packet->valid) { 204 dce110_update_generic_info_packet( 205 enc110, 206 packet_index, 207 info_packet); 208 209 /* enable transmission of packet(s) - 210 * packet transmission begins on the next frame */ 211 cont = 1; 212 /* send packet(s) every frame */ 213 send = 1; 214 /* select line number to send packets on */ 215 line = 2; 216 } else { 217 cont = 0; 218 send = 0; 219 line = 0; 220 } 221 222 /* choose which generic packet control to use */ 223 switch (packet_index) { 224 case 0: 225 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 226 HDMI_GENERIC0_CONT, cont, 227 HDMI_GENERIC0_SEND, send, 228 HDMI_GENERIC0_LINE, line); 229 break; 230 case 1: 231 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 232 HDMI_GENERIC1_CONT, cont, 233 HDMI_GENERIC1_SEND, send, 234 HDMI_GENERIC1_LINE, line); 235 break; 236 case 2: 237 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 238 HDMI_GENERIC0_CONT, cont, 239 HDMI_GENERIC0_SEND, send, 240 HDMI_GENERIC0_LINE, line); 241 break; 242 case 3: 243 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 244 HDMI_GENERIC1_CONT, cont, 245 HDMI_GENERIC1_SEND, send, 246 HDMI_GENERIC1_LINE, line); 247 break; 248 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 249 case 4: 250 if (REG(HDMI_GENERIC_PACKET_CONTROL2)) 251 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 252 HDMI_GENERIC0_CONT, cont, 253 HDMI_GENERIC0_SEND, send, 254 HDMI_GENERIC0_LINE, line); 255 break; 256 case 5: 257 if (REG(HDMI_GENERIC_PACKET_CONTROL2)) 258 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 259 HDMI_GENERIC1_CONT, cont, 260 HDMI_GENERIC1_SEND, send, 261 HDMI_GENERIC1_LINE, line); 262 break; 263 case 6: 264 if (REG(HDMI_GENERIC_PACKET_CONTROL3)) 265 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 266 HDMI_GENERIC0_CONT, cont, 267 HDMI_GENERIC0_SEND, send, 268 HDMI_GENERIC0_LINE, line); 269 break; 270 case 7: 271 if (REG(HDMI_GENERIC_PACKET_CONTROL3)) 272 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 273 HDMI_GENERIC1_CONT, cont, 274 HDMI_GENERIC1_SEND, send, 275 HDMI_GENERIC1_LINE, line); 276 break; 277 #endif 278 default: 279 /* invalid HW packet index */ 280 dm_logger_write( 281 ctx->logger, LOG_WARNING, 282 "Invalid HW packet index: %s()\n", 283 __func__); 284 return; 285 } 286 } 287 288 /* setup stream encoder in dp mode */ 289 static void dce110_stream_encoder_dp_set_stream_attribute( 290 struct stream_encoder *enc, 291 struct dc_crtc_timing *crtc_timing, 292 enum dc_color_space output_color_space) 293 { 294 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 295 uint32_t h_active_start; 296 uint32_t v_active_start; 297 uint32_t misc0 = 0; 298 uint32_t misc1 = 0; 299 uint32_t h_blank; 300 uint32_t h_back_porch; 301 uint8_t synchronous_clock = 0; /* asynchronous mode */ 302 uint8_t colorimetry_bpc; 303 uint8_t dynamic_range_rgb = 0; /*full range*/ 304 uint8_t dynamic_range_ycbcr = 1; /*bt709*/ 305 #endif 306 307 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 308 309 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 310 if (REG(DP_DB_CNTL)) 311 REG_UPDATE(DP_DB_CNTL, DP_DB_DISABLE, 1); 312 #endif 313 314 /* set pixel encoding */ 315 switch (crtc_timing->pixel_encoding) { 316 case PIXEL_ENCODING_YCBCR422: 317 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 318 DP_PIXEL_ENCODING_YCBCR422); 319 break; 320 case PIXEL_ENCODING_YCBCR444: 321 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 322 DP_PIXEL_ENCODING_YCBCR444); 323 324 if (crtc_timing->flags.Y_ONLY) 325 if (crtc_timing->display_color_depth != COLOR_DEPTH_666) 326 /* HW testing only, no use case yet. 327 * Color depth of Y-only could be 328 * 8, 10, 12, 16 bits */ 329 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 330 DP_PIXEL_ENCODING_Y_ONLY); 331 /* Note: DP_MSA_MISC1 bit 7 is the indicator 332 * of Y-only mode. 333 * This bit is set in HW if register 334 * DP_PIXEL_ENCODING is programmed to 0x4 */ 335 break; 336 case PIXEL_ENCODING_YCBCR420: 337 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 338 DP_PIXEL_ENCODING_YCBCR420); 339 if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN) 340 REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1); 341 342 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 343 if (enc110->se_mask->DP_VID_N_MUL) 344 REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1); 345 #endif 346 break; 347 default: 348 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 349 DP_PIXEL_ENCODING_RGB444); 350 break; 351 } 352 353 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 354 if (REG(DP_MSA_MISC)) 355 misc1 = REG_READ(DP_MSA_MISC); 356 #endif 357 358 /* set color depth */ 359 360 switch (crtc_timing->display_color_depth) { 361 case COLOR_DEPTH_666: 362 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 363 0); 364 break; 365 case COLOR_DEPTH_888: 366 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 367 DP_COMPONENT_DEPTH_8BPC); 368 break; 369 case COLOR_DEPTH_101010: 370 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 371 DP_COMPONENT_DEPTH_10BPC); 372 373 break; 374 case COLOR_DEPTH_121212: 375 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 376 DP_COMPONENT_DEPTH_12BPC); 377 break; 378 default: 379 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 380 DP_COMPONENT_DEPTH_6BPC); 381 break; 382 } 383 384 /* set dynamic range and YCbCr range */ 385 386 387 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 388 switch (crtc_timing->display_color_depth) { 389 case COLOR_DEPTH_666: 390 colorimetry_bpc = 0; 391 break; 392 case COLOR_DEPTH_888: 393 colorimetry_bpc = 1; 394 break; 395 case COLOR_DEPTH_101010: 396 colorimetry_bpc = 2; 397 break; 398 case COLOR_DEPTH_121212: 399 colorimetry_bpc = 3; 400 break; 401 default: 402 colorimetry_bpc = 0; 403 break; 404 } 405 406 misc0 = misc0 | synchronous_clock; 407 misc0 = colorimetry_bpc << 5; 408 409 if (REG(DP_MSA_TIMING_PARAM1)) { 410 switch (output_color_space) { 411 case COLOR_SPACE_SRGB: 412 misc0 = misc0 | 0x0; 413 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 414 dynamic_range_rgb = 0; /*full range*/ 415 break; 416 case COLOR_SPACE_SRGB_LIMITED: 417 misc0 = misc0 | 0x8; /* bit3=1 */ 418 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 419 dynamic_range_rgb = 1; /*limited range*/ 420 break; 421 case COLOR_SPACE_YCBCR601: 422 case COLOR_SPACE_YCBCR601_LIMITED: 423 misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */ 424 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 425 dynamic_range_ycbcr = 0; /*bt601*/ 426 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) 427 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 428 else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) 429 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 430 break; 431 case COLOR_SPACE_YCBCR709: 432 case COLOR_SPACE_YCBCR709_LIMITED: 433 misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */ 434 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 435 dynamic_range_ycbcr = 1; /*bt709*/ 436 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) 437 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 438 else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) 439 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 440 break; 441 case COLOR_SPACE_2020_RGB_LIMITEDRANGE: 442 dynamic_range_rgb = 1; /*limited range*/ 443 break; 444 case COLOR_SPACE_2020_RGB_FULLRANGE: 445 case COLOR_SPACE_2020_YCBCR: 446 case COLOR_SPACE_XR_RGB: 447 case COLOR_SPACE_MSREF_SCRGB: 448 case COLOR_SPACE_ADOBERGB: 449 case COLOR_SPACE_DCIP3: 450 case COLOR_SPACE_XV_YCC_709: 451 case COLOR_SPACE_XV_YCC_601: 452 case COLOR_SPACE_DISPLAYNATIVE: 453 case COLOR_SPACE_DOLBYVISION: 454 case COLOR_SPACE_APPCTRL: 455 case COLOR_SPACE_CUSTOMPOINTS: 456 case COLOR_SPACE_UNKNOWN: 457 /* do nothing */ 458 break; 459 } 460 if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE) 461 REG_UPDATE_2( 462 DP_PIXEL_FORMAT, 463 DP_DYN_RANGE, dynamic_range_rgb, 464 DP_YCBCR_RANGE, dynamic_range_ycbcr); 465 466 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 467 if (REG(DP_MSA_COLORIMETRY)) 468 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0); 469 470 if (REG(DP_MSA_MISC)) 471 REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */ 472 473 /* dcn new register 474 * dc_crtc_timing is vesa dmt struct. data from edid 475 */ 476 if (REG(DP_MSA_TIMING_PARAM1)) 477 REG_SET_2(DP_MSA_TIMING_PARAM1, 0, 478 DP_MSA_HTOTAL, crtc_timing->h_total, 479 DP_MSA_VTOTAL, crtc_timing->v_total); 480 #endif 481 482 /* calcuate from vesa timing parameters 483 * h_active_start related to leading edge of sync 484 */ 485 486 h_blank = crtc_timing->h_total - crtc_timing->h_border_left - 487 crtc_timing->h_addressable - crtc_timing->h_border_right; 488 489 h_back_porch = h_blank - crtc_timing->h_front_porch - 490 crtc_timing->h_sync_width; 491 492 /* start at begining of left border */ 493 h_active_start = crtc_timing->h_sync_width + h_back_porch; 494 495 496 v_active_start = crtc_timing->v_total - crtc_timing->v_border_top - 497 crtc_timing->v_addressable - crtc_timing->v_border_bottom - 498 crtc_timing->v_front_porch; 499 500 501 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 502 /* start at begining of left border */ 503 if (REG(DP_MSA_TIMING_PARAM2)) 504 REG_SET_2(DP_MSA_TIMING_PARAM2, 0, 505 DP_MSA_HSTART, h_active_start, 506 DP_MSA_VSTART, v_active_start); 507 508 if (REG(DP_MSA_TIMING_PARAM3)) 509 REG_SET_4(DP_MSA_TIMING_PARAM3, 0, 510 DP_MSA_HSYNCWIDTH, 511 crtc_timing->h_sync_width, 512 DP_MSA_HSYNCPOLARITY, 513 !crtc_timing->flags.HSYNC_POSITIVE_POLARITY, 514 DP_MSA_VSYNCWIDTH, 515 crtc_timing->v_sync_width, 516 DP_MSA_VSYNCPOLARITY, 517 !crtc_timing->flags.VSYNC_POSITIVE_POLARITY); 518 519 /* HWDITH include border or overscan */ 520 if (REG(DP_MSA_TIMING_PARAM4)) 521 REG_SET_2(DP_MSA_TIMING_PARAM4, 0, 522 DP_MSA_HWIDTH, crtc_timing->h_border_left + 523 crtc_timing->h_addressable + crtc_timing->h_border_right, 524 DP_MSA_VHEIGHT, crtc_timing->v_border_top + 525 crtc_timing->v_addressable + crtc_timing->v_border_bottom); 526 #endif 527 } 528 #endif 529 } 530 531 static void dce110_stream_encoder_set_stream_attribute_helper( 532 struct dce110_stream_encoder *enc110, 533 struct dc_crtc_timing *crtc_timing) 534 { 535 if (enc110->regs->TMDS_CNTL) { 536 switch (crtc_timing->pixel_encoding) { 537 case PIXEL_ENCODING_YCBCR422: 538 REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 1); 539 break; 540 default: 541 REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 0); 542 break; 543 } 544 REG_UPDATE(TMDS_CNTL, TMDS_COLOR_FORMAT, 0); 545 } else if (enc110->regs->DIG_FE_CNTL) { 546 switch (crtc_timing->pixel_encoding) { 547 case PIXEL_ENCODING_YCBCR422: 548 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1); 549 break; 550 default: 551 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0); 552 break; 553 } 554 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0); 555 } 556 557 } 558 559 /* setup stream encoder in hdmi mode */ 560 static void dce110_stream_encoder_hdmi_set_stream_attribute( 561 struct stream_encoder *enc, 562 struct dc_crtc_timing *crtc_timing, 563 int actual_pix_clk_khz, 564 bool enable_audio) 565 { 566 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 567 struct bp_encoder_control cntl = {0}; 568 569 cntl.action = ENCODER_CONTROL_SETUP; 570 cntl.engine_id = enc110->base.id; 571 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; 572 cntl.enable_dp_audio = enable_audio; 573 cntl.pixel_clock = actual_pix_clk_khz; 574 cntl.lanes_number = LANE_COUNT_FOUR; 575 576 if (enc110->base.bp->funcs->encoder_control( 577 enc110->base.bp, &cntl) != BP_RESULT_OK) 578 return; 579 580 dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing); 581 582 /* setup HDMI engine */ 583 if (!enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) { 584 REG_UPDATE_3(HDMI_CONTROL, 585 HDMI_PACKET_GEN_VERSION, 1, 586 HDMI_KEEPOUT_MODE, 1, 587 HDMI_DEEP_COLOR_ENABLE, 0); 588 } else if (enc110->regs->DIG_FE_CNTL) { 589 REG_UPDATE_5(HDMI_CONTROL, 590 HDMI_PACKET_GEN_VERSION, 1, 591 HDMI_KEEPOUT_MODE, 1, 592 HDMI_DEEP_COLOR_ENABLE, 0, 593 HDMI_DATA_SCRAMBLE_EN, 0, 594 HDMI_CLOCK_CHANNEL_RATE, 0); 595 } 596 597 switch (crtc_timing->display_color_depth) { 598 case COLOR_DEPTH_888: 599 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 600 break; 601 case COLOR_DEPTH_101010: 602 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 603 REG_UPDATE_2(HDMI_CONTROL, 604 HDMI_DEEP_COLOR_DEPTH, 1, 605 HDMI_DEEP_COLOR_ENABLE, 0); 606 } else { 607 REG_UPDATE_2(HDMI_CONTROL, 608 HDMI_DEEP_COLOR_DEPTH, 1, 609 HDMI_DEEP_COLOR_ENABLE, 1); 610 } 611 break; 612 case COLOR_DEPTH_121212: 613 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 614 REG_UPDATE_2(HDMI_CONTROL, 615 HDMI_DEEP_COLOR_DEPTH, 2, 616 HDMI_DEEP_COLOR_ENABLE, 0); 617 } else { 618 REG_UPDATE_2(HDMI_CONTROL, 619 HDMI_DEEP_COLOR_DEPTH, 2, 620 HDMI_DEEP_COLOR_ENABLE, 1); 621 } 622 break; 623 case COLOR_DEPTH_161616: 624 REG_UPDATE_2(HDMI_CONTROL, 625 HDMI_DEEP_COLOR_DEPTH, 3, 626 HDMI_DEEP_COLOR_ENABLE, 1); 627 break; 628 default: 629 break; 630 } 631 632 if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) { 633 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) { 634 /* enable HDMI data scrambler 635 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M 636 * Clock channel frequency is 1/4 of character rate. 637 */ 638 REG_UPDATE_2(HDMI_CONTROL, 639 HDMI_DATA_SCRAMBLE_EN, 1, 640 HDMI_CLOCK_CHANNEL_RATE, 1); 641 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) { 642 643 /* TODO: New feature for DCE11, still need to implement */ 644 645 /* enable HDMI data scrambler 646 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE 647 * Clock channel frequency is the same 648 * as character rate 649 */ 650 REG_UPDATE_2(HDMI_CONTROL, 651 HDMI_DATA_SCRAMBLE_EN, 1, 652 HDMI_CLOCK_CHANNEL_RATE, 0); 653 } 654 } 655 656 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL, 657 HDMI_GC_CONT, 1, 658 HDMI_GC_SEND, 1, 659 HDMI_NULL_SEND, 1); 660 661 /* following belongs to audio */ 662 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 663 664 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 665 666 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 667 VBI_LINE_0 + 2); 668 669 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); 670 671 } 672 673 /* setup stream encoder in dvi mode */ 674 static void dce110_stream_encoder_dvi_set_stream_attribute( 675 struct stream_encoder *enc, 676 struct dc_crtc_timing *crtc_timing, 677 bool is_dual_link) 678 { 679 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 680 struct bp_encoder_control cntl = {0}; 681 682 cntl.action = ENCODER_CONTROL_SETUP; 683 cntl.engine_id = enc110->base.id; 684 cntl.signal = is_dual_link ? 685 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK; 686 cntl.enable_dp_audio = false; 687 cntl.pixel_clock = crtc_timing->pix_clk_khz; 688 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; 689 690 if (enc110->base.bp->funcs->encoder_control( 691 enc110->base.bp, &cntl) != BP_RESULT_OK) 692 return; 693 694 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); 695 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888); 696 dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing); 697 } 698 699 static void dce110_stream_encoder_set_mst_bandwidth( 700 struct stream_encoder *enc, 701 struct fixed31_32 avg_time_slots_per_mtp) 702 { 703 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 704 uint32_t x = dal_fixed31_32_floor( 705 avg_time_slots_per_mtp); 706 uint32_t y = dal_fixed31_32_ceil( 707 dal_fixed31_32_shl( 708 dal_fixed31_32_sub_int( 709 avg_time_slots_per_mtp, 710 x), 711 26)); 712 713 { 714 REG_SET_2(DP_MSE_RATE_CNTL, 0, 715 DP_MSE_RATE_X, x, 716 DP_MSE_RATE_Y, y); 717 } 718 719 /* wait for update to be completed on the link */ 720 /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */ 721 /* is reset to 0 (not pending) */ 722 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, 723 0, 724 10, DP_MST_UPDATE_MAX_RETRY); 725 } 726 727 static void dce110_stream_encoder_update_hdmi_info_packets( 728 struct stream_encoder *enc, 729 const struct encoder_info_frame *info_frame) 730 { 731 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 732 733 if (enc110->se_mask->HDMI_AVI_INFO_CONT && 734 enc110->se_mask->HDMI_AVI_INFO_SEND) { 735 736 if (info_frame->avi.valid) { 737 const uint32_t *content = 738 (const uint32_t *) &info_frame->avi.sb[0]; 739 740 REG_WRITE(AFMT_AVI_INFO0, content[0]); 741 742 REG_WRITE(AFMT_AVI_INFO1, content[1]); 743 744 REG_WRITE(AFMT_AVI_INFO2, content[2]); 745 746 REG_WRITE(AFMT_AVI_INFO3, content[3]); 747 748 REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, 749 info_frame->avi.hb1); 750 751 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0, 752 HDMI_AVI_INFO_SEND, 1, 753 HDMI_AVI_INFO_CONT, 1); 754 755 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 756 VBI_LINE_0 + 2); 757 758 } else { 759 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0, 760 HDMI_AVI_INFO_SEND, 0, 761 HDMI_AVI_INFO_CONT, 0); 762 } 763 } 764 765 if (enc110->se_mask->HDMI_AVI_INFO_CONT && 766 enc110->se_mask->HDMI_AVI_INFO_SEND) { 767 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor); 768 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut); 769 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd); 770 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd); 771 } 772 773 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 774 if (enc110->se_mask->HDMI_DB_DISABLE) { 775 /* for bring up, disable dp double TODO */ 776 if (REG(HDMI_DB_CONTROL)) 777 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); 778 779 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->avi); 780 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->vendor); 781 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->gamut); 782 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->spd); 783 dce110_update_hdmi_info_packet(enc110, 4, &info_frame->hdrsmd); 784 } 785 #endif 786 } 787 788 static void dce110_stream_encoder_stop_hdmi_info_packets( 789 struct stream_encoder *enc) 790 { 791 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 792 793 /* stop generic packets 0 & 1 on HDMI */ 794 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0, 795 HDMI_GENERIC1_CONT, 0, 796 HDMI_GENERIC1_LINE, 0, 797 HDMI_GENERIC1_SEND, 0, 798 HDMI_GENERIC0_CONT, 0, 799 HDMI_GENERIC0_LINE, 0, 800 HDMI_GENERIC0_SEND, 0); 801 802 /* stop generic packets 2 & 3 on HDMI */ 803 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0, 804 HDMI_GENERIC0_CONT, 0, 805 HDMI_GENERIC0_LINE, 0, 806 HDMI_GENERIC0_SEND, 0, 807 HDMI_GENERIC1_CONT, 0, 808 HDMI_GENERIC1_LINE, 0, 809 HDMI_GENERIC1_SEND, 0); 810 811 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 812 /* stop generic packets 2 & 3 on HDMI */ 813 if (REG(HDMI_GENERIC_PACKET_CONTROL2)) 814 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0, 815 HDMI_GENERIC0_CONT, 0, 816 HDMI_GENERIC0_LINE, 0, 817 HDMI_GENERIC0_SEND, 0, 818 HDMI_GENERIC1_CONT, 0, 819 HDMI_GENERIC1_LINE, 0, 820 HDMI_GENERIC1_SEND, 0); 821 822 if (REG(HDMI_GENERIC_PACKET_CONTROL3)) 823 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0, 824 HDMI_GENERIC0_CONT, 0, 825 HDMI_GENERIC0_LINE, 0, 826 HDMI_GENERIC0_SEND, 0, 827 HDMI_GENERIC1_CONT, 0, 828 HDMI_GENERIC1_LINE, 0, 829 HDMI_GENERIC1_SEND, 0); 830 #endif 831 } 832 833 static void dce110_stream_encoder_update_dp_info_packets( 834 struct stream_encoder *enc, 835 const struct encoder_info_frame *info_frame) 836 { 837 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 838 uint32_t value = REG_READ(DP_SEC_CNTL); 839 840 if (info_frame->vsc.valid) 841 dce110_update_generic_info_packet( 842 enc110, 843 0, /* packetIndex */ 844 &info_frame->vsc); 845 846 if (info_frame->spd.valid) 847 dce110_update_generic_info_packet( 848 enc110, 849 2, /* packetIndex */ 850 &info_frame->spd); 851 852 if (info_frame->hdrsmd.valid) 853 dce110_update_generic_info_packet( 854 enc110, 855 3, /* packetIndex */ 856 &info_frame->hdrsmd); 857 858 /* enable/disable transmission of packet(s). 859 * If enabled, packet transmission begins on the next frame 860 */ 861 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); 862 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); 863 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); 864 865 /* This bit is the master enable bit. 866 * When enabling secondary stream engine, 867 * this master bit must also be set. 868 * This register shared with audio info frame. 869 * Therefore we need to enable master bit 870 * if at least on of the fields is not 0 871 */ 872 if (value) 873 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 874 } 875 876 static void dce110_stream_encoder_stop_dp_info_packets( 877 struct stream_encoder *enc) 878 { 879 /* stop generic packets on DP */ 880 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 881 uint32_t value = REG_READ(DP_SEC_CNTL); 882 883 if (enc110->se_mask->DP_SEC_AVI_ENABLE) { 884 REG_SET_7(DP_SEC_CNTL, 0, 885 DP_SEC_GSP0_ENABLE, 0, 886 DP_SEC_GSP1_ENABLE, 0, 887 DP_SEC_GSP2_ENABLE, 0, 888 DP_SEC_GSP3_ENABLE, 0, 889 DP_SEC_AVI_ENABLE, 0, 890 DP_SEC_MPG_ENABLE, 0, 891 DP_SEC_STREAM_ENABLE, 0); 892 } 893 894 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 895 if (enc110->se_mask->DP_SEC_GSP7_ENABLE) { 896 REG_SET_10(DP_SEC_CNTL, 0, 897 DP_SEC_GSP0_ENABLE, 0, 898 DP_SEC_GSP1_ENABLE, 0, 899 DP_SEC_GSP2_ENABLE, 0, 900 DP_SEC_GSP3_ENABLE, 0, 901 DP_SEC_GSP4_ENABLE, 0, 902 DP_SEC_GSP5_ENABLE, 0, 903 DP_SEC_GSP6_ENABLE, 0, 904 DP_SEC_GSP7_ENABLE, 0, 905 DP_SEC_MPG_ENABLE, 0, 906 DP_SEC_STREAM_ENABLE, 0); 907 } 908 #endif 909 /* this register shared with audio info frame. 910 * therefore we need to keep master enabled 911 * if at least one of the fields is not 0 */ 912 913 if (value) 914 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 915 916 } 917 918 static void dce110_stream_encoder_dp_blank( 919 struct stream_encoder *enc) 920 { 921 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 922 uint32_t retries = 0; 923 uint32_t max_retries = DP_BLANK_MAX_RETRY * 10; 924 925 /* Note: For CZ, we are changing driver default to disable 926 * stream deferred to next VBLANK. If results are positive, we 927 * will make the same change to all DCE versions. There are a 928 * handful of panels that cannot handle disable stream at 929 * HBLANK and will result in a white line flash across the 930 * screen on stream disable. */ 931 932 /* Specify the video stream disable point 933 * (2 = start of the next vertical blank) */ 934 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2); 935 /* Larger delay to wait until VBLANK - use max retry of 936 * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode + 937 * a little more because we may not trust delay accuracy. 938 */ 939 max_retries = DP_BLANK_MAX_RETRY * 150; 940 941 /* disable DP stream */ 942 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); 943 944 /* the encoder stops sending the video stream 945 * at the start of the vertical blanking. 946 * Poll for DP_VID_STREAM_STATUS == 0 947 */ 948 949 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 950 0, 951 10, max_retries); 952 953 ASSERT(retries <= max_retries); 954 955 /* Tell the DP encoder to ignore timing from CRTC, must be done after 956 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is 957 * complete, stream status will be stuck in video stream enabled state, 958 * i.e. DP_VID_STREAM_STATUS stuck at 1. 959 */ 960 961 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true); 962 } 963 964 /* output video stream to link encoder */ 965 static void dce110_stream_encoder_dp_unblank( 966 struct stream_encoder *enc, 967 const struct encoder_unblank_param *param) 968 { 969 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 970 971 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) { 972 uint32_t n_vid = 0x8000; 973 uint32_t m_vid; 974 975 /* M / N = Fstream / Flink 976 * m_vid / n_vid = pixel rate / link rate 977 */ 978 979 uint64_t m_vid_l = n_vid; 980 981 m_vid_l *= param->pixel_clk_khz; 982 m_vid_l = div_u64(m_vid_l, 983 param->link_settings.link_rate 984 * LINK_RATE_REF_FREQ_IN_KHZ); 985 986 m_vid = (uint32_t) m_vid_l; 987 988 /* enable auto measurement */ 989 990 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0); 991 992 /* auto measurement need 1 full 0x8000 symbol cycle to kick in, 993 * therefore program initial value for Mvid and Nvid 994 */ 995 996 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid); 997 998 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid); 999 1000 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1); 1001 } 1002 1003 /* set DIG_START to 0x1 to resync FIFO */ 1004 1005 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); 1006 1007 /* switch DP encoder to CRTC data */ 1008 1009 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); 1010 1011 /* wait 100us for DIG/DP logic to prime 1012 * (i.e. a few video lines) 1013 */ 1014 udelay(100); 1015 1016 /* the hardware would start sending video at the start of the next DP 1017 * frame (i.e. rising edge of the vblank). 1018 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this 1019 * register has no effect on enable transition! HW always guarantees 1020 * VID_STREAM enable at start of next frame, and this is not 1021 * programmable 1022 */ 1023 1024 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); 1025 } 1026 1027 static void dce110_stream_encoder_set_avmute( 1028 struct stream_encoder *enc, 1029 bool enable) 1030 { 1031 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1032 unsigned int value = enable ? 1 : 0; 1033 1034 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value); 1035 } 1036 1037 1038 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000 1039 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1 1040 1041 #include "include/audio_types.h" 1042 1043 /** 1044 * speakersToChannels 1045 * 1046 * @brief 1047 * translate speakers to channels 1048 * 1049 * FL - Front Left 1050 * FR - Front Right 1051 * RL - Rear Left 1052 * RR - Rear Right 1053 * RC - Rear Center 1054 * FC - Front Center 1055 * FLC - Front Left Center 1056 * FRC - Front Right Center 1057 * RLC - Rear Left Center 1058 * RRC - Rear Right Center 1059 * LFE - Low Freq Effect 1060 * 1061 * FC 1062 * FLC FRC 1063 * FL FR 1064 * 1065 * LFE 1066 * () 1067 * 1068 * 1069 * RL RR 1070 * RLC RRC 1071 * RC 1072 * 1073 * ch 8 7 6 5 4 3 2 1 1074 * 0b00000011 - - - - - - FR FL 1075 * 0b00000111 - - - - - LFE FR FL 1076 * 0b00001011 - - - - FC - FR FL 1077 * 0b00001111 - - - - FC LFE FR FL 1078 * 0b00010011 - - - RC - - FR FL 1079 * 0b00010111 - - - RC - LFE FR FL 1080 * 0b00011011 - - - RC FC - FR FL 1081 * 0b00011111 - - - RC FC LFE FR FL 1082 * 0b00110011 - - RR RL - - FR FL 1083 * 0b00110111 - - RR RL - LFE FR FL 1084 * 0b00111011 - - RR RL FC - FR FL 1085 * 0b00111111 - - RR RL FC LFE FR FL 1086 * 0b01110011 - RC RR RL - - FR FL 1087 * 0b01110111 - RC RR RL - LFE FR FL 1088 * 0b01111011 - RC RR RL FC - FR FL 1089 * 0b01111111 - RC RR RL FC LFE FR FL 1090 * 0b11110011 RRC RLC RR RL - - FR FL 1091 * 0b11110111 RRC RLC RR RL - LFE FR FL 1092 * 0b11111011 RRC RLC RR RL FC - FR FL 1093 * 0b11111111 RRC RLC RR RL FC LFE FR FL 1094 * 0b11000011 FRC FLC - - - - FR FL 1095 * 0b11000111 FRC FLC - - - LFE FR FL 1096 * 0b11001011 FRC FLC - - FC - FR FL 1097 * 0b11001111 FRC FLC - - FC LFE FR FL 1098 * 0b11010011 FRC FLC - RC - - FR FL 1099 * 0b11010111 FRC FLC - RC - LFE FR FL 1100 * 0b11011011 FRC FLC - RC FC - FR FL 1101 * 0b11011111 FRC FLC - RC FC LFE FR FL 1102 * 0b11110011 FRC FLC RR RL - - FR FL 1103 * 0b11110111 FRC FLC RR RL - LFE FR FL 1104 * 0b11111011 FRC FLC RR RL FC - FR FL 1105 * 0b11111111 FRC FLC RR RL FC LFE FR FL 1106 * 1107 * @param 1108 * speakers - speaker information as it comes from CEA audio block 1109 */ 1110 /* translate speakers to channels */ 1111 1112 union audio_cea_channels { 1113 uint8_t all; 1114 struct audio_cea_channels_bits { 1115 uint32_t FL:1; 1116 uint32_t FR:1; 1117 uint32_t LFE:1; 1118 uint32_t FC:1; 1119 uint32_t RL_RC:1; 1120 uint32_t RR:1; 1121 uint32_t RC_RLC_FLC:1; 1122 uint32_t RRC_FRC:1; 1123 } channels; 1124 }; 1125 1126 struct audio_clock_info { 1127 /* pixel clock frequency*/ 1128 uint32_t pixel_clock_in_10khz; 1129 /* N - 32KHz audio */ 1130 uint32_t n_32khz; 1131 /* CTS - 32KHz audio*/ 1132 uint32_t cts_32khz; 1133 uint32_t n_44khz; 1134 uint32_t cts_44khz; 1135 uint32_t n_48khz; 1136 uint32_t cts_48khz; 1137 }; 1138 1139 /* 25.2MHz/1.001*/ 1140 /* 25.2MHz/1.001*/ 1141 /* 25.2MHz*/ 1142 /* 27MHz */ 1143 /* 27MHz*1.001*/ 1144 /* 27MHz*1.001*/ 1145 /* 54MHz*/ 1146 /* 54MHz*1.001*/ 1147 /* 74.25MHz/1.001*/ 1148 /* 74.25MHz*/ 1149 /* 148.5MHz/1.001*/ 1150 /* 148.5MHz*/ 1151 1152 static const struct audio_clock_info audio_clock_info_table[16] = { 1153 {2517, 4576, 28125, 7007, 31250, 6864, 28125}, 1154 {2518, 4576, 28125, 7007, 31250, 6864, 28125}, 1155 {2520, 4096, 25200, 6272, 28000, 6144, 25200}, 1156 {2700, 4096, 27000, 6272, 30000, 6144, 27000}, 1157 {2702, 4096, 27027, 6272, 30030, 6144, 27027}, 1158 {2703, 4096, 27027, 6272, 30030, 6144, 27027}, 1159 {5400, 4096, 54000, 6272, 60000, 6144, 54000}, 1160 {5405, 4096, 54054, 6272, 60060, 6144, 54054}, 1161 {7417, 11648, 210937, 17836, 234375, 11648, 140625}, 1162 {7425, 4096, 74250, 6272, 82500, 6144, 74250}, 1163 {14835, 11648, 421875, 8918, 234375, 5824, 140625}, 1164 {14850, 4096, 148500, 6272, 165000, 6144, 148500}, 1165 {29670, 5824, 421875, 4459, 234375, 5824, 281250}, 1166 {29700, 3072, 222750, 4704, 247500, 5120, 247500}, 1167 {59340, 5824, 843750, 8918, 937500, 5824, 562500}, 1168 {59400, 3072, 445500, 9408, 990000, 6144, 594000} 1169 }; 1170 1171 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = { 1172 {2517, 9152, 84375, 7007, 48875, 9152, 56250}, 1173 {2518, 9152, 84375, 7007, 48875, 9152, 56250}, 1174 {2520, 4096, 37800, 6272, 42000, 6144, 37800}, 1175 {2700, 4096, 40500, 6272, 45000, 6144, 40500}, 1176 {2702, 8192, 81081, 6272, 45045, 8192, 54054}, 1177 {2703, 8192, 81081, 6272, 45045, 8192, 54054}, 1178 {5400, 4096, 81000, 6272, 90000, 6144, 81000}, 1179 {5405, 4096, 81081, 6272, 90090, 6144, 81081}, 1180 {7417, 11648, 316406, 17836, 351562, 11648, 210937}, 1181 {7425, 4096, 111375, 6272, 123750, 6144, 111375}, 1182 {14835, 11648, 632812, 17836, 703125, 11648, 421875}, 1183 {14850, 4096, 222750, 6272, 247500, 6144, 222750}, 1184 {29670, 5824, 632812, 8918, 703125, 5824, 421875}, 1185 {29700, 4096, 445500, 4704, 371250, 5120, 371250} 1186 }; 1187 1188 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = { 1189 {2517, 4576, 56250, 7007, 62500, 6864, 56250}, 1190 {2518, 4576, 56250, 7007, 62500, 6864, 56250}, 1191 {2520, 4096, 50400, 6272, 56000, 6144, 50400}, 1192 {2700, 4096, 54000, 6272, 60000, 6144, 54000}, 1193 {2702, 4096, 54054, 6267, 60060, 8192, 54054}, 1194 {2703, 4096, 54054, 6272, 60060, 8192, 54054}, 1195 {5400, 4096, 108000, 6272, 120000, 6144, 108000}, 1196 {5405, 4096, 108108, 6272, 120120, 6144, 108108}, 1197 {7417, 11648, 421875, 17836, 468750, 11648, 281250}, 1198 {7425, 4096, 148500, 6272, 165000, 6144, 148500}, 1199 {14835, 11648, 843750, 8918, 468750, 11648, 281250}, 1200 {14850, 4096, 297000, 6272, 330000, 6144, 297000}, 1201 {29670, 5824, 843750, 4459, 468750, 5824, 562500}, 1202 {29700, 3072, 445500, 4704, 495000, 5120, 495000} 1203 1204 1205 }; 1206 1207 static union audio_cea_channels speakers_to_channels( 1208 struct audio_speaker_flags speaker_flags) 1209 { 1210 union audio_cea_channels cea_channels = {0}; 1211 1212 /* these are one to one */ 1213 cea_channels.channels.FL = speaker_flags.FL_FR; 1214 cea_channels.channels.FR = speaker_flags.FL_FR; 1215 cea_channels.channels.LFE = speaker_flags.LFE; 1216 cea_channels.channels.FC = speaker_flags.FC; 1217 1218 /* if Rear Left and Right exist move RC speaker to channel 7 1219 * otherwise to channel 5 1220 */ 1221 if (speaker_flags.RL_RR) { 1222 cea_channels.channels.RL_RC = speaker_flags.RL_RR; 1223 cea_channels.channels.RR = speaker_flags.RL_RR; 1224 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC; 1225 } else { 1226 cea_channels.channels.RL_RC = speaker_flags.RC; 1227 } 1228 1229 /* FRONT Left Right Center and REAR Left Right Center are exclusive */ 1230 if (speaker_flags.FLC_FRC) { 1231 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC; 1232 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC; 1233 } else { 1234 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC; 1235 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC; 1236 } 1237 1238 return cea_channels; 1239 } 1240 1241 static uint32_t calc_max_audio_packets_per_line( 1242 const struct audio_crtc_info *crtc_info) 1243 { 1244 uint32_t max_packets_per_line; 1245 1246 max_packets_per_line = 1247 crtc_info->h_total - crtc_info->h_active; 1248 1249 if (crtc_info->pixel_repetition) 1250 max_packets_per_line *= crtc_info->pixel_repetition; 1251 1252 /* for other hdmi features */ 1253 max_packets_per_line -= 58; 1254 /* for Control Period */ 1255 max_packets_per_line -= 16; 1256 /* Number of Audio Packets per Line */ 1257 max_packets_per_line /= 32; 1258 1259 return max_packets_per_line; 1260 } 1261 1262 static void get_audio_clock_info( 1263 enum dc_color_depth color_depth, 1264 uint32_t crtc_pixel_clock_in_khz, 1265 uint32_t actual_pixel_clock_in_khz, 1266 struct audio_clock_info *audio_clock_info) 1267 { 1268 const struct audio_clock_info *clock_info; 1269 uint32_t index; 1270 uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10; 1271 uint32_t audio_array_size; 1272 1273 switch (color_depth) { 1274 case COLOR_DEPTH_161616: 1275 clock_info = audio_clock_info_table_48bpc; 1276 audio_array_size = ARRAY_SIZE( 1277 audio_clock_info_table_48bpc); 1278 break; 1279 case COLOR_DEPTH_121212: 1280 clock_info = audio_clock_info_table_36bpc; 1281 audio_array_size = ARRAY_SIZE( 1282 audio_clock_info_table_36bpc); 1283 break; 1284 default: 1285 clock_info = audio_clock_info_table; 1286 audio_array_size = ARRAY_SIZE( 1287 audio_clock_info_table); 1288 break; 1289 } 1290 1291 if (clock_info != NULL) { 1292 /* search for exact pixel clock in table */ 1293 for (index = 0; index < audio_array_size; index++) { 1294 if (clock_info[index].pixel_clock_in_10khz > 1295 crtc_pixel_clock_in_10khz) 1296 break; /* not match */ 1297 else if (clock_info[index].pixel_clock_in_10khz == 1298 crtc_pixel_clock_in_10khz) { 1299 /* match found */ 1300 *audio_clock_info = clock_info[index]; 1301 return; 1302 } 1303 } 1304 } 1305 1306 /* not found */ 1307 if (actual_pixel_clock_in_khz == 0) 1308 actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz; 1309 1310 /* See HDMI spec the table entry under 1311 * pixel clock of "Other". */ 1312 audio_clock_info->pixel_clock_in_10khz = 1313 actual_pixel_clock_in_khz / 10; 1314 audio_clock_info->cts_32khz = actual_pixel_clock_in_khz; 1315 audio_clock_info->cts_44khz = actual_pixel_clock_in_khz; 1316 audio_clock_info->cts_48khz = actual_pixel_clock_in_khz; 1317 1318 audio_clock_info->n_32khz = 4096; 1319 audio_clock_info->n_44khz = 6272; 1320 audio_clock_info->n_48khz = 6144; 1321 } 1322 1323 static void dce110_se_audio_setup( 1324 struct stream_encoder *enc, 1325 unsigned int az_inst, 1326 struct audio_info *audio_info) 1327 { 1328 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1329 1330 uint32_t speakers = 0; 1331 uint32_t channels = 0; 1332 1333 ASSERT(audio_info); 1334 if (audio_info == NULL) 1335 /* This should not happen.it does so we don't get BSOD*/ 1336 return; 1337 1338 speakers = audio_info->flags.info.ALLSPEAKERS; 1339 channels = speakers_to_channels(audio_info->flags.speaker_flags).all; 1340 1341 /* setup the audio stream source select (audio -> dig mapping) */ 1342 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst); 1343 1344 /* Channel allocation */ 1345 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels); 1346 } 1347 1348 static void dce110_se_setup_hdmi_audio( 1349 struct stream_encoder *enc, 1350 const struct audio_crtc_info *crtc_info) 1351 { 1352 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1353 1354 struct audio_clock_info audio_clock_info = {0}; 1355 uint32_t max_packets_per_line; 1356 1357 /* For now still do calculation, although this field is ignored when 1358 above HDMI_PACKET_GEN_VERSION set to 1 */ 1359 max_packets_per_line = calc_max_audio_packets_per_line(crtc_info); 1360 1361 /* HDMI_AUDIO_PACKET_CONTROL */ 1362 REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL, 1363 HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line, 1364 HDMI_AUDIO_DELAY_EN, 1); 1365 1366 /* AFMT_AUDIO_PACKET_CONTROL */ 1367 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1368 1369 /* AFMT_AUDIO_PACKET_CONTROL2 */ 1370 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 1371 AFMT_AUDIO_LAYOUT_OVRD, 0, 1372 AFMT_60958_OSF_OVRD, 0); 1373 1374 /* HDMI_ACR_PACKET_CONTROL */ 1375 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, 1376 HDMI_ACR_AUTO_SEND, 1, 1377 HDMI_ACR_SOURCE, 0, 1378 HDMI_ACR_AUDIO_PRIORITY, 0); 1379 1380 /* Program audio clock sample/regeneration parameters */ 1381 get_audio_clock_info(crtc_info->color_depth, 1382 crtc_info->requested_pixel_clock, 1383 crtc_info->calculated_pixel_clock, 1384 &audio_clock_info); 1385 dm_logger_write(enc->ctx->logger, LOG_HW_AUDIO, 1386 "\n%s:Input::requested_pixel_clock = %d" \ 1387 "calculated_pixel_clock = %d \n", __func__, \ 1388 crtc_info->requested_pixel_clock, \ 1389 crtc_info->calculated_pixel_clock); 1390 1391 /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */ 1392 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); 1393 1394 /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */ 1395 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); 1396 1397 /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */ 1398 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz); 1399 1400 /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */ 1401 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); 1402 1403 /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */ 1404 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); 1405 1406 /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */ 1407 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz); 1408 1409 /* Video driver cannot know in advance which sample rate will 1410 be used by HD Audio driver 1411 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is 1412 programmed below in interruppt callback */ 1413 1414 /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK & 1415 AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */ 1416 REG_UPDATE_2(AFMT_60958_0, 1417 AFMT_60958_CS_CHANNEL_NUMBER_L, 1, 1418 AFMT_60958_CS_CLOCK_ACCURACY, 0); 1419 1420 /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */ 1421 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1422 1423 /*AFMT_60958_2 now keep this settings until 1424 * Programming guide comes out*/ 1425 REG_UPDATE_6(AFMT_60958_2, 1426 AFMT_60958_CS_CHANNEL_NUMBER_2, 3, 1427 AFMT_60958_CS_CHANNEL_NUMBER_3, 4, 1428 AFMT_60958_CS_CHANNEL_NUMBER_4, 5, 1429 AFMT_60958_CS_CHANNEL_NUMBER_5, 6, 1430 AFMT_60958_CS_CHANNEL_NUMBER_6, 7, 1431 AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1432 } 1433 1434 static void dce110_se_setup_dp_audio( 1435 struct stream_encoder *enc) 1436 { 1437 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1438 1439 /* --- DP Audio packet configurations --- */ 1440 1441 /* ATP Configuration */ 1442 REG_SET(DP_SEC_AUD_N, 0, 1443 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT); 1444 1445 /* Async/auto-calc timestamp mode */ 1446 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE, 1447 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC); 1448 1449 /* --- The following are the registers 1450 * copied from the SetupHDMI --- */ 1451 1452 /* AFMT_AUDIO_PACKET_CONTROL */ 1453 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1454 1455 /* AFMT_AUDIO_PACKET_CONTROL2 */ 1456 /* Program the ATP and AIP next */ 1457 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 1458 AFMT_AUDIO_LAYOUT_OVRD, 0, 1459 AFMT_60958_OSF_OVRD, 0); 1460 1461 /* AFMT_INFOFRAME_CONTROL0 */ 1462 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1463 1464 /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */ 1465 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0); 1466 } 1467 1468 static void dce110_se_enable_audio_clock( 1469 struct stream_encoder *enc, 1470 bool enable) 1471 { 1472 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1473 1474 if (REG(AFMT_CNTL) == 0) 1475 return; /* DCE8/10 does not have this register */ 1476 1477 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable); 1478 1479 /* wait for AFMT clock to turn on, 1480 * expectation: this should complete in 1-2 reads 1481 * 1482 * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10); 1483 * 1484 * TODO: wait for clock_on does not work well. May need HW 1485 * program sequence. But audio seems work normally even without wait 1486 * for clock_on status change 1487 */ 1488 } 1489 1490 static void dce110_se_enable_dp_audio( 1491 struct stream_encoder *enc) 1492 { 1493 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1494 1495 /* Enable Audio packets */ 1496 REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); 1497 1498 /* Program the ATP and AIP next */ 1499 REG_UPDATE_2(DP_SEC_CNTL, 1500 DP_SEC_ATP_ENABLE, 1, 1501 DP_SEC_AIP_ENABLE, 1); 1502 1503 /* Program STREAM_ENABLE after all the other enables. */ 1504 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1505 } 1506 1507 static void dce110_se_disable_dp_audio( 1508 struct stream_encoder *enc) 1509 { 1510 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1511 uint32_t value = REG_READ(DP_SEC_CNTL); 1512 1513 /* Disable Audio packets */ 1514 REG_UPDATE_5(DP_SEC_CNTL, 1515 DP_SEC_ASP_ENABLE, 0, 1516 DP_SEC_ATP_ENABLE, 0, 1517 DP_SEC_AIP_ENABLE, 0, 1518 DP_SEC_ACM_ENABLE, 0, 1519 DP_SEC_STREAM_ENABLE, 0); 1520 1521 /* This register shared with encoder info frame. Therefore we need to 1522 keep master enabled if at least on of the fields is not 0 */ 1523 if (value != 0) 1524 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1525 1526 } 1527 1528 void dce110_se_audio_mute_control( 1529 struct stream_encoder *enc, 1530 bool mute) 1531 { 1532 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1533 1534 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute); 1535 } 1536 1537 void dce110_se_dp_audio_setup( 1538 struct stream_encoder *enc, 1539 unsigned int az_inst, 1540 struct audio_info *info) 1541 { 1542 dce110_se_audio_setup(enc, az_inst, info); 1543 } 1544 1545 void dce110_se_dp_audio_enable( 1546 struct stream_encoder *enc) 1547 { 1548 dce110_se_enable_audio_clock(enc, true); 1549 dce110_se_setup_dp_audio(enc); 1550 dce110_se_enable_dp_audio(enc); 1551 } 1552 1553 void dce110_se_dp_audio_disable( 1554 struct stream_encoder *enc) 1555 { 1556 dce110_se_disable_dp_audio(enc); 1557 dce110_se_enable_audio_clock(enc, false); 1558 } 1559 1560 void dce110_se_hdmi_audio_setup( 1561 struct stream_encoder *enc, 1562 unsigned int az_inst, 1563 struct audio_info *info, 1564 struct audio_crtc_info *audio_crtc_info) 1565 { 1566 dce110_se_enable_audio_clock(enc, true); 1567 dce110_se_setup_hdmi_audio(enc, audio_crtc_info); 1568 dce110_se_audio_setup(enc, az_inst, info); 1569 } 1570 1571 void dce110_se_hdmi_audio_disable( 1572 struct stream_encoder *enc) 1573 { 1574 dce110_se_enable_audio_clock(enc, false); 1575 } 1576 1577 1578 static void setup_stereo_sync( 1579 struct stream_encoder *enc, 1580 int tg_inst, bool enable) 1581 { 1582 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1583 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); 1584 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable); 1585 } 1586 1587 1588 static const struct stream_encoder_funcs dce110_str_enc_funcs = { 1589 .dp_set_stream_attribute = 1590 dce110_stream_encoder_dp_set_stream_attribute, 1591 .hdmi_set_stream_attribute = 1592 dce110_stream_encoder_hdmi_set_stream_attribute, 1593 .dvi_set_stream_attribute = 1594 dce110_stream_encoder_dvi_set_stream_attribute, 1595 .set_mst_bandwidth = 1596 dce110_stream_encoder_set_mst_bandwidth, 1597 .update_hdmi_info_packets = 1598 dce110_stream_encoder_update_hdmi_info_packets, 1599 .stop_hdmi_info_packets = 1600 dce110_stream_encoder_stop_hdmi_info_packets, 1601 .update_dp_info_packets = 1602 dce110_stream_encoder_update_dp_info_packets, 1603 .stop_dp_info_packets = 1604 dce110_stream_encoder_stop_dp_info_packets, 1605 .dp_blank = 1606 dce110_stream_encoder_dp_blank, 1607 .dp_unblank = 1608 dce110_stream_encoder_dp_unblank, 1609 .audio_mute_control = dce110_se_audio_mute_control, 1610 1611 .dp_audio_setup = dce110_se_dp_audio_setup, 1612 .dp_audio_enable = dce110_se_dp_audio_enable, 1613 .dp_audio_disable = dce110_se_dp_audio_disable, 1614 1615 .hdmi_audio_setup = dce110_se_hdmi_audio_setup, 1616 .hdmi_audio_disable = dce110_se_hdmi_audio_disable, 1617 .setup_stereo_sync = setup_stereo_sync, 1618 .set_avmute = dce110_stream_encoder_set_avmute, 1619 1620 }; 1621 1622 void dce110_stream_encoder_construct( 1623 struct dce110_stream_encoder *enc110, 1624 struct dc_context *ctx, 1625 struct dc_bios *bp, 1626 enum engine_id eng_id, 1627 const struct dce110_stream_enc_registers *regs, 1628 const struct dce_stream_encoder_shift *se_shift, 1629 const struct dce_stream_encoder_mask *se_mask) 1630 { 1631 enc110->base.funcs = &dce110_str_enc_funcs; 1632 enc110->base.ctx = ctx; 1633 enc110->base.id = eng_id; 1634 enc110->base.bp = bp; 1635 enc110->regs = regs; 1636 enc110->se_shift = se_shift; 1637 enc110->se_mask = se_mask; 1638 } 1639