1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dc_bios_types.h" 27 #include "dce_stream_encoder.h" 28 #include "reg_helper.h" 29 #include "hw_shared.h" 30 31 #define DC_LOGGER \ 32 enc110->base.ctx->logger 33 34 35 #define REG(reg)\ 36 (enc110->regs->reg) 37 38 #undef FN 39 #define FN(reg_name, field_name) \ 40 enc110->se_shift->field_name, enc110->se_mask->field_name 41 42 #define VBI_LINE_0 0 43 #define DP_BLANK_MAX_RETRY 20 44 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 45 46 #ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 47 #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x00000010L 48 #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x00000300L 49 #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x00000004 50 #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x00000008 51 #endif 52 53 enum { 54 DP_MST_UPDATE_MAX_RETRY = 50 55 }; 56 57 #define DCE110_SE(audio)\ 58 container_of(audio, struct dce110_stream_encoder, base) 59 60 #define CTX \ 61 enc110->base.ctx 62 63 static void dce110_update_generic_info_packet( 64 struct dce110_stream_encoder *enc110, 65 uint32_t packet_index, 66 const struct dc_info_packet *info_packet) 67 { 68 uint32_t regval; 69 /* TODOFPGA Figure out a proper number for max_retries polling for lock 70 * use 50 for now. 71 */ 72 uint32_t max_retries = 50; 73 74 /*we need turn on clock before programming AFMT block*/ 75 if (REG(AFMT_CNTL)) 76 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 77 78 if (REG(AFMT_VBI_PACKET_CONTROL1)) { 79 if (packet_index >= 8) 80 ASSERT(0); 81 82 /* poll dig_update_lock is not locked -> asic internal signal 83 * assume otg master lock will unlock it 84 */ 85 /* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, 86 0, 10, max_retries);*/ 87 88 /* check if HW reading GSP memory */ 89 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, 90 0, 10, max_retries); 91 92 /* HW does is not reading GSP memory not reading too long -> 93 * something wrong. clear GPS memory access and notify? 94 * hw SW is writing to GSP memory 95 */ 96 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); 97 } 98 /* choose which generic packet to use */ 99 { 100 regval = REG_READ(AFMT_VBI_PACKET_CONTROL); 101 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, 102 AFMT_GENERIC_INDEX, packet_index); 103 } 104 105 /* write generic packet header 106 * (4th byte is for GENERIC0 only) */ 107 { 108 REG_SET_4(AFMT_GENERIC_HDR, 0, 109 AFMT_GENERIC_HB0, info_packet->hb0, 110 AFMT_GENERIC_HB1, info_packet->hb1, 111 AFMT_GENERIC_HB2, info_packet->hb2, 112 AFMT_GENERIC_HB3, info_packet->hb3); 113 } 114 115 /* write generic packet contents 116 * (we never use last 4 bytes) 117 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers */ 118 { 119 const uint32_t *content = 120 (const uint32_t *) &info_packet->sb[0]; 121 122 REG_WRITE(AFMT_GENERIC_0, *content++); 123 REG_WRITE(AFMT_GENERIC_1, *content++); 124 REG_WRITE(AFMT_GENERIC_2, *content++); 125 REG_WRITE(AFMT_GENERIC_3, *content++); 126 REG_WRITE(AFMT_GENERIC_4, *content++); 127 REG_WRITE(AFMT_GENERIC_5, *content++); 128 REG_WRITE(AFMT_GENERIC_6, *content++); 129 REG_WRITE(AFMT_GENERIC_7, *content); 130 } 131 132 if (!REG(AFMT_VBI_PACKET_CONTROL1)) { 133 /* force double-buffered packet update */ 134 REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL, 135 AFMT_GENERIC0_UPDATE, (packet_index == 0), 136 AFMT_GENERIC2_UPDATE, (packet_index == 2)); 137 } 138 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 139 if (REG(AFMT_VBI_PACKET_CONTROL1)) { 140 switch (packet_index) { 141 case 0: 142 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 143 AFMT_GENERIC0_FRAME_UPDATE, 1); 144 break; 145 case 1: 146 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 147 AFMT_GENERIC1_FRAME_UPDATE, 1); 148 break; 149 case 2: 150 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 151 AFMT_GENERIC2_FRAME_UPDATE, 1); 152 break; 153 case 3: 154 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 155 AFMT_GENERIC3_FRAME_UPDATE, 1); 156 break; 157 case 4: 158 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 159 AFMT_GENERIC4_FRAME_UPDATE, 1); 160 break; 161 case 5: 162 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 163 AFMT_GENERIC5_FRAME_UPDATE, 1); 164 break; 165 case 6: 166 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 167 AFMT_GENERIC6_FRAME_UPDATE, 1); 168 break; 169 case 7: 170 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 171 AFMT_GENERIC7_FRAME_UPDATE, 1); 172 break; 173 default: 174 break; 175 } 176 } 177 #endif 178 } 179 180 static void dce110_update_hdmi_info_packet( 181 struct dce110_stream_encoder *enc110, 182 uint32_t packet_index, 183 const struct dc_info_packet *info_packet) 184 { 185 uint32_t cont, send, line; 186 187 if (info_packet->valid) { 188 dce110_update_generic_info_packet( 189 enc110, 190 packet_index, 191 info_packet); 192 193 /* enable transmission of packet(s) - 194 * packet transmission begins on the next frame */ 195 cont = 1; 196 /* send packet(s) every frame */ 197 send = 1; 198 /* select line number to send packets on */ 199 line = 2; 200 } else { 201 cont = 0; 202 send = 0; 203 line = 0; 204 } 205 206 /* choose which generic packet control to use */ 207 switch (packet_index) { 208 case 0: 209 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 210 HDMI_GENERIC0_CONT, cont, 211 HDMI_GENERIC0_SEND, send, 212 HDMI_GENERIC0_LINE, line); 213 break; 214 case 1: 215 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 216 HDMI_GENERIC1_CONT, cont, 217 HDMI_GENERIC1_SEND, send, 218 HDMI_GENERIC1_LINE, line); 219 break; 220 case 2: 221 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 222 HDMI_GENERIC0_CONT, cont, 223 HDMI_GENERIC0_SEND, send, 224 HDMI_GENERIC0_LINE, line); 225 break; 226 case 3: 227 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 228 HDMI_GENERIC1_CONT, cont, 229 HDMI_GENERIC1_SEND, send, 230 HDMI_GENERIC1_LINE, line); 231 break; 232 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 233 case 4: 234 if (REG(HDMI_GENERIC_PACKET_CONTROL2)) 235 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 236 HDMI_GENERIC0_CONT, cont, 237 HDMI_GENERIC0_SEND, send, 238 HDMI_GENERIC0_LINE, line); 239 break; 240 case 5: 241 if (REG(HDMI_GENERIC_PACKET_CONTROL2)) 242 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 243 HDMI_GENERIC1_CONT, cont, 244 HDMI_GENERIC1_SEND, send, 245 HDMI_GENERIC1_LINE, line); 246 break; 247 case 6: 248 if (REG(HDMI_GENERIC_PACKET_CONTROL3)) 249 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 250 HDMI_GENERIC0_CONT, cont, 251 HDMI_GENERIC0_SEND, send, 252 HDMI_GENERIC0_LINE, line); 253 break; 254 case 7: 255 if (REG(HDMI_GENERIC_PACKET_CONTROL3)) 256 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 257 HDMI_GENERIC1_CONT, cont, 258 HDMI_GENERIC1_SEND, send, 259 HDMI_GENERIC1_LINE, line); 260 break; 261 #endif 262 default: 263 /* invalid HW packet index */ 264 DC_LOG_WARNING( 265 "Invalid HW packet index: %s()\n", 266 __func__); 267 return; 268 } 269 } 270 271 /* setup stream encoder in dp mode */ 272 static void dce110_stream_encoder_dp_set_stream_attribute( 273 struct stream_encoder *enc, 274 struct dc_crtc_timing *crtc_timing, 275 enum dc_color_space output_color_space) 276 { 277 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 278 uint32_t h_active_start; 279 uint32_t v_active_start; 280 uint32_t misc0 = 0; 281 uint32_t misc1 = 0; 282 uint32_t h_blank; 283 uint32_t h_back_porch; 284 uint8_t synchronous_clock = 0; /* asynchronous mode */ 285 uint8_t colorimetry_bpc; 286 uint8_t dynamic_range_rgb = 0; /*full range*/ 287 uint8_t dynamic_range_ycbcr = 1; /*bt709*/ 288 #endif 289 290 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 291 292 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 293 if (REG(DP_DB_CNTL)) 294 REG_UPDATE(DP_DB_CNTL, DP_DB_DISABLE, 1); 295 #endif 296 297 /* set pixel encoding */ 298 switch (crtc_timing->pixel_encoding) { 299 case PIXEL_ENCODING_YCBCR422: 300 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 301 DP_PIXEL_ENCODING_TYPE_YCBCR422); 302 break; 303 case PIXEL_ENCODING_YCBCR444: 304 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 305 DP_PIXEL_ENCODING_TYPE_YCBCR444); 306 307 if (crtc_timing->flags.Y_ONLY) 308 if (crtc_timing->display_color_depth != COLOR_DEPTH_666) 309 /* HW testing only, no use case yet. 310 * Color depth of Y-only could be 311 * 8, 10, 12, 16 bits */ 312 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 313 DP_PIXEL_ENCODING_TYPE_Y_ONLY); 314 /* Note: DP_MSA_MISC1 bit 7 is the indicator 315 * of Y-only mode. 316 * This bit is set in HW if register 317 * DP_PIXEL_ENCODING is programmed to 0x4 */ 318 break; 319 case PIXEL_ENCODING_YCBCR420: 320 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 321 DP_PIXEL_ENCODING_TYPE_YCBCR420); 322 if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN) 323 REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1); 324 325 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 326 if (enc110->se_mask->DP_VID_N_MUL) 327 REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1); 328 #endif 329 break; 330 default: 331 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 332 DP_PIXEL_ENCODING_TYPE_RGB444); 333 break; 334 } 335 336 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 337 if (REG(DP_MSA_MISC)) 338 misc1 = REG_READ(DP_MSA_MISC); 339 #endif 340 341 /* set color depth */ 342 343 switch (crtc_timing->display_color_depth) { 344 case COLOR_DEPTH_666: 345 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 346 0); 347 break; 348 case COLOR_DEPTH_888: 349 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 350 DP_COMPONENT_PIXEL_DEPTH_8BPC); 351 break; 352 case COLOR_DEPTH_101010: 353 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 354 DP_COMPONENT_PIXEL_DEPTH_10BPC); 355 356 break; 357 case COLOR_DEPTH_121212: 358 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 359 DP_COMPONENT_PIXEL_DEPTH_12BPC); 360 break; 361 default: 362 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 363 DP_COMPONENT_PIXEL_DEPTH_6BPC); 364 break; 365 } 366 367 /* set dynamic range and YCbCr range */ 368 369 370 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 371 switch (crtc_timing->display_color_depth) { 372 case COLOR_DEPTH_666: 373 colorimetry_bpc = 0; 374 break; 375 case COLOR_DEPTH_888: 376 colorimetry_bpc = 1; 377 break; 378 case COLOR_DEPTH_101010: 379 colorimetry_bpc = 2; 380 break; 381 case COLOR_DEPTH_121212: 382 colorimetry_bpc = 3; 383 break; 384 default: 385 colorimetry_bpc = 0; 386 break; 387 } 388 389 misc0 = misc0 | synchronous_clock; 390 misc0 = colorimetry_bpc << 5; 391 392 if (REG(DP_MSA_TIMING_PARAM1)) { 393 switch (output_color_space) { 394 case COLOR_SPACE_SRGB: 395 misc0 = misc0 | 0x0; 396 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 397 dynamic_range_rgb = 0; /*full range*/ 398 break; 399 case COLOR_SPACE_SRGB_LIMITED: 400 misc0 = misc0 | 0x8; /* bit3=1 */ 401 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 402 dynamic_range_rgb = 1; /*limited range*/ 403 break; 404 case COLOR_SPACE_YCBCR601: 405 case COLOR_SPACE_YCBCR601_LIMITED: 406 misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */ 407 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 408 dynamic_range_ycbcr = 0; /*bt601*/ 409 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) 410 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 411 else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) 412 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 413 break; 414 case COLOR_SPACE_YCBCR709: 415 case COLOR_SPACE_YCBCR709_LIMITED: 416 misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */ 417 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 418 dynamic_range_ycbcr = 1; /*bt709*/ 419 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) 420 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 421 else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) 422 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 423 break; 424 case COLOR_SPACE_2020_RGB_LIMITEDRANGE: 425 dynamic_range_rgb = 1; /*limited range*/ 426 break; 427 case COLOR_SPACE_2020_RGB_FULLRANGE: 428 case COLOR_SPACE_2020_YCBCR: 429 case COLOR_SPACE_XR_RGB: 430 case COLOR_SPACE_MSREF_SCRGB: 431 case COLOR_SPACE_ADOBERGB: 432 case COLOR_SPACE_DCIP3: 433 case COLOR_SPACE_XV_YCC_709: 434 case COLOR_SPACE_XV_YCC_601: 435 case COLOR_SPACE_DISPLAYNATIVE: 436 case COLOR_SPACE_DOLBYVISION: 437 case COLOR_SPACE_APPCTRL: 438 case COLOR_SPACE_CUSTOMPOINTS: 439 case COLOR_SPACE_UNKNOWN: 440 /* do nothing */ 441 break; 442 } 443 if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE) 444 REG_UPDATE_2( 445 DP_PIXEL_FORMAT, 446 DP_DYN_RANGE, dynamic_range_rgb, 447 DP_YCBCR_RANGE, dynamic_range_ycbcr); 448 449 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 450 if (REG(DP_MSA_COLORIMETRY)) 451 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0); 452 453 if (REG(DP_MSA_MISC)) 454 REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */ 455 456 /* dcn new register 457 * dc_crtc_timing is vesa dmt struct. data from edid 458 */ 459 if (REG(DP_MSA_TIMING_PARAM1)) 460 REG_SET_2(DP_MSA_TIMING_PARAM1, 0, 461 DP_MSA_HTOTAL, crtc_timing->h_total, 462 DP_MSA_VTOTAL, crtc_timing->v_total); 463 #endif 464 465 /* calcuate from vesa timing parameters 466 * h_active_start related to leading edge of sync 467 */ 468 469 h_blank = crtc_timing->h_total - crtc_timing->h_border_left - 470 crtc_timing->h_addressable - crtc_timing->h_border_right; 471 472 h_back_porch = h_blank - crtc_timing->h_front_porch - 473 crtc_timing->h_sync_width; 474 475 /* start at begining of left border */ 476 h_active_start = crtc_timing->h_sync_width + h_back_porch; 477 478 479 v_active_start = crtc_timing->v_total - crtc_timing->v_border_top - 480 crtc_timing->v_addressable - crtc_timing->v_border_bottom - 481 crtc_timing->v_front_porch; 482 483 484 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 485 /* start at begining of left border */ 486 if (REG(DP_MSA_TIMING_PARAM2)) 487 REG_SET_2(DP_MSA_TIMING_PARAM2, 0, 488 DP_MSA_HSTART, h_active_start, 489 DP_MSA_VSTART, v_active_start); 490 491 if (REG(DP_MSA_TIMING_PARAM3)) 492 REG_SET_4(DP_MSA_TIMING_PARAM3, 0, 493 DP_MSA_HSYNCWIDTH, 494 crtc_timing->h_sync_width, 495 DP_MSA_HSYNCPOLARITY, 496 !crtc_timing->flags.HSYNC_POSITIVE_POLARITY, 497 DP_MSA_VSYNCWIDTH, 498 crtc_timing->v_sync_width, 499 DP_MSA_VSYNCPOLARITY, 500 !crtc_timing->flags.VSYNC_POSITIVE_POLARITY); 501 502 /* HWDITH include border or overscan */ 503 if (REG(DP_MSA_TIMING_PARAM4)) 504 REG_SET_2(DP_MSA_TIMING_PARAM4, 0, 505 DP_MSA_HWIDTH, crtc_timing->h_border_left + 506 crtc_timing->h_addressable + crtc_timing->h_border_right, 507 DP_MSA_VHEIGHT, crtc_timing->v_border_top + 508 crtc_timing->v_addressable + crtc_timing->v_border_bottom); 509 #endif 510 } 511 #endif 512 } 513 514 static void dce110_stream_encoder_set_stream_attribute_helper( 515 struct dce110_stream_encoder *enc110, 516 struct dc_crtc_timing *crtc_timing) 517 { 518 if (enc110->regs->TMDS_CNTL) { 519 switch (crtc_timing->pixel_encoding) { 520 case PIXEL_ENCODING_YCBCR422: 521 REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 1); 522 break; 523 default: 524 REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 0); 525 break; 526 } 527 REG_UPDATE(TMDS_CNTL, TMDS_COLOR_FORMAT, 0); 528 } else if (enc110->regs->DIG_FE_CNTL) { 529 switch (crtc_timing->pixel_encoding) { 530 case PIXEL_ENCODING_YCBCR422: 531 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1); 532 break; 533 default: 534 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0); 535 break; 536 } 537 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0); 538 } 539 540 } 541 542 /* setup stream encoder in hdmi mode */ 543 static void dce110_stream_encoder_hdmi_set_stream_attribute( 544 struct stream_encoder *enc, 545 struct dc_crtc_timing *crtc_timing, 546 int actual_pix_clk_khz, 547 bool enable_audio) 548 { 549 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 550 struct bp_encoder_control cntl = {0}; 551 552 cntl.action = ENCODER_CONTROL_SETUP; 553 cntl.engine_id = enc110->base.id; 554 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; 555 cntl.enable_dp_audio = enable_audio; 556 cntl.pixel_clock = actual_pix_clk_khz; 557 cntl.lanes_number = LANE_COUNT_FOUR; 558 559 if (enc110->base.bp->funcs->encoder_control( 560 enc110->base.bp, &cntl) != BP_RESULT_OK) 561 return; 562 563 dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing); 564 565 /* setup HDMI engine */ 566 if (!enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) { 567 REG_UPDATE_3(HDMI_CONTROL, 568 HDMI_PACKET_GEN_VERSION, 1, 569 HDMI_KEEPOUT_MODE, 1, 570 HDMI_DEEP_COLOR_ENABLE, 0); 571 } else if (enc110->regs->DIG_FE_CNTL) { 572 REG_UPDATE_5(HDMI_CONTROL, 573 HDMI_PACKET_GEN_VERSION, 1, 574 HDMI_KEEPOUT_MODE, 1, 575 HDMI_DEEP_COLOR_ENABLE, 0, 576 HDMI_DATA_SCRAMBLE_EN, 0, 577 HDMI_CLOCK_CHANNEL_RATE, 0); 578 } 579 580 switch (crtc_timing->display_color_depth) { 581 case COLOR_DEPTH_888: 582 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 583 break; 584 case COLOR_DEPTH_101010: 585 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 586 REG_UPDATE_2(HDMI_CONTROL, 587 HDMI_DEEP_COLOR_DEPTH, 1, 588 HDMI_DEEP_COLOR_ENABLE, 0); 589 } else { 590 REG_UPDATE_2(HDMI_CONTROL, 591 HDMI_DEEP_COLOR_DEPTH, 1, 592 HDMI_DEEP_COLOR_ENABLE, 1); 593 } 594 break; 595 case COLOR_DEPTH_121212: 596 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 597 REG_UPDATE_2(HDMI_CONTROL, 598 HDMI_DEEP_COLOR_DEPTH, 2, 599 HDMI_DEEP_COLOR_ENABLE, 0); 600 } else { 601 REG_UPDATE_2(HDMI_CONTROL, 602 HDMI_DEEP_COLOR_DEPTH, 2, 603 HDMI_DEEP_COLOR_ENABLE, 1); 604 } 605 break; 606 case COLOR_DEPTH_161616: 607 REG_UPDATE_2(HDMI_CONTROL, 608 HDMI_DEEP_COLOR_DEPTH, 3, 609 HDMI_DEEP_COLOR_ENABLE, 1); 610 break; 611 default: 612 break; 613 } 614 615 if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) { 616 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) { 617 /* enable HDMI data scrambler 618 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M 619 * Clock channel frequency is 1/4 of character rate. 620 */ 621 REG_UPDATE_2(HDMI_CONTROL, 622 HDMI_DATA_SCRAMBLE_EN, 1, 623 HDMI_CLOCK_CHANNEL_RATE, 1); 624 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) { 625 626 /* TODO: New feature for DCE11, still need to implement */ 627 628 /* enable HDMI data scrambler 629 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE 630 * Clock channel frequency is the same 631 * as character rate 632 */ 633 REG_UPDATE_2(HDMI_CONTROL, 634 HDMI_DATA_SCRAMBLE_EN, 1, 635 HDMI_CLOCK_CHANNEL_RATE, 0); 636 } 637 } 638 639 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL, 640 HDMI_GC_CONT, 1, 641 HDMI_GC_SEND, 1, 642 HDMI_NULL_SEND, 1); 643 644 /* following belongs to audio */ 645 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 646 647 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 648 649 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 650 VBI_LINE_0 + 2); 651 652 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); 653 654 } 655 656 /* setup stream encoder in dvi mode */ 657 static void dce110_stream_encoder_dvi_set_stream_attribute( 658 struct stream_encoder *enc, 659 struct dc_crtc_timing *crtc_timing, 660 bool is_dual_link) 661 { 662 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 663 struct bp_encoder_control cntl = {0}; 664 665 cntl.action = ENCODER_CONTROL_SETUP; 666 cntl.engine_id = enc110->base.id; 667 cntl.signal = is_dual_link ? 668 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK; 669 cntl.enable_dp_audio = false; 670 cntl.pixel_clock = crtc_timing->pix_clk_khz; 671 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; 672 673 if (enc110->base.bp->funcs->encoder_control( 674 enc110->base.bp, &cntl) != BP_RESULT_OK) 675 return; 676 677 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); 678 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888); 679 dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing); 680 } 681 682 static void dce110_stream_encoder_set_mst_bandwidth( 683 struct stream_encoder *enc, 684 struct fixed31_32 avg_time_slots_per_mtp) 685 { 686 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 687 uint32_t x = dc_fixpt_floor( 688 avg_time_slots_per_mtp); 689 uint32_t y = dc_fixpt_ceil( 690 dc_fixpt_shl( 691 dc_fixpt_sub_int( 692 avg_time_slots_per_mtp, 693 x), 694 26)); 695 696 { 697 REG_SET_2(DP_MSE_RATE_CNTL, 0, 698 DP_MSE_RATE_X, x, 699 DP_MSE_RATE_Y, y); 700 } 701 702 /* wait for update to be completed on the link */ 703 /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */ 704 /* is reset to 0 (not pending) */ 705 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, 706 0, 707 10, DP_MST_UPDATE_MAX_RETRY); 708 } 709 710 static void dce110_stream_encoder_update_hdmi_info_packets( 711 struct stream_encoder *enc, 712 const struct encoder_info_frame *info_frame) 713 { 714 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 715 716 if (enc110->se_mask->HDMI_AVI_INFO_CONT && 717 enc110->se_mask->HDMI_AVI_INFO_SEND) { 718 719 if (info_frame->avi.valid) { 720 const uint32_t *content = 721 (const uint32_t *) &info_frame->avi.sb[0]; 722 /*we need turn on clock before programming AFMT block*/ 723 if (REG(AFMT_CNTL)) 724 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 725 726 REG_WRITE(AFMT_AVI_INFO0, content[0]); 727 728 REG_WRITE(AFMT_AVI_INFO1, content[1]); 729 730 REG_WRITE(AFMT_AVI_INFO2, content[2]); 731 732 REG_WRITE(AFMT_AVI_INFO3, content[3]); 733 734 REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, 735 info_frame->avi.hb1); 736 737 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0, 738 HDMI_AVI_INFO_SEND, 1, 739 HDMI_AVI_INFO_CONT, 1); 740 741 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 742 VBI_LINE_0 + 2); 743 744 } else { 745 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0, 746 HDMI_AVI_INFO_SEND, 0, 747 HDMI_AVI_INFO_CONT, 0); 748 } 749 } 750 751 if (enc110->se_mask->HDMI_AVI_INFO_CONT && 752 enc110->se_mask->HDMI_AVI_INFO_SEND) { 753 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor); 754 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut); 755 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd); 756 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd); 757 } 758 759 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 760 if (enc110->se_mask->HDMI_DB_DISABLE) { 761 /* for bring up, disable dp double TODO */ 762 if (REG(HDMI_DB_CONTROL)) 763 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); 764 765 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->avi); 766 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->vendor); 767 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->gamut); 768 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->spd); 769 dce110_update_hdmi_info_packet(enc110, 4, &info_frame->hdrsmd); 770 } 771 #endif 772 } 773 774 static void dce110_stream_encoder_stop_hdmi_info_packets( 775 struct stream_encoder *enc) 776 { 777 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 778 779 /* stop generic packets 0 & 1 on HDMI */ 780 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0, 781 HDMI_GENERIC1_CONT, 0, 782 HDMI_GENERIC1_LINE, 0, 783 HDMI_GENERIC1_SEND, 0, 784 HDMI_GENERIC0_CONT, 0, 785 HDMI_GENERIC0_LINE, 0, 786 HDMI_GENERIC0_SEND, 0); 787 788 /* stop generic packets 2 & 3 on HDMI */ 789 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0, 790 HDMI_GENERIC0_CONT, 0, 791 HDMI_GENERIC0_LINE, 0, 792 HDMI_GENERIC0_SEND, 0, 793 HDMI_GENERIC1_CONT, 0, 794 HDMI_GENERIC1_LINE, 0, 795 HDMI_GENERIC1_SEND, 0); 796 797 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 798 /* stop generic packets 2 & 3 on HDMI */ 799 if (REG(HDMI_GENERIC_PACKET_CONTROL2)) 800 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0, 801 HDMI_GENERIC0_CONT, 0, 802 HDMI_GENERIC0_LINE, 0, 803 HDMI_GENERIC0_SEND, 0, 804 HDMI_GENERIC1_CONT, 0, 805 HDMI_GENERIC1_LINE, 0, 806 HDMI_GENERIC1_SEND, 0); 807 808 if (REG(HDMI_GENERIC_PACKET_CONTROL3)) 809 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0, 810 HDMI_GENERIC0_CONT, 0, 811 HDMI_GENERIC0_LINE, 0, 812 HDMI_GENERIC0_SEND, 0, 813 HDMI_GENERIC1_CONT, 0, 814 HDMI_GENERIC1_LINE, 0, 815 HDMI_GENERIC1_SEND, 0); 816 #endif 817 } 818 819 static void dce110_stream_encoder_update_dp_info_packets( 820 struct stream_encoder *enc, 821 const struct encoder_info_frame *info_frame) 822 { 823 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 824 uint32_t value = 0; 825 826 if (info_frame->vsc.valid) 827 dce110_update_generic_info_packet( 828 enc110, 829 0, /* packetIndex */ 830 &info_frame->vsc); 831 832 if (info_frame->spd.valid) 833 dce110_update_generic_info_packet( 834 enc110, 835 2, /* packetIndex */ 836 &info_frame->spd); 837 838 if (info_frame->hdrsmd.valid) 839 dce110_update_generic_info_packet( 840 enc110, 841 3, /* packetIndex */ 842 &info_frame->hdrsmd); 843 844 /* enable/disable transmission of packet(s). 845 * If enabled, packet transmission begins on the next frame 846 */ 847 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); 848 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); 849 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); 850 851 /* This bit is the master enable bit. 852 * When enabling secondary stream engine, 853 * this master bit must also be set. 854 * This register shared with audio info frame. 855 * Therefore we need to enable master bit 856 * if at least on of the fields is not 0 857 */ 858 value = REG_READ(DP_SEC_CNTL); 859 if (value) 860 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 861 } 862 863 static void dce110_stream_encoder_stop_dp_info_packets( 864 struct stream_encoder *enc) 865 { 866 /* stop generic packets on DP */ 867 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 868 uint32_t value = 0; 869 870 if (enc110->se_mask->DP_SEC_AVI_ENABLE) { 871 REG_SET_7(DP_SEC_CNTL, 0, 872 DP_SEC_GSP0_ENABLE, 0, 873 DP_SEC_GSP1_ENABLE, 0, 874 DP_SEC_GSP2_ENABLE, 0, 875 DP_SEC_GSP3_ENABLE, 0, 876 DP_SEC_AVI_ENABLE, 0, 877 DP_SEC_MPG_ENABLE, 0, 878 DP_SEC_STREAM_ENABLE, 0); 879 } 880 881 /* this register shared with audio info frame. 882 * therefore we need to keep master enabled 883 * if at least one of the fields is not 0 */ 884 value = REG_READ(DP_SEC_CNTL); 885 if (value) 886 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 887 888 } 889 890 static void dce110_stream_encoder_dp_blank( 891 struct stream_encoder *enc) 892 { 893 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 894 uint32_t retries = 0; 895 uint32_t reg1 = 0; 896 uint32_t max_retries = DP_BLANK_MAX_RETRY * 10; 897 898 /* Note: For CZ, we are changing driver default to disable 899 * stream deferred to next VBLANK. If results are positive, we 900 * will make the same change to all DCE versions. There are a 901 * handful of panels that cannot handle disable stream at 902 * HBLANK and will result in a white line flash across the 903 * screen on stream disable. */ 904 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1); 905 if ((reg1 & 0x1) == 0) 906 /*stream not enabled*/ 907 return; 908 /* Specify the video stream disable point 909 * (2 = start of the next vertical blank) */ 910 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2); 911 /* Larger delay to wait until VBLANK - use max retry of 912 * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode + 913 * a little more because we may not trust delay accuracy. 914 */ 915 max_retries = DP_BLANK_MAX_RETRY * 150; 916 917 /* disable DP stream */ 918 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); 919 920 /* the encoder stops sending the video stream 921 * at the start of the vertical blanking. 922 * Poll for DP_VID_STREAM_STATUS == 0 923 */ 924 925 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 926 0, 927 10, max_retries); 928 929 ASSERT(retries <= max_retries); 930 931 /* Tell the DP encoder to ignore timing from CRTC, must be done after 932 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is 933 * complete, stream status will be stuck in video stream enabled state, 934 * i.e. DP_VID_STREAM_STATUS stuck at 1. 935 */ 936 937 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true); 938 } 939 940 /* output video stream to link encoder */ 941 static void dce110_stream_encoder_dp_unblank( 942 struct stream_encoder *enc, 943 const struct encoder_unblank_param *param) 944 { 945 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 946 947 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) { 948 uint32_t n_vid = 0x8000; 949 uint32_t m_vid; 950 951 /* M / N = Fstream / Flink 952 * m_vid / n_vid = pixel rate / link rate 953 */ 954 955 uint64_t m_vid_l = n_vid; 956 957 m_vid_l *= param->pixel_clk_khz; 958 m_vid_l = div_u64(m_vid_l, 959 param->link_settings.link_rate 960 * LINK_RATE_REF_FREQ_IN_KHZ); 961 962 m_vid = (uint32_t) m_vid_l; 963 964 /* enable auto measurement */ 965 966 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0); 967 968 /* auto measurement need 1 full 0x8000 symbol cycle to kick in, 969 * therefore program initial value for Mvid and Nvid 970 */ 971 972 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid); 973 974 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid); 975 976 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1); 977 } 978 979 /* set DIG_START to 0x1 to resync FIFO */ 980 981 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); 982 983 /* switch DP encoder to CRTC data */ 984 985 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); 986 987 /* wait 100us for DIG/DP logic to prime 988 * (i.e. a few video lines) 989 */ 990 udelay(100); 991 992 /* the hardware would start sending video at the start of the next DP 993 * frame (i.e. rising edge of the vblank). 994 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this 995 * register has no effect on enable transition! HW always guarantees 996 * VID_STREAM enable at start of next frame, and this is not 997 * programmable 998 */ 999 1000 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); 1001 } 1002 1003 static void dce110_stream_encoder_set_avmute( 1004 struct stream_encoder *enc, 1005 bool enable) 1006 { 1007 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1008 unsigned int value = enable ? 1 : 0; 1009 1010 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value); 1011 } 1012 1013 1014 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000 1015 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1 1016 1017 #include "include/audio_types.h" 1018 1019 /** 1020 * speakersToChannels 1021 * 1022 * @brief 1023 * translate speakers to channels 1024 * 1025 * FL - Front Left 1026 * FR - Front Right 1027 * RL - Rear Left 1028 * RR - Rear Right 1029 * RC - Rear Center 1030 * FC - Front Center 1031 * FLC - Front Left Center 1032 * FRC - Front Right Center 1033 * RLC - Rear Left Center 1034 * RRC - Rear Right Center 1035 * LFE - Low Freq Effect 1036 * 1037 * FC 1038 * FLC FRC 1039 * FL FR 1040 * 1041 * LFE 1042 * () 1043 * 1044 * 1045 * RL RR 1046 * RLC RRC 1047 * RC 1048 * 1049 * ch 8 7 6 5 4 3 2 1 1050 * 0b00000011 - - - - - - FR FL 1051 * 0b00000111 - - - - - LFE FR FL 1052 * 0b00001011 - - - - FC - FR FL 1053 * 0b00001111 - - - - FC LFE FR FL 1054 * 0b00010011 - - - RC - - FR FL 1055 * 0b00010111 - - - RC - LFE FR FL 1056 * 0b00011011 - - - RC FC - FR FL 1057 * 0b00011111 - - - RC FC LFE FR FL 1058 * 0b00110011 - - RR RL - - FR FL 1059 * 0b00110111 - - RR RL - LFE FR FL 1060 * 0b00111011 - - RR RL FC - FR FL 1061 * 0b00111111 - - RR RL FC LFE FR FL 1062 * 0b01110011 - RC RR RL - - FR FL 1063 * 0b01110111 - RC RR RL - LFE FR FL 1064 * 0b01111011 - RC RR RL FC - FR FL 1065 * 0b01111111 - RC RR RL FC LFE FR FL 1066 * 0b11110011 RRC RLC RR RL - - FR FL 1067 * 0b11110111 RRC RLC RR RL - LFE FR FL 1068 * 0b11111011 RRC RLC RR RL FC - FR FL 1069 * 0b11111111 RRC RLC RR RL FC LFE FR FL 1070 * 0b11000011 FRC FLC - - - - FR FL 1071 * 0b11000111 FRC FLC - - - LFE FR FL 1072 * 0b11001011 FRC FLC - - FC - FR FL 1073 * 0b11001111 FRC FLC - - FC LFE FR FL 1074 * 0b11010011 FRC FLC - RC - - FR FL 1075 * 0b11010111 FRC FLC - RC - LFE FR FL 1076 * 0b11011011 FRC FLC - RC FC - FR FL 1077 * 0b11011111 FRC FLC - RC FC LFE FR FL 1078 * 0b11110011 FRC FLC RR RL - - FR FL 1079 * 0b11110111 FRC FLC RR RL - LFE FR FL 1080 * 0b11111011 FRC FLC RR RL FC - FR FL 1081 * 0b11111111 FRC FLC RR RL FC LFE FR FL 1082 * 1083 * @param 1084 * speakers - speaker information as it comes from CEA audio block 1085 */ 1086 /* translate speakers to channels */ 1087 1088 union audio_cea_channels { 1089 uint8_t all; 1090 struct audio_cea_channels_bits { 1091 uint32_t FL:1; 1092 uint32_t FR:1; 1093 uint32_t LFE:1; 1094 uint32_t FC:1; 1095 uint32_t RL_RC:1; 1096 uint32_t RR:1; 1097 uint32_t RC_RLC_FLC:1; 1098 uint32_t RRC_FRC:1; 1099 } channels; 1100 }; 1101 1102 struct audio_clock_info { 1103 /* pixel clock frequency*/ 1104 uint32_t pixel_clock_in_10khz; 1105 /* N - 32KHz audio */ 1106 uint32_t n_32khz; 1107 /* CTS - 32KHz audio*/ 1108 uint32_t cts_32khz; 1109 uint32_t n_44khz; 1110 uint32_t cts_44khz; 1111 uint32_t n_48khz; 1112 uint32_t cts_48khz; 1113 }; 1114 1115 /* 25.2MHz/1.001*/ 1116 /* 25.2MHz/1.001*/ 1117 /* 25.2MHz*/ 1118 /* 27MHz */ 1119 /* 27MHz*1.001*/ 1120 /* 27MHz*1.001*/ 1121 /* 54MHz*/ 1122 /* 54MHz*1.001*/ 1123 /* 74.25MHz/1.001*/ 1124 /* 74.25MHz*/ 1125 /* 148.5MHz/1.001*/ 1126 /* 148.5MHz*/ 1127 1128 static const struct audio_clock_info audio_clock_info_table[16] = { 1129 {2517, 4576, 28125, 7007, 31250, 6864, 28125}, 1130 {2518, 4576, 28125, 7007, 31250, 6864, 28125}, 1131 {2520, 4096, 25200, 6272, 28000, 6144, 25200}, 1132 {2700, 4096, 27000, 6272, 30000, 6144, 27000}, 1133 {2702, 4096, 27027, 6272, 30030, 6144, 27027}, 1134 {2703, 4096, 27027, 6272, 30030, 6144, 27027}, 1135 {5400, 4096, 54000, 6272, 60000, 6144, 54000}, 1136 {5405, 4096, 54054, 6272, 60060, 6144, 54054}, 1137 {7417, 11648, 210937, 17836, 234375, 11648, 140625}, 1138 {7425, 4096, 74250, 6272, 82500, 6144, 74250}, 1139 {14835, 11648, 421875, 8918, 234375, 5824, 140625}, 1140 {14850, 4096, 148500, 6272, 165000, 6144, 148500}, 1141 {29670, 5824, 421875, 4459, 234375, 5824, 281250}, 1142 {29700, 3072, 222750, 4704, 247500, 5120, 247500}, 1143 {59340, 5824, 843750, 8918, 937500, 5824, 562500}, 1144 {59400, 3072, 445500, 9408, 990000, 6144, 594000} 1145 }; 1146 1147 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = { 1148 {2517, 9152, 84375, 7007, 48875, 9152, 56250}, 1149 {2518, 9152, 84375, 7007, 48875, 9152, 56250}, 1150 {2520, 4096, 37800, 6272, 42000, 6144, 37800}, 1151 {2700, 4096, 40500, 6272, 45000, 6144, 40500}, 1152 {2702, 8192, 81081, 6272, 45045, 8192, 54054}, 1153 {2703, 8192, 81081, 6272, 45045, 8192, 54054}, 1154 {5400, 4096, 81000, 6272, 90000, 6144, 81000}, 1155 {5405, 4096, 81081, 6272, 90090, 6144, 81081}, 1156 {7417, 11648, 316406, 17836, 351562, 11648, 210937}, 1157 {7425, 4096, 111375, 6272, 123750, 6144, 111375}, 1158 {14835, 11648, 632812, 17836, 703125, 11648, 421875}, 1159 {14850, 4096, 222750, 6272, 247500, 6144, 222750}, 1160 {29670, 5824, 632812, 8918, 703125, 5824, 421875}, 1161 {29700, 4096, 445500, 4704, 371250, 5120, 371250} 1162 }; 1163 1164 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = { 1165 {2517, 4576, 56250, 7007, 62500, 6864, 56250}, 1166 {2518, 4576, 56250, 7007, 62500, 6864, 56250}, 1167 {2520, 4096, 50400, 6272, 56000, 6144, 50400}, 1168 {2700, 4096, 54000, 6272, 60000, 6144, 54000}, 1169 {2702, 4096, 54054, 6267, 60060, 8192, 54054}, 1170 {2703, 4096, 54054, 6272, 60060, 8192, 54054}, 1171 {5400, 4096, 108000, 6272, 120000, 6144, 108000}, 1172 {5405, 4096, 108108, 6272, 120120, 6144, 108108}, 1173 {7417, 11648, 421875, 17836, 468750, 11648, 281250}, 1174 {7425, 4096, 148500, 6272, 165000, 6144, 148500}, 1175 {14835, 11648, 843750, 8918, 468750, 11648, 281250}, 1176 {14850, 4096, 297000, 6272, 330000, 6144, 297000}, 1177 {29670, 5824, 843750, 4459, 468750, 5824, 562500}, 1178 {29700, 3072, 445500, 4704, 495000, 5120, 495000} 1179 1180 1181 }; 1182 1183 static union audio_cea_channels speakers_to_channels( 1184 struct audio_speaker_flags speaker_flags) 1185 { 1186 union audio_cea_channels cea_channels = {0}; 1187 1188 /* these are one to one */ 1189 cea_channels.channels.FL = speaker_flags.FL_FR; 1190 cea_channels.channels.FR = speaker_flags.FL_FR; 1191 cea_channels.channels.LFE = speaker_flags.LFE; 1192 cea_channels.channels.FC = speaker_flags.FC; 1193 1194 /* if Rear Left and Right exist move RC speaker to channel 7 1195 * otherwise to channel 5 1196 */ 1197 if (speaker_flags.RL_RR) { 1198 cea_channels.channels.RL_RC = speaker_flags.RL_RR; 1199 cea_channels.channels.RR = speaker_flags.RL_RR; 1200 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC; 1201 } else { 1202 cea_channels.channels.RL_RC = speaker_flags.RC; 1203 } 1204 1205 /* FRONT Left Right Center and REAR Left Right Center are exclusive */ 1206 if (speaker_flags.FLC_FRC) { 1207 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC; 1208 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC; 1209 } else { 1210 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC; 1211 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC; 1212 } 1213 1214 return cea_channels; 1215 } 1216 1217 static uint32_t calc_max_audio_packets_per_line( 1218 const struct audio_crtc_info *crtc_info) 1219 { 1220 uint32_t max_packets_per_line; 1221 1222 max_packets_per_line = 1223 crtc_info->h_total - crtc_info->h_active; 1224 1225 if (crtc_info->pixel_repetition) 1226 max_packets_per_line *= crtc_info->pixel_repetition; 1227 1228 /* for other hdmi features */ 1229 max_packets_per_line -= 58; 1230 /* for Control Period */ 1231 max_packets_per_line -= 16; 1232 /* Number of Audio Packets per Line */ 1233 max_packets_per_line /= 32; 1234 1235 return max_packets_per_line; 1236 } 1237 1238 static void get_audio_clock_info( 1239 enum dc_color_depth color_depth, 1240 uint32_t crtc_pixel_clock_in_khz, 1241 uint32_t actual_pixel_clock_in_khz, 1242 struct audio_clock_info *audio_clock_info) 1243 { 1244 const struct audio_clock_info *clock_info; 1245 uint32_t index; 1246 uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10; 1247 uint32_t audio_array_size; 1248 1249 switch (color_depth) { 1250 case COLOR_DEPTH_161616: 1251 clock_info = audio_clock_info_table_48bpc; 1252 audio_array_size = ARRAY_SIZE( 1253 audio_clock_info_table_48bpc); 1254 break; 1255 case COLOR_DEPTH_121212: 1256 clock_info = audio_clock_info_table_36bpc; 1257 audio_array_size = ARRAY_SIZE( 1258 audio_clock_info_table_36bpc); 1259 break; 1260 default: 1261 clock_info = audio_clock_info_table; 1262 audio_array_size = ARRAY_SIZE( 1263 audio_clock_info_table); 1264 break; 1265 } 1266 1267 if (clock_info != NULL) { 1268 /* search for exact pixel clock in table */ 1269 for (index = 0; index < audio_array_size; index++) { 1270 if (clock_info[index].pixel_clock_in_10khz > 1271 crtc_pixel_clock_in_10khz) 1272 break; /* not match */ 1273 else if (clock_info[index].pixel_clock_in_10khz == 1274 crtc_pixel_clock_in_10khz) { 1275 /* match found */ 1276 *audio_clock_info = clock_info[index]; 1277 return; 1278 } 1279 } 1280 } 1281 1282 /* not found */ 1283 if (actual_pixel_clock_in_khz == 0) 1284 actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz; 1285 1286 /* See HDMI spec the table entry under 1287 * pixel clock of "Other". */ 1288 audio_clock_info->pixel_clock_in_10khz = 1289 actual_pixel_clock_in_khz / 10; 1290 audio_clock_info->cts_32khz = actual_pixel_clock_in_khz; 1291 audio_clock_info->cts_44khz = actual_pixel_clock_in_khz; 1292 audio_clock_info->cts_48khz = actual_pixel_clock_in_khz; 1293 1294 audio_clock_info->n_32khz = 4096; 1295 audio_clock_info->n_44khz = 6272; 1296 audio_clock_info->n_48khz = 6144; 1297 } 1298 1299 static void dce110_se_audio_setup( 1300 struct stream_encoder *enc, 1301 unsigned int az_inst, 1302 struct audio_info *audio_info) 1303 { 1304 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1305 1306 uint32_t speakers = 0; 1307 uint32_t channels = 0; 1308 1309 ASSERT(audio_info); 1310 if (audio_info == NULL) 1311 /* This should not happen.it does so we don't get BSOD*/ 1312 return; 1313 1314 speakers = audio_info->flags.info.ALLSPEAKERS; 1315 channels = speakers_to_channels(audio_info->flags.speaker_flags).all; 1316 1317 /* setup the audio stream source select (audio -> dig mapping) */ 1318 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst); 1319 1320 /* Channel allocation */ 1321 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels); 1322 } 1323 1324 static void dce110_se_setup_hdmi_audio( 1325 struct stream_encoder *enc, 1326 const struct audio_crtc_info *crtc_info) 1327 { 1328 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1329 1330 struct audio_clock_info audio_clock_info = {0}; 1331 uint32_t max_packets_per_line; 1332 1333 /* For now still do calculation, although this field is ignored when 1334 above HDMI_PACKET_GEN_VERSION set to 1 */ 1335 max_packets_per_line = calc_max_audio_packets_per_line(crtc_info); 1336 1337 /* HDMI_AUDIO_PACKET_CONTROL */ 1338 REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL, 1339 HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line, 1340 HDMI_AUDIO_DELAY_EN, 1); 1341 1342 /* AFMT_AUDIO_PACKET_CONTROL */ 1343 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1344 1345 /* AFMT_AUDIO_PACKET_CONTROL2 */ 1346 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 1347 AFMT_AUDIO_LAYOUT_OVRD, 0, 1348 AFMT_60958_OSF_OVRD, 0); 1349 1350 /* HDMI_ACR_PACKET_CONTROL */ 1351 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, 1352 HDMI_ACR_AUTO_SEND, 1, 1353 HDMI_ACR_SOURCE, 0, 1354 HDMI_ACR_AUDIO_PRIORITY, 0); 1355 1356 /* Program audio clock sample/regeneration parameters */ 1357 get_audio_clock_info(crtc_info->color_depth, 1358 crtc_info->requested_pixel_clock, 1359 crtc_info->calculated_pixel_clock, 1360 &audio_clock_info); 1361 DC_LOG_HW_AUDIO( 1362 "\n%s:Input::requested_pixel_clock = %d" \ 1363 "calculated_pixel_clock = %d \n", __func__, \ 1364 crtc_info->requested_pixel_clock, \ 1365 crtc_info->calculated_pixel_clock); 1366 1367 /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */ 1368 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); 1369 1370 /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */ 1371 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); 1372 1373 /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */ 1374 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz); 1375 1376 /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */ 1377 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); 1378 1379 /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */ 1380 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); 1381 1382 /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */ 1383 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz); 1384 1385 /* Video driver cannot know in advance which sample rate will 1386 be used by HD Audio driver 1387 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is 1388 programmed below in interruppt callback */ 1389 1390 /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK & 1391 AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */ 1392 REG_UPDATE_2(AFMT_60958_0, 1393 AFMT_60958_CS_CHANNEL_NUMBER_L, 1, 1394 AFMT_60958_CS_CLOCK_ACCURACY, 0); 1395 1396 /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */ 1397 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1398 1399 /*AFMT_60958_2 now keep this settings until 1400 * Programming guide comes out*/ 1401 REG_UPDATE_6(AFMT_60958_2, 1402 AFMT_60958_CS_CHANNEL_NUMBER_2, 3, 1403 AFMT_60958_CS_CHANNEL_NUMBER_3, 4, 1404 AFMT_60958_CS_CHANNEL_NUMBER_4, 5, 1405 AFMT_60958_CS_CHANNEL_NUMBER_5, 6, 1406 AFMT_60958_CS_CHANNEL_NUMBER_6, 7, 1407 AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1408 } 1409 1410 static void dce110_se_setup_dp_audio( 1411 struct stream_encoder *enc) 1412 { 1413 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1414 1415 /* --- DP Audio packet configurations --- */ 1416 1417 /* ATP Configuration */ 1418 REG_SET(DP_SEC_AUD_N, 0, 1419 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT); 1420 1421 /* Async/auto-calc timestamp mode */ 1422 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE, 1423 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC); 1424 1425 /* --- The following are the registers 1426 * copied from the SetupHDMI --- */ 1427 1428 /* AFMT_AUDIO_PACKET_CONTROL */ 1429 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1430 1431 /* AFMT_AUDIO_PACKET_CONTROL2 */ 1432 /* Program the ATP and AIP next */ 1433 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 1434 AFMT_AUDIO_LAYOUT_OVRD, 0, 1435 AFMT_60958_OSF_OVRD, 0); 1436 1437 /* AFMT_INFOFRAME_CONTROL0 */ 1438 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1439 1440 /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */ 1441 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0); 1442 } 1443 1444 static void dce110_se_enable_audio_clock( 1445 struct stream_encoder *enc, 1446 bool enable) 1447 { 1448 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1449 1450 if (REG(AFMT_CNTL) == 0) 1451 return; /* DCE8/10 does not have this register */ 1452 1453 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable); 1454 1455 /* wait for AFMT clock to turn on, 1456 * expectation: this should complete in 1-2 reads 1457 * 1458 * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10); 1459 * 1460 * TODO: wait for clock_on does not work well. May need HW 1461 * program sequence. But audio seems work normally even without wait 1462 * for clock_on status change 1463 */ 1464 } 1465 1466 static void dce110_se_enable_dp_audio( 1467 struct stream_encoder *enc) 1468 { 1469 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1470 1471 /* Enable Audio packets */ 1472 REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); 1473 1474 /* Program the ATP and AIP next */ 1475 REG_UPDATE_2(DP_SEC_CNTL, 1476 DP_SEC_ATP_ENABLE, 1, 1477 DP_SEC_AIP_ENABLE, 1); 1478 1479 /* Program STREAM_ENABLE after all the other enables. */ 1480 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1481 } 1482 1483 static void dce110_se_disable_dp_audio( 1484 struct stream_encoder *enc) 1485 { 1486 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1487 uint32_t value = 0; 1488 1489 /* Disable Audio packets */ 1490 REG_UPDATE_5(DP_SEC_CNTL, 1491 DP_SEC_ASP_ENABLE, 0, 1492 DP_SEC_ATP_ENABLE, 0, 1493 DP_SEC_AIP_ENABLE, 0, 1494 DP_SEC_ACM_ENABLE, 0, 1495 DP_SEC_STREAM_ENABLE, 0); 1496 1497 /* This register shared with encoder info frame. Therefore we need to 1498 keep master enabled if at least on of the fields is not 0 */ 1499 value = REG_READ(DP_SEC_CNTL); 1500 if (value != 0) 1501 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1502 1503 } 1504 1505 void dce110_se_audio_mute_control( 1506 struct stream_encoder *enc, 1507 bool mute) 1508 { 1509 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1510 1511 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute); 1512 } 1513 1514 void dce110_se_dp_audio_setup( 1515 struct stream_encoder *enc, 1516 unsigned int az_inst, 1517 struct audio_info *info) 1518 { 1519 dce110_se_audio_setup(enc, az_inst, info); 1520 } 1521 1522 void dce110_se_dp_audio_enable( 1523 struct stream_encoder *enc) 1524 { 1525 dce110_se_enable_audio_clock(enc, true); 1526 dce110_se_setup_dp_audio(enc); 1527 dce110_se_enable_dp_audio(enc); 1528 } 1529 1530 void dce110_se_dp_audio_disable( 1531 struct stream_encoder *enc) 1532 { 1533 dce110_se_disable_dp_audio(enc); 1534 dce110_se_enable_audio_clock(enc, false); 1535 } 1536 1537 void dce110_se_hdmi_audio_setup( 1538 struct stream_encoder *enc, 1539 unsigned int az_inst, 1540 struct audio_info *info, 1541 struct audio_crtc_info *audio_crtc_info) 1542 { 1543 dce110_se_enable_audio_clock(enc, true); 1544 dce110_se_setup_hdmi_audio(enc, audio_crtc_info); 1545 dce110_se_audio_setup(enc, az_inst, info); 1546 } 1547 1548 void dce110_se_hdmi_audio_disable( 1549 struct stream_encoder *enc) 1550 { 1551 dce110_se_enable_audio_clock(enc, false); 1552 } 1553 1554 1555 static void setup_stereo_sync( 1556 struct stream_encoder *enc, 1557 int tg_inst, bool enable) 1558 { 1559 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1560 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); 1561 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable); 1562 } 1563 1564 1565 static const struct stream_encoder_funcs dce110_str_enc_funcs = { 1566 .dp_set_stream_attribute = 1567 dce110_stream_encoder_dp_set_stream_attribute, 1568 .hdmi_set_stream_attribute = 1569 dce110_stream_encoder_hdmi_set_stream_attribute, 1570 .dvi_set_stream_attribute = 1571 dce110_stream_encoder_dvi_set_stream_attribute, 1572 .set_mst_bandwidth = 1573 dce110_stream_encoder_set_mst_bandwidth, 1574 .update_hdmi_info_packets = 1575 dce110_stream_encoder_update_hdmi_info_packets, 1576 .stop_hdmi_info_packets = 1577 dce110_stream_encoder_stop_hdmi_info_packets, 1578 .update_dp_info_packets = 1579 dce110_stream_encoder_update_dp_info_packets, 1580 .stop_dp_info_packets = 1581 dce110_stream_encoder_stop_dp_info_packets, 1582 .dp_blank = 1583 dce110_stream_encoder_dp_blank, 1584 .dp_unblank = 1585 dce110_stream_encoder_dp_unblank, 1586 .audio_mute_control = dce110_se_audio_mute_control, 1587 1588 .dp_audio_setup = dce110_se_dp_audio_setup, 1589 .dp_audio_enable = dce110_se_dp_audio_enable, 1590 .dp_audio_disable = dce110_se_dp_audio_disable, 1591 1592 .hdmi_audio_setup = dce110_se_hdmi_audio_setup, 1593 .hdmi_audio_disable = dce110_se_hdmi_audio_disable, 1594 .setup_stereo_sync = setup_stereo_sync, 1595 .set_avmute = dce110_stream_encoder_set_avmute, 1596 1597 }; 1598 1599 void dce110_stream_encoder_construct( 1600 struct dce110_stream_encoder *enc110, 1601 struct dc_context *ctx, 1602 struct dc_bios *bp, 1603 enum engine_id eng_id, 1604 const struct dce110_stream_enc_registers *regs, 1605 const struct dce_stream_encoder_shift *se_shift, 1606 const struct dce_stream_encoder_mask *se_mask) 1607 { 1608 enc110->base.funcs = &dce110_str_enc_funcs; 1609 enc110->base.ctx = ctx; 1610 enc110->base.id = eng_id; 1611 enc110->base.bp = bp; 1612 enc110->regs = regs; 1613 enc110->se_shift = se_shift; 1614 enc110->se_mask = se_mask; 1615 } 1616