1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dc_bios_types.h" 27 #include "dce_stream_encoder.h" 28 #include "reg_helper.h" 29 #include "hw_shared.h" 30 31 #define DC_LOGGER \ 32 enc110->base.ctx->logger 33 34 35 #define REG(reg)\ 36 (enc110->regs->reg) 37 38 #undef FN 39 #define FN(reg_name, field_name) \ 40 enc110->se_shift->field_name, enc110->se_mask->field_name 41 42 #define VBI_LINE_0 0 43 #define DP_BLANK_MAX_RETRY 20 44 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 45 46 #ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 47 #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x00000010L 48 #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x00000300L 49 #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x00000004 50 #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x00000008 51 #endif 52 53 enum { 54 DP_MST_UPDATE_MAX_RETRY = 50 55 }; 56 57 #define DCE110_SE(audio)\ 58 container_of(audio, struct dce110_stream_encoder, base) 59 60 #define CTX \ 61 enc110->base.ctx 62 63 static void dce110_update_generic_info_packet( 64 struct dce110_stream_encoder *enc110, 65 uint32_t packet_index, 66 const struct dc_info_packet *info_packet) 67 { 68 uint32_t regval; 69 /* TODOFPGA Figure out a proper number for max_retries polling for lock 70 * use 50 for now. 71 */ 72 uint32_t max_retries = 50; 73 74 /*we need turn on clock before programming AFMT block*/ 75 if (REG(AFMT_CNTL)) 76 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 77 78 if (REG(AFMT_VBI_PACKET_CONTROL1)) { 79 if (packet_index >= 8) 80 ASSERT(0); 81 82 /* poll dig_update_lock is not locked -> asic internal signal 83 * assume otg master lock will unlock it 84 */ 85 /* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, 86 0, 10, max_retries);*/ 87 88 /* check if HW reading GSP memory */ 89 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, 90 0, 10, max_retries); 91 92 /* HW does is not reading GSP memory not reading too long -> 93 * something wrong. clear GPS memory access and notify? 94 * hw SW is writing to GSP memory 95 */ 96 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); 97 } 98 /* choose which generic packet to use */ 99 { 100 regval = REG_READ(AFMT_VBI_PACKET_CONTROL); 101 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, 102 AFMT_GENERIC_INDEX, packet_index); 103 } 104 105 /* write generic packet header 106 * (4th byte is for GENERIC0 only) */ 107 { 108 REG_SET_4(AFMT_GENERIC_HDR, 0, 109 AFMT_GENERIC_HB0, info_packet->hb0, 110 AFMT_GENERIC_HB1, info_packet->hb1, 111 AFMT_GENERIC_HB2, info_packet->hb2, 112 AFMT_GENERIC_HB3, info_packet->hb3); 113 } 114 115 /* write generic packet contents 116 * (we never use last 4 bytes) 117 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers */ 118 { 119 const uint32_t *content = 120 (const uint32_t *) &info_packet->sb[0]; 121 122 REG_WRITE(AFMT_GENERIC_0, *content++); 123 REG_WRITE(AFMT_GENERIC_1, *content++); 124 REG_WRITE(AFMT_GENERIC_2, *content++); 125 REG_WRITE(AFMT_GENERIC_3, *content++); 126 REG_WRITE(AFMT_GENERIC_4, *content++); 127 REG_WRITE(AFMT_GENERIC_5, *content++); 128 REG_WRITE(AFMT_GENERIC_6, *content++); 129 REG_WRITE(AFMT_GENERIC_7, *content); 130 } 131 132 if (!REG(AFMT_VBI_PACKET_CONTROL1)) { 133 /* force double-buffered packet update */ 134 REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL, 135 AFMT_GENERIC0_UPDATE, (packet_index == 0), 136 AFMT_GENERIC2_UPDATE, (packet_index == 2)); 137 } 138 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 139 if (REG(AFMT_VBI_PACKET_CONTROL1)) { 140 switch (packet_index) { 141 case 0: 142 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 143 AFMT_GENERIC0_FRAME_UPDATE, 1); 144 break; 145 case 1: 146 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 147 AFMT_GENERIC1_FRAME_UPDATE, 1); 148 break; 149 case 2: 150 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 151 AFMT_GENERIC2_FRAME_UPDATE, 1); 152 break; 153 case 3: 154 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 155 AFMT_GENERIC3_FRAME_UPDATE, 1); 156 break; 157 case 4: 158 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 159 AFMT_GENERIC4_FRAME_UPDATE, 1); 160 break; 161 case 5: 162 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 163 AFMT_GENERIC5_FRAME_UPDATE, 1); 164 break; 165 case 6: 166 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 167 AFMT_GENERIC6_FRAME_UPDATE, 1); 168 break; 169 case 7: 170 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 171 AFMT_GENERIC7_FRAME_UPDATE, 1); 172 break; 173 default: 174 break; 175 } 176 } 177 #endif 178 } 179 180 static void dce110_update_hdmi_info_packet( 181 struct dce110_stream_encoder *enc110, 182 uint32_t packet_index, 183 const struct dc_info_packet *info_packet) 184 { 185 uint32_t cont, send, line; 186 187 if (info_packet->valid) { 188 dce110_update_generic_info_packet( 189 enc110, 190 packet_index, 191 info_packet); 192 193 /* enable transmission of packet(s) - 194 * packet transmission begins on the next frame */ 195 cont = 1; 196 /* send packet(s) every frame */ 197 send = 1; 198 /* select line number to send packets on */ 199 line = 2; 200 } else { 201 cont = 0; 202 send = 0; 203 line = 0; 204 } 205 206 /* choose which generic packet control to use */ 207 switch (packet_index) { 208 case 0: 209 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 210 HDMI_GENERIC0_CONT, cont, 211 HDMI_GENERIC0_SEND, send, 212 HDMI_GENERIC0_LINE, line); 213 break; 214 case 1: 215 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 216 HDMI_GENERIC1_CONT, cont, 217 HDMI_GENERIC1_SEND, send, 218 HDMI_GENERIC1_LINE, line); 219 break; 220 case 2: 221 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 222 HDMI_GENERIC0_CONT, cont, 223 HDMI_GENERIC0_SEND, send, 224 HDMI_GENERIC0_LINE, line); 225 break; 226 case 3: 227 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 228 HDMI_GENERIC1_CONT, cont, 229 HDMI_GENERIC1_SEND, send, 230 HDMI_GENERIC1_LINE, line); 231 break; 232 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 233 case 4: 234 if (REG(HDMI_GENERIC_PACKET_CONTROL2)) 235 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 236 HDMI_GENERIC0_CONT, cont, 237 HDMI_GENERIC0_SEND, send, 238 HDMI_GENERIC0_LINE, line); 239 break; 240 case 5: 241 if (REG(HDMI_GENERIC_PACKET_CONTROL2)) 242 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 243 HDMI_GENERIC1_CONT, cont, 244 HDMI_GENERIC1_SEND, send, 245 HDMI_GENERIC1_LINE, line); 246 break; 247 case 6: 248 if (REG(HDMI_GENERIC_PACKET_CONTROL3)) 249 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 250 HDMI_GENERIC0_CONT, cont, 251 HDMI_GENERIC0_SEND, send, 252 HDMI_GENERIC0_LINE, line); 253 break; 254 case 7: 255 if (REG(HDMI_GENERIC_PACKET_CONTROL3)) 256 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 257 HDMI_GENERIC1_CONT, cont, 258 HDMI_GENERIC1_SEND, send, 259 HDMI_GENERIC1_LINE, line); 260 break; 261 #endif 262 default: 263 /* invalid HW packet index */ 264 DC_LOG_WARNING( 265 "Invalid HW packet index: %s()\n", 266 __func__); 267 return; 268 } 269 } 270 271 /* setup stream encoder in dp mode */ 272 static void dce110_stream_encoder_dp_set_stream_attribute( 273 struct stream_encoder *enc, 274 struct dc_crtc_timing *crtc_timing, 275 enum dc_color_space output_color_space) 276 { 277 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 278 uint32_t h_active_start; 279 uint32_t v_active_start; 280 uint32_t misc0 = 0; 281 uint32_t misc1 = 0; 282 uint32_t h_blank; 283 uint32_t h_back_porch; 284 uint8_t synchronous_clock = 0; /* asynchronous mode */ 285 uint8_t colorimetry_bpc; 286 uint8_t dynamic_range_rgb = 0; /*full range*/ 287 uint8_t dynamic_range_ycbcr = 1; /*bt709*/ 288 #endif 289 290 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 291 292 /* set pixel encoding */ 293 switch (crtc_timing->pixel_encoding) { 294 case PIXEL_ENCODING_YCBCR422: 295 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 296 DP_PIXEL_ENCODING_TYPE_YCBCR422); 297 break; 298 case PIXEL_ENCODING_YCBCR444: 299 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 300 DP_PIXEL_ENCODING_TYPE_YCBCR444); 301 302 if (crtc_timing->flags.Y_ONLY) 303 if (crtc_timing->display_color_depth != COLOR_DEPTH_666) 304 /* HW testing only, no use case yet. 305 * Color depth of Y-only could be 306 * 8, 10, 12, 16 bits */ 307 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 308 DP_PIXEL_ENCODING_TYPE_Y_ONLY); 309 /* Note: DP_MSA_MISC1 bit 7 is the indicator 310 * of Y-only mode. 311 * This bit is set in HW if register 312 * DP_PIXEL_ENCODING is programmed to 0x4 */ 313 break; 314 case PIXEL_ENCODING_YCBCR420: 315 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 316 DP_PIXEL_ENCODING_TYPE_YCBCR420); 317 if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN) 318 REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1); 319 320 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 321 if (enc110->se_mask->DP_VID_N_MUL) 322 REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1); 323 #endif 324 break; 325 default: 326 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 327 DP_PIXEL_ENCODING_TYPE_RGB444); 328 break; 329 } 330 331 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 332 if (REG(DP_MSA_MISC)) 333 misc1 = REG_READ(DP_MSA_MISC); 334 #endif 335 336 /* set color depth */ 337 338 switch (crtc_timing->display_color_depth) { 339 case COLOR_DEPTH_666: 340 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 341 0); 342 break; 343 case COLOR_DEPTH_888: 344 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 345 DP_COMPONENT_PIXEL_DEPTH_8BPC); 346 break; 347 case COLOR_DEPTH_101010: 348 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 349 DP_COMPONENT_PIXEL_DEPTH_10BPC); 350 351 break; 352 case COLOR_DEPTH_121212: 353 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 354 DP_COMPONENT_PIXEL_DEPTH_12BPC); 355 break; 356 default: 357 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 358 DP_COMPONENT_PIXEL_DEPTH_6BPC); 359 break; 360 } 361 362 /* set dynamic range and YCbCr range */ 363 364 365 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 366 switch (crtc_timing->display_color_depth) { 367 case COLOR_DEPTH_666: 368 colorimetry_bpc = 0; 369 break; 370 case COLOR_DEPTH_888: 371 colorimetry_bpc = 1; 372 break; 373 case COLOR_DEPTH_101010: 374 colorimetry_bpc = 2; 375 break; 376 case COLOR_DEPTH_121212: 377 colorimetry_bpc = 3; 378 break; 379 default: 380 colorimetry_bpc = 0; 381 break; 382 } 383 384 misc0 = misc0 | synchronous_clock; 385 misc0 = colorimetry_bpc << 5; 386 387 if (REG(DP_MSA_TIMING_PARAM1)) { 388 switch (output_color_space) { 389 case COLOR_SPACE_SRGB: 390 misc0 = misc0 | 0x0; 391 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 392 dynamic_range_rgb = 0; /*full range*/ 393 break; 394 case COLOR_SPACE_SRGB_LIMITED: 395 misc0 = misc0 | 0x8; /* bit3=1 */ 396 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 397 dynamic_range_rgb = 1; /*limited range*/ 398 break; 399 case COLOR_SPACE_YCBCR601: 400 case COLOR_SPACE_YCBCR601_LIMITED: 401 misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */ 402 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 403 dynamic_range_ycbcr = 0; /*bt601*/ 404 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) 405 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 406 else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) 407 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 408 break; 409 case COLOR_SPACE_YCBCR709: 410 case COLOR_SPACE_YCBCR709_LIMITED: 411 misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */ 412 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 413 dynamic_range_ycbcr = 1; /*bt709*/ 414 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) 415 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 416 else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) 417 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 418 break; 419 case COLOR_SPACE_2020_RGB_LIMITEDRANGE: 420 dynamic_range_rgb = 1; /*limited range*/ 421 break; 422 case COLOR_SPACE_2020_RGB_FULLRANGE: 423 case COLOR_SPACE_2020_YCBCR: 424 case COLOR_SPACE_XR_RGB: 425 case COLOR_SPACE_MSREF_SCRGB: 426 case COLOR_SPACE_ADOBERGB: 427 case COLOR_SPACE_DCIP3: 428 case COLOR_SPACE_XV_YCC_709: 429 case COLOR_SPACE_XV_YCC_601: 430 case COLOR_SPACE_DISPLAYNATIVE: 431 case COLOR_SPACE_DOLBYVISION: 432 case COLOR_SPACE_APPCTRL: 433 case COLOR_SPACE_CUSTOMPOINTS: 434 case COLOR_SPACE_UNKNOWN: 435 /* do nothing */ 436 break; 437 } 438 if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE) 439 REG_UPDATE_2( 440 DP_PIXEL_FORMAT, 441 DP_DYN_RANGE, dynamic_range_rgb, 442 DP_YCBCR_RANGE, dynamic_range_ycbcr); 443 444 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 445 if (REG(DP_MSA_COLORIMETRY)) 446 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0); 447 448 if (REG(DP_MSA_MISC)) 449 REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */ 450 451 /* dcn new register 452 * dc_crtc_timing is vesa dmt struct. data from edid 453 */ 454 if (REG(DP_MSA_TIMING_PARAM1)) 455 REG_SET_2(DP_MSA_TIMING_PARAM1, 0, 456 DP_MSA_HTOTAL, crtc_timing->h_total, 457 DP_MSA_VTOTAL, crtc_timing->v_total); 458 #endif 459 460 /* calcuate from vesa timing parameters 461 * h_active_start related to leading edge of sync 462 */ 463 464 h_blank = crtc_timing->h_total - crtc_timing->h_border_left - 465 crtc_timing->h_addressable - crtc_timing->h_border_right; 466 467 h_back_porch = h_blank - crtc_timing->h_front_porch - 468 crtc_timing->h_sync_width; 469 470 /* start at begining of left border */ 471 h_active_start = crtc_timing->h_sync_width + h_back_porch; 472 473 474 v_active_start = crtc_timing->v_total - crtc_timing->v_border_top - 475 crtc_timing->v_addressable - crtc_timing->v_border_bottom - 476 crtc_timing->v_front_porch; 477 478 479 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 480 /* start at begining of left border */ 481 if (REG(DP_MSA_TIMING_PARAM2)) 482 REG_SET_2(DP_MSA_TIMING_PARAM2, 0, 483 DP_MSA_HSTART, h_active_start, 484 DP_MSA_VSTART, v_active_start); 485 486 if (REG(DP_MSA_TIMING_PARAM3)) 487 REG_SET_4(DP_MSA_TIMING_PARAM3, 0, 488 DP_MSA_HSYNCWIDTH, 489 crtc_timing->h_sync_width, 490 DP_MSA_HSYNCPOLARITY, 491 !crtc_timing->flags.HSYNC_POSITIVE_POLARITY, 492 DP_MSA_VSYNCWIDTH, 493 crtc_timing->v_sync_width, 494 DP_MSA_VSYNCPOLARITY, 495 !crtc_timing->flags.VSYNC_POSITIVE_POLARITY); 496 497 /* HWDITH include border or overscan */ 498 if (REG(DP_MSA_TIMING_PARAM4)) 499 REG_SET_2(DP_MSA_TIMING_PARAM4, 0, 500 DP_MSA_HWIDTH, crtc_timing->h_border_left + 501 crtc_timing->h_addressable + crtc_timing->h_border_right, 502 DP_MSA_VHEIGHT, crtc_timing->v_border_top + 503 crtc_timing->v_addressable + crtc_timing->v_border_bottom); 504 #endif 505 } 506 #endif 507 } 508 509 static void dce110_stream_encoder_set_stream_attribute_helper( 510 struct dce110_stream_encoder *enc110, 511 struct dc_crtc_timing *crtc_timing) 512 { 513 if (enc110->regs->TMDS_CNTL) { 514 switch (crtc_timing->pixel_encoding) { 515 case PIXEL_ENCODING_YCBCR422: 516 REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 1); 517 break; 518 default: 519 REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 0); 520 break; 521 } 522 REG_UPDATE(TMDS_CNTL, TMDS_COLOR_FORMAT, 0); 523 } else if (enc110->regs->DIG_FE_CNTL) { 524 switch (crtc_timing->pixel_encoding) { 525 case PIXEL_ENCODING_YCBCR422: 526 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1); 527 break; 528 default: 529 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0); 530 break; 531 } 532 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0); 533 } 534 535 } 536 537 /* setup stream encoder in hdmi mode */ 538 static void dce110_stream_encoder_hdmi_set_stream_attribute( 539 struct stream_encoder *enc, 540 struct dc_crtc_timing *crtc_timing, 541 int actual_pix_clk_khz, 542 bool enable_audio) 543 { 544 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 545 struct bp_encoder_control cntl = {0}; 546 547 cntl.action = ENCODER_CONTROL_SETUP; 548 cntl.engine_id = enc110->base.id; 549 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; 550 cntl.enable_dp_audio = enable_audio; 551 cntl.pixel_clock = actual_pix_clk_khz; 552 cntl.lanes_number = LANE_COUNT_FOUR; 553 554 if (enc110->base.bp->funcs->encoder_control( 555 enc110->base.bp, &cntl) != BP_RESULT_OK) 556 return; 557 558 dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing); 559 560 /* setup HDMI engine */ 561 if (!enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) { 562 REG_UPDATE_3(HDMI_CONTROL, 563 HDMI_PACKET_GEN_VERSION, 1, 564 HDMI_KEEPOUT_MODE, 1, 565 HDMI_DEEP_COLOR_ENABLE, 0); 566 } else if (enc110->regs->DIG_FE_CNTL) { 567 REG_UPDATE_5(HDMI_CONTROL, 568 HDMI_PACKET_GEN_VERSION, 1, 569 HDMI_KEEPOUT_MODE, 1, 570 HDMI_DEEP_COLOR_ENABLE, 0, 571 HDMI_DATA_SCRAMBLE_EN, 0, 572 HDMI_CLOCK_CHANNEL_RATE, 0); 573 } 574 575 switch (crtc_timing->display_color_depth) { 576 case COLOR_DEPTH_888: 577 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 578 break; 579 case COLOR_DEPTH_101010: 580 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 581 REG_UPDATE_2(HDMI_CONTROL, 582 HDMI_DEEP_COLOR_DEPTH, 1, 583 HDMI_DEEP_COLOR_ENABLE, 0); 584 } else { 585 REG_UPDATE_2(HDMI_CONTROL, 586 HDMI_DEEP_COLOR_DEPTH, 1, 587 HDMI_DEEP_COLOR_ENABLE, 1); 588 } 589 break; 590 case COLOR_DEPTH_121212: 591 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 592 REG_UPDATE_2(HDMI_CONTROL, 593 HDMI_DEEP_COLOR_DEPTH, 2, 594 HDMI_DEEP_COLOR_ENABLE, 0); 595 } else { 596 REG_UPDATE_2(HDMI_CONTROL, 597 HDMI_DEEP_COLOR_DEPTH, 2, 598 HDMI_DEEP_COLOR_ENABLE, 1); 599 } 600 break; 601 case COLOR_DEPTH_161616: 602 REG_UPDATE_2(HDMI_CONTROL, 603 HDMI_DEEP_COLOR_DEPTH, 3, 604 HDMI_DEEP_COLOR_ENABLE, 1); 605 break; 606 default: 607 break; 608 } 609 610 if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) { 611 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) { 612 /* enable HDMI data scrambler 613 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M 614 * Clock channel frequency is 1/4 of character rate. 615 */ 616 REG_UPDATE_2(HDMI_CONTROL, 617 HDMI_DATA_SCRAMBLE_EN, 1, 618 HDMI_CLOCK_CHANNEL_RATE, 1); 619 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) { 620 621 /* TODO: New feature for DCE11, still need to implement */ 622 623 /* enable HDMI data scrambler 624 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE 625 * Clock channel frequency is the same 626 * as character rate 627 */ 628 REG_UPDATE_2(HDMI_CONTROL, 629 HDMI_DATA_SCRAMBLE_EN, 1, 630 HDMI_CLOCK_CHANNEL_RATE, 0); 631 } 632 } 633 634 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL, 635 HDMI_GC_CONT, 1, 636 HDMI_GC_SEND, 1, 637 HDMI_NULL_SEND, 1); 638 639 /* following belongs to audio */ 640 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 641 642 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 643 644 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 645 VBI_LINE_0 + 2); 646 647 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); 648 649 } 650 651 /* setup stream encoder in dvi mode */ 652 static void dce110_stream_encoder_dvi_set_stream_attribute( 653 struct stream_encoder *enc, 654 struct dc_crtc_timing *crtc_timing, 655 bool is_dual_link) 656 { 657 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 658 struct bp_encoder_control cntl = {0}; 659 660 cntl.action = ENCODER_CONTROL_SETUP; 661 cntl.engine_id = enc110->base.id; 662 cntl.signal = is_dual_link ? 663 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK; 664 cntl.enable_dp_audio = false; 665 cntl.pixel_clock = crtc_timing->pix_clk_khz; 666 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; 667 668 if (enc110->base.bp->funcs->encoder_control( 669 enc110->base.bp, &cntl) != BP_RESULT_OK) 670 return; 671 672 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); 673 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888); 674 dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing); 675 } 676 677 /* setup stream encoder in LVDS mode */ 678 static void dce110_stream_encoder_lvds_set_stream_attribute( 679 struct stream_encoder *enc, 680 struct dc_crtc_timing *crtc_timing) 681 { 682 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 683 struct bp_encoder_control cntl = {0}; 684 685 cntl.action = ENCODER_CONTROL_SETUP; 686 cntl.engine_id = enc110->base.id; 687 cntl.signal = SIGNAL_TYPE_LVDS; 688 cntl.enable_dp_audio = false; 689 cntl.pixel_clock = crtc_timing->pix_clk_khz; 690 cntl.lanes_number = LANE_COUNT_FOUR; 691 692 if (enc110->base.bp->funcs->encoder_control( 693 enc110->base.bp, &cntl) != BP_RESULT_OK) 694 return; 695 696 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); 697 } 698 699 static void dce110_stream_encoder_set_mst_bandwidth( 700 struct stream_encoder *enc, 701 struct fixed31_32 avg_time_slots_per_mtp) 702 { 703 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 704 uint32_t x = dc_fixpt_floor( 705 avg_time_slots_per_mtp); 706 uint32_t y = dc_fixpt_ceil( 707 dc_fixpt_shl( 708 dc_fixpt_sub_int( 709 avg_time_slots_per_mtp, 710 x), 711 26)); 712 713 { 714 REG_SET_2(DP_MSE_RATE_CNTL, 0, 715 DP_MSE_RATE_X, x, 716 DP_MSE_RATE_Y, y); 717 } 718 719 /* wait for update to be completed on the link */ 720 /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */ 721 /* is reset to 0 (not pending) */ 722 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, 723 0, 724 10, DP_MST_UPDATE_MAX_RETRY); 725 } 726 727 static void dce110_stream_encoder_update_hdmi_info_packets( 728 struct stream_encoder *enc, 729 const struct encoder_info_frame *info_frame) 730 { 731 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 732 733 if (enc110->se_mask->HDMI_AVI_INFO_CONT && 734 enc110->se_mask->HDMI_AVI_INFO_SEND) { 735 736 if (info_frame->avi.valid) { 737 const uint32_t *content = 738 (const uint32_t *) &info_frame->avi.sb[0]; 739 /*we need turn on clock before programming AFMT block*/ 740 if (REG(AFMT_CNTL)) 741 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 742 743 REG_WRITE(AFMT_AVI_INFO0, content[0]); 744 745 REG_WRITE(AFMT_AVI_INFO1, content[1]); 746 747 REG_WRITE(AFMT_AVI_INFO2, content[2]); 748 749 REG_WRITE(AFMT_AVI_INFO3, content[3]); 750 751 REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, 752 info_frame->avi.hb1); 753 754 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0, 755 HDMI_AVI_INFO_SEND, 1, 756 HDMI_AVI_INFO_CONT, 1); 757 758 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 759 VBI_LINE_0 + 2); 760 761 } else { 762 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0, 763 HDMI_AVI_INFO_SEND, 0, 764 HDMI_AVI_INFO_CONT, 0); 765 } 766 } 767 768 if (enc110->se_mask->HDMI_AVI_INFO_CONT && 769 enc110->se_mask->HDMI_AVI_INFO_SEND) { 770 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor); 771 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut); 772 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd); 773 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd); 774 } 775 776 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 777 if (enc110->se_mask->HDMI_DB_DISABLE) { 778 /* for bring up, disable dp double TODO */ 779 if (REG(HDMI_DB_CONTROL)) 780 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); 781 782 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->avi); 783 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->vendor); 784 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->gamut); 785 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->spd); 786 dce110_update_hdmi_info_packet(enc110, 4, &info_frame->hdrsmd); 787 } 788 #endif 789 } 790 791 static void dce110_stream_encoder_stop_hdmi_info_packets( 792 struct stream_encoder *enc) 793 { 794 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 795 796 /* stop generic packets 0 & 1 on HDMI */ 797 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0, 798 HDMI_GENERIC1_CONT, 0, 799 HDMI_GENERIC1_LINE, 0, 800 HDMI_GENERIC1_SEND, 0, 801 HDMI_GENERIC0_CONT, 0, 802 HDMI_GENERIC0_LINE, 0, 803 HDMI_GENERIC0_SEND, 0); 804 805 /* stop generic packets 2 & 3 on HDMI */ 806 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0, 807 HDMI_GENERIC0_CONT, 0, 808 HDMI_GENERIC0_LINE, 0, 809 HDMI_GENERIC0_SEND, 0, 810 HDMI_GENERIC1_CONT, 0, 811 HDMI_GENERIC1_LINE, 0, 812 HDMI_GENERIC1_SEND, 0); 813 814 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 815 /* stop generic packets 2 & 3 on HDMI */ 816 if (REG(HDMI_GENERIC_PACKET_CONTROL2)) 817 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0, 818 HDMI_GENERIC0_CONT, 0, 819 HDMI_GENERIC0_LINE, 0, 820 HDMI_GENERIC0_SEND, 0, 821 HDMI_GENERIC1_CONT, 0, 822 HDMI_GENERIC1_LINE, 0, 823 HDMI_GENERIC1_SEND, 0); 824 825 if (REG(HDMI_GENERIC_PACKET_CONTROL3)) 826 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0, 827 HDMI_GENERIC0_CONT, 0, 828 HDMI_GENERIC0_LINE, 0, 829 HDMI_GENERIC0_SEND, 0, 830 HDMI_GENERIC1_CONT, 0, 831 HDMI_GENERIC1_LINE, 0, 832 HDMI_GENERIC1_SEND, 0); 833 #endif 834 } 835 836 static void dce110_stream_encoder_update_dp_info_packets( 837 struct stream_encoder *enc, 838 const struct encoder_info_frame *info_frame) 839 { 840 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 841 uint32_t value = 0; 842 843 if (info_frame->vsc.valid) 844 dce110_update_generic_info_packet( 845 enc110, 846 0, /* packetIndex */ 847 &info_frame->vsc); 848 849 if (info_frame->spd.valid) 850 dce110_update_generic_info_packet( 851 enc110, 852 2, /* packetIndex */ 853 &info_frame->spd); 854 855 if (info_frame->hdrsmd.valid) 856 dce110_update_generic_info_packet( 857 enc110, 858 3, /* packetIndex */ 859 &info_frame->hdrsmd); 860 861 /* enable/disable transmission of packet(s). 862 * If enabled, packet transmission begins on the next frame 863 */ 864 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); 865 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); 866 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); 867 868 /* This bit is the master enable bit. 869 * When enabling secondary stream engine, 870 * this master bit must also be set. 871 * This register shared with audio info frame. 872 * Therefore we need to enable master bit 873 * if at least on of the fields is not 0 874 */ 875 value = REG_READ(DP_SEC_CNTL); 876 if (value) 877 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 878 } 879 880 static void dce110_stream_encoder_stop_dp_info_packets( 881 struct stream_encoder *enc) 882 { 883 /* stop generic packets on DP */ 884 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 885 uint32_t value = 0; 886 887 if (enc110->se_mask->DP_SEC_AVI_ENABLE) { 888 REG_SET_7(DP_SEC_CNTL, 0, 889 DP_SEC_GSP0_ENABLE, 0, 890 DP_SEC_GSP1_ENABLE, 0, 891 DP_SEC_GSP2_ENABLE, 0, 892 DP_SEC_GSP3_ENABLE, 0, 893 DP_SEC_AVI_ENABLE, 0, 894 DP_SEC_MPG_ENABLE, 0, 895 DP_SEC_STREAM_ENABLE, 0); 896 } 897 898 /* this register shared with audio info frame. 899 * therefore we need to keep master enabled 900 * if at least one of the fields is not 0 */ 901 value = REG_READ(DP_SEC_CNTL); 902 if (value) 903 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 904 905 } 906 907 static void dce110_stream_encoder_dp_blank( 908 struct stream_encoder *enc) 909 { 910 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 911 uint32_t reg1 = 0; 912 uint32_t max_retries = DP_BLANK_MAX_RETRY * 10; 913 914 /* Note: For CZ, we are changing driver default to disable 915 * stream deferred to next VBLANK. If results are positive, we 916 * will make the same change to all DCE versions. There are a 917 * handful of panels that cannot handle disable stream at 918 * HBLANK and will result in a white line flash across the 919 * screen on stream disable. */ 920 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1); 921 if ((reg1 & 0x1) == 0) 922 /*stream not enabled*/ 923 return; 924 /* Specify the video stream disable point 925 * (2 = start of the next vertical blank) */ 926 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2); 927 /* Larger delay to wait until VBLANK - use max retry of 928 * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode + 929 * a little more because we may not trust delay accuracy. 930 */ 931 max_retries = DP_BLANK_MAX_RETRY * 150; 932 933 /* disable DP stream */ 934 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); 935 936 /* the encoder stops sending the video stream 937 * at the start of the vertical blanking. 938 * Poll for DP_VID_STREAM_STATUS == 0 939 */ 940 941 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 942 0, 943 10, max_retries); 944 945 /* Tell the DP encoder to ignore timing from CRTC, must be done after 946 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is 947 * complete, stream status will be stuck in video stream enabled state, 948 * i.e. DP_VID_STREAM_STATUS stuck at 1. 949 */ 950 951 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true); 952 } 953 954 /* output video stream to link encoder */ 955 static void dce110_stream_encoder_dp_unblank( 956 struct stream_encoder *enc, 957 const struct encoder_unblank_param *param) 958 { 959 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 960 961 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) { 962 uint32_t n_vid = 0x8000; 963 uint32_t m_vid; 964 965 /* M / N = Fstream / Flink 966 * m_vid / n_vid = pixel rate / link rate 967 */ 968 969 uint64_t m_vid_l = n_vid; 970 971 m_vid_l *= param->pixel_clk_khz; 972 m_vid_l = div_u64(m_vid_l, 973 param->link_settings.link_rate 974 * LINK_RATE_REF_FREQ_IN_KHZ); 975 976 m_vid = (uint32_t) m_vid_l; 977 978 /* enable auto measurement */ 979 980 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0); 981 982 /* auto measurement need 1 full 0x8000 symbol cycle to kick in, 983 * therefore program initial value for Mvid and Nvid 984 */ 985 986 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid); 987 988 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid); 989 990 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1); 991 } 992 993 /* set DIG_START to 0x1 to resync FIFO */ 994 995 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); 996 997 /* switch DP encoder to CRTC data */ 998 999 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); 1000 1001 /* wait 100us for DIG/DP logic to prime 1002 * (i.e. a few video lines) 1003 */ 1004 udelay(100); 1005 1006 /* the hardware would start sending video at the start of the next DP 1007 * frame (i.e. rising edge of the vblank). 1008 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this 1009 * register has no effect on enable transition! HW always guarantees 1010 * VID_STREAM enable at start of next frame, and this is not 1011 * programmable 1012 */ 1013 1014 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); 1015 } 1016 1017 static void dce110_stream_encoder_set_avmute( 1018 struct stream_encoder *enc, 1019 bool enable) 1020 { 1021 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1022 unsigned int value = enable ? 1 : 0; 1023 1024 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value); 1025 } 1026 1027 1028 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000 1029 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1 1030 1031 #include "include/audio_types.h" 1032 1033 /** 1034 * speakersToChannels 1035 * 1036 * @brief 1037 * translate speakers to channels 1038 * 1039 * FL - Front Left 1040 * FR - Front Right 1041 * RL - Rear Left 1042 * RR - Rear Right 1043 * RC - Rear Center 1044 * FC - Front Center 1045 * FLC - Front Left Center 1046 * FRC - Front Right Center 1047 * RLC - Rear Left Center 1048 * RRC - Rear Right Center 1049 * LFE - Low Freq Effect 1050 * 1051 * FC 1052 * FLC FRC 1053 * FL FR 1054 * 1055 * LFE 1056 * () 1057 * 1058 * 1059 * RL RR 1060 * RLC RRC 1061 * RC 1062 * 1063 * ch 8 7 6 5 4 3 2 1 1064 * 0b00000011 - - - - - - FR FL 1065 * 0b00000111 - - - - - LFE FR FL 1066 * 0b00001011 - - - - FC - FR FL 1067 * 0b00001111 - - - - FC LFE FR FL 1068 * 0b00010011 - - - RC - - FR FL 1069 * 0b00010111 - - - RC - LFE FR FL 1070 * 0b00011011 - - - RC FC - FR FL 1071 * 0b00011111 - - - RC FC LFE FR FL 1072 * 0b00110011 - - RR RL - - FR FL 1073 * 0b00110111 - - RR RL - LFE FR FL 1074 * 0b00111011 - - RR RL FC - FR FL 1075 * 0b00111111 - - RR RL FC LFE FR FL 1076 * 0b01110011 - RC RR RL - - FR FL 1077 * 0b01110111 - RC RR RL - LFE FR FL 1078 * 0b01111011 - RC RR RL FC - FR FL 1079 * 0b01111111 - RC RR RL FC LFE FR FL 1080 * 0b11110011 RRC RLC RR RL - - FR FL 1081 * 0b11110111 RRC RLC RR RL - LFE FR FL 1082 * 0b11111011 RRC RLC RR RL FC - FR FL 1083 * 0b11111111 RRC RLC RR RL FC LFE FR FL 1084 * 0b11000011 FRC FLC - - - - FR FL 1085 * 0b11000111 FRC FLC - - - LFE FR FL 1086 * 0b11001011 FRC FLC - - FC - FR FL 1087 * 0b11001111 FRC FLC - - FC LFE FR FL 1088 * 0b11010011 FRC FLC - RC - - FR FL 1089 * 0b11010111 FRC FLC - RC - LFE FR FL 1090 * 0b11011011 FRC FLC - RC FC - FR FL 1091 * 0b11011111 FRC FLC - RC FC LFE FR FL 1092 * 0b11110011 FRC FLC RR RL - - FR FL 1093 * 0b11110111 FRC FLC RR RL - LFE FR FL 1094 * 0b11111011 FRC FLC RR RL FC - FR FL 1095 * 0b11111111 FRC FLC RR RL FC LFE FR FL 1096 * 1097 * @param 1098 * speakers - speaker information as it comes from CEA audio block 1099 */ 1100 /* translate speakers to channels */ 1101 1102 union audio_cea_channels { 1103 uint8_t all; 1104 struct audio_cea_channels_bits { 1105 uint32_t FL:1; 1106 uint32_t FR:1; 1107 uint32_t LFE:1; 1108 uint32_t FC:1; 1109 uint32_t RL_RC:1; 1110 uint32_t RR:1; 1111 uint32_t RC_RLC_FLC:1; 1112 uint32_t RRC_FRC:1; 1113 } channels; 1114 }; 1115 1116 struct audio_clock_info { 1117 /* pixel clock frequency*/ 1118 uint32_t pixel_clock_in_10khz; 1119 /* N - 32KHz audio */ 1120 uint32_t n_32khz; 1121 /* CTS - 32KHz audio*/ 1122 uint32_t cts_32khz; 1123 uint32_t n_44khz; 1124 uint32_t cts_44khz; 1125 uint32_t n_48khz; 1126 uint32_t cts_48khz; 1127 }; 1128 1129 /* 25.2MHz/1.001*/ 1130 /* 25.2MHz/1.001*/ 1131 /* 25.2MHz*/ 1132 /* 27MHz */ 1133 /* 27MHz*1.001*/ 1134 /* 27MHz*1.001*/ 1135 /* 54MHz*/ 1136 /* 54MHz*1.001*/ 1137 /* 74.25MHz/1.001*/ 1138 /* 74.25MHz*/ 1139 /* 148.5MHz/1.001*/ 1140 /* 148.5MHz*/ 1141 1142 static const struct audio_clock_info audio_clock_info_table[16] = { 1143 {2517, 4576, 28125, 7007, 31250, 6864, 28125}, 1144 {2518, 4576, 28125, 7007, 31250, 6864, 28125}, 1145 {2520, 4096, 25200, 6272, 28000, 6144, 25200}, 1146 {2700, 4096, 27000, 6272, 30000, 6144, 27000}, 1147 {2702, 4096, 27027, 6272, 30030, 6144, 27027}, 1148 {2703, 4096, 27027, 6272, 30030, 6144, 27027}, 1149 {5400, 4096, 54000, 6272, 60000, 6144, 54000}, 1150 {5405, 4096, 54054, 6272, 60060, 6144, 54054}, 1151 {7417, 11648, 210937, 17836, 234375, 11648, 140625}, 1152 {7425, 4096, 74250, 6272, 82500, 6144, 74250}, 1153 {14835, 11648, 421875, 8918, 234375, 5824, 140625}, 1154 {14850, 4096, 148500, 6272, 165000, 6144, 148500}, 1155 {29670, 5824, 421875, 4459, 234375, 5824, 281250}, 1156 {29700, 3072, 222750, 4704, 247500, 5120, 247500}, 1157 {59340, 5824, 843750, 8918, 937500, 5824, 562500}, 1158 {59400, 3072, 445500, 9408, 990000, 6144, 594000} 1159 }; 1160 1161 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = { 1162 {2517, 9152, 84375, 7007, 48875, 9152, 56250}, 1163 {2518, 9152, 84375, 7007, 48875, 9152, 56250}, 1164 {2520, 4096, 37800, 6272, 42000, 6144, 37800}, 1165 {2700, 4096, 40500, 6272, 45000, 6144, 40500}, 1166 {2702, 8192, 81081, 6272, 45045, 8192, 54054}, 1167 {2703, 8192, 81081, 6272, 45045, 8192, 54054}, 1168 {5400, 4096, 81000, 6272, 90000, 6144, 81000}, 1169 {5405, 4096, 81081, 6272, 90090, 6144, 81081}, 1170 {7417, 11648, 316406, 17836, 351562, 11648, 210937}, 1171 {7425, 4096, 111375, 6272, 123750, 6144, 111375}, 1172 {14835, 11648, 632812, 17836, 703125, 11648, 421875}, 1173 {14850, 4096, 222750, 6272, 247500, 6144, 222750}, 1174 {29670, 5824, 632812, 8918, 703125, 5824, 421875}, 1175 {29700, 4096, 445500, 4704, 371250, 5120, 371250} 1176 }; 1177 1178 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = { 1179 {2517, 4576, 56250, 7007, 62500, 6864, 56250}, 1180 {2518, 4576, 56250, 7007, 62500, 6864, 56250}, 1181 {2520, 4096, 50400, 6272, 56000, 6144, 50400}, 1182 {2700, 4096, 54000, 6272, 60000, 6144, 54000}, 1183 {2702, 4096, 54054, 6267, 60060, 8192, 54054}, 1184 {2703, 4096, 54054, 6272, 60060, 8192, 54054}, 1185 {5400, 4096, 108000, 6272, 120000, 6144, 108000}, 1186 {5405, 4096, 108108, 6272, 120120, 6144, 108108}, 1187 {7417, 11648, 421875, 17836, 468750, 11648, 281250}, 1188 {7425, 4096, 148500, 6272, 165000, 6144, 148500}, 1189 {14835, 11648, 843750, 8918, 468750, 11648, 281250}, 1190 {14850, 4096, 297000, 6272, 330000, 6144, 297000}, 1191 {29670, 5824, 843750, 4459, 468750, 5824, 562500}, 1192 {29700, 3072, 445500, 4704, 495000, 5120, 495000} 1193 1194 1195 }; 1196 1197 static union audio_cea_channels speakers_to_channels( 1198 struct audio_speaker_flags speaker_flags) 1199 { 1200 union audio_cea_channels cea_channels = {0}; 1201 1202 /* these are one to one */ 1203 cea_channels.channels.FL = speaker_flags.FL_FR; 1204 cea_channels.channels.FR = speaker_flags.FL_FR; 1205 cea_channels.channels.LFE = speaker_flags.LFE; 1206 cea_channels.channels.FC = speaker_flags.FC; 1207 1208 /* if Rear Left and Right exist move RC speaker to channel 7 1209 * otherwise to channel 5 1210 */ 1211 if (speaker_flags.RL_RR) { 1212 cea_channels.channels.RL_RC = speaker_flags.RL_RR; 1213 cea_channels.channels.RR = speaker_flags.RL_RR; 1214 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC; 1215 } else { 1216 cea_channels.channels.RL_RC = speaker_flags.RC; 1217 } 1218 1219 /* FRONT Left Right Center and REAR Left Right Center are exclusive */ 1220 if (speaker_flags.FLC_FRC) { 1221 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC; 1222 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC; 1223 } else { 1224 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC; 1225 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC; 1226 } 1227 1228 return cea_channels; 1229 } 1230 1231 static uint32_t calc_max_audio_packets_per_line( 1232 const struct audio_crtc_info *crtc_info) 1233 { 1234 uint32_t max_packets_per_line; 1235 1236 max_packets_per_line = 1237 crtc_info->h_total - crtc_info->h_active; 1238 1239 if (crtc_info->pixel_repetition) 1240 max_packets_per_line *= crtc_info->pixel_repetition; 1241 1242 /* for other hdmi features */ 1243 max_packets_per_line -= 58; 1244 /* for Control Period */ 1245 max_packets_per_line -= 16; 1246 /* Number of Audio Packets per Line */ 1247 max_packets_per_line /= 32; 1248 1249 return max_packets_per_line; 1250 } 1251 1252 static void get_audio_clock_info( 1253 enum dc_color_depth color_depth, 1254 uint32_t crtc_pixel_clock_in_khz, 1255 uint32_t actual_pixel_clock_in_khz, 1256 struct audio_clock_info *audio_clock_info) 1257 { 1258 const struct audio_clock_info *clock_info; 1259 uint32_t index; 1260 uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10; 1261 uint32_t audio_array_size; 1262 1263 switch (color_depth) { 1264 case COLOR_DEPTH_161616: 1265 clock_info = audio_clock_info_table_48bpc; 1266 audio_array_size = ARRAY_SIZE( 1267 audio_clock_info_table_48bpc); 1268 break; 1269 case COLOR_DEPTH_121212: 1270 clock_info = audio_clock_info_table_36bpc; 1271 audio_array_size = ARRAY_SIZE( 1272 audio_clock_info_table_36bpc); 1273 break; 1274 default: 1275 clock_info = audio_clock_info_table; 1276 audio_array_size = ARRAY_SIZE( 1277 audio_clock_info_table); 1278 break; 1279 } 1280 1281 if (clock_info != NULL) { 1282 /* search for exact pixel clock in table */ 1283 for (index = 0; index < audio_array_size; index++) { 1284 if (clock_info[index].pixel_clock_in_10khz > 1285 crtc_pixel_clock_in_10khz) 1286 break; /* not match */ 1287 else if (clock_info[index].pixel_clock_in_10khz == 1288 crtc_pixel_clock_in_10khz) { 1289 /* match found */ 1290 *audio_clock_info = clock_info[index]; 1291 return; 1292 } 1293 } 1294 } 1295 1296 /* not found */ 1297 if (actual_pixel_clock_in_khz == 0) 1298 actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz; 1299 1300 /* See HDMI spec the table entry under 1301 * pixel clock of "Other". */ 1302 audio_clock_info->pixel_clock_in_10khz = 1303 actual_pixel_clock_in_khz / 10; 1304 audio_clock_info->cts_32khz = actual_pixel_clock_in_khz; 1305 audio_clock_info->cts_44khz = actual_pixel_clock_in_khz; 1306 audio_clock_info->cts_48khz = actual_pixel_clock_in_khz; 1307 1308 audio_clock_info->n_32khz = 4096; 1309 audio_clock_info->n_44khz = 6272; 1310 audio_clock_info->n_48khz = 6144; 1311 } 1312 1313 static void dce110_se_audio_setup( 1314 struct stream_encoder *enc, 1315 unsigned int az_inst, 1316 struct audio_info *audio_info) 1317 { 1318 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1319 1320 uint32_t speakers = 0; 1321 uint32_t channels = 0; 1322 1323 ASSERT(audio_info); 1324 if (audio_info == NULL) 1325 /* This should not happen.it does so we don't get BSOD*/ 1326 return; 1327 1328 speakers = audio_info->flags.info.ALLSPEAKERS; 1329 channels = speakers_to_channels(audio_info->flags.speaker_flags).all; 1330 1331 /* setup the audio stream source select (audio -> dig mapping) */ 1332 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst); 1333 1334 /* Channel allocation */ 1335 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels); 1336 } 1337 1338 static void dce110_se_setup_hdmi_audio( 1339 struct stream_encoder *enc, 1340 const struct audio_crtc_info *crtc_info) 1341 { 1342 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1343 1344 struct audio_clock_info audio_clock_info = {0}; 1345 uint32_t max_packets_per_line; 1346 1347 /* For now still do calculation, although this field is ignored when 1348 above HDMI_PACKET_GEN_VERSION set to 1 */ 1349 max_packets_per_line = calc_max_audio_packets_per_line(crtc_info); 1350 1351 /* HDMI_AUDIO_PACKET_CONTROL */ 1352 REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL, 1353 HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line, 1354 HDMI_AUDIO_DELAY_EN, 1); 1355 1356 /* AFMT_AUDIO_PACKET_CONTROL */ 1357 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1358 1359 /* AFMT_AUDIO_PACKET_CONTROL2 */ 1360 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 1361 AFMT_AUDIO_LAYOUT_OVRD, 0, 1362 AFMT_60958_OSF_OVRD, 0); 1363 1364 /* HDMI_ACR_PACKET_CONTROL */ 1365 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, 1366 HDMI_ACR_AUTO_SEND, 1, 1367 HDMI_ACR_SOURCE, 0, 1368 HDMI_ACR_AUDIO_PRIORITY, 0); 1369 1370 /* Program audio clock sample/regeneration parameters */ 1371 get_audio_clock_info(crtc_info->color_depth, 1372 crtc_info->requested_pixel_clock, 1373 crtc_info->calculated_pixel_clock, 1374 &audio_clock_info); 1375 DC_LOG_HW_AUDIO( 1376 "\n%s:Input::requested_pixel_clock = %d" \ 1377 "calculated_pixel_clock = %d \n", __func__, \ 1378 crtc_info->requested_pixel_clock, \ 1379 crtc_info->calculated_pixel_clock); 1380 1381 /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */ 1382 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); 1383 1384 /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */ 1385 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); 1386 1387 /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */ 1388 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz); 1389 1390 /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */ 1391 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); 1392 1393 /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */ 1394 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); 1395 1396 /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */ 1397 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz); 1398 1399 /* Video driver cannot know in advance which sample rate will 1400 be used by HD Audio driver 1401 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is 1402 programmed below in interruppt callback */ 1403 1404 /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK & 1405 AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */ 1406 REG_UPDATE_2(AFMT_60958_0, 1407 AFMT_60958_CS_CHANNEL_NUMBER_L, 1, 1408 AFMT_60958_CS_CLOCK_ACCURACY, 0); 1409 1410 /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */ 1411 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1412 1413 /*AFMT_60958_2 now keep this settings until 1414 * Programming guide comes out*/ 1415 REG_UPDATE_6(AFMT_60958_2, 1416 AFMT_60958_CS_CHANNEL_NUMBER_2, 3, 1417 AFMT_60958_CS_CHANNEL_NUMBER_3, 4, 1418 AFMT_60958_CS_CHANNEL_NUMBER_4, 5, 1419 AFMT_60958_CS_CHANNEL_NUMBER_5, 6, 1420 AFMT_60958_CS_CHANNEL_NUMBER_6, 7, 1421 AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1422 } 1423 1424 static void dce110_se_setup_dp_audio( 1425 struct stream_encoder *enc) 1426 { 1427 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1428 1429 /* --- DP Audio packet configurations --- */ 1430 1431 /* ATP Configuration */ 1432 REG_SET(DP_SEC_AUD_N, 0, 1433 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT); 1434 1435 /* Async/auto-calc timestamp mode */ 1436 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE, 1437 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC); 1438 1439 /* --- The following are the registers 1440 * copied from the SetupHDMI --- */ 1441 1442 /* AFMT_AUDIO_PACKET_CONTROL */ 1443 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1444 1445 /* AFMT_AUDIO_PACKET_CONTROL2 */ 1446 /* Program the ATP and AIP next */ 1447 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 1448 AFMT_AUDIO_LAYOUT_OVRD, 0, 1449 AFMT_60958_OSF_OVRD, 0); 1450 1451 /* AFMT_INFOFRAME_CONTROL0 */ 1452 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1453 1454 /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */ 1455 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0); 1456 } 1457 1458 static void dce110_se_enable_audio_clock( 1459 struct stream_encoder *enc, 1460 bool enable) 1461 { 1462 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1463 1464 if (REG(AFMT_CNTL) == 0) 1465 return; /* DCE8/10 does not have this register */ 1466 1467 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable); 1468 1469 /* wait for AFMT clock to turn on, 1470 * expectation: this should complete in 1-2 reads 1471 * 1472 * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10); 1473 * 1474 * TODO: wait for clock_on does not work well. May need HW 1475 * program sequence. But audio seems work normally even without wait 1476 * for clock_on status change 1477 */ 1478 } 1479 1480 static void dce110_se_enable_dp_audio( 1481 struct stream_encoder *enc) 1482 { 1483 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1484 1485 /* Enable Audio packets */ 1486 REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); 1487 1488 /* Program the ATP and AIP next */ 1489 REG_UPDATE_2(DP_SEC_CNTL, 1490 DP_SEC_ATP_ENABLE, 1, 1491 DP_SEC_AIP_ENABLE, 1); 1492 1493 /* Program STREAM_ENABLE after all the other enables. */ 1494 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1495 } 1496 1497 static void dce110_se_disable_dp_audio( 1498 struct stream_encoder *enc) 1499 { 1500 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1501 uint32_t value = 0; 1502 1503 /* Disable Audio packets */ 1504 REG_UPDATE_5(DP_SEC_CNTL, 1505 DP_SEC_ASP_ENABLE, 0, 1506 DP_SEC_ATP_ENABLE, 0, 1507 DP_SEC_AIP_ENABLE, 0, 1508 DP_SEC_ACM_ENABLE, 0, 1509 DP_SEC_STREAM_ENABLE, 0); 1510 1511 /* This register shared with encoder info frame. Therefore we need to 1512 keep master enabled if at least on of the fields is not 0 */ 1513 value = REG_READ(DP_SEC_CNTL); 1514 if (value != 0) 1515 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1516 1517 } 1518 1519 void dce110_se_audio_mute_control( 1520 struct stream_encoder *enc, 1521 bool mute) 1522 { 1523 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1524 1525 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute); 1526 } 1527 1528 void dce110_se_dp_audio_setup( 1529 struct stream_encoder *enc, 1530 unsigned int az_inst, 1531 struct audio_info *info) 1532 { 1533 dce110_se_audio_setup(enc, az_inst, info); 1534 } 1535 1536 void dce110_se_dp_audio_enable( 1537 struct stream_encoder *enc) 1538 { 1539 dce110_se_enable_audio_clock(enc, true); 1540 dce110_se_setup_dp_audio(enc); 1541 dce110_se_enable_dp_audio(enc); 1542 } 1543 1544 void dce110_se_dp_audio_disable( 1545 struct stream_encoder *enc) 1546 { 1547 dce110_se_disable_dp_audio(enc); 1548 dce110_se_enable_audio_clock(enc, false); 1549 } 1550 1551 void dce110_se_hdmi_audio_setup( 1552 struct stream_encoder *enc, 1553 unsigned int az_inst, 1554 struct audio_info *info, 1555 struct audio_crtc_info *audio_crtc_info) 1556 { 1557 dce110_se_enable_audio_clock(enc, true); 1558 dce110_se_setup_hdmi_audio(enc, audio_crtc_info); 1559 dce110_se_audio_setup(enc, az_inst, info); 1560 } 1561 1562 void dce110_se_hdmi_audio_disable( 1563 struct stream_encoder *enc) 1564 { 1565 dce110_se_enable_audio_clock(enc, false); 1566 } 1567 1568 1569 static void setup_stereo_sync( 1570 struct stream_encoder *enc, 1571 int tg_inst, bool enable) 1572 { 1573 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1574 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); 1575 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable); 1576 } 1577 1578 1579 static const struct stream_encoder_funcs dce110_str_enc_funcs = { 1580 .dp_set_stream_attribute = 1581 dce110_stream_encoder_dp_set_stream_attribute, 1582 .hdmi_set_stream_attribute = 1583 dce110_stream_encoder_hdmi_set_stream_attribute, 1584 .dvi_set_stream_attribute = 1585 dce110_stream_encoder_dvi_set_stream_attribute, 1586 .lvds_set_stream_attribute = 1587 dce110_stream_encoder_lvds_set_stream_attribute, 1588 .set_mst_bandwidth = 1589 dce110_stream_encoder_set_mst_bandwidth, 1590 .update_hdmi_info_packets = 1591 dce110_stream_encoder_update_hdmi_info_packets, 1592 .stop_hdmi_info_packets = 1593 dce110_stream_encoder_stop_hdmi_info_packets, 1594 .update_dp_info_packets = 1595 dce110_stream_encoder_update_dp_info_packets, 1596 .stop_dp_info_packets = 1597 dce110_stream_encoder_stop_dp_info_packets, 1598 .dp_blank = 1599 dce110_stream_encoder_dp_blank, 1600 .dp_unblank = 1601 dce110_stream_encoder_dp_unblank, 1602 .audio_mute_control = dce110_se_audio_mute_control, 1603 1604 .dp_audio_setup = dce110_se_dp_audio_setup, 1605 .dp_audio_enable = dce110_se_dp_audio_enable, 1606 .dp_audio_disable = dce110_se_dp_audio_disable, 1607 1608 .hdmi_audio_setup = dce110_se_hdmi_audio_setup, 1609 .hdmi_audio_disable = dce110_se_hdmi_audio_disable, 1610 .setup_stereo_sync = setup_stereo_sync, 1611 .set_avmute = dce110_stream_encoder_set_avmute, 1612 1613 }; 1614 1615 void dce110_stream_encoder_construct( 1616 struct dce110_stream_encoder *enc110, 1617 struct dc_context *ctx, 1618 struct dc_bios *bp, 1619 enum engine_id eng_id, 1620 const struct dce110_stream_enc_registers *regs, 1621 const struct dce_stream_encoder_shift *se_shift, 1622 const struct dce_stream_encoder_mask *se_mask) 1623 { 1624 enc110->base.funcs = &dce110_str_enc_funcs; 1625 enc110->base.ctx = ctx; 1626 enc110->base.id = eng_id; 1627 enc110->base.bp = bp; 1628 enc110->regs = regs; 1629 enc110->se_shift = se_shift; 1630 enc110->se_mask = se_mask; 1631 } 1632