1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string.h> 27 #include <linux/acpi.h> 28 #include <linux/i2c.h> 29 30 #include <drm/drm_atomic.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/amdgpu_drm.h> 33 #include <drm/drm_edid.h> 34 #include <drm/drm_fixed.h> 35 36 #include "dm_services.h" 37 #include "amdgpu.h" 38 #include "dc.h" 39 #include "amdgpu_dm.h" 40 #include "amdgpu_dm_irq.h" 41 #include "amdgpu_dm_mst_types.h" 42 #include "dpcd_defs.h" 43 #include "dc/inc/core_types.h" 44 45 #include "dm_helpers.h" 46 #include "ddc_service_types.h" 47 48 static u32 edid_extract_panel_id(struct edid *edid) 49 { 50 return (u32)edid->mfg_id[0] << 24 | 51 (u32)edid->mfg_id[1] << 16 | 52 (u32)EDID_PRODUCT_ID(edid); 53 } 54 55 static void apply_edid_quirks(struct edid *edid, struct dc_edid_caps *edid_caps) 56 { 57 uint32_t panel_id = edid_extract_panel_id(edid); 58 59 switch (panel_id) { 60 /* Workaround for some monitors which does not work well with FAMS */ 61 case drm_edid_encode_panel_id('S', 'A', 'M', 0x0E5E): 62 case drm_edid_encode_panel_id('S', 'A', 'M', 0x7053): 63 case drm_edid_encode_panel_id('S', 'A', 'M', 0x71AC): 64 DRM_DEBUG_DRIVER("Disabling FAMS on monitor with panel id %X\n", panel_id); 65 edid_caps->panel_patch.disable_fams = true; 66 break; 67 default: 68 return; 69 } 70 } 71 72 /** 73 * dm_helpers_parse_edid_caps() - Parse edid caps 74 * 75 * @link: current detected link 76 * @edid: [in] pointer to edid 77 * @edid_caps: [in] pointer to edid caps 78 * 79 * Return: void 80 */ 81 enum dc_edid_status dm_helpers_parse_edid_caps( 82 struct dc_link *link, 83 const struct dc_edid *edid, 84 struct dc_edid_caps *edid_caps) 85 { 86 struct amdgpu_dm_connector *aconnector = link->priv; 87 struct drm_connector *connector = &aconnector->base; 88 struct edid *edid_buf = edid ? (struct edid *) edid->raw_edid : NULL; 89 struct cea_sad *sads; 90 int sad_count = -1; 91 int sadb_count = -1; 92 int i = 0; 93 uint8_t *sadb = NULL; 94 95 enum dc_edid_status result = EDID_OK; 96 97 if (!edid_caps || !edid) 98 return EDID_BAD_INPUT; 99 100 if (!drm_edid_is_valid(edid_buf)) 101 result = EDID_BAD_CHECKSUM; 102 103 edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] | 104 ((uint16_t) edid_buf->mfg_id[1])<<8; 105 edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] | 106 ((uint16_t) edid_buf->prod_code[1])<<8; 107 edid_caps->serial_number = edid_buf->serial; 108 edid_caps->manufacture_week = edid_buf->mfg_week; 109 edid_caps->manufacture_year = edid_buf->mfg_year; 110 111 drm_edid_get_monitor_name(edid_buf, 112 edid_caps->display_name, 113 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 114 115 edid_caps->edid_hdmi = connector->display_info.is_hdmi; 116 117 sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads); 118 if (sad_count <= 0) 119 return result; 120 121 edid_caps->audio_mode_count = min(sad_count, DC_MAX_AUDIO_DESC_COUNT); 122 for (i = 0; i < edid_caps->audio_mode_count; ++i) { 123 struct cea_sad *sad = &sads[i]; 124 125 edid_caps->audio_modes[i].format_code = sad->format; 126 edid_caps->audio_modes[i].channel_count = sad->channels + 1; 127 edid_caps->audio_modes[i].sample_rate = sad->freq; 128 edid_caps->audio_modes[i].sample_size = sad->byte2; 129 } 130 131 sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb); 132 133 if (sadb_count < 0) { 134 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count); 135 sadb_count = 0; 136 } 137 138 if (sadb_count) 139 edid_caps->speaker_flags = sadb[0]; 140 else 141 edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION; 142 143 apply_edid_quirks(edid_buf, edid_caps); 144 145 kfree(sads); 146 kfree(sadb); 147 148 return result; 149 } 150 151 static void 152 fill_dc_mst_payload_table_from_drm(struct dc_link *link, 153 bool enable, 154 struct drm_dp_mst_atomic_payload *target_payload, 155 struct dc_dp_mst_stream_allocation_table *table) 156 { 157 struct dc_dp_mst_stream_allocation_table new_table = { 0 }; 158 struct dc_dp_mst_stream_allocation *sa; 159 struct link_mst_stream_allocation_table copy_of_link_table = 160 link->mst_stream_alloc_table; 161 162 int i; 163 int current_hw_table_stream_cnt = copy_of_link_table.stream_count; 164 struct link_mst_stream_allocation *dc_alloc; 165 166 /* TODO: refactor to set link->mst_stream_alloc_table directly if possible.*/ 167 if (enable) { 168 dc_alloc = 169 ©_of_link_table.stream_allocations[current_hw_table_stream_cnt]; 170 dc_alloc->vcp_id = target_payload->vcpi; 171 dc_alloc->slot_count = target_payload->time_slots; 172 } else { 173 for (i = 0; i < copy_of_link_table.stream_count; i++) { 174 dc_alloc = 175 ©_of_link_table.stream_allocations[i]; 176 177 if (dc_alloc->vcp_id == target_payload->vcpi) { 178 dc_alloc->vcp_id = 0; 179 dc_alloc->slot_count = 0; 180 break; 181 } 182 } 183 ASSERT(i != copy_of_link_table.stream_count); 184 } 185 186 /* Fill payload info*/ 187 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 188 dc_alloc = 189 ©_of_link_table.stream_allocations[i]; 190 if (dc_alloc->vcp_id > 0 && dc_alloc->slot_count > 0) { 191 sa = &new_table.stream_allocations[new_table.stream_count]; 192 sa->slot_count = dc_alloc->slot_count; 193 sa->vcp_id = dc_alloc->vcp_id; 194 new_table.stream_count++; 195 } 196 } 197 198 /* Overwrite the old table */ 199 *table = new_table; 200 } 201 202 void dm_helpers_dp_update_branch_info( 203 struct dc_context *ctx, 204 const struct dc_link *link) 205 {} 206 207 static void dm_helpers_construct_old_payload( 208 struct drm_dp_mst_topology_mgr *mgr, 209 struct drm_dp_mst_topology_state *mst_state, 210 struct drm_dp_mst_atomic_payload *new_payload, 211 struct drm_dp_mst_atomic_payload *old_payload) 212 { 213 struct drm_dp_mst_atomic_payload *pos; 214 int pbn_per_slot = dfixed_trunc(mst_state->pbn_div); 215 u8 next_payload_vc_start = mgr->next_start_slot; 216 u8 payload_vc_start = new_payload->vc_start_slot; 217 u8 allocated_time_slots; 218 219 *old_payload = *new_payload; 220 221 /* Set correct time_slots/PBN of old payload. 222 * other fields (delete & dsc_enabled) in 223 * struct drm_dp_mst_atomic_payload are don't care fields 224 * while calling drm_dp_remove_payload_part2() 225 */ 226 list_for_each_entry(pos, &mst_state->payloads, next) { 227 if (pos != new_payload && 228 pos->vc_start_slot > payload_vc_start && 229 pos->vc_start_slot < next_payload_vc_start) 230 next_payload_vc_start = pos->vc_start_slot; 231 } 232 233 allocated_time_slots = next_payload_vc_start - payload_vc_start; 234 235 old_payload->time_slots = allocated_time_slots; 236 old_payload->pbn = allocated_time_slots * pbn_per_slot; 237 } 238 239 /* 240 * Writes payload allocation table in immediate downstream device. 241 */ 242 bool dm_helpers_dp_mst_write_payload_allocation_table( 243 struct dc_context *ctx, 244 const struct dc_stream_state *stream, 245 struct dc_dp_mst_stream_allocation_table *proposed_table, 246 bool enable) 247 { 248 struct amdgpu_dm_connector *aconnector; 249 struct drm_dp_mst_topology_state *mst_state; 250 struct drm_dp_mst_atomic_payload *target_payload, *new_payload, old_payload; 251 struct drm_dp_mst_topology_mgr *mst_mgr; 252 253 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 254 /* Accessing the connector state is required for vcpi_slots allocation 255 * and directly relies on behaviour in commit check 256 * that blocks before commit guaranteeing that the state 257 * is not gonna be swapped while still in use in commit tail 258 */ 259 260 if (!aconnector || !aconnector->mst_root) 261 return false; 262 263 mst_mgr = &aconnector->mst_root->mst_mgr; 264 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); 265 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); 266 267 if (enable) { 268 target_payload = new_payload; 269 270 /* It's OK for this to fail */ 271 drm_dp_add_payload_part1(mst_mgr, mst_state, new_payload); 272 } else { 273 /* construct old payload by VCPI*/ 274 dm_helpers_construct_old_payload(mst_mgr, mst_state, 275 new_payload, &old_payload); 276 target_payload = &old_payload; 277 278 drm_dp_remove_payload_part1(mst_mgr, mst_state, new_payload); 279 } 280 281 /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or 282 * AUX message. The sequence is slot 1-63 allocated sequence for each 283 * stream. AMD ASIC stream slot allocation should follow the same 284 * sequence. copy DRM MST allocation to dc 285 */ 286 fill_dc_mst_payload_table_from_drm(stream->link, enable, target_payload, proposed_table); 287 288 return true; 289 } 290 291 /* 292 * poll pending down reply 293 */ 294 void dm_helpers_dp_mst_poll_pending_down_reply( 295 struct dc_context *ctx, 296 const struct dc_link *link) 297 {} 298 299 /* 300 * Clear payload allocation table before enable MST DP link. 301 */ 302 void dm_helpers_dp_mst_clear_payload_allocation_table( 303 struct dc_context *ctx, 304 const struct dc_link *link) 305 {} 306 307 /* 308 * Polls for ACT (allocation change trigger) handled and sends 309 * ALLOCATE_PAYLOAD message. 310 */ 311 enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger( 312 struct dc_context *ctx, 313 const struct dc_stream_state *stream) 314 { 315 struct amdgpu_dm_connector *aconnector; 316 struct drm_dp_mst_topology_mgr *mst_mgr; 317 int ret; 318 319 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 320 321 if (!aconnector || !aconnector->mst_root) 322 return ACT_FAILED; 323 324 mst_mgr = &aconnector->mst_root->mst_mgr; 325 326 if (!mst_mgr->mst_state) 327 return ACT_FAILED; 328 329 ret = drm_dp_check_act_status(mst_mgr); 330 331 if (ret) 332 return ACT_FAILED; 333 334 return ACT_SUCCESS; 335 } 336 337 void dm_helpers_dp_mst_send_payload_allocation( 338 struct dc_context *ctx, 339 const struct dc_stream_state *stream) 340 { 341 struct amdgpu_dm_connector *aconnector; 342 struct drm_dp_mst_topology_state *mst_state; 343 struct drm_dp_mst_topology_mgr *mst_mgr; 344 struct drm_dp_mst_atomic_payload *new_payload; 345 enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD; 346 enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD; 347 int ret = 0; 348 349 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 350 351 if (!aconnector || !aconnector->mst_root) 352 return; 353 354 mst_mgr = &aconnector->mst_root->mst_mgr; 355 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); 356 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); 357 358 ret = drm_dp_add_payload_part2(mst_mgr, mst_state->base.state, new_payload); 359 360 if (ret) { 361 amdgpu_dm_set_mst_status(&aconnector->mst_status, 362 set_flag, false); 363 } else { 364 amdgpu_dm_set_mst_status(&aconnector->mst_status, 365 set_flag, true); 366 amdgpu_dm_set_mst_status(&aconnector->mst_status, 367 clr_flag, false); 368 } 369 } 370 371 void dm_helpers_dp_mst_update_mst_mgr_for_deallocation( 372 struct dc_context *ctx, 373 const struct dc_stream_state *stream) 374 { 375 struct amdgpu_dm_connector *aconnector; 376 struct drm_dp_mst_topology_state *mst_state; 377 struct drm_dp_mst_topology_mgr *mst_mgr; 378 struct drm_dp_mst_atomic_payload *new_payload, old_payload; 379 enum mst_progress_status set_flag = MST_CLEAR_ALLOCATED_PAYLOAD; 380 enum mst_progress_status clr_flag = MST_ALLOCATE_NEW_PAYLOAD; 381 382 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 383 384 if (!aconnector || !aconnector->mst_root) 385 return; 386 387 mst_mgr = &aconnector->mst_root->mst_mgr; 388 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); 389 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); 390 dm_helpers_construct_old_payload(mst_mgr, mst_state, 391 new_payload, &old_payload); 392 393 drm_dp_remove_payload_part2(mst_mgr, mst_state, &old_payload, new_payload); 394 395 amdgpu_dm_set_mst_status(&aconnector->mst_status, set_flag, true); 396 amdgpu_dm_set_mst_status(&aconnector->mst_status, clr_flag, false); 397 } 398 399 void dm_dtn_log_begin(struct dc_context *ctx, 400 struct dc_log_buffer_ctx *log_ctx) 401 { 402 static const char msg[] = "[dtn begin]\n"; 403 404 if (!log_ctx) { 405 pr_info("%s", msg); 406 return; 407 } 408 409 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); 410 } 411 412 __printf(3, 4) 413 void dm_dtn_log_append_v(struct dc_context *ctx, 414 struct dc_log_buffer_ctx *log_ctx, 415 const char *msg, ...) 416 { 417 va_list args; 418 size_t total; 419 int n; 420 421 if (!log_ctx) { 422 /* No context, redirect to dmesg. */ 423 struct va_format vaf; 424 425 vaf.fmt = msg; 426 vaf.va = &args; 427 428 va_start(args, msg); 429 pr_info("%pV", &vaf); 430 va_end(args); 431 432 return; 433 } 434 435 /* Measure the output. */ 436 va_start(args, msg); 437 n = vsnprintf(NULL, 0, msg, args); 438 va_end(args); 439 440 if (n <= 0) 441 return; 442 443 /* Reallocate the string buffer as needed. */ 444 total = log_ctx->pos + n + 1; 445 446 if (total > log_ctx->size) { 447 char *buf = kvcalloc(total, sizeof(char), GFP_KERNEL); 448 449 if (buf) { 450 memcpy(buf, log_ctx->buf, log_ctx->pos); 451 kfree(log_ctx->buf); 452 453 log_ctx->buf = buf; 454 log_ctx->size = total; 455 } 456 } 457 458 if (!log_ctx->buf) 459 return; 460 461 /* Write the formatted string to the log buffer. */ 462 va_start(args, msg); 463 n = vscnprintf( 464 log_ctx->buf + log_ctx->pos, 465 log_ctx->size - log_ctx->pos, 466 msg, 467 args); 468 va_end(args); 469 470 if (n > 0) 471 log_ctx->pos += n; 472 } 473 474 void dm_dtn_log_end(struct dc_context *ctx, 475 struct dc_log_buffer_ctx *log_ctx) 476 { 477 static const char msg[] = "[dtn end]\n"; 478 479 if (!log_ctx) { 480 pr_info("%s", msg); 481 return; 482 } 483 484 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); 485 } 486 487 bool dm_helpers_dp_mst_start_top_mgr( 488 struct dc_context *ctx, 489 const struct dc_link *link, 490 bool boot) 491 { 492 struct amdgpu_dm_connector *aconnector = link->priv; 493 int ret; 494 495 if (!aconnector) { 496 DRM_ERROR("Failed to find connector for link!"); 497 return false; 498 } 499 500 if (boot) { 501 DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n", 502 aconnector, aconnector->base.base.id); 503 return true; 504 } 505 506 DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n", 507 aconnector, aconnector->base.base.id); 508 509 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 510 if (ret < 0) { 511 DRM_ERROR("DM_MST: Failed to set the device into MST mode!"); 512 return false; 513 } 514 515 DRM_INFO("DM_MST: DP%x, %d-lane link detected\n", aconnector->mst_mgr.dpcd[0], 516 aconnector->mst_mgr.dpcd[2] & DP_MAX_LANE_COUNT_MASK); 517 518 return true; 519 } 520 521 bool dm_helpers_dp_mst_stop_top_mgr( 522 struct dc_context *ctx, 523 struct dc_link *link) 524 { 525 struct amdgpu_dm_connector *aconnector = link->priv; 526 527 if (!aconnector) { 528 DRM_ERROR("Failed to find connector for link!"); 529 return false; 530 } 531 532 DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n", 533 aconnector, aconnector->base.base.id); 534 535 if (aconnector->mst_mgr.mst_state == true) { 536 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false); 537 link->cur_link_settings.lane_count = 0; 538 } 539 540 return false; 541 } 542 543 bool dm_helpers_dp_read_dpcd( 544 struct dc_context *ctx, 545 const struct dc_link *link, 546 uint32_t address, 547 uint8_t *data, 548 uint32_t size) 549 { 550 551 struct amdgpu_dm_connector *aconnector = link->priv; 552 553 if (!aconnector) 554 return false; 555 556 return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address, data, 557 size) == size; 558 } 559 560 bool dm_helpers_dp_write_dpcd( 561 struct dc_context *ctx, 562 const struct dc_link *link, 563 uint32_t address, 564 const uint8_t *data, 565 uint32_t size) 566 { 567 struct amdgpu_dm_connector *aconnector = link->priv; 568 569 if (!aconnector) { 570 DRM_ERROR("Failed to find connector for link!"); 571 return false; 572 } 573 574 return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux, 575 address, (uint8_t *)data, size) > 0; 576 } 577 578 bool dm_helpers_submit_i2c( 579 struct dc_context *ctx, 580 const struct dc_link *link, 581 struct i2c_command *cmd) 582 { 583 struct amdgpu_dm_connector *aconnector = link->priv; 584 struct i2c_msg *msgs; 585 int i = 0; 586 int num = cmd->number_of_payloads; 587 bool result; 588 589 if (!aconnector) { 590 DRM_ERROR("Failed to find connector for link!"); 591 return false; 592 } 593 594 msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL); 595 596 if (!msgs) 597 return false; 598 599 for (i = 0; i < num; i++) { 600 msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD; 601 msgs[i].addr = cmd->payloads[i].address; 602 msgs[i].len = cmd->payloads[i].length; 603 msgs[i].buf = cmd->payloads[i].data; 604 } 605 606 result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num; 607 608 kfree(msgs); 609 610 return result; 611 } 612 613 static bool execute_synaptics_rc_command(struct drm_dp_aux *aux, 614 bool is_write_cmd, 615 unsigned char cmd, 616 unsigned int length, 617 unsigned int offset, 618 unsigned char *data) 619 { 620 bool success = false; 621 unsigned char rc_data[16] = {0}; 622 unsigned char rc_offset[4] = {0}; 623 unsigned char rc_length[2] = {0}; 624 unsigned char rc_cmd = 0; 625 unsigned char rc_result = 0xFF; 626 unsigned char i = 0; 627 int ret; 628 629 if (is_write_cmd) { 630 // write rc data 631 memmove(rc_data, data, length); 632 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_DATA, rc_data, sizeof(rc_data)); 633 } 634 635 // write rc offset 636 rc_offset[0] = (unsigned char) offset & 0xFF; 637 rc_offset[1] = (unsigned char) (offset >> 8) & 0xFF; 638 rc_offset[2] = (unsigned char) (offset >> 16) & 0xFF; 639 rc_offset[3] = (unsigned char) (offset >> 24) & 0xFF; 640 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_OFFSET, rc_offset, sizeof(rc_offset)); 641 642 // write rc length 643 rc_length[0] = (unsigned char) length & 0xFF; 644 rc_length[1] = (unsigned char) (length >> 8) & 0xFF; 645 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_LENGTH, rc_length, sizeof(rc_length)); 646 647 // write rc cmd 648 rc_cmd = cmd | 0x80; 649 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd)); 650 651 if (ret < 0) { 652 DRM_ERROR("%s: write cmd ..., err = %d\n", __func__, ret); 653 return false; 654 } 655 656 // poll until active is 0 657 for (i = 0; i < 10; i++) { 658 drm_dp_dpcd_read(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd)); 659 if (rc_cmd == cmd) 660 // active is 0 661 break; 662 msleep(10); 663 } 664 665 // read rc result 666 drm_dp_dpcd_read(aux, SYNAPTICS_RC_RESULT, &rc_result, sizeof(rc_result)); 667 success = (rc_result == 0); 668 669 if (success && !is_write_cmd) { 670 // read rc data 671 drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length); 672 } 673 674 drm_dbg_dp(aux->drm_dev, "success = %d\n", success); 675 676 return success; 677 } 678 679 static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux) 680 { 681 unsigned char data[16] = {0}; 682 683 drm_dbg_dp(aux->drm_dev, "Start\n"); 684 685 // Step 2 686 data[0] = 'P'; 687 data[1] = 'R'; 688 data[2] = 'I'; 689 data[3] = 'U'; 690 data[4] = 'S'; 691 692 if (!execute_synaptics_rc_command(aux, true, 0x01, 5, 0, data)) 693 return; 694 695 // Step 3 and 4 696 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data)) 697 return; 698 699 data[0] &= (~(1 << 1)); // set bit 1 to 0 700 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data)) 701 return; 702 703 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data)) 704 return; 705 706 data[0] &= (~(1 << 1)); // set bit 1 to 0 707 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220D98, data)) 708 return; 709 710 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data)) 711 return; 712 713 data[0] &= (~(1 << 1)); // set bit 1 to 0 714 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data)) 715 return; 716 717 // Step 3 and 5 718 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data)) 719 return; 720 721 data[0] |= (1 << 1); // set bit 1 to 1 722 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data)) 723 return; 724 725 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data)) 726 return; 727 728 data[0] |= (1 << 1); // set bit 1 to 1 729 730 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data)) 731 return; 732 733 data[0] |= (1 << 1); // set bit 1 to 1 734 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data)) 735 return; 736 737 // Step 6 738 if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL)) 739 return; 740 741 drm_dbg_dp(aux->drm_dev, "Done\n"); 742 } 743 744 /* MST Dock */ 745 static const uint8_t SYNAPTICS_DEVICE_ID[] = "SYNA"; 746 747 static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst( 748 struct drm_dp_aux *aux, 749 const struct dc_stream_state *stream, 750 bool enable) 751 { 752 uint8_t ret = 0; 753 754 drm_dbg_dp(aux->drm_dev, 755 "Configure DSC to non-virtual dpcd synaptics\n"); 756 757 if (enable) { 758 /* When DSC is enabled on previous boot and reboot with the hub, 759 * there is a chance that Synaptics hub gets stuck during reboot sequence. 760 * Applying a workaround to reset Synaptics SDP fifo before enabling the first stream 761 */ 762 if (!stream->link->link_status.link_active && 763 memcmp(stream->link->dpcd_caps.branch_dev_name, 764 (int8_t *)SYNAPTICS_DEVICE_ID, 4) == 0) 765 apply_synaptics_fifo_reset_wa(aux); 766 767 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1); 768 DRM_INFO("Send DSC enable to synaptics\n"); 769 770 } else { 771 /* Synaptics hub not support virtual dpcd, 772 * external monitor occur garbage while disable DSC, 773 * Disable DSC only when entire link status turn to false, 774 */ 775 if (!stream->link->link_status.link_active) { 776 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1); 777 DRM_INFO("Send DSC disable to synaptics\n"); 778 } 779 } 780 781 return ret; 782 } 783 784 bool dm_helpers_dp_write_dsc_enable( 785 struct dc_context *ctx, 786 const struct dc_stream_state *stream, 787 bool enable) 788 { 789 static const uint8_t DSC_DISABLE; 790 static const uint8_t DSC_DECODING = 0x01; 791 static const uint8_t DSC_PASSTHROUGH = 0x02; 792 793 struct amdgpu_dm_connector *aconnector = 794 (struct amdgpu_dm_connector *)stream->dm_stream_context; 795 struct drm_device *dev = aconnector->base.dev; 796 struct drm_dp_mst_port *port; 797 uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE; 798 uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE; 799 uint8_t ret = 0; 800 801 if (!stream) 802 return false; 803 804 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 805 if (!aconnector->dsc_aux) 806 return false; 807 808 // apply w/a to synaptics 809 if (needs_dsc_aux_workaround(aconnector->dc_link) && 810 (aconnector->mst_downstream_port_present.byte & 0x7) != 0x3) 811 return write_dsc_enable_synaptics_non_virtual_dpcd_mst( 812 aconnector->dsc_aux, stream, enable_dsc); 813 814 port = aconnector->mst_output_port; 815 816 if (enable) { 817 if (port->passthrough_aux) { 818 ret = drm_dp_dpcd_write(port->passthrough_aux, 819 DP_DSC_ENABLE, 820 &enable_passthrough, 1); 821 drm_dbg_dp(dev, 822 "Sent DSC pass-through enable to virtual dpcd port, ret = %u\n", 823 ret); 824 } 825 826 ret = drm_dp_dpcd_write(aconnector->dsc_aux, 827 DP_DSC_ENABLE, &enable_dsc, 1); 828 drm_dbg_dp(dev, 829 "Sent DSC decoding enable to %s port, ret = %u\n", 830 (port->passthrough_aux) ? "remote RX" : 831 "virtual dpcd", 832 ret); 833 } else { 834 ret = drm_dp_dpcd_write(aconnector->dsc_aux, 835 DP_DSC_ENABLE, &enable_dsc, 1); 836 drm_dbg_dp(dev, 837 "Sent DSC decoding disable to %s port, ret = %u\n", 838 (port->passthrough_aux) ? "remote RX" : 839 "virtual dpcd", 840 ret); 841 842 if (port->passthrough_aux) { 843 ret = drm_dp_dpcd_write(port->passthrough_aux, 844 DP_DSC_ENABLE, 845 &enable_passthrough, 1); 846 drm_dbg_dp(dev, 847 "Sent DSC pass-through disable to virtual dpcd port, ret = %u\n", 848 ret); 849 } 850 } 851 } 852 853 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) { 854 if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { 855 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); 856 drm_dbg_dp(dev, 857 "Send DSC %s to SST RX\n", 858 enable_dsc ? "enable" : "disable"); 859 } else if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { 860 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); 861 drm_dbg_dp(dev, 862 "Send DSC %s to DP-HDMI PCON\n", 863 enable_dsc ? "enable" : "disable"); 864 } 865 } 866 867 return ret; 868 } 869 870 bool dm_helpers_is_dp_sink_present(struct dc_link *link) 871 { 872 bool dp_sink_present; 873 struct amdgpu_dm_connector *aconnector = link->priv; 874 875 if (!aconnector) { 876 BUG_ON("Failed to find connector for link!"); 877 return true; 878 } 879 880 mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex); 881 dp_sink_present = dc_link_is_dp_sink_present(link); 882 mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex); 883 return dp_sink_present; 884 } 885 886 enum dc_edid_status dm_helpers_read_local_edid( 887 struct dc_context *ctx, 888 struct dc_link *link, 889 struct dc_sink *sink) 890 { 891 struct amdgpu_dm_connector *aconnector = link->priv; 892 struct drm_connector *connector = &aconnector->base; 893 struct i2c_adapter *ddc; 894 int retry = 3; 895 enum dc_edid_status edid_status; 896 struct edid *edid; 897 898 if (link->aux_mode) 899 ddc = &aconnector->dm_dp_aux.aux.ddc; 900 else 901 ddc = &aconnector->i2c->base; 902 903 /* some dongles read edid incorrectly the first time, 904 * do check sum and retry to make sure read correct edid. 905 */ 906 do { 907 908 edid = drm_get_edid(&aconnector->base, ddc); 909 910 /* DP Compliance Test 4.2.2.6 */ 911 if (link->aux_mode && connector->edid_corrupt) 912 drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum); 913 914 if (!edid && connector->edid_corrupt) { 915 connector->edid_corrupt = false; 916 return EDID_BAD_CHECKSUM; 917 } 918 919 if (!edid) 920 return EDID_NO_RESPONSE; 921 922 sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1); 923 memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length); 924 925 /* We don't need the original edid anymore */ 926 kfree(edid); 927 928 edid_status = dm_helpers_parse_edid_caps( 929 link, 930 &sink->dc_edid, 931 &sink->edid_caps); 932 933 } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0); 934 935 if (edid_status != EDID_OK) 936 DRM_ERROR("EDID err: %d, on connector: %s", 937 edid_status, 938 aconnector->base.name); 939 if (link->aux_mode) { 940 union test_request test_request = {0}; 941 union test_response test_response = {0}; 942 943 dm_helpers_dp_read_dpcd(ctx, 944 link, 945 DP_TEST_REQUEST, 946 &test_request.raw, 947 sizeof(union test_request)); 948 949 if (!test_request.bits.EDID_READ) 950 return edid_status; 951 952 test_response.bits.EDID_CHECKSUM_WRITE = 1; 953 954 dm_helpers_dp_write_dpcd(ctx, 955 link, 956 DP_TEST_EDID_CHECKSUM, 957 &sink->dc_edid.raw_edid[sink->dc_edid.length-1], 958 1); 959 960 dm_helpers_dp_write_dpcd(ctx, 961 link, 962 DP_TEST_RESPONSE, 963 &test_response.raw, 964 sizeof(test_response)); 965 966 } 967 968 return edid_status; 969 } 970 int dm_helper_dmub_aux_transfer_sync( 971 struct dc_context *ctx, 972 const struct dc_link *link, 973 struct aux_payload *payload, 974 enum aux_return_code_type *operation_result) 975 { 976 return amdgpu_dm_process_dmub_aux_transfer_sync(ctx, link->link_index, payload, 977 operation_result); 978 } 979 980 int dm_helpers_dmub_set_config_sync(struct dc_context *ctx, 981 const struct dc_link *link, 982 struct set_config_cmd_payload *payload, 983 enum set_config_status *operation_result) 984 { 985 return amdgpu_dm_process_dmub_set_config_sync(ctx, link->link_index, payload, 986 operation_result); 987 } 988 989 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks) 990 { 991 /* TODO: something */ 992 } 993 994 void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us) 995 { 996 // TODO: 997 //amdgpu_device_gpu_recover(dc_context->driver-context, NULL); 998 } 999 1000 void dm_helpers_init_panel_settings( 1001 struct dc_context *ctx, 1002 struct dc_panel_config *panel_config, 1003 struct dc_sink *sink) 1004 { 1005 // Extra Panel Power Sequence 1006 panel_config->pps.extra_t3_ms = sink->edid_caps.panel_patch.extra_t3_ms; 1007 panel_config->pps.extra_t7_ms = sink->edid_caps.panel_patch.extra_t7_ms; 1008 panel_config->pps.extra_delay_backlight_off = sink->edid_caps.panel_patch.extra_delay_backlight_off; 1009 panel_config->pps.extra_post_t7_ms = 0; 1010 panel_config->pps.extra_pre_t11_ms = 0; 1011 panel_config->pps.extra_t12_ms = sink->edid_caps.panel_patch.extra_t12_ms; 1012 panel_config->pps.extra_post_OUI_ms = 0; 1013 // Feature DSC 1014 panel_config->dsc.disable_dsc_edp = false; 1015 panel_config->dsc.force_dsc_edp_policy = 0; 1016 } 1017 1018 void dm_helpers_override_panel_settings( 1019 struct dc_context *ctx, 1020 struct dc_panel_config *panel_config) 1021 { 1022 // Feature DSC 1023 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) 1024 panel_config->dsc.disable_dsc_edp = true; 1025 } 1026 1027 void *dm_helpers_allocate_gpu_mem( 1028 struct dc_context *ctx, 1029 enum dc_gpu_mem_alloc_type type, 1030 size_t size, 1031 long long *addr) 1032 { 1033 struct amdgpu_device *adev = ctx->driver_context; 1034 struct dal_allocation *da; 1035 u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ? 1036 AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM; 1037 int ret; 1038 1039 da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL); 1040 if (!da) 1041 return NULL; 1042 1043 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 1044 domain, &da->bo, 1045 &da->gpu_addr, &da->cpu_ptr); 1046 1047 *addr = da->gpu_addr; 1048 1049 if (ret) { 1050 kfree(da); 1051 return NULL; 1052 } 1053 1054 /* add da to list in dm */ 1055 list_add(&da->list, &adev->dm.da_list); 1056 1057 return da->cpu_ptr; 1058 } 1059 1060 void dm_helpers_free_gpu_mem( 1061 struct dc_context *ctx, 1062 enum dc_gpu_mem_alloc_type type, 1063 void *pvMem) 1064 { 1065 struct amdgpu_device *adev = ctx->driver_context; 1066 struct dal_allocation *da; 1067 1068 /* walk the da list in DM */ 1069 list_for_each_entry(da, &adev->dm.da_list, list) { 1070 if (pvMem == da->cpu_ptr) { 1071 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); 1072 list_del(&da->list); 1073 kfree(da); 1074 break; 1075 } 1076 } 1077 } 1078 1079 bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable) 1080 { 1081 enum dc_irq_source irq_source; 1082 bool ret; 1083 1084 irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX; 1085 1086 ret = dc_interrupt_set(ctx->dc, irq_source, enable); 1087 1088 DRM_DEBUG_DRIVER("Dmub trace irq %sabling: r=%d\n", 1089 enable ? "en" : "dis", ret); 1090 return ret; 1091 } 1092 1093 void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream) 1094 { 1095 /* TODO: virtual DPCD */ 1096 struct dc_link *link = stream->link; 1097 union down_spread_ctrl old_downspread; 1098 union down_spread_ctrl new_downspread; 1099 1100 if (link->aux_access_disabled) 1101 return; 1102 1103 if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL, 1104 &old_downspread.raw, 1105 sizeof(old_downspread))) 1106 return; 1107 1108 new_downspread.raw = old_downspread.raw; 1109 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 1110 (stream->ignore_msa_timing_param) ? 1 : 0; 1111 1112 if (new_downspread.raw != old_downspread.raw) 1113 dm_helpers_dp_write_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL, 1114 &new_downspread.raw, 1115 sizeof(new_downspread)); 1116 } 1117 1118 bool dm_helpers_dp_handle_test_pattern_request( 1119 struct dc_context *ctx, 1120 const struct dc_link *link, 1121 union link_test_pattern dpcd_test_pattern, 1122 union test_misc dpcd_test_params) 1123 { 1124 enum dp_test_pattern test_pattern; 1125 enum dp_test_pattern_color_space test_pattern_color_space = 1126 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED; 1127 enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED; 1128 enum dc_pixel_encoding requestPixelEncoding = PIXEL_ENCODING_UNDEFINED; 1129 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; 1130 struct pipe_ctx *pipe_ctx = NULL; 1131 struct amdgpu_dm_connector *aconnector = link->priv; 1132 struct drm_device *dev = aconnector->base.dev; 1133 int i; 1134 1135 for (i = 0; i < MAX_PIPES; i++) { 1136 if (pipes[i].stream == NULL) 1137 continue; 1138 1139 if (pipes[i].stream->link == link && !pipes[i].top_pipe && 1140 !pipes[i].prev_odm_pipe) { 1141 pipe_ctx = &pipes[i]; 1142 break; 1143 } 1144 } 1145 1146 if (pipe_ctx == NULL) 1147 return false; 1148 1149 switch (dpcd_test_pattern.bits.PATTERN) { 1150 case LINK_TEST_PATTERN_COLOR_RAMP: 1151 test_pattern = DP_TEST_PATTERN_COLOR_RAMP; 1152 break; 1153 case LINK_TEST_PATTERN_VERTICAL_BARS: 1154 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS; 1155 break; /* black and white */ 1156 case LINK_TEST_PATTERN_COLOR_SQUARES: 1157 test_pattern = (dpcd_test_params.bits.DYN_RANGE == 1158 TEST_DYN_RANGE_VESA ? 1159 DP_TEST_PATTERN_COLOR_SQUARES : 1160 DP_TEST_PATTERN_COLOR_SQUARES_CEA); 1161 break; 1162 default: 1163 test_pattern = DP_TEST_PATTERN_VIDEO_MODE; 1164 break; 1165 } 1166 1167 if (dpcd_test_params.bits.CLR_FORMAT == 0) 1168 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB; 1169 else 1170 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ? 1171 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 : 1172 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601; 1173 1174 switch (dpcd_test_params.bits.BPC) { 1175 case 0: // 6 bits 1176 requestColorDepth = COLOR_DEPTH_666; 1177 break; 1178 case 1: // 8 bits 1179 requestColorDepth = COLOR_DEPTH_888; 1180 break; 1181 case 2: // 10 bits 1182 requestColorDepth = COLOR_DEPTH_101010; 1183 break; 1184 case 3: // 12 bits 1185 requestColorDepth = COLOR_DEPTH_121212; 1186 break; 1187 default: 1188 break; 1189 } 1190 1191 switch (dpcd_test_params.bits.CLR_FORMAT) { 1192 case 0: 1193 requestPixelEncoding = PIXEL_ENCODING_RGB; 1194 break; 1195 case 1: 1196 requestPixelEncoding = PIXEL_ENCODING_YCBCR422; 1197 break; 1198 case 2: 1199 requestPixelEncoding = PIXEL_ENCODING_YCBCR444; 1200 break; 1201 default: 1202 requestPixelEncoding = PIXEL_ENCODING_RGB; 1203 break; 1204 } 1205 1206 if ((requestColorDepth != COLOR_DEPTH_UNDEFINED 1207 && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) 1208 || (requestPixelEncoding != PIXEL_ENCODING_UNDEFINED 1209 && pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) { 1210 drm_dbg(dev, 1211 "original bpc %d pix encoding %d, changing to %d %d\n", 1212 pipe_ctx->stream->timing.display_color_depth, 1213 pipe_ctx->stream->timing.pixel_encoding, 1214 requestColorDepth, 1215 requestPixelEncoding); 1216 pipe_ctx->stream->timing.display_color_depth = requestColorDepth; 1217 pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding; 1218 1219 dc_link_update_dsc_config(pipe_ctx); 1220 1221 aconnector->timing_changed = true; 1222 /* store current timing */ 1223 if (aconnector->timing_requested) 1224 *aconnector->timing_requested = pipe_ctx->stream->timing; 1225 else 1226 drm_err(dev, "timing storage failed\n"); 1227 1228 } 1229 1230 pipe_ctx->stream->test_pattern.type = test_pattern; 1231 pipe_ctx->stream->test_pattern.color_space = test_pattern_color_space; 1232 1233 dc_link_dp_set_test_pattern( 1234 (struct dc_link *) link, 1235 test_pattern, 1236 test_pattern_color_space, 1237 NULL, 1238 NULL, 1239 0); 1240 1241 return false; 1242 } 1243 1244 void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz) 1245 { 1246 // TODO 1247 } 1248 1249 void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable) 1250 { 1251 /* TODO: add periodic detection implementation */ 1252 } 1253 1254 void dm_helpers_dp_mst_update_branch_bandwidth( 1255 struct dc_context *ctx, 1256 struct dc_link *link) 1257 { 1258 // TODO 1259 } 1260 1261 static bool dm_is_freesync_pcon_whitelist(const uint32_t branch_dev_id) 1262 { 1263 bool ret_val = false; 1264 1265 switch (branch_dev_id) { 1266 case DP_BRANCH_DEVICE_ID_0060AD: 1267 case DP_BRANCH_DEVICE_ID_00E04C: 1268 case DP_BRANCH_DEVICE_ID_90CC24: 1269 ret_val = true; 1270 break; 1271 default: 1272 break; 1273 } 1274 1275 return ret_val; 1276 } 1277 1278 enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link) 1279 { 1280 struct dpcd_caps *dpcd_caps = &link->dpcd_caps; 1281 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; 1282 1283 switch (dpcd_caps->dongle_type) { 1284 case DISPLAY_DONGLE_DP_HDMI_CONVERTER: 1285 if (dpcd_caps->adaptive_sync_caps.dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT == true && 1286 dpcd_caps->allow_invalid_MSA_timing_param == true && 1287 dm_is_freesync_pcon_whitelist(dpcd_caps->branch_dev_id)) 1288 as_type = FREESYNC_TYPE_PCON_IN_WHITELIST; 1289 break; 1290 default: 1291 break; 1292 } 1293 1294 return as_type; 1295 } 1296