1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string.h> 27 #include <linux/acpi.h> 28 #include <linux/i2c.h> 29 30 #include <drm/drm_atomic.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/amdgpu_drm.h> 33 #include <drm/drm_edid.h> 34 35 #include "dm_services.h" 36 #include "amdgpu.h" 37 #include "dc.h" 38 #include "amdgpu_dm.h" 39 #include "amdgpu_dm_irq.h" 40 #include "amdgpu_dm_mst_types.h" 41 #include "dpcd_defs.h" 42 #include "dc/inc/core_types.h" 43 44 #include "dm_helpers.h" 45 #include "ddc_service_types.h" 46 47 /* dm_helpers_parse_edid_caps 48 * 49 * Parse edid caps 50 * 51 * @edid: [in] pointer to edid 52 * edid_caps: [in] pointer to edid caps 53 * @return 54 * void 55 * */ 56 enum dc_edid_status dm_helpers_parse_edid_caps( 57 struct dc_link *link, 58 const struct dc_edid *edid, 59 struct dc_edid_caps *edid_caps) 60 { 61 struct amdgpu_dm_connector *aconnector = link->priv; 62 struct drm_connector *connector = &aconnector->base; 63 struct edid *edid_buf = edid ? (struct edid *) edid->raw_edid : NULL; 64 struct cea_sad *sads; 65 int sad_count = -1; 66 int sadb_count = -1; 67 int i = 0; 68 uint8_t *sadb = NULL; 69 70 enum dc_edid_status result = EDID_OK; 71 72 if (!edid_caps || !edid) 73 return EDID_BAD_INPUT; 74 75 if (!drm_edid_is_valid(edid_buf)) 76 result = EDID_BAD_CHECKSUM; 77 78 edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] | 79 ((uint16_t) edid_buf->mfg_id[1])<<8; 80 edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] | 81 ((uint16_t) edid_buf->prod_code[1])<<8; 82 edid_caps->serial_number = edid_buf->serial; 83 edid_caps->manufacture_week = edid_buf->mfg_week; 84 edid_caps->manufacture_year = edid_buf->mfg_year; 85 86 drm_edid_get_monitor_name(edid_buf, 87 edid_caps->display_name, 88 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 89 90 edid_caps->edid_hdmi = connector->display_info.is_hdmi; 91 92 sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads); 93 if (sad_count <= 0) 94 return result; 95 96 edid_caps->audio_mode_count = sad_count < DC_MAX_AUDIO_DESC_COUNT ? sad_count : DC_MAX_AUDIO_DESC_COUNT; 97 for (i = 0; i < edid_caps->audio_mode_count; ++i) { 98 struct cea_sad *sad = &sads[i]; 99 100 edid_caps->audio_modes[i].format_code = sad->format; 101 edid_caps->audio_modes[i].channel_count = sad->channels + 1; 102 edid_caps->audio_modes[i].sample_rate = sad->freq; 103 edid_caps->audio_modes[i].sample_size = sad->byte2; 104 } 105 106 sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb); 107 108 if (sadb_count < 0) { 109 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count); 110 sadb_count = 0; 111 } 112 113 if (sadb_count) 114 edid_caps->speaker_flags = sadb[0]; 115 else 116 edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION; 117 118 kfree(sads); 119 kfree(sadb); 120 121 return result; 122 } 123 124 static void 125 fill_dc_mst_payload_table_from_drm(struct dc_link *link, 126 bool enable, 127 struct drm_dp_mst_atomic_payload *target_payload, 128 struct dc_dp_mst_stream_allocation_table *table) 129 { 130 struct dc_dp_mst_stream_allocation_table new_table = { 0 }; 131 struct dc_dp_mst_stream_allocation *sa; 132 struct link_mst_stream_allocation_table copy_of_link_table = 133 link->mst_stream_alloc_table; 134 135 int i; 136 int current_hw_table_stream_cnt = copy_of_link_table.stream_count; 137 struct link_mst_stream_allocation *dc_alloc; 138 139 /* TODO: refactor to set link->mst_stream_alloc_table directly if possible.*/ 140 if (enable) { 141 dc_alloc = 142 ©_of_link_table.stream_allocations[current_hw_table_stream_cnt]; 143 dc_alloc->vcp_id = target_payload->vcpi; 144 dc_alloc->slot_count = target_payload->time_slots; 145 } else { 146 for (i = 0; i < copy_of_link_table.stream_count; i++) { 147 dc_alloc = 148 ©_of_link_table.stream_allocations[i]; 149 150 if (dc_alloc->vcp_id == target_payload->vcpi) { 151 dc_alloc->vcp_id = 0; 152 dc_alloc->slot_count = 0; 153 break; 154 } 155 } 156 ASSERT(i != copy_of_link_table.stream_count); 157 } 158 159 /* Fill payload info*/ 160 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 161 dc_alloc = 162 ©_of_link_table.stream_allocations[i]; 163 if (dc_alloc->vcp_id > 0 && dc_alloc->slot_count > 0) { 164 sa = &new_table.stream_allocations[new_table.stream_count]; 165 sa->slot_count = dc_alloc->slot_count; 166 sa->vcp_id = dc_alloc->vcp_id; 167 new_table.stream_count++; 168 } 169 } 170 171 /* Overwrite the old table */ 172 *table = new_table; 173 } 174 175 void dm_helpers_dp_update_branch_info( 176 struct dc_context *ctx, 177 const struct dc_link *link) 178 {} 179 180 /* 181 * Writes payload allocation table in immediate downstream device. 182 */ 183 bool dm_helpers_dp_mst_write_payload_allocation_table( 184 struct dc_context *ctx, 185 const struct dc_stream_state *stream, 186 struct dc_dp_mst_stream_allocation_table *proposed_table, 187 bool enable) 188 { 189 struct amdgpu_dm_connector *aconnector; 190 struct drm_dp_mst_topology_state *mst_state; 191 struct drm_dp_mst_atomic_payload *payload; 192 struct drm_dp_mst_topology_mgr *mst_mgr; 193 194 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 195 /* Accessing the connector state is required for vcpi_slots allocation 196 * and directly relies on behaviour in commit check 197 * that blocks before commit guaranteeing that the state 198 * is not gonna be swapped while still in use in commit tail */ 199 200 if (!aconnector || !aconnector->mst_root) 201 return false; 202 203 mst_mgr = &aconnector->mst_root->mst_mgr; 204 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); 205 206 /* It's OK for this to fail */ 207 payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); 208 if (enable) 209 drm_dp_add_payload_part1(mst_mgr, mst_state, payload); 210 else 211 drm_dp_remove_payload(mst_mgr, mst_state, payload); 212 213 /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or 214 * AUX message. The sequence is slot 1-63 allocated sequence for each 215 * stream. AMD ASIC stream slot allocation should follow the same 216 * sequence. copy DRM MST allocation to dc */ 217 fill_dc_mst_payload_table_from_drm(stream->link, enable, payload, proposed_table); 218 219 return true; 220 } 221 222 /* 223 * poll pending down reply 224 */ 225 void dm_helpers_dp_mst_poll_pending_down_reply( 226 struct dc_context *ctx, 227 const struct dc_link *link) 228 {} 229 230 /* 231 * Clear payload allocation table before enable MST DP link. 232 */ 233 void dm_helpers_dp_mst_clear_payload_allocation_table( 234 struct dc_context *ctx, 235 const struct dc_link *link) 236 {} 237 238 /* 239 * Polls for ACT (allocation change trigger) handled and sends 240 * ALLOCATE_PAYLOAD message. 241 */ 242 enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger( 243 struct dc_context *ctx, 244 const struct dc_stream_state *stream) 245 { 246 struct amdgpu_dm_connector *aconnector; 247 struct drm_dp_mst_topology_mgr *mst_mgr; 248 int ret; 249 250 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 251 252 if (!aconnector || !aconnector->mst_root) 253 return ACT_FAILED; 254 255 mst_mgr = &aconnector->mst_root->mst_mgr; 256 257 if (!mst_mgr->mst_state) 258 return ACT_FAILED; 259 260 ret = drm_dp_check_act_status(mst_mgr); 261 262 if (ret) 263 return ACT_FAILED; 264 265 return ACT_SUCCESS; 266 } 267 268 bool dm_helpers_dp_mst_send_payload_allocation( 269 struct dc_context *ctx, 270 const struct dc_stream_state *stream, 271 bool enable) 272 { 273 struct amdgpu_dm_connector *aconnector; 274 struct drm_dp_mst_topology_state *mst_state; 275 struct drm_dp_mst_topology_mgr *mst_mgr; 276 struct drm_dp_mst_atomic_payload *payload; 277 enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD; 278 enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD; 279 int ret = 0; 280 281 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 282 283 if (!aconnector || !aconnector->mst_root) 284 return false; 285 286 mst_mgr = &aconnector->mst_root->mst_mgr; 287 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); 288 289 payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); 290 291 if (!enable) { 292 set_flag = MST_CLEAR_ALLOCATED_PAYLOAD; 293 clr_flag = MST_ALLOCATE_NEW_PAYLOAD; 294 } 295 296 if (enable) 297 ret = drm_dp_add_payload_part2(mst_mgr, mst_state->base.state, payload); 298 299 if (ret) { 300 amdgpu_dm_set_mst_status(&aconnector->mst_status, 301 set_flag, false); 302 } else { 303 amdgpu_dm_set_mst_status(&aconnector->mst_status, 304 set_flag, true); 305 amdgpu_dm_set_mst_status(&aconnector->mst_status, 306 clr_flag, false); 307 } 308 309 return true; 310 } 311 312 void dm_dtn_log_begin(struct dc_context *ctx, 313 struct dc_log_buffer_ctx *log_ctx) 314 { 315 static const char msg[] = "[dtn begin]\n"; 316 317 if (!log_ctx) { 318 pr_info("%s", msg); 319 return; 320 } 321 322 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); 323 } 324 325 __printf(3, 4) 326 void dm_dtn_log_append_v(struct dc_context *ctx, 327 struct dc_log_buffer_ctx *log_ctx, 328 const char *msg, ...) 329 { 330 va_list args; 331 size_t total; 332 int n; 333 334 if (!log_ctx) { 335 /* No context, redirect to dmesg. */ 336 struct va_format vaf; 337 338 vaf.fmt = msg; 339 vaf.va = &args; 340 341 va_start(args, msg); 342 pr_info("%pV", &vaf); 343 va_end(args); 344 345 return; 346 } 347 348 /* Measure the output. */ 349 va_start(args, msg); 350 n = vsnprintf(NULL, 0, msg, args); 351 va_end(args); 352 353 if (n <= 0) 354 return; 355 356 /* Reallocate the string buffer as needed. */ 357 total = log_ctx->pos + n + 1; 358 359 if (total > log_ctx->size) { 360 char *buf = (char *)kvcalloc(total, sizeof(char), GFP_KERNEL); 361 362 if (buf) { 363 memcpy(buf, log_ctx->buf, log_ctx->pos); 364 kfree(log_ctx->buf); 365 366 log_ctx->buf = buf; 367 log_ctx->size = total; 368 } 369 } 370 371 if (!log_ctx->buf) 372 return; 373 374 /* Write the formatted string to the log buffer. */ 375 va_start(args, msg); 376 n = vscnprintf( 377 log_ctx->buf + log_ctx->pos, 378 log_ctx->size - log_ctx->pos, 379 msg, 380 args); 381 va_end(args); 382 383 if (n > 0) 384 log_ctx->pos += n; 385 } 386 387 void dm_dtn_log_end(struct dc_context *ctx, 388 struct dc_log_buffer_ctx *log_ctx) 389 { 390 static const char msg[] = "[dtn end]\n"; 391 392 if (!log_ctx) { 393 pr_info("%s", msg); 394 return; 395 } 396 397 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); 398 } 399 400 bool dm_helpers_dp_mst_start_top_mgr( 401 struct dc_context *ctx, 402 const struct dc_link *link, 403 bool boot) 404 { 405 struct amdgpu_dm_connector *aconnector = link->priv; 406 407 if (!aconnector) { 408 DRM_ERROR("Failed to find connector for link!"); 409 return false; 410 } 411 412 if (boot) { 413 DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n", 414 aconnector, aconnector->base.base.id); 415 return true; 416 } 417 418 DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n", 419 aconnector, aconnector->base.base.id); 420 421 return (drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true) == 0); 422 } 423 424 bool dm_helpers_dp_mst_stop_top_mgr( 425 struct dc_context *ctx, 426 struct dc_link *link) 427 { 428 struct amdgpu_dm_connector *aconnector = link->priv; 429 430 if (!aconnector) { 431 DRM_ERROR("Failed to find connector for link!"); 432 return false; 433 } 434 435 DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n", 436 aconnector, aconnector->base.base.id); 437 438 if (aconnector->mst_mgr.mst_state == true) { 439 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false); 440 link->cur_link_settings.lane_count = 0; 441 } 442 443 return false; 444 } 445 446 bool dm_helpers_dp_read_dpcd( 447 struct dc_context *ctx, 448 const struct dc_link *link, 449 uint32_t address, 450 uint8_t *data, 451 uint32_t size) 452 { 453 454 struct amdgpu_dm_connector *aconnector = link->priv; 455 456 if (!aconnector) { 457 DC_LOG_DC("Failed to find connector for link!\n"); 458 return false; 459 } 460 461 return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address, 462 data, size) > 0; 463 } 464 465 bool dm_helpers_dp_write_dpcd( 466 struct dc_context *ctx, 467 const struct dc_link *link, 468 uint32_t address, 469 const uint8_t *data, 470 uint32_t size) 471 { 472 struct amdgpu_dm_connector *aconnector = link->priv; 473 474 if (!aconnector) { 475 DRM_ERROR("Failed to find connector for link!"); 476 return false; 477 } 478 479 return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux, 480 address, (uint8_t *)data, size) > 0; 481 } 482 483 bool dm_helpers_submit_i2c( 484 struct dc_context *ctx, 485 const struct dc_link *link, 486 struct i2c_command *cmd) 487 { 488 struct amdgpu_dm_connector *aconnector = link->priv; 489 struct i2c_msg *msgs; 490 int i = 0; 491 int num = cmd->number_of_payloads; 492 bool result; 493 494 if (!aconnector) { 495 DRM_ERROR("Failed to find connector for link!"); 496 return false; 497 } 498 499 msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL); 500 501 if (!msgs) 502 return false; 503 504 for (i = 0; i < num; i++) { 505 msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD; 506 msgs[i].addr = cmd->payloads[i].address; 507 msgs[i].len = cmd->payloads[i].length; 508 msgs[i].buf = cmd->payloads[i].data; 509 } 510 511 result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num; 512 513 kfree(msgs); 514 515 return result; 516 } 517 518 #if defined(CONFIG_DRM_AMD_DC_DCN) 519 static bool execute_synaptics_rc_command(struct drm_dp_aux *aux, 520 bool is_write_cmd, 521 unsigned char cmd, 522 unsigned int length, 523 unsigned int offset, 524 unsigned char *data) 525 { 526 bool success = false; 527 unsigned char rc_data[16] = {0}; 528 unsigned char rc_offset[4] = {0}; 529 unsigned char rc_length[2] = {0}; 530 unsigned char rc_cmd = 0; 531 unsigned char rc_result = 0xFF; 532 unsigned char i = 0; 533 int ret; 534 535 if (is_write_cmd) { 536 // write rc data 537 memmove(rc_data, data, length); 538 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_DATA, rc_data, sizeof(rc_data)); 539 } 540 541 // write rc offset 542 rc_offset[0] = (unsigned char) offset & 0xFF; 543 rc_offset[1] = (unsigned char) (offset >> 8) & 0xFF; 544 rc_offset[2] = (unsigned char) (offset >> 16) & 0xFF; 545 rc_offset[3] = (unsigned char) (offset >> 24) & 0xFF; 546 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_OFFSET, rc_offset, sizeof(rc_offset)); 547 548 // write rc length 549 rc_length[0] = (unsigned char) length & 0xFF; 550 rc_length[1] = (unsigned char) (length >> 8) & 0xFF; 551 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_LENGTH, rc_length, sizeof(rc_length)); 552 553 // write rc cmd 554 rc_cmd = cmd | 0x80; 555 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd)); 556 557 if (ret < 0) { 558 DRM_ERROR(" execute_synaptics_rc_command - write cmd ..., err = %d\n", ret); 559 return false; 560 } 561 562 // poll until active is 0 563 for (i = 0; i < 10; i++) { 564 drm_dp_dpcd_read(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd)); 565 if (rc_cmd == cmd) 566 // active is 0 567 break; 568 msleep(10); 569 } 570 571 // read rc result 572 drm_dp_dpcd_read(aux, SYNAPTICS_RC_RESULT, &rc_result, sizeof(rc_result)); 573 success = (rc_result == 0); 574 575 if (success && !is_write_cmd) { 576 // read rc data 577 drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length); 578 } 579 580 DC_LOG_DC(" execute_synaptics_rc_command - success = %d\n", success); 581 582 return success; 583 } 584 585 static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux) 586 { 587 unsigned char data[16] = {0}; 588 589 DC_LOG_DC("Start apply_synaptics_fifo_reset_wa\n"); 590 591 // Step 2 592 data[0] = 'P'; 593 data[1] = 'R'; 594 data[2] = 'I'; 595 data[3] = 'U'; 596 data[4] = 'S'; 597 598 if (!execute_synaptics_rc_command(aux, true, 0x01, 5, 0, data)) 599 return; 600 601 // Step 3 and 4 602 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data)) 603 return; 604 605 data[0] &= (~(1 << 1)); // set bit 1 to 0 606 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data)) 607 return; 608 609 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data)) 610 return; 611 612 data[0] &= (~(1 << 1)); // set bit 1 to 0 613 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220D98, data)) 614 return; 615 616 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data)) 617 return; 618 619 data[0] &= (~(1 << 1)); // set bit 1 to 0 620 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data)) 621 return; 622 623 // Step 3 and 5 624 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data)) 625 return; 626 627 data[0] |= (1 << 1); // set bit 1 to 1 628 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data)) 629 return; 630 631 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data)) 632 return; 633 634 data[0] |= (1 << 1); // set bit 1 to 1 635 return; 636 637 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data)) 638 return; 639 640 data[0] |= (1 << 1); // set bit 1 to 1 641 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data)) 642 return; 643 644 // Step 6 645 if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL)) 646 return; 647 648 DC_LOG_DC("Done apply_synaptics_fifo_reset_wa\n"); 649 } 650 651 static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst( 652 struct drm_dp_aux *aux, 653 const struct dc_stream_state *stream, 654 bool enable) 655 { 656 uint8_t ret = 0; 657 658 DC_LOG_DC("Configure DSC to non-virtual dpcd synaptics\n"); 659 660 if (enable) { 661 /* When DSC is enabled on previous boot and reboot with the hub, 662 * there is a chance that Synaptics hub gets stuck during reboot sequence. 663 * Applying a workaround to reset Synaptics SDP fifo before enabling the first stream 664 */ 665 if (!stream->link->link_status.link_active && 666 memcmp(stream->link->dpcd_caps.branch_dev_name, 667 (int8_t *)SYNAPTICS_DEVICE_ID, 4) == 0) 668 apply_synaptics_fifo_reset_wa(aux); 669 670 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1); 671 DRM_INFO("Send DSC enable to synaptics\n"); 672 673 } else { 674 /* Synaptics hub not support virtual dpcd, 675 * external monitor occur garbage while disable DSC, 676 * Disable DSC only when entire link status turn to false, 677 */ 678 if (!stream->link->link_status.link_active) { 679 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1); 680 DRM_INFO("Send DSC disable to synaptics\n"); 681 } 682 } 683 684 return ret; 685 } 686 #endif 687 688 bool dm_helpers_dp_write_dsc_enable( 689 struct dc_context *ctx, 690 const struct dc_stream_state *stream, 691 bool enable) 692 { 693 static const uint8_t DSC_DISABLE; 694 static const uint8_t DSC_DECODING = 0x01; 695 static const uint8_t DSC_PASSTHROUGH = 0x02; 696 697 struct amdgpu_dm_connector *aconnector; 698 struct drm_dp_mst_port *port; 699 uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE; 700 uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE; 701 uint8_t ret = 0; 702 703 if (!stream) 704 return false; 705 706 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 707 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 708 709 if (!aconnector->dsc_aux) 710 return false; 711 712 #if defined(CONFIG_DRM_AMD_DC_DCN) 713 // apply w/a to synaptics 714 if (needs_dsc_aux_workaround(aconnector->dc_link) && 715 (aconnector->mst_downstream_port_present.byte & 0x7) != 0x3) 716 return write_dsc_enable_synaptics_non_virtual_dpcd_mst( 717 aconnector->dsc_aux, stream, enable_dsc); 718 #endif 719 720 port = aconnector->mst_output_port; 721 722 if (enable) { 723 if (port->passthrough_aux) { 724 ret = drm_dp_dpcd_write(port->passthrough_aux, 725 DP_DSC_ENABLE, 726 &enable_passthrough, 1); 727 DC_LOG_DC("Sent DSC pass-through enable to virtual dpcd port, ret = %u\n", 728 ret); 729 } 730 731 ret = drm_dp_dpcd_write(aconnector->dsc_aux, 732 DP_DSC_ENABLE, &enable_dsc, 1); 733 DC_LOG_DC("Sent DSC decoding enable to %s port, ret = %u\n", 734 (port->passthrough_aux) ? "remote RX" : 735 "virtual dpcd", 736 ret); 737 } else { 738 ret = drm_dp_dpcd_write(aconnector->dsc_aux, 739 DP_DSC_ENABLE, &enable_dsc, 1); 740 DC_LOG_DC("Sent DSC decoding disable to %s port, ret = %u\n", 741 (port->passthrough_aux) ? "remote RX" : 742 "virtual dpcd", 743 ret); 744 745 if (port->passthrough_aux) { 746 ret = drm_dp_dpcd_write(port->passthrough_aux, 747 DP_DSC_ENABLE, 748 &enable_passthrough, 1); 749 DC_LOG_DC("Sent DSC pass-through disable to virtual dpcd port, ret = %u\n", 750 ret); 751 } 752 } 753 } 754 755 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) { 756 #if defined(CONFIG_DRM_AMD_DC_DCN) 757 if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { 758 #endif 759 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); 760 DC_LOG_DC("Send DSC %s to SST RX\n", enable_dsc ? "enable" : "disable"); 761 #if defined(CONFIG_DRM_AMD_DC_DCN) 762 } else if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { 763 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); 764 DC_LOG_DC("Send DSC %s to DP-HDMI PCON\n", enable_dsc ? "enable" : "disable"); 765 } 766 #endif 767 } 768 769 return ret; 770 } 771 772 bool dm_helpers_is_dp_sink_present(struct dc_link *link) 773 { 774 bool dp_sink_present; 775 struct amdgpu_dm_connector *aconnector = link->priv; 776 777 if (!aconnector) { 778 BUG_ON("Failed to find connector for link!"); 779 return true; 780 } 781 782 mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex); 783 dp_sink_present = dc_link_is_dp_sink_present(link); 784 mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex); 785 return dp_sink_present; 786 } 787 788 enum dc_edid_status dm_helpers_read_local_edid( 789 struct dc_context *ctx, 790 struct dc_link *link, 791 struct dc_sink *sink) 792 { 793 struct amdgpu_dm_connector *aconnector = link->priv; 794 struct drm_connector *connector = &aconnector->base; 795 struct i2c_adapter *ddc; 796 int retry = 3; 797 enum dc_edid_status edid_status; 798 struct edid *edid; 799 800 if (link->aux_mode) 801 ddc = &aconnector->dm_dp_aux.aux.ddc; 802 else 803 ddc = &aconnector->i2c->base; 804 805 /* some dongles read edid incorrectly the first time, 806 * do check sum and retry to make sure read correct edid. 807 */ 808 do { 809 810 edid = drm_get_edid(&aconnector->base, ddc); 811 812 /* DP Compliance Test 4.2.2.6 */ 813 if (link->aux_mode && connector->edid_corrupt) 814 drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum); 815 816 if (!edid && connector->edid_corrupt) { 817 connector->edid_corrupt = false; 818 return EDID_BAD_CHECKSUM; 819 } 820 821 if (!edid) 822 return EDID_NO_RESPONSE; 823 824 sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1); 825 memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length); 826 827 /* We don't need the original edid anymore */ 828 kfree(edid); 829 830 edid_status = dm_helpers_parse_edid_caps( 831 link, 832 &sink->dc_edid, 833 &sink->edid_caps); 834 835 } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0); 836 837 if (edid_status != EDID_OK) 838 DRM_ERROR("EDID err: %d, on connector: %s", 839 edid_status, 840 aconnector->base.name); 841 842 /* DP Compliance Test 4.2.2.3 */ 843 if (link->aux_mode) 844 drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, sink->dc_edid.raw_edid[sink->dc_edid.length-1]); 845 846 return edid_status; 847 } 848 int dm_helper_dmub_aux_transfer_sync( 849 struct dc_context *ctx, 850 const struct dc_link *link, 851 struct aux_payload *payload, 852 enum aux_return_code_type *operation_result) 853 { 854 return amdgpu_dm_process_dmub_aux_transfer_sync(ctx, link->link_index, payload, 855 operation_result); 856 } 857 858 int dm_helpers_dmub_set_config_sync(struct dc_context *ctx, 859 const struct dc_link *link, 860 struct set_config_cmd_payload *payload, 861 enum set_config_status *operation_result) 862 { 863 return amdgpu_dm_process_dmub_set_config_sync(ctx, link->link_index, payload, 864 operation_result); 865 } 866 867 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks) 868 { 869 /* TODO: something */ 870 } 871 872 void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us) 873 { 874 // TODO: 875 //amdgpu_device_gpu_recover(dc_context->driver-context, NULL); 876 } 877 878 void dm_helpers_init_panel_settings( 879 struct dc_context *ctx, 880 struct dc_panel_config *panel_config, 881 struct dc_sink *sink) 882 { 883 // Extra Panel Power Sequence 884 panel_config->pps.extra_t3_ms = sink->edid_caps.panel_patch.extra_t3_ms; 885 panel_config->pps.extra_t7_ms = sink->edid_caps.panel_patch.extra_t7_ms; 886 panel_config->pps.extra_delay_backlight_off = sink->edid_caps.panel_patch.extra_delay_backlight_off; 887 panel_config->pps.extra_post_t7_ms = 0; 888 panel_config->pps.extra_pre_t11_ms = 0; 889 panel_config->pps.extra_t12_ms = sink->edid_caps.panel_patch.extra_t12_ms; 890 panel_config->pps.extra_post_OUI_ms = 0; 891 // Feature DSC 892 panel_config->dsc.disable_dsc_edp = false; 893 panel_config->dsc.force_dsc_edp_policy = 0; 894 } 895 896 void dm_helpers_override_panel_settings( 897 struct dc_context *ctx, 898 struct dc_panel_config *panel_config) 899 { 900 // Feature DSC 901 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) { 902 panel_config->dsc.disable_dsc_edp = true; 903 } 904 } 905 906 void *dm_helpers_allocate_gpu_mem( 907 struct dc_context *ctx, 908 enum dc_gpu_mem_alloc_type type, 909 size_t size, 910 long long *addr) 911 { 912 struct amdgpu_device *adev = ctx->driver_context; 913 struct dal_allocation *da; 914 u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ? 915 AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM; 916 int ret; 917 918 da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL); 919 if (!da) 920 return NULL; 921 922 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 923 domain, &da->bo, 924 &da->gpu_addr, &da->cpu_ptr); 925 926 *addr = da->gpu_addr; 927 928 if (ret) { 929 kfree(da); 930 return NULL; 931 } 932 933 /* add da to list in dm */ 934 list_add(&da->list, &adev->dm.da_list); 935 936 return da->cpu_ptr; 937 } 938 939 void dm_helpers_free_gpu_mem( 940 struct dc_context *ctx, 941 enum dc_gpu_mem_alloc_type type, 942 void *pvMem) 943 { 944 struct amdgpu_device *adev = ctx->driver_context; 945 struct dal_allocation *da; 946 947 /* walk the da list in DM */ 948 list_for_each_entry(da, &adev->dm.da_list, list) { 949 if (pvMem == da->cpu_ptr) { 950 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); 951 list_del(&da->list); 952 kfree(da); 953 break; 954 } 955 } 956 } 957 958 bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable) 959 { 960 enum dc_irq_source irq_source; 961 bool ret; 962 963 irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX; 964 965 ret = dc_interrupt_set(ctx->dc, irq_source, enable); 966 967 DRM_DEBUG_DRIVER("Dmub trace irq %sabling: r=%d\n", 968 enable ? "en" : "dis", ret); 969 return ret; 970 } 971 972 void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream) 973 { 974 /* TODO: virtual DPCD */ 975 struct dc_link *link = stream->link; 976 union down_spread_ctrl old_downspread; 977 union down_spread_ctrl new_downspread; 978 979 if (link->aux_access_disabled) 980 return; 981 982 if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL, 983 &old_downspread.raw, 984 sizeof(old_downspread))) 985 return; 986 987 new_downspread.raw = old_downspread.raw; 988 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 989 (stream->ignore_msa_timing_param) ? 1 : 0; 990 991 if (new_downspread.raw != old_downspread.raw) 992 dm_helpers_dp_write_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL, 993 &new_downspread.raw, 994 sizeof(new_downspread)); 995 } 996 997 bool dm_helpers_dp_handle_test_pattern_request( 998 struct dc_context *ctx, 999 const struct dc_link *link, 1000 union link_test_pattern dpcd_test_pattern, 1001 union test_misc dpcd_test_params) 1002 { 1003 enum dp_test_pattern test_pattern; 1004 enum dp_test_pattern_color_space test_pattern_color_space = 1005 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED; 1006 enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED; 1007 enum dc_pixel_encoding requestPixelEncoding = PIXEL_ENCODING_UNDEFINED; 1008 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; 1009 struct pipe_ctx *pipe_ctx = NULL; 1010 struct amdgpu_dm_connector *aconnector = link->priv; 1011 int i; 1012 1013 for (i = 0; i < MAX_PIPES; i++) { 1014 if (pipes[i].stream == NULL) 1015 continue; 1016 1017 if (pipes[i].stream->link == link && !pipes[i].top_pipe && 1018 !pipes[i].prev_odm_pipe) { 1019 pipe_ctx = &pipes[i]; 1020 break; 1021 } 1022 } 1023 1024 if (pipe_ctx == NULL) 1025 return false; 1026 1027 switch (dpcd_test_pattern.bits.PATTERN) { 1028 case LINK_TEST_PATTERN_COLOR_RAMP: 1029 test_pattern = DP_TEST_PATTERN_COLOR_RAMP; 1030 break; 1031 case LINK_TEST_PATTERN_VERTICAL_BARS: 1032 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS; 1033 break; /* black and white */ 1034 case LINK_TEST_PATTERN_COLOR_SQUARES: 1035 test_pattern = (dpcd_test_params.bits.DYN_RANGE == 1036 TEST_DYN_RANGE_VESA ? 1037 DP_TEST_PATTERN_COLOR_SQUARES : 1038 DP_TEST_PATTERN_COLOR_SQUARES_CEA); 1039 break; 1040 default: 1041 test_pattern = DP_TEST_PATTERN_VIDEO_MODE; 1042 break; 1043 } 1044 1045 if (dpcd_test_params.bits.CLR_FORMAT == 0) 1046 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB; 1047 else 1048 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ? 1049 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 : 1050 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601; 1051 1052 switch (dpcd_test_params.bits.BPC) { 1053 case 0: // 6 bits 1054 requestColorDepth = COLOR_DEPTH_666; 1055 break; 1056 case 1: // 8 bits 1057 requestColorDepth = COLOR_DEPTH_888; 1058 break; 1059 case 2: // 10 bits 1060 requestColorDepth = COLOR_DEPTH_101010; 1061 break; 1062 case 3: // 12 bits 1063 requestColorDepth = COLOR_DEPTH_121212; 1064 break; 1065 default: 1066 break; 1067 } 1068 1069 switch (dpcd_test_params.bits.CLR_FORMAT) { 1070 case 0: 1071 requestPixelEncoding = PIXEL_ENCODING_RGB; 1072 break; 1073 case 1: 1074 requestPixelEncoding = PIXEL_ENCODING_YCBCR422; 1075 break; 1076 case 2: 1077 requestPixelEncoding = PIXEL_ENCODING_YCBCR444; 1078 break; 1079 default: 1080 requestPixelEncoding = PIXEL_ENCODING_RGB; 1081 break; 1082 } 1083 1084 if ((requestColorDepth != COLOR_DEPTH_UNDEFINED 1085 && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) 1086 || (requestPixelEncoding != PIXEL_ENCODING_UNDEFINED 1087 && pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) { 1088 DC_LOG_DEBUG("%s: original bpc %d pix encoding %d, changing to %d %d\n", 1089 __func__, 1090 pipe_ctx->stream->timing.display_color_depth, 1091 pipe_ctx->stream->timing.pixel_encoding, 1092 requestColorDepth, 1093 requestPixelEncoding); 1094 pipe_ctx->stream->timing.display_color_depth = requestColorDepth; 1095 pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding; 1096 1097 dp_update_dsc_config(pipe_ctx); 1098 1099 aconnector->timing_changed = true; 1100 /* store current timing */ 1101 if (aconnector->timing_requested) 1102 *aconnector->timing_requested = pipe_ctx->stream->timing; 1103 else 1104 DC_LOG_ERROR("%s: timing storage failed\n", __func__); 1105 1106 } 1107 1108 dc_link_dp_set_test_pattern( 1109 (struct dc_link *) link, 1110 test_pattern, 1111 test_pattern_color_space, 1112 NULL, 1113 NULL, 1114 0); 1115 1116 return false; 1117 } 1118 1119 void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz) 1120 { 1121 // TODO 1122 } 1123 1124 void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable) 1125 { 1126 /* TODO: add periodic detection implementation */ 1127 } 1128 1129 void dm_helpers_dp_mst_update_branch_bandwidth( 1130 struct dc_context *ctx, 1131 struct dc_link *link) 1132 { 1133 // TODO 1134 } 1135 1136