1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string.h> 27 #include <linux/acpi.h> 28 #include <linux/version.h> 29 #include <linux/i2c.h> 30 31 #include <drm/drm_probe_helper.h> 32 #include <drm/amdgpu_drm.h> 33 #include <drm/drm_edid.h> 34 35 #include "dm_services.h" 36 #include "amdgpu.h" 37 #include "dc.h" 38 #include "amdgpu_dm.h" 39 #include "amdgpu_dm_irq.h" 40 #include "amdgpu_dm_mst_types.h" 41 42 #include "dm_helpers.h" 43 44 /* dm_helpers_parse_edid_caps 45 * 46 * Parse edid caps 47 * 48 * @edid: [in] pointer to edid 49 * edid_caps: [in] pointer to edid caps 50 * @return 51 * void 52 * */ 53 enum dc_edid_status dm_helpers_parse_edid_caps( 54 struct dc_context *ctx, 55 const struct dc_edid *edid, 56 struct dc_edid_caps *edid_caps) 57 { 58 struct edid *edid_buf = (struct edid *) edid->raw_edid; 59 struct cea_sad *sads; 60 int sad_count = -1; 61 int sadb_count = -1; 62 int i = 0; 63 int j = 0; 64 uint8_t *sadb = NULL; 65 66 enum dc_edid_status result = EDID_OK; 67 68 if (!edid_caps || !edid) 69 return EDID_BAD_INPUT; 70 71 if (!drm_edid_is_valid(edid_buf)) 72 result = EDID_BAD_CHECKSUM; 73 74 edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] | 75 ((uint16_t) edid_buf->mfg_id[1])<<8; 76 edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] | 77 ((uint16_t) edid_buf->prod_code[1])<<8; 78 edid_caps->serial_number = edid_buf->serial; 79 edid_caps->manufacture_week = edid_buf->mfg_week; 80 edid_caps->manufacture_year = edid_buf->mfg_year; 81 82 /* One of the four detailed_timings stores the monitor name. It's 83 * stored in an array of length 13. */ 84 for (i = 0; i < 4; i++) { 85 if (edid_buf->detailed_timings[i].data.other_data.type == 0xfc) { 86 while (j < 13 && edid_buf->detailed_timings[i].data.other_data.data.str.str[j]) { 87 if (edid_buf->detailed_timings[i].data.other_data.data.str.str[j] == '\n') 88 break; 89 90 edid_caps->display_name[j] = 91 edid_buf->detailed_timings[i].data.other_data.data.str.str[j]; 92 j++; 93 } 94 } 95 } 96 97 edid_caps->edid_hdmi = drm_detect_hdmi_monitor( 98 (struct edid *) edid->raw_edid); 99 100 sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads); 101 if (sad_count <= 0) 102 return result; 103 104 edid_caps->audio_mode_count = sad_count < DC_MAX_AUDIO_DESC_COUNT ? sad_count : DC_MAX_AUDIO_DESC_COUNT; 105 for (i = 0; i < edid_caps->audio_mode_count; ++i) { 106 struct cea_sad *sad = &sads[i]; 107 108 edid_caps->audio_modes[i].format_code = sad->format; 109 edid_caps->audio_modes[i].channel_count = sad->channels + 1; 110 edid_caps->audio_modes[i].sample_rate = sad->freq; 111 edid_caps->audio_modes[i].sample_size = sad->byte2; 112 } 113 114 sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb); 115 116 if (sadb_count < 0) { 117 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count); 118 sadb_count = 0; 119 } 120 121 if (sadb_count) 122 edid_caps->speaker_flags = sadb[0]; 123 else 124 edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION; 125 126 kfree(sads); 127 kfree(sadb); 128 129 return result; 130 } 131 132 static void get_payload_table( 133 struct amdgpu_dm_connector *aconnector, 134 struct dp_mst_stream_allocation_table *proposed_table) 135 { 136 int i; 137 struct drm_dp_mst_topology_mgr *mst_mgr = 138 &aconnector->mst_port->mst_mgr; 139 140 mutex_lock(&mst_mgr->payload_lock); 141 142 proposed_table->stream_count = 0; 143 144 /* number of active streams */ 145 for (i = 0; i < mst_mgr->max_payloads; i++) { 146 if (mst_mgr->payloads[i].num_slots == 0) 147 break; /* end of vcp_id table */ 148 149 ASSERT(mst_mgr->payloads[i].payload_state != 150 DP_PAYLOAD_DELETE_LOCAL); 151 152 if (mst_mgr->payloads[i].payload_state == DP_PAYLOAD_LOCAL || 153 mst_mgr->payloads[i].payload_state == 154 DP_PAYLOAD_REMOTE) { 155 156 struct dp_mst_stream_allocation *sa = 157 &proposed_table->stream_allocations[ 158 proposed_table->stream_count]; 159 160 sa->slot_count = mst_mgr->payloads[i].num_slots; 161 sa->vcp_id = mst_mgr->proposed_vcpis[i]->vcpi; 162 proposed_table->stream_count++; 163 } 164 } 165 166 mutex_unlock(&mst_mgr->payload_lock); 167 } 168 169 void dm_helpers_dp_update_branch_info( 170 struct dc_context *ctx, 171 const struct dc_link *link) 172 {} 173 174 /* 175 * Writes payload allocation table in immediate downstream device. 176 */ 177 bool dm_helpers_dp_mst_write_payload_allocation_table( 178 struct dc_context *ctx, 179 const struct dc_stream_state *stream, 180 struct dp_mst_stream_allocation_table *proposed_table, 181 bool enable) 182 { 183 struct amdgpu_dm_connector *aconnector; 184 struct dm_connector_state *dm_conn_state; 185 struct drm_dp_mst_topology_mgr *mst_mgr; 186 struct drm_dp_mst_port *mst_port; 187 bool ret; 188 189 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 190 /* Accessing the connector state is required for vcpi_slots allocation 191 * and directly relies on behaviour in commit check 192 * that blocks before commit guaranteeing that the state 193 * is not gonna be swapped while still in use in commit tail */ 194 195 if (!aconnector || !aconnector->mst_port) 196 return false; 197 198 dm_conn_state = to_dm_connector_state(aconnector->base.state); 199 200 mst_mgr = &aconnector->mst_port->mst_mgr; 201 202 if (!mst_mgr->mst_state) 203 return false; 204 205 mst_port = aconnector->port; 206 207 if (enable) { 208 209 ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, 210 dm_conn_state->pbn, 211 dm_conn_state->vcpi_slots); 212 if (!ret) 213 return false; 214 215 } else { 216 drm_dp_mst_reset_vcpi_slots(mst_mgr, mst_port); 217 } 218 219 /* It's OK for this to fail */ 220 drm_dp_update_payload_part1(mst_mgr); 221 222 /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or 223 * AUX message. The sequence is slot 1-63 allocated sequence for each 224 * stream. AMD ASIC stream slot allocation should follow the same 225 * sequence. copy DRM MST allocation to dc */ 226 227 get_payload_table(aconnector, proposed_table); 228 229 return true; 230 } 231 232 /* 233 * poll pending down reply 234 */ 235 void dm_helpers_dp_mst_poll_pending_down_reply( 236 struct dc_context *ctx, 237 const struct dc_link *link) 238 {} 239 240 /* 241 * Clear payload allocation table before enable MST DP link. 242 */ 243 void dm_helpers_dp_mst_clear_payload_allocation_table( 244 struct dc_context *ctx, 245 const struct dc_link *link) 246 {} 247 248 /* 249 * Polls for ACT (allocation change trigger) handled and sends 250 * ALLOCATE_PAYLOAD message. 251 */ 252 enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger( 253 struct dc_context *ctx, 254 const struct dc_stream_state *stream) 255 { 256 struct amdgpu_dm_connector *aconnector; 257 struct drm_dp_mst_topology_mgr *mst_mgr; 258 int ret; 259 260 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 261 262 if (!aconnector || !aconnector->mst_port) 263 return ACT_FAILED; 264 265 mst_mgr = &aconnector->mst_port->mst_mgr; 266 267 if (!mst_mgr->mst_state) 268 return ACT_FAILED; 269 270 ret = drm_dp_check_act_status(mst_mgr); 271 272 if (ret) 273 return ACT_FAILED; 274 275 return ACT_SUCCESS; 276 } 277 278 bool dm_helpers_dp_mst_send_payload_allocation( 279 struct dc_context *ctx, 280 const struct dc_stream_state *stream, 281 bool enable) 282 { 283 struct amdgpu_dm_connector *aconnector; 284 struct drm_dp_mst_topology_mgr *mst_mgr; 285 struct drm_dp_mst_port *mst_port; 286 287 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 288 289 if (!aconnector || !aconnector->mst_port) 290 return false; 291 292 mst_port = aconnector->port; 293 294 mst_mgr = &aconnector->mst_port->mst_mgr; 295 296 if (!mst_mgr->mst_state) 297 return false; 298 299 /* It's OK for this to fail */ 300 drm_dp_update_payload_part2(mst_mgr); 301 302 if (!enable) 303 drm_dp_mst_deallocate_vcpi(mst_mgr, mst_port); 304 305 return true; 306 } 307 308 void dm_dtn_log_begin(struct dc_context *ctx, 309 struct dc_log_buffer_ctx *log_ctx) 310 { 311 static const char msg[] = "[dtn begin]\n"; 312 313 if (!log_ctx) { 314 pr_info("%s", msg); 315 return; 316 } 317 318 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); 319 } 320 321 __printf(3, 4) 322 void dm_dtn_log_append_v(struct dc_context *ctx, 323 struct dc_log_buffer_ctx *log_ctx, 324 const char *msg, ...) 325 { 326 va_list args; 327 size_t total; 328 int n; 329 330 if (!log_ctx) { 331 /* No context, redirect to dmesg. */ 332 struct va_format vaf; 333 334 vaf.fmt = msg; 335 vaf.va = &args; 336 337 va_start(args, msg); 338 pr_info("%pV", &vaf); 339 va_end(args); 340 341 return; 342 } 343 344 /* Measure the output. */ 345 va_start(args, msg); 346 n = vsnprintf(NULL, 0, msg, args); 347 va_end(args); 348 349 if (n <= 0) 350 return; 351 352 /* Reallocate the string buffer as needed. */ 353 total = log_ctx->pos + n + 1; 354 355 if (total > log_ctx->size) { 356 char *buf = (char *)kvcalloc(total, sizeof(char), GFP_KERNEL); 357 358 if (buf) { 359 memcpy(buf, log_ctx->buf, log_ctx->pos); 360 kfree(log_ctx->buf); 361 362 log_ctx->buf = buf; 363 log_ctx->size = total; 364 } 365 } 366 367 if (!log_ctx->buf) 368 return; 369 370 /* Write the formatted string to the log buffer. */ 371 va_start(args, msg); 372 n = vscnprintf( 373 log_ctx->buf + log_ctx->pos, 374 log_ctx->size - log_ctx->pos, 375 msg, 376 args); 377 va_end(args); 378 379 if (n > 0) 380 log_ctx->pos += n; 381 } 382 383 void dm_dtn_log_end(struct dc_context *ctx, 384 struct dc_log_buffer_ctx *log_ctx) 385 { 386 static const char msg[] = "[dtn end]\n"; 387 388 if (!log_ctx) { 389 pr_info("%s", msg); 390 return; 391 } 392 393 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); 394 } 395 396 bool dm_helpers_dp_mst_start_top_mgr( 397 struct dc_context *ctx, 398 const struct dc_link *link, 399 bool boot) 400 { 401 struct amdgpu_dm_connector *aconnector = link->priv; 402 403 if (!aconnector) { 404 DRM_ERROR("Failed to find connector for link!"); 405 return false; 406 } 407 408 if (boot) { 409 DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n", 410 aconnector, aconnector->base.base.id); 411 return true; 412 } 413 414 DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n", 415 aconnector, aconnector->base.base.id); 416 417 return (drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true) == 0); 418 } 419 420 void dm_helpers_dp_mst_stop_top_mgr( 421 struct dc_context *ctx, 422 struct dc_link *link) 423 { 424 struct amdgpu_dm_connector *aconnector = link->priv; 425 uint8_t i; 426 427 if (!aconnector) { 428 DRM_ERROR("Failed to find connector for link!"); 429 return; 430 } 431 432 DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n", 433 aconnector, aconnector->base.base.id); 434 435 if (aconnector->mst_mgr.mst_state == true) { 436 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false); 437 438 for (i = 0; i < MAX_SINKS_PER_LINK; i++) { 439 if (link->remote_sinks[i] == NULL) 440 continue; 441 442 if (link->remote_sinks[i]->sink_signal == 443 SIGNAL_TYPE_DISPLAY_PORT_MST) { 444 dc_link_remove_remote_sink(link, link->remote_sinks[i]); 445 446 if (aconnector->dc_sink) { 447 dc_sink_release(aconnector->dc_sink); 448 aconnector->dc_sink = NULL; 449 aconnector->dc_link->cur_link_settings.lane_count = 0; 450 } 451 } 452 } 453 } 454 } 455 456 bool dm_helpers_dp_read_dpcd( 457 struct dc_context *ctx, 458 const struct dc_link *link, 459 uint32_t address, 460 uint8_t *data, 461 uint32_t size) 462 { 463 464 struct amdgpu_dm_connector *aconnector = link->priv; 465 466 if (!aconnector) { 467 DC_LOG_DC("Failed to find connector for link!\n"); 468 return false; 469 } 470 471 return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address, 472 data, size) > 0; 473 } 474 475 bool dm_helpers_dp_write_dpcd( 476 struct dc_context *ctx, 477 const struct dc_link *link, 478 uint32_t address, 479 const uint8_t *data, 480 uint32_t size) 481 { 482 struct amdgpu_dm_connector *aconnector = link->priv; 483 484 if (!aconnector) { 485 DRM_ERROR("Failed to find connector for link!"); 486 return false; 487 } 488 489 return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux, 490 address, (uint8_t *)data, size) > 0; 491 } 492 493 bool dm_helpers_submit_i2c( 494 struct dc_context *ctx, 495 const struct dc_link *link, 496 struct i2c_command *cmd) 497 { 498 struct amdgpu_dm_connector *aconnector = link->priv; 499 struct i2c_msg *msgs; 500 int i = 0; 501 int num = cmd->number_of_payloads; 502 bool result; 503 504 if (!aconnector) { 505 DRM_ERROR("Failed to find connector for link!"); 506 return false; 507 } 508 509 msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL); 510 511 if (!msgs) 512 return false; 513 514 for (i = 0; i < num; i++) { 515 msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD; 516 msgs[i].addr = cmd->payloads[i].address; 517 msgs[i].len = cmd->payloads[i].length; 518 msgs[i].buf = cmd->payloads[i].data; 519 } 520 521 result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num; 522 523 kfree(msgs); 524 525 return result; 526 } 527 bool dm_helpers_dp_write_dsc_enable( 528 struct dc_context *ctx, 529 const struct dc_stream_state *stream, 530 bool enable 531 ) 532 { 533 uint8_t enable_dsc = enable ? 1 : 0; 534 struct amdgpu_dm_connector *aconnector; 535 536 if (!stream) 537 return false; 538 539 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 540 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 541 542 if (!aconnector->dsc_aux) 543 return false; 544 545 return (drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, &enable_dsc, 1) >= 0); 546 } 547 548 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT) 549 return dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); 550 551 return false; 552 } 553 554 bool dm_helpers_is_dp_sink_present(struct dc_link *link) 555 { 556 bool dp_sink_present; 557 struct amdgpu_dm_connector *aconnector = link->priv; 558 559 if (!aconnector) { 560 BUG_ON("Failed to find connector for link!"); 561 return true; 562 } 563 564 mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex); 565 dp_sink_present = dc_link_is_dp_sink_present(link); 566 mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex); 567 return dp_sink_present; 568 } 569 570 enum dc_edid_status dm_helpers_read_local_edid( 571 struct dc_context *ctx, 572 struct dc_link *link, 573 struct dc_sink *sink) 574 { 575 struct amdgpu_dm_connector *aconnector = link->priv; 576 struct drm_connector *connector = &aconnector->base; 577 struct i2c_adapter *ddc; 578 int retry = 3; 579 enum dc_edid_status edid_status; 580 struct edid *edid; 581 582 if (link->aux_mode) 583 ddc = &aconnector->dm_dp_aux.aux.ddc; 584 else 585 ddc = &aconnector->i2c->base; 586 587 /* some dongles read edid incorrectly the first time, 588 * do check sum and retry to make sure read correct edid. 589 */ 590 do { 591 592 edid = drm_get_edid(&aconnector->base, ddc); 593 594 /* DP Compliance Test 4.2.2.6 */ 595 if (link->aux_mode && connector->edid_corrupt) 596 drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum); 597 598 if (!edid && connector->edid_corrupt) { 599 connector->edid_corrupt = false; 600 return EDID_BAD_CHECKSUM; 601 } 602 603 if (!edid) 604 return EDID_NO_RESPONSE; 605 606 sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1); 607 memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length); 608 609 /* We don't need the original edid anymore */ 610 kfree(edid); 611 612 /* connector->display_info will be parsed from EDID and saved 613 * into drm_connector->display_info from edid by call stack 614 * below: 615 * drm_parse_ycbcr420_deep_color_info 616 * drm_parse_hdmi_forum_vsdb 617 * drm_parse_cea_ext 618 * drm_add_display_info 619 * drm_connector_update_edid_property 620 * 621 * drm_connector->display_info will be used by amdgpu_dm funcs, 622 * like fill_stream_properties_from_drm_display_mode 623 */ 624 amdgpu_dm_update_connector_after_detect(aconnector); 625 626 edid_status = dm_helpers_parse_edid_caps( 627 ctx, 628 &sink->dc_edid, 629 &sink->edid_caps); 630 631 } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0); 632 633 if (edid_status != EDID_OK) 634 DRM_ERROR("EDID err: %d, on connector: %s", 635 edid_status, 636 aconnector->base.name); 637 638 /* DP Compliance Test 4.2.2.3 */ 639 if (link->aux_mode) 640 drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, sink->dc_edid.raw_edid[sink->dc_edid.length-1]); 641 642 return edid_status; 643 } 644 645 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks) 646 { 647 /* TODO: something */ 648 } 649 650 void *dm_helpers_allocate_gpu_mem( 651 struct dc_context *ctx, 652 enum dc_gpu_mem_alloc_type type, 653 size_t size, 654 long long *addr) 655 { 656 // TODO 657 return NULL; 658 } 659 660 void dm_helpers_free_gpu_mem( 661 struct dc_context *ctx, 662 enum dc_gpu_mem_alloc_type type, 663 void *pvMem) 664 { 665 // TODO 666 } 667