1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string.h> 27 #include <linux/acpi.h> 28 #include <linux/i2c.h> 29 30 #include <drm/drm_atomic.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/amdgpu_drm.h> 33 #include <drm/drm_edid.h> 34 35 #include "dm_services.h" 36 #include "amdgpu.h" 37 #include "dc.h" 38 #include "amdgpu_dm.h" 39 #include "amdgpu_dm_irq.h" 40 #include "amdgpu_dm_mst_types.h" 41 #include "dpcd_defs.h" 42 #include "dc/inc/core_types.h" 43 44 #include "dm_helpers.h" 45 #include "ddc_service_types.h" 46 47 /* dm_helpers_parse_edid_caps 48 * 49 * Parse edid caps 50 * 51 * @edid: [in] pointer to edid 52 * edid_caps: [in] pointer to edid caps 53 * @return 54 * void 55 * */ 56 enum dc_edid_status dm_helpers_parse_edid_caps( 57 struct dc_link *link, 58 const struct dc_edid *edid, 59 struct dc_edid_caps *edid_caps) 60 { 61 struct amdgpu_dm_connector *aconnector = link->priv; 62 struct drm_connector *connector = &aconnector->base; 63 struct edid *edid_buf = edid ? (struct edid *) edid->raw_edid : NULL; 64 struct cea_sad *sads; 65 int sad_count = -1; 66 int sadb_count = -1; 67 int i = 0; 68 uint8_t *sadb = NULL; 69 70 enum dc_edid_status result = EDID_OK; 71 72 if (!edid_caps || !edid) 73 return EDID_BAD_INPUT; 74 75 if (!drm_edid_is_valid(edid_buf)) 76 result = EDID_BAD_CHECKSUM; 77 78 edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] | 79 ((uint16_t) edid_buf->mfg_id[1])<<8; 80 edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] | 81 ((uint16_t) edid_buf->prod_code[1])<<8; 82 edid_caps->serial_number = edid_buf->serial; 83 edid_caps->manufacture_week = edid_buf->mfg_week; 84 edid_caps->manufacture_year = edid_buf->mfg_year; 85 86 drm_edid_get_monitor_name(edid_buf, 87 edid_caps->display_name, 88 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 89 90 edid_caps->edid_hdmi = connector->display_info.is_hdmi; 91 92 sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads); 93 if (sad_count <= 0) 94 return result; 95 96 edid_caps->audio_mode_count = sad_count < DC_MAX_AUDIO_DESC_COUNT ? sad_count : DC_MAX_AUDIO_DESC_COUNT; 97 for (i = 0; i < edid_caps->audio_mode_count; ++i) { 98 struct cea_sad *sad = &sads[i]; 99 100 edid_caps->audio_modes[i].format_code = sad->format; 101 edid_caps->audio_modes[i].channel_count = sad->channels + 1; 102 edid_caps->audio_modes[i].sample_rate = sad->freq; 103 edid_caps->audio_modes[i].sample_size = sad->byte2; 104 } 105 106 sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb); 107 108 if (sadb_count < 0) { 109 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count); 110 sadb_count = 0; 111 } 112 113 if (sadb_count) 114 edid_caps->speaker_flags = sadb[0]; 115 else 116 edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION; 117 118 kfree(sads); 119 kfree(sadb); 120 121 return result; 122 } 123 124 static void 125 fill_dc_mst_payload_table_from_drm(struct dc_link *link, 126 bool enable, 127 struct drm_dp_mst_atomic_payload *target_payload, 128 struct dc_dp_mst_stream_allocation_table *table) 129 { 130 struct dc_dp_mst_stream_allocation_table new_table = { 0 }; 131 struct dc_dp_mst_stream_allocation *sa; 132 struct link_mst_stream_allocation_table copy_of_link_table = 133 link->mst_stream_alloc_table; 134 135 int i; 136 int current_hw_table_stream_cnt = copy_of_link_table.stream_count; 137 struct link_mst_stream_allocation *dc_alloc; 138 139 /* TODO: refactor to set link->mst_stream_alloc_table directly if possible.*/ 140 if (enable) { 141 dc_alloc = 142 ©_of_link_table.stream_allocations[current_hw_table_stream_cnt]; 143 dc_alloc->vcp_id = target_payload->vcpi; 144 dc_alloc->slot_count = target_payload->time_slots; 145 } else { 146 for (i = 0; i < copy_of_link_table.stream_count; i++) { 147 dc_alloc = 148 ©_of_link_table.stream_allocations[i]; 149 150 if (dc_alloc->vcp_id == target_payload->vcpi) { 151 dc_alloc->vcp_id = 0; 152 dc_alloc->slot_count = 0; 153 break; 154 } 155 } 156 ASSERT(i != copy_of_link_table.stream_count); 157 } 158 159 /* Fill payload info*/ 160 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 161 dc_alloc = 162 ©_of_link_table.stream_allocations[i]; 163 if (dc_alloc->vcp_id > 0 && dc_alloc->slot_count > 0) { 164 sa = &new_table.stream_allocations[new_table.stream_count]; 165 sa->slot_count = dc_alloc->slot_count; 166 sa->vcp_id = dc_alloc->vcp_id; 167 new_table.stream_count++; 168 } 169 } 170 171 /* Overwrite the old table */ 172 *table = new_table; 173 } 174 175 void dm_helpers_dp_update_branch_info( 176 struct dc_context *ctx, 177 const struct dc_link *link) 178 {} 179 180 static void dm_helpers_construct_old_payload( 181 struct dc_link *link, 182 int pbn_per_slot, 183 struct drm_dp_mst_atomic_payload *new_payload, 184 struct drm_dp_mst_atomic_payload *old_payload) 185 { 186 struct link_mst_stream_allocation_table current_link_table = 187 link->mst_stream_alloc_table; 188 struct link_mst_stream_allocation *dc_alloc; 189 int i; 190 191 *old_payload = *new_payload; 192 193 /* Set correct time_slots/PBN of old payload. 194 * other fields (delete & dsc_enabled) in 195 * struct drm_dp_mst_atomic_payload are don't care fields 196 * while calling drm_dp_remove_payload() 197 */ 198 for (i = 0; i < current_link_table.stream_count; i++) { 199 dc_alloc = 200 ¤t_link_table.stream_allocations[i]; 201 202 if (dc_alloc->vcp_id == new_payload->vcpi) { 203 old_payload->time_slots = dc_alloc->slot_count; 204 old_payload->pbn = dc_alloc->slot_count * pbn_per_slot; 205 break; 206 } 207 } 208 209 /* make sure there is an old payload*/ 210 ASSERT(i != current_link_table.stream_count); 211 212 } 213 214 /* 215 * Writes payload allocation table in immediate downstream device. 216 */ 217 bool dm_helpers_dp_mst_write_payload_allocation_table( 218 struct dc_context *ctx, 219 const struct dc_stream_state *stream, 220 struct dc_dp_mst_stream_allocation_table *proposed_table, 221 bool enable) 222 { 223 struct amdgpu_dm_connector *aconnector; 224 struct drm_dp_mst_topology_state *mst_state; 225 struct drm_dp_mst_atomic_payload *target_payload, *new_payload, old_payload; 226 struct drm_dp_mst_topology_mgr *mst_mgr; 227 228 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 229 /* Accessing the connector state is required for vcpi_slots allocation 230 * and directly relies on behaviour in commit check 231 * that blocks before commit guaranteeing that the state 232 * is not gonna be swapped while still in use in commit tail */ 233 234 if (!aconnector || !aconnector->mst_root) 235 return false; 236 237 mst_mgr = &aconnector->mst_root->mst_mgr; 238 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); 239 240 /* It's OK for this to fail */ 241 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); 242 243 if (enable) { 244 target_payload = new_payload; 245 246 drm_dp_add_payload_part1(mst_mgr, mst_state, new_payload); 247 } else { 248 /* construct old payload by VCPI*/ 249 dm_helpers_construct_old_payload(stream->link, mst_state->pbn_div, 250 new_payload, &old_payload); 251 target_payload = &old_payload; 252 253 drm_dp_remove_payload(mst_mgr, mst_state, &old_payload, new_payload); 254 } 255 256 /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or 257 * AUX message. The sequence is slot 1-63 allocated sequence for each 258 * stream. AMD ASIC stream slot allocation should follow the same 259 * sequence. copy DRM MST allocation to dc */ 260 fill_dc_mst_payload_table_from_drm(stream->link, enable, target_payload, proposed_table); 261 262 return true; 263 } 264 265 /* 266 * poll pending down reply 267 */ 268 void dm_helpers_dp_mst_poll_pending_down_reply( 269 struct dc_context *ctx, 270 const struct dc_link *link) 271 {} 272 273 /* 274 * Clear payload allocation table before enable MST DP link. 275 */ 276 void dm_helpers_dp_mst_clear_payload_allocation_table( 277 struct dc_context *ctx, 278 const struct dc_link *link) 279 {} 280 281 /* 282 * Polls for ACT (allocation change trigger) handled and sends 283 * ALLOCATE_PAYLOAD message. 284 */ 285 enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger( 286 struct dc_context *ctx, 287 const struct dc_stream_state *stream) 288 { 289 struct amdgpu_dm_connector *aconnector; 290 struct drm_dp_mst_topology_mgr *mst_mgr; 291 int ret; 292 293 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 294 295 if (!aconnector || !aconnector->mst_root) 296 return ACT_FAILED; 297 298 mst_mgr = &aconnector->mst_root->mst_mgr; 299 300 if (!mst_mgr->mst_state) 301 return ACT_FAILED; 302 303 ret = drm_dp_check_act_status(mst_mgr); 304 305 if (ret) 306 return ACT_FAILED; 307 308 return ACT_SUCCESS; 309 } 310 311 bool dm_helpers_dp_mst_send_payload_allocation( 312 struct dc_context *ctx, 313 const struct dc_stream_state *stream, 314 bool enable) 315 { 316 struct amdgpu_dm_connector *aconnector; 317 struct drm_dp_mst_topology_state *mst_state; 318 struct drm_dp_mst_topology_mgr *mst_mgr; 319 struct drm_dp_mst_atomic_payload *payload; 320 enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD; 321 enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD; 322 int ret = 0; 323 324 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 325 326 if (!aconnector || !aconnector->mst_root) 327 return false; 328 329 mst_mgr = &aconnector->mst_root->mst_mgr; 330 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); 331 332 payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); 333 334 if (!enable) { 335 set_flag = MST_CLEAR_ALLOCATED_PAYLOAD; 336 clr_flag = MST_ALLOCATE_NEW_PAYLOAD; 337 } 338 339 if (enable) 340 ret = drm_dp_add_payload_part2(mst_mgr, mst_state->base.state, payload); 341 342 if (ret) { 343 amdgpu_dm_set_mst_status(&aconnector->mst_status, 344 set_flag, false); 345 } else { 346 amdgpu_dm_set_mst_status(&aconnector->mst_status, 347 set_flag, true); 348 amdgpu_dm_set_mst_status(&aconnector->mst_status, 349 clr_flag, false); 350 } 351 352 return true; 353 } 354 355 void dm_dtn_log_begin(struct dc_context *ctx, 356 struct dc_log_buffer_ctx *log_ctx) 357 { 358 static const char msg[] = "[dtn begin]\n"; 359 360 if (!log_ctx) { 361 pr_info("%s", msg); 362 return; 363 } 364 365 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); 366 } 367 368 __printf(3, 4) 369 void dm_dtn_log_append_v(struct dc_context *ctx, 370 struct dc_log_buffer_ctx *log_ctx, 371 const char *msg, ...) 372 { 373 va_list args; 374 size_t total; 375 int n; 376 377 if (!log_ctx) { 378 /* No context, redirect to dmesg. */ 379 struct va_format vaf; 380 381 vaf.fmt = msg; 382 vaf.va = &args; 383 384 va_start(args, msg); 385 pr_info("%pV", &vaf); 386 va_end(args); 387 388 return; 389 } 390 391 /* Measure the output. */ 392 va_start(args, msg); 393 n = vsnprintf(NULL, 0, msg, args); 394 va_end(args); 395 396 if (n <= 0) 397 return; 398 399 /* Reallocate the string buffer as needed. */ 400 total = log_ctx->pos + n + 1; 401 402 if (total > log_ctx->size) { 403 char *buf = (char *)kvcalloc(total, sizeof(char), GFP_KERNEL); 404 405 if (buf) { 406 memcpy(buf, log_ctx->buf, log_ctx->pos); 407 kfree(log_ctx->buf); 408 409 log_ctx->buf = buf; 410 log_ctx->size = total; 411 } 412 } 413 414 if (!log_ctx->buf) 415 return; 416 417 /* Write the formatted string to the log buffer. */ 418 va_start(args, msg); 419 n = vscnprintf( 420 log_ctx->buf + log_ctx->pos, 421 log_ctx->size - log_ctx->pos, 422 msg, 423 args); 424 va_end(args); 425 426 if (n > 0) 427 log_ctx->pos += n; 428 } 429 430 void dm_dtn_log_end(struct dc_context *ctx, 431 struct dc_log_buffer_ctx *log_ctx) 432 { 433 static const char msg[] = "[dtn end]\n"; 434 435 if (!log_ctx) { 436 pr_info("%s", msg); 437 return; 438 } 439 440 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); 441 } 442 443 bool dm_helpers_dp_mst_start_top_mgr( 444 struct dc_context *ctx, 445 const struct dc_link *link, 446 bool boot) 447 { 448 struct amdgpu_dm_connector *aconnector = link->priv; 449 int ret; 450 451 if (!aconnector) { 452 DRM_ERROR("Failed to find connector for link!"); 453 return false; 454 } 455 456 if (boot) { 457 DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n", 458 aconnector, aconnector->base.base.id); 459 return true; 460 } 461 462 DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n", 463 aconnector, aconnector->base.base.id); 464 465 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 466 if (ret < 0) { 467 DRM_ERROR("DM_MST: Failed to set the device into MST mode!"); 468 return false; 469 } 470 471 DRM_INFO("DM_MST: DP%x, %d-lane link detected\n", aconnector->mst_mgr.dpcd[0], 472 aconnector->mst_mgr.dpcd[2] & DP_MAX_LANE_COUNT_MASK); 473 474 return true; 475 } 476 477 bool dm_helpers_dp_mst_stop_top_mgr( 478 struct dc_context *ctx, 479 struct dc_link *link) 480 { 481 struct amdgpu_dm_connector *aconnector = link->priv; 482 483 if (!aconnector) { 484 DRM_ERROR("Failed to find connector for link!"); 485 return false; 486 } 487 488 DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n", 489 aconnector, aconnector->base.base.id); 490 491 if (aconnector->mst_mgr.mst_state == true) { 492 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false); 493 link->cur_link_settings.lane_count = 0; 494 } 495 496 return false; 497 } 498 499 bool dm_helpers_dp_read_dpcd( 500 struct dc_context *ctx, 501 const struct dc_link *link, 502 uint32_t address, 503 uint8_t *data, 504 uint32_t size) 505 { 506 507 struct amdgpu_dm_connector *aconnector = link->priv; 508 509 if (!aconnector) { 510 DC_LOG_DC("Failed to find connector for link!\n"); 511 return false; 512 } 513 514 return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address, 515 data, size) > 0; 516 } 517 518 bool dm_helpers_dp_write_dpcd( 519 struct dc_context *ctx, 520 const struct dc_link *link, 521 uint32_t address, 522 const uint8_t *data, 523 uint32_t size) 524 { 525 struct amdgpu_dm_connector *aconnector = link->priv; 526 527 if (!aconnector) { 528 DRM_ERROR("Failed to find connector for link!"); 529 return false; 530 } 531 532 return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux, 533 address, (uint8_t *)data, size) > 0; 534 } 535 536 bool dm_helpers_submit_i2c( 537 struct dc_context *ctx, 538 const struct dc_link *link, 539 struct i2c_command *cmd) 540 { 541 struct amdgpu_dm_connector *aconnector = link->priv; 542 struct i2c_msg *msgs; 543 int i = 0; 544 int num = cmd->number_of_payloads; 545 bool result; 546 547 if (!aconnector) { 548 DRM_ERROR("Failed to find connector for link!"); 549 return false; 550 } 551 552 msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL); 553 554 if (!msgs) 555 return false; 556 557 for (i = 0; i < num; i++) { 558 msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD; 559 msgs[i].addr = cmd->payloads[i].address; 560 msgs[i].len = cmd->payloads[i].length; 561 msgs[i].buf = cmd->payloads[i].data; 562 } 563 564 result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num; 565 566 kfree(msgs); 567 568 return result; 569 } 570 571 static bool execute_synaptics_rc_command(struct drm_dp_aux *aux, 572 bool is_write_cmd, 573 unsigned char cmd, 574 unsigned int length, 575 unsigned int offset, 576 unsigned char *data) 577 { 578 bool success = false; 579 unsigned char rc_data[16] = {0}; 580 unsigned char rc_offset[4] = {0}; 581 unsigned char rc_length[2] = {0}; 582 unsigned char rc_cmd = 0; 583 unsigned char rc_result = 0xFF; 584 unsigned char i = 0; 585 int ret; 586 587 if (is_write_cmd) { 588 // write rc data 589 memmove(rc_data, data, length); 590 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_DATA, rc_data, sizeof(rc_data)); 591 } 592 593 // write rc offset 594 rc_offset[0] = (unsigned char) offset & 0xFF; 595 rc_offset[1] = (unsigned char) (offset >> 8) & 0xFF; 596 rc_offset[2] = (unsigned char) (offset >> 16) & 0xFF; 597 rc_offset[3] = (unsigned char) (offset >> 24) & 0xFF; 598 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_OFFSET, rc_offset, sizeof(rc_offset)); 599 600 // write rc length 601 rc_length[0] = (unsigned char) length & 0xFF; 602 rc_length[1] = (unsigned char) (length >> 8) & 0xFF; 603 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_LENGTH, rc_length, sizeof(rc_length)); 604 605 // write rc cmd 606 rc_cmd = cmd | 0x80; 607 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd)); 608 609 if (ret < 0) { 610 DRM_ERROR(" execute_synaptics_rc_command - write cmd ..., err = %d\n", ret); 611 return false; 612 } 613 614 // poll until active is 0 615 for (i = 0; i < 10; i++) { 616 drm_dp_dpcd_read(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd)); 617 if (rc_cmd == cmd) 618 // active is 0 619 break; 620 msleep(10); 621 } 622 623 // read rc result 624 drm_dp_dpcd_read(aux, SYNAPTICS_RC_RESULT, &rc_result, sizeof(rc_result)); 625 success = (rc_result == 0); 626 627 if (success && !is_write_cmd) { 628 // read rc data 629 drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length); 630 } 631 632 DC_LOG_DC(" execute_synaptics_rc_command - success = %d\n", success); 633 634 return success; 635 } 636 637 static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux) 638 { 639 unsigned char data[16] = {0}; 640 641 DC_LOG_DC("Start apply_synaptics_fifo_reset_wa\n"); 642 643 // Step 2 644 data[0] = 'P'; 645 data[1] = 'R'; 646 data[2] = 'I'; 647 data[3] = 'U'; 648 data[4] = 'S'; 649 650 if (!execute_synaptics_rc_command(aux, true, 0x01, 5, 0, data)) 651 return; 652 653 // Step 3 and 4 654 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data)) 655 return; 656 657 data[0] &= (~(1 << 1)); // set bit 1 to 0 658 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data)) 659 return; 660 661 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data)) 662 return; 663 664 data[0] &= (~(1 << 1)); // set bit 1 to 0 665 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220D98, data)) 666 return; 667 668 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data)) 669 return; 670 671 data[0] &= (~(1 << 1)); // set bit 1 to 0 672 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data)) 673 return; 674 675 // Step 3 and 5 676 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data)) 677 return; 678 679 data[0] |= (1 << 1); // set bit 1 to 1 680 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data)) 681 return; 682 683 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data)) 684 return; 685 686 data[0] |= (1 << 1); // set bit 1 to 1 687 return; 688 689 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data)) 690 return; 691 692 data[0] |= (1 << 1); // set bit 1 to 1 693 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data)) 694 return; 695 696 // Step 6 697 if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL)) 698 return; 699 700 DC_LOG_DC("Done apply_synaptics_fifo_reset_wa\n"); 701 } 702 703 static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst( 704 struct drm_dp_aux *aux, 705 const struct dc_stream_state *stream, 706 bool enable) 707 { 708 uint8_t ret = 0; 709 710 DC_LOG_DC("Configure DSC to non-virtual dpcd synaptics\n"); 711 712 if (enable) { 713 /* When DSC is enabled on previous boot and reboot with the hub, 714 * there is a chance that Synaptics hub gets stuck during reboot sequence. 715 * Applying a workaround to reset Synaptics SDP fifo before enabling the first stream 716 */ 717 if (!stream->link->link_status.link_active && 718 memcmp(stream->link->dpcd_caps.branch_dev_name, 719 (int8_t *)SYNAPTICS_DEVICE_ID, 4) == 0) 720 apply_synaptics_fifo_reset_wa(aux); 721 722 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1); 723 DRM_INFO("Send DSC enable to synaptics\n"); 724 725 } else { 726 /* Synaptics hub not support virtual dpcd, 727 * external monitor occur garbage while disable DSC, 728 * Disable DSC only when entire link status turn to false, 729 */ 730 if (!stream->link->link_status.link_active) { 731 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1); 732 DRM_INFO("Send DSC disable to synaptics\n"); 733 } 734 } 735 736 return ret; 737 } 738 739 bool dm_helpers_dp_write_dsc_enable( 740 struct dc_context *ctx, 741 const struct dc_stream_state *stream, 742 bool enable) 743 { 744 static const uint8_t DSC_DISABLE; 745 static const uint8_t DSC_DECODING = 0x01; 746 static const uint8_t DSC_PASSTHROUGH = 0x02; 747 748 struct amdgpu_dm_connector *aconnector; 749 struct drm_dp_mst_port *port; 750 uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE; 751 uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE; 752 uint8_t ret = 0; 753 754 if (!stream) 755 return false; 756 757 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 758 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 759 760 if (!aconnector->dsc_aux) 761 return false; 762 763 // apply w/a to synaptics 764 if (needs_dsc_aux_workaround(aconnector->dc_link) && 765 (aconnector->mst_downstream_port_present.byte & 0x7) != 0x3) 766 return write_dsc_enable_synaptics_non_virtual_dpcd_mst( 767 aconnector->dsc_aux, stream, enable_dsc); 768 769 port = aconnector->mst_output_port; 770 771 if (enable) { 772 if (port->passthrough_aux) { 773 ret = drm_dp_dpcd_write(port->passthrough_aux, 774 DP_DSC_ENABLE, 775 &enable_passthrough, 1); 776 DC_LOG_DC("Sent DSC pass-through enable to virtual dpcd port, ret = %u\n", 777 ret); 778 } 779 780 ret = drm_dp_dpcd_write(aconnector->dsc_aux, 781 DP_DSC_ENABLE, &enable_dsc, 1); 782 DC_LOG_DC("Sent DSC decoding enable to %s port, ret = %u\n", 783 (port->passthrough_aux) ? "remote RX" : 784 "virtual dpcd", 785 ret); 786 } else { 787 ret = drm_dp_dpcd_write(aconnector->dsc_aux, 788 DP_DSC_ENABLE, &enable_dsc, 1); 789 DC_LOG_DC("Sent DSC decoding disable to %s port, ret = %u\n", 790 (port->passthrough_aux) ? "remote RX" : 791 "virtual dpcd", 792 ret); 793 794 if (port->passthrough_aux) { 795 ret = drm_dp_dpcd_write(port->passthrough_aux, 796 DP_DSC_ENABLE, 797 &enable_passthrough, 1); 798 DC_LOG_DC("Sent DSC pass-through disable to virtual dpcd port, ret = %u\n", 799 ret); 800 } 801 } 802 } 803 804 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) { 805 if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { 806 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); 807 DC_LOG_DC("Send DSC %s to SST RX\n", enable_dsc ? "enable" : "disable"); 808 } else if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { 809 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); 810 DC_LOG_DC("Send DSC %s to DP-HDMI PCON\n", enable_dsc ? "enable" : "disable"); 811 } 812 } 813 814 return ret; 815 } 816 817 bool dm_helpers_is_dp_sink_present(struct dc_link *link) 818 { 819 bool dp_sink_present; 820 struct amdgpu_dm_connector *aconnector = link->priv; 821 822 if (!aconnector) { 823 BUG_ON("Failed to find connector for link!"); 824 return true; 825 } 826 827 mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex); 828 dp_sink_present = dc_link_is_dp_sink_present(link); 829 mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex); 830 return dp_sink_present; 831 } 832 833 enum dc_edid_status dm_helpers_read_local_edid( 834 struct dc_context *ctx, 835 struct dc_link *link, 836 struct dc_sink *sink) 837 { 838 struct amdgpu_dm_connector *aconnector = link->priv; 839 struct drm_connector *connector = &aconnector->base; 840 struct i2c_adapter *ddc; 841 int retry = 3; 842 enum dc_edid_status edid_status; 843 struct edid *edid; 844 845 if (link->aux_mode) 846 ddc = &aconnector->dm_dp_aux.aux.ddc; 847 else 848 ddc = &aconnector->i2c->base; 849 850 /* some dongles read edid incorrectly the first time, 851 * do check sum and retry to make sure read correct edid. 852 */ 853 do { 854 855 edid = drm_get_edid(&aconnector->base, ddc); 856 857 /* DP Compliance Test 4.2.2.6 */ 858 if (link->aux_mode && connector->edid_corrupt) 859 drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum); 860 861 if (!edid && connector->edid_corrupt) { 862 connector->edid_corrupt = false; 863 return EDID_BAD_CHECKSUM; 864 } 865 866 if (!edid) 867 return EDID_NO_RESPONSE; 868 869 sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1); 870 memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length); 871 872 /* We don't need the original edid anymore */ 873 kfree(edid); 874 875 edid_status = dm_helpers_parse_edid_caps( 876 link, 877 &sink->dc_edid, 878 &sink->edid_caps); 879 880 } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0); 881 882 if (edid_status != EDID_OK) 883 DRM_ERROR("EDID err: %d, on connector: %s", 884 edid_status, 885 aconnector->base.name); 886 887 /* DP Compliance Test 4.2.2.3 */ 888 if (link->aux_mode) 889 drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, sink->dc_edid.raw_edid[sink->dc_edid.length-1]); 890 891 return edid_status; 892 } 893 int dm_helper_dmub_aux_transfer_sync( 894 struct dc_context *ctx, 895 const struct dc_link *link, 896 struct aux_payload *payload, 897 enum aux_return_code_type *operation_result) 898 { 899 return amdgpu_dm_process_dmub_aux_transfer_sync(ctx, link->link_index, payload, 900 operation_result); 901 } 902 903 int dm_helpers_dmub_set_config_sync(struct dc_context *ctx, 904 const struct dc_link *link, 905 struct set_config_cmd_payload *payload, 906 enum set_config_status *operation_result) 907 { 908 return amdgpu_dm_process_dmub_set_config_sync(ctx, link->link_index, payload, 909 operation_result); 910 } 911 912 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks) 913 { 914 /* TODO: something */ 915 } 916 917 void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us) 918 { 919 // TODO: 920 //amdgpu_device_gpu_recover(dc_context->driver-context, NULL); 921 } 922 923 void dm_helpers_init_panel_settings( 924 struct dc_context *ctx, 925 struct dc_panel_config *panel_config, 926 struct dc_sink *sink) 927 { 928 // Extra Panel Power Sequence 929 panel_config->pps.extra_t3_ms = sink->edid_caps.panel_patch.extra_t3_ms; 930 panel_config->pps.extra_t7_ms = sink->edid_caps.panel_patch.extra_t7_ms; 931 panel_config->pps.extra_delay_backlight_off = sink->edid_caps.panel_patch.extra_delay_backlight_off; 932 panel_config->pps.extra_post_t7_ms = 0; 933 panel_config->pps.extra_pre_t11_ms = 0; 934 panel_config->pps.extra_t12_ms = sink->edid_caps.panel_patch.extra_t12_ms; 935 panel_config->pps.extra_post_OUI_ms = 0; 936 // Feature DSC 937 panel_config->dsc.disable_dsc_edp = false; 938 panel_config->dsc.force_dsc_edp_policy = 0; 939 } 940 941 void dm_helpers_override_panel_settings( 942 struct dc_context *ctx, 943 struct dc_panel_config *panel_config) 944 { 945 // Feature DSC 946 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) { 947 panel_config->dsc.disable_dsc_edp = true; 948 } 949 } 950 951 void *dm_helpers_allocate_gpu_mem( 952 struct dc_context *ctx, 953 enum dc_gpu_mem_alloc_type type, 954 size_t size, 955 long long *addr) 956 { 957 struct amdgpu_device *adev = ctx->driver_context; 958 struct dal_allocation *da; 959 u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ? 960 AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM; 961 int ret; 962 963 da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL); 964 if (!da) 965 return NULL; 966 967 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 968 domain, &da->bo, 969 &da->gpu_addr, &da->cpu_ptr); 970 971 *addr = da->gpu_addr; 972 973 if (ret) { 974 kfree(da); 975 return NULL; 976 } 977 978 /* add da to list in dm */ 979 list_add(&da->list, &adev->dm.da_list); 980 981 return da->cpu_ptr; 982 } 983 984 void dm_helpers_free_gpu_mem( 985 struct dc_context *ctx, 986 enum dc_gpu_mem_alloc_type type, 987 void *pvMem) 988 { 989 struct amdgpu_device *adev = ctx->driver_context; 990 struct dal_allocation *da; 991 992 /* walk the da list in DM */ 993 list_for_each_entry(da, &adev->dm.da_list, list) { 994 if (pvMem == da->cpu_ptr) { 995 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); 996 list_del(&da->list); 997 kfree(da); 998 break; 999 } 1000 } 1001 } 1002 1003 bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable) 1004 { 1005 enum dc_irq_source irq_source; 1006 bool ret; 1007 1008 irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX; 1009 1010 ret = dc_interrupt_set(ctx->dc, irq_source, enable); 1011 1012 DRM_DEBUG_DRIVER("Dmub trace irq %sabling: r=%d\n", 1013 enable ? "en" : "dis", ret); 1014 return ret; 1015 } 1016 1017 void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream) 1018 { 1019 /* TODO: virtual DPCD */ 1020 struct dc_link *link = stream->link; 1021 union down_spread_ctrl old_downspread; 1022 union down_spread_ctrl new_downspread; 1023 1024 if (link->aux_access_disabled) 1025 return; 1026 1027 if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL, 1028 &old_downspread.raw, 1029 sizeof(old_downspread))) 1030 return; 1031 1032 new_downspread.raw = old_downspread.raw; 1033 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 1034 (stream->ignore_msa_timing_param) ? 1 : 0; 1035 1036 if (new_downspread.raw != old_downspread.raw) 1037 dm_helpers_dp_write_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL, 1038 &new_downspread.raw, 1039 sizeof(new_downspread)); 1040 } 1041 1042 bool dm_helpers_dp_handle_test_pattern_request( 1043 struct dc_context *ctx, 1044 const struct dc_link *link, 1045 union link_test_pattern dpcd_test_pattern, 1046 union test_misc dpcd_test_params) 1047 { 1048 enum dp_test_pattern test_pattern; 1049 enum dp_test_pattern_color_space test_pattern_color_space = 1050 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED; 1051 enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED; 1052 enum dc_pixel_encoding requestPixelEncoding = PIXEL_ENCODING_UNDEFINED; 1053 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; 1054 struct pipe_ctx *pipe_ctx = NULL; 1055 struct amdgpu_dm_connector *aconnector = link->priv; 1056 int i; 1057 1058 for (i = 0; i < MAX_PIPES; i++) { 1059 if (pipes[i].stream == NULL) 1060 continue; 1061 1062 if (pipes[i].stream->link == link && !pipes[i].top_pipe && 1063 !pipes[i].prev_odm_pipe) { 1064 pipe_ctx = &pipes[i]; 1065 break; 1066 } 1067 } 1068 1069 if (pipe_ctx == NULL) 1070 return false; 1071 1072 switch (dpcd_test_pattern.bits.PATTERN) { 1073 case LINK_TEST_PATTERN_COLOR_RAMP: 1074 test_pattern = DP_TEST_PATTERN_COLOR_RAMP; 1075 break; 1076 case LINK_TEST_PATTERN_VERTICAL_BARS: 1077 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS; 1078 break; /* black and white */ 1079 case LINK_TEST_PATTERN_COLOR_SQUARES: 1080 test_pattern = (dpcd_test_params.bits.DYN_RANGE == 1081 TEST_DYN_RANGE_VESA ? 1082 DP_TEST_PATTERN_COLOR_SQUARES : 1083 DP_TEST_PATTERN_COLOR_SQUARES_CEA); 1084 break; 1085 default: 1086 test_pattern = DP_TEST_PATTERN_VIDEO_MODE; 1087 break; 1088 } 1089 1090 if (dpcd_test_params.bits.CLR_FORMAT == 0) 1091 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB; 1092 else 1093 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ? 1094 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 : 1095 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601; 1096 1097 switch (dpcd_test_params.bits.BPC) { 1098 case 0: // 6 bits 1099 requestColorDepth = COLOR_DEPTH_666; 1100 break; 1101 case 1: // 8 bits 1102 requestColorDepth = COLOR_DEPTH_888; 1103 break; 1104 case 2: // 10 bits 1105 requestColorDepth = COLOR_DEPTH_101010; 1106 break; 1107 case 3: // 12 bits 1108 requestColorDepth = COLOR_DEPTH_121212; 1109 break; 1110 default: 1111 break; 1112 } 1113 1114 switch (dpcd_test_params.bits.CLR_FORMAT) { 1115 case 0: 1116 requestPixelEncoding = PIXEL_ENCODING_RGB; 1117 break; 1118 case 1: 1119 requestPixelEncoding = PIXEL_ENCODING_YCBCR422; 1120 break; 1121 case 2: 1122 requestPixelEncoding = PIXEL_ENCODING_YCBCR444; 1123 break; 1124 default: 1125 requestPixelEncoding = PIXEL_ENCODING_RGB; 1126 break; 1127 } 1128 1129 if ((requestColorDepth != COLOR_DEPTH_UNDEFINED 1130 && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) 1131 || (requestPixelEncoding != PIXEL_ENCODING_UNDEFINED 1132 && pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) { 1133 DC_LOG_DEBUG("%s: original bpc %d pix encoding %d, changing to %d %d\n", 1134 __func__, 1135 pipe_ctx->stream->timing.display_color_depth, 1136 pipe_ctx->stream->timing.pixel_encoding, 1137 requestColorDepth, 1138 requestPixelEncoding); 1139 pipe_ctx->stream->timing.display_color_depth = requestColorDepth; 1140 pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding; 1141 1142 dc_link_update_dsc_config(pipe_ctx); 1143 1144 aconnector->timing_changed = true; 1145 /* store current timing */ 1146 if (aconnector->timing_requested) 1147 *aconnector->timing_requested = pipe_ctx->stream->timing; 1148 else 1149 DC_LOG_ERROR("%s: timing storage failed\n", __func__); 1150 1151 } 1152 1153 dc_link_dp_set_test_pattern( 1154 (struct dc_link *) link, 1155 test_pattern, 1156 test_pattern_color_space, 1157 NULL, 1158 NULL, 1159 0); 1160 1161 return false; 1162 } 1163 1164 void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz) 1165 { 1166 // TODO 1167 } 1168 1169 void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable) 1170 { 1171 /* TODO: add periodic detection implementation */ 1172 } 1173 1174 void dm_helpers_dp_mst_update_branch_bandwidth( 1175 struct dc_context *ctx, 1176 struct dc_link *link) 1177 { 1178 // TODO 1179 } 1180 1181 static bool dm_is_freesync_pcon_whitelist(const uint32_t branch_dev_id) 1182 { 1183 bool ret_val = false; 1184 1185 switch (branch_dev_id) { 1186 case DP_BRANCH_DEVICE_ID_0060AD: 1187 case DP_BRANCH_DEVICE_ID_00E04C: 1188 case DP_BRANCH_DEVICE_ID_90CC24: 1189 ret_val = true; 1190 break; 1191 default: 1192 break; 1193 } 1194 1195 return ret_val; 1196 } 1197 1198 enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link) 1199 { 1200 struct dpcd_caps *dpcd_caps = &link->dpcd_caps; 1201 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; 1202 1203 switch (dpcd_caps->dongle_type) { 1204 case DISPLAY_DONGLE_DP_HDMI_CONVERTER: 1205 if (dpcd_caps->adaptive_sync_caps.dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT == true && 1206 dpcd_caps->allow_invalid_MSA_timing_param == true && 1207 dm_is_freesync_pcon_whitelist(dpcd_caps->branch_dev_id)) 1208 as_type = FREESYNC_TYPE_PCON_IN_WHITELIST; 1209 break; 1210 default: 1211 break; 1212 } 1213 1214 return as_type; 1215 } 1216