1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string.h> 27 #include <linux/acpi.h> 28 #include <linux/version.h> 29 #include <linux/i2c.h> 30 31 #include <drm/drmP.h> 32 #include <drm/drm_crtc_helper.h> 33 #include <drm/amdgpu_drm.h> 34 #include <drm/drm_edid.h> 35 36 #include "dm_services.h" 37 #include "amdgpu.h" 38 #include "dc.h" 39 #include "amdgpu_dm.h" 40 #include "amdgpu_dm_irq.h" 41 42 #include "dm_helpers.h" 43 44 /* dm_helpers_parse_edid_caps 45 * 46 * Parse edid caps 47 * 48 * @edid: [in] pointer to edid 49 * edid_caps: [in] pointer to edid caps 50 * @return 51 * void 52 * */ 53 enum dc_edid_status dm_helpers_parse_edid_caps( 54 struct dc_context *ctx, 55 const struct dc_edid *edid, 56 struct dc_edid_caps *edid_caps) 57 { 58 struct edid *edid_buf = (struct edid *) edid->raw_edid; 59 struct cea_sad *sads; 60 int sad_count = -1; 61 int sadb_count = -1; 62 int i = 0; 63 int j = 0; 64 uint8_t *sadb = NULL; 65 66 enum dc_edid_status result = EDID_OK; 67 68 if (!edid_caps || !edid) 69 return EDID_BAD_INPUT; 70 71 if (!drm_edid_is_valid(edid_buf)) 72 result = EDID_BAD_CHECKSUM; 73 74 edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] | 75 ((uint16_t) edid_buf->mfg_id[1])<<8; 76 edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] | 77 ((uint16_t) edid_buf->prod_code[1])<<8; 78 edid_caps->serial_number = edid_buf->serial; 79 edid_caps->manufacture_week = edid_buf->mfg_week; 80 edid_caps->manufacture_year = edid_buf->mfg_year; 81 82 /* One of the four detailed_timings stores the monitor name. It's 83 * stored in an array of length 13. */ 84 for (i = 0; i < 4; i++) { 85 if (edid_buf->detailed_timings[i].data.other_data.type == 0xfc) { 86 while (j < 13 && edid_buf->detailed_timings[i].data.other_data.data.str.str[j]) { 87 if (edid_buf->detailed_timings[i].data.other_data.data.str.str[j] == '\n') 88 break; 89 90 edid_caps->display_name[j] = 91 edid_buf->detailed_timings[i].data.other_data.data.str.str[j]; 92 j++; 93 } 94 } 95 } 96 97 edid_caps->edid_hdmi = drm_detect_hdmi_monitor( 98 (struct edid *) edid->raw_edid); 99 100 sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads); 101 if (sad_count <= 0) { 102 DRM_INFO("SADs count is: %d, don't need to read it\n", 103 sad_count); 104 return result; 105 } 106 107 edid_caps->audio_mode_count = sad_count < DC_MAX_AUDIO_DESC_COUNT ? sad_count : DC_MAX_AUDIO_DESC_COUNT; 108 for (i = 0; i < edid_caps->audio_mode_count; ++i) { 109 struct cea_sad *sad = &sads[i]; 110 111 edid_caps->audio_modes[i].format_code = sad->format; 112 edid_caps->audio_modes[i].channel_count = sad->channels + 1; 113 edid_caps->audio_modes[i].sample_rate = sad->freq; 114 edid_caps->audio_modes[i].sample_size = sad->byte2; 115 } 116 117 sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb); 118 119 if (sadb_count < 0) { 120 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count); 121 sadb_count = 0; 122 } 123 124 if (sadb_count) 125 edid_caps->speaker_flags = sadb[0]; 126 else 127 edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION; 128 129 kfree(sads); 130 kfree(sadb); 131 132 return result; 133 } 134 135 static void get_payload_table( 136 struct amdgpu_dm_connector *aconnector, 137 struct dp_mst_stream_allocation_table *proposed_table) 138 { 139 int i; 140 struct drm_dp_mst_topology_mgr *mst_mgr = 141 &aconnector->mst_port->mst_mgr; 142 143 mutex_lock(&mst_mgr->payload_lock); 144 145 proposed_table->stream_count = 0; 146 147 /* number of active streams */ 148 for (i = 0; i < mst_mgr->max_payloads; i++) { 149 if (mst_mgr->payloads[i].num_slots == 0) 150 break; /* end of vcp_id table */ 151 152 ASSERT(mst_mgr->payloads[i].payload_state != 153 DP_PAYLOAD_DELETE_LOCAL); 154 155 if (mst_mgr->payloads[i].payload_state == DP_PAYLOAD_LOCAL || 156 mst_mgr->payloads[i].payload_state == 157 DP_PAYLOAD_REMOTE) { 158 159 struct dp_mst_stream_allocation *sa = 160 &proposed_table->stream_allocations[ 161 proposed_table->stream_count]; 162 163 sa->slot_count = mst_mgr->payloads[i].num_slots; 164 sa->vcp_id = mst_mgr->proposed_vcpis[i]->vcpi; 165 proposed_table->stream_count++; 166 } 167 } 168 169 mutex_unlock(&mst_mgr->payload_lock); 170 } 171 172 void dm_helpers_dp_update_branch_info( 173 struct dc_context *ctx, 174 const struct dc_link *link) 175 {} 176 177 /* 178 * Writes payload allocation table in immediate downstream device. 179 */ 180 bool dm_helpers_dp_mst_write_payload_allocation_table( 181 struct dc_context *ctx, 182 const struct dc_stream_state *stream, 183 struct dp_mst_stream_allocation_table *proposed_table, 184 bool enable) 185 { 186 struct amdgpu_dm_connector *aconnector; 187 struct drm_dp_mst_topology_mgr *mst_mgr; 188 struct drm_dp_mst_port *mst_port; 189 int slots = 0; 190 bool ret; 191 int clock; 192 int bpp = 0; 193 int pbn = 0; 194 195 aconnector = stream->sink->priv; 196 197 if (!aconnector || !aconnector->mst_port) 198 return false; 199 200 mst_mgr = &aconnector->mst_port->mst_mgr; 201 202 if (!mst_mgr->mst_state) 203 return false; 204 205 mst_port = aconnector->port; 206 207 if (enable) { 208 clock = stream->timing.pix_clk_khz; 209 210 switch (stream->timing.display_color_depth) { 211 212 case COLOR_DEPTH_666: 213 bpp = 6; 214 break; 215 case COLOR_DEPTH_888: 216 bpp = 8; 217 break; 218 case COLOR_DEPTH_101010: 219 bpp = 10; 220 break; 221 case COLOR_DEPTH_121212: 222 bpp = 12; 223 break; 224 case COLOR_DEPTH_141414: 225 bpp = 14; 226 break; 227 case COLOR_DEPTH_161616: 228 bpp = 16; 229 break; 230 default: 231 ASSERT(bpp != 0); 232 break; 233 } 234 235 bpp = bpp * 3; 236 237 /* TODO need to know link rate */ 238 239 pbn = drm_dp_calc_pbn_mode(clock, bpp); 240 241 slots = drm_dp_find_vcpi_slots(mst_mgr, pbn); 242 ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, slots); 243 244 if (!ret) 245 return false; 246 247 } else { 248 drm_dp_mst_reset_vcpi_slots(mst_mgr, mst_port); 249 } 250 251 ret = drm_dp_update_payload_part1(mst_mgr); 252 253 /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or 254 * AUX message. The sequence is slot 1-63 allocated sequence for each 255 * stream. AMD ASIC stream slot allocation should follow the same 256 * sequence. copy DRM MST allocation to dc */ 257 258 get_payload_table(aconnector, proposed_table); 259 260 if (ret) 261 return false; 262 263 return true; 264 } 265 266 267 /* 268 * Clear payload allocation table before enable MST DP link. 269 */ 270 void dm_helpers_dp_mst_clear_payload_allocation_table( 271 struct dc_context *ctx, 272 const struct dc_link *link) 273 {} 274 275 /* 276 * Polls for ACT (allocation change trigger) handled and sends 277 * ALLOCATE_PAYLOAD message. 278 */ 279 bool dm_helpers_dp_mst_poll_for_allocation_change_trigger( 280 struct dc_context *ctx, 281 const struct dc_stream_state *stream) 282 { 283 struct amdgpu_dm_connector *aconnector; 284 struct drm_dp_mst_topology_mgr *mst_mgr; 285 int ret; 286 287 aconnector = stream->sink->priv; 288 289 if (!aconnector || !aconnector->mst_port) 290 return false; 291 292 mst_mgr = &aconnector->mst_port->mst_mgr; 293 294 if (!mst_mgr->mst_state) 295 return false; 296 297 ret = drm_dp_check_act_status(mst_mgr); 298 299 if (ret) 300 return false; 301 302 return true; 303 } 304 305 bool dm_helpers_dp_mst_send_payload_allocation( 306 struct dc_context *ctx, 307 const struct dc_stream_state *stream, 308 bool enable) 309 { 310 struct amdgpu_dm_connector *aconnector; 311 struct drm_dp_mst_topology_mgr *mst_mgr; 312 struct drm_dp_mst_port *mst_port; 313 int ret; 314 315 aconnector = stream->sink->priv; 316 317 if (!aconnector || !aconnector->mst_port) 318 return false; 319 320 mst_port = aconnector->port; 321 322 mst_mgr = &aconnector->mst_port->mst_mgr; 323 324 if (!mst_mgr->mst_state) 325 return false; 326 327 ret = drm_dp_update_payload_part2(mst_mgr); 328 329 if (ret) 330 return false; 331 332 if (!enable) 333 drm_dp_mst_deallocate_vcpi(mst_mgr, mst_port); 334 335 return true; 336 } 337 338 void dm_dtn_log_begin(struct dc_context *ctx, 339 struct dc_log_buffer_ctx *log_ctx) 340 { 341 static const char msg[] = "[dtn begin]\n"; 342 343 if (!log_ctx) { 344 pr_info("%s", msg); 345 return; 346 } 347 348 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); 349 } 350 351 void dm_dtn_log_append_v(struct dc_context *ctx, 352 struct dc_log_buffer_ctx *log_ctx, 353 const char *msg, ...) 354 { 355 va_list args; 356 size_t total; 357 int n; 358 359 if (!log_ctx) { 360 /* No context, redirect to dmesg. */ 361 struct va_format vaf; 362 363 vaf.fmt = msg; 364 vaf.va = &args; 365 366 va_start(args, msg); 367 pr_info("%pV", &vaf); 368 va_end(args); 369 370 return; 371 } 372 373 /* Measure the output. */ 374 va_start(args, msg); 375 n = vsnprintf(NULL, 0, msg, args); 376 va_end(args); 377 378 if (n <= 0) 379 return; 380 381 /* Reallocate the string buffer as needed. */ 382 total = log_ctx->pos + n + 1; 383 384 if (total > log_ctx->size) { 385 char *buf = (char *)kvcalloc(total, sizeof(char), GFP_KERNEL); 386 387 if (buf) { 388 memcpy(buf, log_ctx->buf, log_ctx->pos); 389 kfree(log_ctx->buf); 390 391 log_ctx->buf = buf; 392 log_ctx->size = total; 393 } 394 } 395 396 if (!log_ctx->buf) 397 return; 398 399 /* Write the formatted string to the log buffer. */ 400 va_start(args, msg); 401 n = vscnprintf( 402 log_ctx->buf + log_ctx->pos, 403 log_ctx->size - log_ctx->pos, 404 msg, 405 args); 406 va_end(args); 407 408 if (n > 0) 409 log_ctx->pos += n; 410 } 411 412 void dm_dtn_log_end(struct dc_context *ctx, 413 struct dc_log_buffer_ctx *log_ctx) 414 { 415 static const char msg[] = "[dtn end]\n"; 416 417 if (!log_ctx) { 418 pr_info("%s", msg); 419 return; 420 } 421 422 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); 423 } 424 425 bool dm_helpers_dp_mst_start_top_mgr( 426 struct dc_context *ctx, 427 const struct dc_link *link, 428 bool boot) 429 { 430 struct amdgpu_dm_connector *aconnector = link->priv; 431 432 if (!aconnector) { 433 DRM_ERROR("Failed to found connector for link!"); 434 return false; 435 } 436 437 if (boot) { 438 DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n", 439 aconnector, aconnector->base.base.id); 440 return true; 441 } 442 443 DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n", 444 aconnector, aconnector->base.base.id); 445 446 return (drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true) == 0); 447 } 448 449 void dm_helpers_dp_mst_stop_top_mgr( 450 struct dc_context *ctx, 451 const struct dc_link *link) 452 { 453 struct amdgpu_dm_connector *aconnector = link->priv; 454 455 if (!aconnector) { 456 DRM_ERROR("Failed to found connector for link!"); 457 return; 458 } 459 460 DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n", 461 aconnector, aconnector->base.base.id); 462 463 if (aconnector->mst_mgr.mst_state == true) 464 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false); 465 } 466 467 bool dm_helpers_dp_read_dpcd( 468 struct dc_context *ctx, 469 const struct dc_link *link, 470 uint32_t address, 471 uint8_t *data, 472 uint32_t size) 473 { 474 475 struct amdgpu_dm_connector *aconnector = link->priv; 476 477 if (!aconnector) { 478 DRM_ERROR("Failed to found connector for link!"); 479 return false; 480 } 481 482 return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address, 483 data, size) > 0; 484 } 485 486 bool dm_helpers_dp_write_dpcd( 487 struct dc_context *ctx, 488 const struct dc_link *link, 489 uint32_t address, 490 const uint8_t *data, 491 uint32_t size) 492 { 493 struct amdgpu_dm_connector *aconnector = link->priv; 494 495 if (!aconnector) { 496 DRM_ERROR("Failed to found connector for link!"); 497 return false; 498 } 499 500 return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux, 501 address, (uint8_t *)data, size) > 0; 502 } 503 504 bool dm_helpers_submit_i2c( 505 struct dc_context *ctx, 506 const struct dc_link *link, 507 struct i2c_command *cmd) 508 { 509 struct amdgpu_dm_connector *aconnector = link->priv; 510 struct i2c_msg *msgs; 511 int i = 0; 512 int num = cmd->number_of_payloads; 513 bool result; 514 515 if (!aconnector) { 516 DRM_ERROR("Failed to found connector for link!"); 517 return false; 518 } 519 520 msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL); 521 522 if (!msgs) 523 return false; 524 525 for (i = 0; i < num; i++) { 526 msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD; 527 msgs[i].addr = cmd->payloads[i].address; 528 msgs[i].len = cmd->payloads[i].length; 529 msgs[i].buf = cmd->payloads[i].data; 530 } 531 532 result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num; 533 534 kfree(msgs); 535 536 return result; 537 } 538 539 bool dm_helpers_is_dp_sink_present(struct dc_link *link) 540 { 541 bool dp_sink_present; 542 struct amdgpu_dm_connector *aconnector = link->priv; 543 544 if (!aconnector) { 545 BUG_ON("Failed to found connector for link!"); 546 return true; 547 } 548 549 mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex); 550 dp_sink_present = dc_link_is_dp_sink_present(link); 551 mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex); 552 return dp_sink_present; 553 } 554 555 enum dc_edid_status dm_helpers_read_local_edid( 556 struct dc_context *ctx, 557 struct dc_link *link, 558 struct dc_sink *sink) 559 { 560 struct amdgpu_dm_connector *aconnector = link->priv; 561 struct i2c_adapter *ddc; 562 int retry = 3; 563 enum dc_edid_status edid_status; 564 struct edid *edid; 565 566 if (link->aux_mode) 567 ddc = &aconnector->dm_dp_aux.aux.ddc; 568 else 569 ddc = &aconnector->i2c->base; 570 571 /* some dongles read edid incorrectly the first time, 572 * do check sum and retry to make sure read correct edid. 573 */ 574 do { 575 576 edid = drm_get_edid(&aconnector->base, ddc); 577 578 if (!edid) 579 return EDID_NO_RESPONSE; 580 581 sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1); 582 memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length); 583 584 /* We don't need the original edid anymore */ 585 kfree(edid); 586 587 edid_status = dm_helpers_parse_edid_caps( 588 ctx, 589 &sink->dc_edid, 590 &sink->edid_caps); 591 592 } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0); 593 594 if (edid_status != EDID_OK) 595 DRM_ERROR("EDID err: %d, on connector: %s", 596 edid_status, 597 aconnector->base.name); 598 if (link->aux_mode) { 599 union test_request test_request = { {0} }; 600 union test_response test_response = { {0} }; 601 602 dm_helpers_dp_read_dpcd(ctx, 603 link, 604 DP_TEST_REQUEST, 605 &test_request.raw, 606 sizeof(union test_request)); 607 608 if (!test_request.bits.EDID_READ) 609 return edid_status; 610 611 test_response.bits.EDID_CHECKSUM_WRITE = 1; 612 613 dm_helpers_dp_write_dpcd(ctx, 614 link, 615 DP_TEST_EDID_CHECKSUM, 616 &sink->dc_edid.raw_edid[sink->dc_edid.length-1], 617 1); 618 619 dm_helpers_dp_write_dpcd(ctx, 620 link, 621 DP_TEST_RESPONSE, 622 &test_response.raw, 623 sizeof(test_response)); 624 625 } 626 627 return edid_status; 628 } 629 630 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks) 631 { 632 /* TODO: something */ 633 } 634