1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string.h> 27 #include <linux/acpi.h> 28 #include <linux/i2c.h> 29 30 #include <drm/drm_atomic.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/amdgpu_drm.h> 33 #include <drm/drm_edid.h> 34 #include <drm/drm_fixed.h> 35 36 #include "dm_services.h" 37 #include "amdgpu.h" 38 #include "dc.h" 39 #include "amdgpu_dm.h" 40 #include "amdgpu_dm_irq.h" 41 #include "amdgpu_dm_mst_types.h" 42 #include "dpcd_defs.h" 43 #include "dc/inc/core_types.h" 44 45 #include "dm_helpers.h" 46 #include "ddc_service_types.h" 47 48 static u32 edid_extract_panel_id(struct edid *edid) 49 { 50 return (u32)edid->mfg_id[0] << 24 | 51 (u32)edid->mfg_id[1] << 16 | 52 (u32)EDID_PRODUCT_ID(edid); 53 } 54 55 static void apply_edid_quirks(struct edid *edid, struct dc_edid_caps *edid_caps) 56 { 57 uint32_t panel_id = edid_extract_panel_id(edid); 58 59 switch (panel_id) { 60 /* Workaround for some monitors which does not work well with FAMS */ 61 case drm_edid_encode_panel_id('S', 'A', 'M', 0x0E5E): 62 case drm_edid_encode_panel_id('S', 'A', 'M', 0x7053): 63 case drm_edid_encode_panel_id('S', 'A', 'M', 0x71AC): 64 DRM_DEBUG_DRIVER("Disabling FAMS on monitor with panel id %X\n", panel_id); 65 edid_caps->panel_patch.disable_fams = true; 66 break; 67 /* Workaround for some monitors that do not clear DPCD 0x317 if FreeSync is unsupported */ 68 case drm_edid_encode_panel_id('A', 'U', 'O', 0xA7AB): 69 case drm_edid_encode_panel_id('A', 'U', 'O', 0xE69B): 70 DRM_DEBUG_DRIVER("Clearing DPCD 0x317 on monitor with panel id %X\n", panel_id); 71 edid_caps->panel_patch.remove_sink_ext_caps = true; 72 break; 73 default: 74 return; 75 } 76 } 77 78 /** 79 * dm_helpers_parse_edid_caps() - Parse edid caps 80 * 81 * @link: current detected link 82 * @edid: [in] pointer to edid 83 * @edid_caps: [in] pointer to edid caps 84 * 85 * Return: void 86 */ 87 enum dc_edid_status dm_helpers_parse_edid_caps( 88 struct dc_link *link, 89 const struct dc_edid *edid, 90 struct dc_edid_caps *edid_caps) 91 { 92 struct amdgpu_dm_connector *aconnector = link->priv; 93 struct drm_connector *connector = &aconnector->base; 94 struct edid *edid_buf = edid ? (struct edid *) edid->raw_edid : NULL; 95 struct cea_sad *sads; 96 int sad_count = -1; 97 int sadb_count = -1; 98 int i = 0; 99 uint8_t *sadb = NULL; 100 101 enum dc_edid_status result = EDID_OK; 102 103 if (!edid_caps || !edid) 104 return EDID_BAD_INPUT; 105 106 if (!drm_edid_is_valid(edid_buf)) 107 result = EDID_BAD_CHECKSUM; 108 109 edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] | 110 ((uint16_t) edid_buf->mfg_id[1])<<8; 111 edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] | 112 ((uint16_t) edid_buf->prod_code[1])<<8; 113 edid_caps->serial_number = edid_buf->serial; 114 edid_caps->manufacture_week = edid_buf->mfg_week; 115 edid_caps->manufacture_year = edid_buf->mfg_year; 116 117 drm_edid_get_monitor_name(edid_buf, 118 edid_caps->display_name, 119 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 120 121 edid_caps->edid_hdmi = connector->display_info.is_hdmi; 122 123 sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads); 124 if (sad_count <= 0) 125 return result; 126 127 edid_caps->audio_mode_count = min(sad_count, DC_MAX_AUDIO_DESC_COUNT); 128 for (i = 0; i < edid_caps->audio_mode_count; ++i) { 129 struct cea_sad *sad = &sads[i]; 130 131 edid_caps->audio_modes[i].format_code = sad->format; 132 edid_caps->audio_modes[i].channel_count = sad->channels + 1; 133 edid_caps->audio_modes[i].sample_rate = sad->freq; 134 edid_caps->audio_modes[i].sample_size = sad->byte2; 135 } 136 137 sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb); 138 139 if (sadb_count < 0) { 140 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count); 141 sadb_count = 0; 142 } 143 144 if (sadb_count) 145 edid_caps->speaker_flags = sadb[0]; 146 else 147 edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION; 148 149 apply_edid_quirks(edid_buf, edid_caps); 150 151 kfree(sads); 152 kfree(sadb); 153 154 return result; 155 } 156 157 static void 158 fill_dc_mst_payload_table_from_drm(struct dc_link *link, 159 bool enable, 160 struct drm_dp_mst_atomic_payload *target_payload, 161 struct dc_dp_mst_stream_allocation_table *table) 162 { 163 struct dc_dp_mst_stream_allocation_table new_table = { 0 }; 164 struct dc_dp_mst_stream_allocation *sa; 165 struct link_mst_stream_allocation_table copy_of_link_table = 166 link->mst_stream_alloc_table; 167 168 int i; 169 int current_hw_table_stream_cnt = copy_of_link_table.stream_count; 170 struct link_mst_stream_allocation *dc_alloc; 171 172 /* TODO: refactor to set link->mst_stream_alloc_table directly if possible.*/ 173 if (enable) { 174 dc_alloc = 175 ©_of_link_table.stream_allocations[current_hw_table_stream_cnt]; 176 dc_alloc->vcp_id = target_payload->vcpi; 177 dc_alloc->slot_count = target_payload->time_slots; 178 } else { 179 for (i = 0; i < copy_of_link_table.stream_count; i++) { 180 dc_alloc = 181 ©_of_link_table.stream_allocations[i]; 182 183 if (dc_alloc->vcp_id == target_payload->vcpi) { 184 dc_alloc->vcp_id = 0; 185 dc_alloc->slot_count = 0; 186 break; 187 } 188 } 189 ASSERT(i != copy_of_link_table.stream_count); 190 } 191 192 /* Fill payload info*/ 193 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 194 dc_alloc = 195 ©_of_link_table.stream_allocations[i]; 196 if (dc_alloc->vcp_id > 0 && dc_alloc->slot_count > 0) { 197 sa = &new_table.stream_allocations[new_table.stream_count]; 198 sa->slot_count = dc_alloc->slot_count; 199 sa->vcp_id = dc_alloc->vcp_id; 200 new_table.stream_count++; 201 } 202 } 203 204 /* Overwrite the old table */ 205 *table = new_table; 206 } 207 208 void dm_helpers_dp_update_branch_info( 209 struct dc_context *ctx, 210 const struct dc_link *link) 211 {} 212 213 static void dm_helpers_construct_old_payload( 214 struct drm_dp_mst_topology_mgr *mgr, 215 struct drm_dp_mst_topology_state *mst_state, 216 struct drm_dp_mst_atomic_payload *new_payload, 217 struct drm_dp_mst_atomic_payload *old_payload) 218 { 219 struct drm_dp_mst_atomic_payload *pos; 220 int pbn_per_slot = dfixed_trunc(mst_state->pbn_div); 221 u8 next_payload_vc_start = mgr->next_start_slot; 222 u8 payload_vc_start = new_payload->vc_start_slot; 223 u8 allocated_time_slots; 224 225 *old_payload = *new_payload; 226 227 /* Set correct time_slots/PBN of old payload. 228 * other fields (delete & dsc_enabled) in 229 * struct drm_dp_mst_atomic_payload are don't care fields 230 * while calling drm_dp_remove_payload_part2() 231 */ 232 list_for_each_entry(pos, &mst_state->payloads, next) { 233 if (pos != new_payload && 234 pos->vc_start_slot > payload_vc_start && 235 pos->vc_start_slot < next_payload_vc_start) 236 next_payload_vc_start = pos->vc_start_slot; 237 } 238 239 allocated_time_slots = next_payload_vc_start - payload_vc_start; 240 241 old_payload->time_slots = allocated_time_slots; 242 old_payload->pbn = allocated_time_slots * pbn_per_slot; 243 } 244 245 /* 246 * Writes payload allocation table in immediate downstream device. 247 */ 248 bool dm_helpers_dp_mst_write_payload_allocation_table( 249 struct dc_context *ctx, 250 const struct dc_stream_state *stream, 251 struct dc_dp_mst_stream_allocation_table *proposed_table, 252 bool enable) 253 { 254 struct amdgpu_dm_connector *aconnector; 255 struct drm_dp_mst_topology_state *mst_state; 256 struct drm_dp_mst_atomic_payload *target_payload, *new_payload, old_payload; 257 struct drm_dp_mst_topology_mgr *mst_mgr; 258 259 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 260 /* Accessing the connector state is required for vcpi_slots allocation 261 * and directly relies on behaviour in commit check 262 * that blocks before commit guaranteeing that the state 263 * is not gonna be swapped while still in use in commit tail 264 */ 265 266 if (!aconnector || !aconnector->mst_root) 267 return false; 268 269 mst_mgr = &aconnector->mst_root->mst_mgr; 270 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); 271 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); 272 273 if (enable) { 274 target_payload = new_payload; 275 276 /* It's OK for this to fail */ 277 drm_dp_add_payload_part1(mst_mgr, mst_state, new_payload); 278 } else { 279 /* construct old payload by VCPI*/ 280 dm_helpers_construct_old_payload(mst_mgr, mst_state, 281 new_payload, &old_payload); 282 target_payload = &old_payload; 283 284 drm_dp_remove_payload_part1(mst_mgr, mst_state, new_payload); 285 } 286 287 /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or 288 * AUX message. The sequence is slot 1-63 allocated sequence for each 289 * stream. AMD ASIC stream slot allocation should follow the same 290 * sequence. copy DRM MST allocation to dc 291 */ 292 fill_dc_mst_payload_table_from_drm(stream->link, enable, target_payload, proposed_table); 293 294 return true; 295 } 296 297 /* 298 * poll pending down reply 299 */ 300 void dm_helpers_dp_mst_poll_pending_down_reply( 301 struct dc_context *ctx, 302 const struct dc_link *link) 303 {} 304 305 /* 306 * Clear payload allocation table before enable MST DP link. 307 */ 308 void dm_helpers_dp_mst_clear_payload_allocation_table( 309 struct dc_context *ctx, 310 const struct dc_link *link) 311 {} 312 313 /* 314 * Polls for ACT (allocation change trigger) handled and sends 315 * ALLOCATE_PAYLOAD message. 316 */ 317 enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger( 318 struct dc_context *ctx, 319 const struct dc_stream_state *stream) 320 { 321 struct amdgpu_dm_connector *aconnector; 322 struct drm_dp_mst_topology_mgr *mst_mgr; 323 int ret; 324 325 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 326 327 if (!aconnector || !aconnector->mst_root) 328 return ACT_FAILED; 329 330 mst_mgr = &aconnector->mst_root->mst_mgr; 331 332 if (!mst_mgr->mst_state) 333 return ACT_FAILED; 334 335 ret = drm_dp_check_act_status(mst_mgr); 336 337 if (ret) 338 return ACT_FAILED; 339 340 return ACT_SUCCESS; 341 } 342 343 void dm_helpers_dp_mst_send_payload_allocation( 344 struct dc_context *ctx, 345 const struct dc_stream_state *stream) 346 { 347 struct amdgpu_dm_connector *aconnector; 348 struct drm_dp_mst_topology_state *mst_state; 349 struct drm_dp_mst_topology_mgr *mst_mgr; 350 struct drm_dp_mst_atomic_payload *new_payload; 351 enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD; 352 enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD; 353 int ret = 0; 354 355 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 356 357 if (!aconnector || !aconnector->mst_root) 358 return; 359 360 mst_mgr = &aconnector->mst_root->mst_mgr; 361 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); 362 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); 363 364 ret = drm_dp_add_payload_part2(mst_mgr, mst_state->base.state, new_payload); 365 366 if (ret) { 367 amdgpu_dm_set_mst_status(&aconnector->mst_status, 368 set_flag, false); 369 } else { 370 amdgpu_dm_set_mst_status(&aconnector->mst_status, 371 set_flag, true); 372 amdgpu_dm_set_mst_status(&aconnector->mst_status, 373 clr_flag, false); 374 } 375 } 376 377 void dm_helpers_dp_mst_update_mst_mgr_for_deallocation( 378 struct dc_context *ctx, 379 const struct dc_stream_state *stream) 380 { 381 struct amdgpu_dm_connector *aconnector; 382 struct drm_dp_mst_topology_state *mst_state; 383 struct drm_dp_mst_topology_mgr *mst_mgr; 384 struct drm_dp_mst_atomic_payload *new_payload, old_payload; 385 enum mst_progress_status set_flag = MST_CLEAR_ALLOCATED_PAYLOAD; 386 enum mst_progress_status clr_flag = MST_ALLOCATE_NEW_PAYLOAD; 387 388 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 389 390 if (!aconnector || !aconnector->mst_root) 391 return; 392 393 mst_mgr = &aconnector->mst_root->mst_mgr; 394 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); 395 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); 396 dm_helpers_construct_old_payload(mst_mgr, mst_state, 397 new_payload, &old_payload); 398 399 drm_dp_remove_payload_part2(mst_mgr, mst_state, &old_payload, new_payload); 400 401 amdgpu_dm_set_mst_status(&aconnector->mst_status, set_flag, true); 402 amdgpu_dm_set_mst_status(&aconnector->mst_status, clr_flag, false); 403 } 404 405 void dm_dtn_log_begin(struct dc_context *ctx, 406 struct dc_log_buffer_ctx *log_ctx) 407 { 408 static const char msg[] = "[dtn begin]\n"; 409 410 if (!log_ctx) { 411 pr_info("%s", msg); 412 return; 413 } 414 415 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); 416 } 417 418 __printf(3, 4) 419 void dm_dtn_log_append_v(struct dc_context *ctx, 420 struct dc_log_buffer_ctx *log_ctx, 421 const char *msg, ...) 422 { 423 va_list args; 424 size_t total; 425 int n; 426 427 if (!log_ctx) { 428 /* No context, redirect to dmesg. */ 429 struct va_format vaf; 430 431 vaf.fmt = msg; 432 vaf.va = &args; 433 434 va_start(args, msg); 435 pr_info("%pV", &vaf); 436 va_end(args); 437 438 return; 439 } 440 441 /* Measure the output. */ 442 va_start(args, msg); 443 n = vsnprintf(NULL, 0, msg, args); 444 va_end(args); 445 446 if (n <= 0) 447 return; 448 449 /* Reallocate the string buffer as needed. */ 450 total = log_ctx->pos + n + 1; 451 452 if (total > log_ctx->size) { 453 char *buf = kvcalloc(total, sizeof(char), GFP_KERNEL); 454 455 if (buf) { 456 memcpy(buf, log_ctx->buf, log_ctx->pos); 457 kfree(log_ctx->buf); 458 459 log_ctx->buf = buf; 460 log_ctx->size = total; 461 } 462 } 463 464 if (!log_ctx->buf) 465 return; 466 467 /* Write the formatted string to the log buffer. */ 468 va_start(args, msg); 469 n = vscnprintf( 470 log_ctx->buf + log_ctx->pos, 471 log_ctx->size - log_ctx->pos, 472 msg, 473 args); 474 va_end(args); 475 476 if (n > 0) 477 log_ctx->pos += n; 478 } 479 480 void dm_dtn_log_end(struct dc_context *ctx, 481 struct dc_log_buffer_ctx *log_ctx) 482 { 483 static const char msg[] = "[dtn end]\n"; 484 485 if (!log_ctx) { 486 pr_info("%s", msg); 487 return; 488 } 489 490 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); 491 } 492 493 bool dm_helpers_dp_mst_start_top_mgr( 494 struct dc_context *ctx, 495 const struct dc_link *link, 496 bool boot) 497 { 498 struct amdgpu_dm_connector *aconnector = link->priv; 499 int ret; 500 501 if (!aconnector) { 502 DRM_ERROR("Failed to find connector for link!"); 503 return false; 504 } 505 506 if (boot) { 507 DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n", 508 aconnector, aconnector->base.base.id); 509 return true; 510 } 511 512 DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n", 513 aconnector, aconnector->base.base.id); 514 515 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 516 if (ret < 0) { 517 DRM_ERROR("DM_MST: Failed to set the device into MST mode!"); 518 return false; 519 } 520 521 DRM_INFO("DM_MST: DP%x, %d-lane link detected\n", aconnector->mst_mgr.dpcd[0], 522 aconnector->mst_mgr.dpcd[2] & DP_MAX_LANE_COUNT_MASK); 523 524 return true; 525 } 526 527 bool dm_helpers_dp_mst_stop_top_mgr( 528 struct dc_context *ctx, 529 struct dc_link *link) 530 { 531 struct amdgpu_dm_connector *aconnector = link->priv; 532 533 if (!aconnector) { 534 DRM_ERROR("Failed to find connector for link!"); 535 return false; 536 } 537 538 DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n", 539 aconnector, aconnector->base.base.id); 540 541 if (aconnector->mst_mgr.mst_state == true) { 542 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false); 543 link->cur_link_settings.lane_count = 0; 544 } 545 546 return false; 547 } 548 549 bool dm_helpers_dp_read_dpcd( 550 struct dc_context *ctx, 551 const struct dc_link *link, 552 uint32_t address, 553 uint8_t *data, 554 uint32_t size) 555 { 556 557 struct amdgpu_dm_connector *aconnector = link->priv; 558 559 if (!aconnector) 560 return false; 561 562 return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address, data, 563 size) == size; 564 } 565 566 bool dm_helpers_dp_write_dpcd( 567 struct dc_context *ctx, 568 const struct dc_link *link, 569 uint32_t address, 570 const uint8_t *data, 571 uint32_t size) 572 { 573 struct amdgpu_dm_connector *aconnector = link->priv; 574 575 if (!aconnector) { 576 DRM_ERROR("Failed to find connector for link!"); 577 return false; 578 } 579 580 return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux, 581 address, (uint8_t *)data, size) > 0; 582 } 583 584 bool dm_helpers_submit_i2c( 585 struct dc_context *ctx, 586 const struct dc_link *link, 587 struct i2c_command *cmd) 588 { 589 struct amdgpu_dm_connector *aconnector = link->priv; 590 struct i2c_msg *msgs; 591 int i = 0; 592 int num = cmd->number_of_payloads; 593 bool result; 594 595 if (!aconnector) { 596 DRM_ERROR("Failed to find connector for link!"); 597 return false; 598 } 599 600 msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL); 601 602 if (!msgs) 603 return false; 604 605 for (i = 0; i < num; i++) { 606 msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD; 607 msgs[i].addr = cmd->payloads[i].address; 608 msgs[i].len = cmd->payloads[i].length; 609 msgs[i].buf = cmd->payloads[i].data; 610 } 611 612 result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num; 613 614 kfree(msgs); 615 616 return result; 617 } 618 619 static bool execute_synaptics_rc_command(struct drm_dp_aux *aux, 620 bool is_write_cmd, 621 unsigned char cmd, 622 unsigned int length, 623 unsigned int offset, 624 unsigned char *data) 625 { 626 bool success = false; 627 unsigned char rc_data[16] = {0}; 628 unsigned char rc_offset[4] = {0}; 629 unsigned char rc_length[2] = {0}; 630 unsigned char rc_cmd = 0; 631 unsigned char rc_result = 0xFF; 632 unsigned char i = 0; 633 int ret; 634 635 if (is_write_cmd) { 636 // write rc data 637 memmove(rc_data, data, length); 638 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_DATA, rc_data, sizeof(rc_data)); 639 } 640 641 // write rc offset 642 rc_offset[0] = (unsigned char) offset & 0xFF; 643 rc_offset[1] = (unsigned char) (offset >> 8) & 0xFF; 644 rc_offset[2] = (unsigned char) (offset >> 16) & 0xFF; 645 rc_offset[3] = (unsigned char) (offset >> 24) & 0xFF; 646 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_OFFSET, rc_offset, sizeof(rc_offset)); 647 648 // write rc length 649 rc_length[0] = (unsigned char) length & 0xFF; 650 rc_length[1] = (unsigned char) (length >> 8) & 0xFF; 651 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_LENGTH, rc_length, sizeof(rc_length)); 652 653 // write rc cmd 654 rc_cmd = cmd | 0x80; 655 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd)); 656 657 if (ret < 0) { 658 DRM_ERROR("%s: write cmd ..., err = %d\n", __func__, ret); 659 return false; 660 } 661 662 // poll until active is 0 663 for (i = 0; i < 10; i++) { 664 drm_dp_dpcd_read(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd)); 665 if (rc_cmd == cmd) 666 // active is 0 667 break; 668 msleep(10); 669 } 670 671 // read rc result 672 drm_dp_dpcd_read(aux, SYNAPTICS_RC_RESULT, &rc_result, sizeof(rc_result)); 673 success = (rc_result == 0); 674 675 if (success && !is_write_cmd) { 676 // read rc data 677 drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length); 678 } 679 680 drm_dbg_dp(aux->drm_dev, "success = %d\n", success); 681 682 return success; 683 } 684 685 static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux) 686 { 687 unsigned char data[16] = {0}; 688 689 drm_dbg_dp(aux->drm_dev, "Start\n"); 690 691 // Step 2 692 data[0] = 'P'; 693 data[1] = 'R'; 694 data[2] = 'I'; 695 data[3] = 'U'; 696 data[4] = 'S'; 697 698 if (!execute_synaptics_rc_command(aux, true, 0x01, 5, 0, data)) 699 return; 700 701 // Step 3 and 4 702 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data)) 703 return; 704 705 data[0] &= (~(1 << 1)); // set bit 1 to 0 706 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data)) 707 return; 708 709 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data)) 710 return; 711 712 data[0] &= (~(1 << 1)); // set bit 1 to 0 713 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220D98, data)) 714 return; 715 716 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data)) 717 return; 718 719 data[0] &= (~(1 << 1)); // set bit 1 to 0 720 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data)) 721 return; 722 723 // Step 3 and 5 724 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data)) 725 return; 726 727 data[0] |= (1 << 1); // set bit 1 to 1 728 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data)) 729 return; 730 731 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data)) 732 return; 733 734 data[0] |= (1 << 1); // set bit 1 to 1 735 736 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data)) 737 return; 738 739 data[0] |= (1 << 1); // set bit 1 to 1 740 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data)) 741 return; 742 743 // Step 6 744 if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL)) 745 return; 746 747 drm_dbg_dp(aux->drm_dev, "Done\n"); 748 } 749 750 /* MST Dock */ 751 static const uint8_t SYNAPTICS_DEVICE_ID[] = "SYNA"; 752 753 static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst( 754 struct drm_dp_aux *aux, 755 const struct dc_stream_state *stream, 756 bool enable) 757 { 758 uint8_t ret = 0; 759 760 drm_dbg_dp(aux->drm_dev, 761 "Configure DSC to non-virtual dpcd synaptics\n"); 762 763 if (enable) { 764 /* When DSC is enabled on previous boot and reboot with the hub, 765 * there is a chance that Synaptics hub gets stuck during reboot sequence. 766 * Applying a workaround to reset Synaptics SDP fifo before enabling the first stream 767 */ 768 if (!stream->link->link_status.link_active && 769 memcmp(stream->link->dpcd_caps.branch_dev_name, 770 (int8_t *)SYNAPTICS_DEVICE_ID, 4) == 0) 771 apply_synaptics_fifo_reset_wa(aux); 772 773 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1); 774 DRM_INFO("Send DSC enable to synaptics\n"); 775 776 } else { 777 /* Synaptics hub not support virtual dpcd, 778 * external monitor occur garbage while disable DSC, 779 * Disable DSC only when entire link status turn to false, 780 */ 781 if (!stream->link->link_status.link_active) { 782 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1); 783 DRM_INFO("Send DSC disable to synaptics\n"); 784 } 785 } 786 787 return ret; 788 } 789 790 bool dm_helpers_dp_write_dsc_enable( 791 struct dc_context *ctx, 792 const struct dc_stream_state *stream, 793 bool enable) 794 { 795 static const uint8_t DSC_DISABLE; 796 static const uint8_t DSC_DECODING = 0x01; 797 static const uint8_t DSC_PASSTHROUGH = 0x02; 798 799 struct amdgpu_dm_connector *aconnector = 800 (struct amdgpu_dm_connector *)stream->dm_stream_context; 801 struct drm_device *dev = aconnector->base.dev; 802 struct drm_dp_mst_port *port; 803 uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE; 804 uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE; 805 uint8_t ret = 0; 806 807 if (!stream) 808 return false; 809 810 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 811 if (!aconnector->dsc_aux) 812 return false; 813 814 // apply w/a to synaptics 815 if (needs_dsc_aux_workaround(aconnector->dc_link) && 816 (aconnector->mst_downstream_port_present.byte & 0x7) != 0x3) 817 return write_dsc_enable_synaptics_non_virtual_dpcd_mst( 818 aconnector->dsc_aux, stream, enable_dsc); 819 820 port = aconnector->mst_output_port; 821 822 if (enable) { 823 if (port->passthrough_aux) { 824 ret = drm_dp_dpcd_write(port->passthrough_aux, 825 DP_DSC_ENABLE, 826 &enable_passthrough, 1); 827 drm_dbg_dp(dev, 828 "Sent DSC pass-through enable to virtual dpcd port, ret = %u\n", 829 ret); 830 } 831 832 ret = drm_dp_dpcd_write(aconnector->dsc_aux, 833 DP_DSC_ENABLE, &enable_dsc, 1); 834 drm_dbg_dp(dev, 835 "Sent DSC decoding enable to %s port, ret = %u\n", 836 (port->passthrough_aux) ? "remote RX" : 837 "virtual dpcd", 838 ret); 839 } else { 840 ret = drm_dp_dpcd_write(aconnector->dsc_aux, 841 DP_DSC_ENABLE, &enable_dsc, 1); 842 drm_dbg_dp(dev, 843 "Sent DSC decoding disable to %s port, ret = %u\n", 844 (port->passthrough_aux) ? "remote RX" : 845 "virtual dpcd", 846 ret); 847 848 if (port->passthrough_aux) { 849 ret = drm_dp_dpcd_write(port->passthrough_aux, 850 DP_DSC_ENABLE, 851 &enable_passthrough, 1); 852 drm_dbg_dp(dev, 853 "Sent DSC pass-through disable to virtual dpcd port, ret = %u\n", 854 ret); 855 } 856 } 857 } 858 859 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) { 860 if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { 861 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); 862 drm_dbg_dp(dev, 863 "Send DSC %s to SST RX\n", 864 enable_dsc ? "enable" : "disable"); 865 } else if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { 866 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); 867 drm_dbg_dp(dev, 868 "Send DSC %s to DP-HDMI PCON\n", 869 enable_dsc ? "enable" : "disable"); 870 } 871 } 872 873 return ret; 874 } 875 876 bool dm_helpers_is_dp_sink_present(struct dc_link *link) 877 { 878 bool dp_sink_present; 879 struct amdgpu_dm_connector *aconnector = link->priv; 880 881 if (!aconnector) { 882 BUG_ON("Failed to find connector for link!"); 883 return true; 884 } 885 886 mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex); 887 dp_sink_present = dc_link_is_dp_sink_present(link); 888 mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex); 889 return dp_sink_present; 890 } 891 892 enum dc_edid_status dm_helpers_read_local_edid( 893 struct dc_context *ctx, 894 struct dc_link *link, 895 struct dc_sink *sink) 896 { 897 struct amdgpu_dm_connector *aconnector = link->priv; 898 struct drm_connector *connector = &aconnector->base; 899 struct i2c_adapter *ddc; 900 int retry = 3; 901 enum dc_edid_status edid_status; 902 struct edid *edid; 903 904 if (link->aux_mode) 905 ddc = &aconnector->dm_dp_aux.aux.ddc; 906 else 907 ddc = &aconnector->i2c->base; 908 909 /* some dongles read edid incorrectly the first time, 910 * do check sum and retry to make sure read correct edid. 911 */ 912 do { 913 914 edid = drm_get_edid(&aconnector->base, ddc); 915 916 /* DP Compliance Test 4.2.2.6 */ 917 if (link->aux_mode && connector->edid_corrupt) 918 drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum); 919 920 if (!edid && connector->edid_corrupt) { 921 connector->edid_corrupt = false; 922 return EDID_BAD_CHECKSUM; 923 } 924 925 if (!edid) 926 return EDID_NO_RESPONSE; 927 928 sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1); 929 memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length); 930 931 /* We don't need the original edid anymore */ 932 kfree(edid); 933 934 edid_status = dm_helpers_parse_edid_caps( 935 link, 936 &sink->dc_edid, 937 &sink->edid_caps); 938 939 } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0); 940 941 if (edid_status != EDID_OK) 942 DRM_ERROR("EDID err: %d, on connector: %s", 943 edid_status, 944 aconnector->base.name); 945 if (link->aux_mode) { 946 union test_request test_request = {0}; 947 union test_response test_response = {0}; 948 949 dm_helpers_dp_read_dpcd(ctx, 950 link, 951 DP_TEST_REQUEST, 952 &test_request.raw, 953 sizeof(union test_request)); 954 955 if (!test_request.bits.EDID_READ) 956 return edid_status; 957 958 test_response.bits.EDID_CHECKSUM_WRITE = 1; 959 960 dm_helpers_dp_write_dpcd(ctx, 961 link, 962 DP_TEST_EDID_CHECKSUM, 963 &sink->dc_edid.raw_edid[sink->dc_edid.length-1], 964 1); 965 966 dm_helpers_dp_write_dpcd(ctx, 967 link, 968 DP_TEST_RESPONSE, 969 &test_response.raw, 970 sizeof(test_response)); 971 972 } 973 974 return edid_status; 975 } 976 int dm_helper_dmub_aux_transfer_sync( 977 struct dc_context *ctx, 978 const struct dc_link *link, 979 struct aux_payload *payload, 980 enum aux_return_code_type *operation_result) 981 { 982 if (!link->hpd_status) { 983 *operation_result = AUX_RET_ERROR_HPD_DISCON; 984 return -1; 985 } 986 987 return amdgpu_dm_process_dmub_aux_transfer_sync(ctx, link->link_index, payload, 988 operation_result); 989 } 990 991 int dm_helpers_dmub_set_config_sync(struct dc_context *ctx, 992 const struct dc_link *link, 993 struct set_config_cmd_payload *payload, 994 enum set_config_status *operation_result) 995 { 996 return amdgpu_dm_process_dmub_set_config_sync(ctx, link->link_index, payload, 997 operation_result); 998 } 999 1000 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks) 1001 { 1002 /* TODO: something */ 1003 } 1004 1005 void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us) 1006 { 1007 // TODO: 1008 //amdgpu_device_gpu_recover(dc_context->driver-context, NULL); 1009 } 1010 1011 void dm_helpers_init_panel_settings( 1012 struct dc_context *ctx, 1013 struct dc_panel_config *panel_config, 1014 struct dc_sink *sink) 1015 { 1016 // Extra Panel Power Sequence 1017 panel_config->pps.extra_t3_ms = sink->edid_caps.panel_patch.extra_t3_ms; 1018 panel_config->pps.extra_t7_ms = sink->edid_caps.panel_patch.extra_t7_ms; 1019 panel_config->pps.extra_delay_backlight_off = sink->edid_caps.panel_patch.extra_delay_backlight_off; 1020 panel_config->pps.extra_post_t7_ms = 0; 1021 panel_config->pps.extra_pre_t11_ms = 0; 1022 panel_config->pps.extra_t12_ms = sink->edid_caps.panel_patch.extra_t12_ms; 1023 panel_config->pps.extra_post_OUI_ms = 0; 1024 // Feature DSC 1025 panel_config->dsc.disable_dsc_edp = false; 1026 panel_config->dsc.force_dsc_edp_policy = 0; 1027 } 1028 1029 void dm_helpers_override_panel_settings( 1030 struct dc_context *ctx, 1031 struct dc_panel_config *panel_config) 1032 { 1033 // Feature DSC 1034 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) 1035 panel_config->dsc.disable_dsc_edp = true; 1036 } 1037 1038 void *dm_helpers_allocate_gpu_mem( 1039 struct dc_context *ctx, 1040 enum dc_gpu_mem_alloc_type type, 1041 size_t size, 1042 long long *addr) 1043 { 1044 struct amdgpu_device *adev = ctx->driver_context; 1045 struct dal_allocation *da; 1046 u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ? 1047 AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM; 1048 int ret; 1049 1050 da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL); 1051 if (!da) 1052 return NULL; 1053 1054 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 1055 domain, &da->bo, 1056 &da->gpu_addr, &da->cpu_ptr); 1057 1058 *addr = da->gpu_addr; 1059 1060 if (ret) { 1061 kfree(da); 1062 return NULL; 1063 } 1064 1065 /* add da to list in dm */ 1066 list_add(&da->list, &adev->dm.da_list); 1067 1068 return da->cpu_ptr; 1069 } 1070 1071 void dm_helpers_free_gpu_mem( 1072 struct dc_context *ctx, 1073 enum dc_gpu_mem_alloc_type type, 1074 void *pvMem) 1075 { 1076 struct amdgpu_device *adev = ctx->driver_context; 1077 struct dal_allocation *da; 1078 1079 /* walk the da list in DM */ 1080 list_for_each_entry(da, &adev->dm.da_list, list) { 1081 if (pvMem == da->cpu_ptr) { 1082 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); 1083 list_del(&da->list); 1084 kfree(da); 1085 break; 1086 } 1087 } 1088 } 1089 1090 bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable) 1091 { 1092 enum dc_irq_source irq_source; 1093 bool ret; 1094 1095 irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX; 1096 1097 ret = dc_interrupt_set(ctx->dc, irq_source, enable); 1098 1099 DRM_DEBUG_DRIVER("Dmub trace irq %sabling: r=%d\n", 1100 enable ? "en" : "dis", ret); 1101 return ret; 1102 } 1103 1104 void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream) 1105 { 1106 /* TODO: virtual DPCD */ 1107 struct dc_link *link = stream->link; 1108 union down_spread_ctrl old_downspread; 1109 union down_spread_ctrl new_downspread; 1110 1111 if (link->aux_access_disabled) 1112 return; 1113 1114 if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL, 1115 &old_downspread.raw, 1116 sizeof(old_downspread))) 1117 return; 1118 1119 new_downspread.raw = old_downspread.raw; 1120 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 1121 (stream->ignore_msa_timing_param) ? 1 : 0; 1122 1123 if (new_downspread.raw != old_downspread.raw) 1124 dm_helpers_dp_write_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL, 1125 &new_downspread.raw, 1126 sizeof(new_downspread)); 1127 } 1128 1129 bool dm_helpers_dp_handle_test_pattern_request( 1130 struct dc_context *ctx, 1131 const struct dc_link *link, 1132 union link_test_pattern dpcd_test_pattern, 1133 union test_misc dpcd_test_params) 1134 { 1135 enum dp_test_pattern test_pattern; 1136 enum dp_test_pattern_color_space test_pattern_color_space = 1137 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED; 1138 enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED; 1139 enum dc_pixel_encoding requestPixelEncoding = PIXEL_ENCODING_UNDEFINED; 1140 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; 1141 struct pipe_ctx *pipe_ctx = NULL; 1142 struct amdgpu_dm_connector *aconnector = link->priv; 1143 struct drm_device *dev = aconnector->base.dev; 1144 int i; 1145 1146 for (i = 0; i < MAX_PIPES; i++) { 1147 if (pipes[i].stream == NULL) 1148 continue; 1149 1150 if (pipes[i].stream->link == link && !pipes[i].top_pipe && 1151 !pipes[i].prev_odm_pipe) { 1152 pipe_ctx = &pipes[i]; 1153 break; 1154 } 1155 } 1156 1157 if (pipe_ctx == NULL) 1158 return false; 1159 1160 switch (dpcd_test_pattern.bits.PATTERN) { 1161 case LINK_TEST_PATTERN_COLOR_RAMP: 1162 test_pattern = DP_TEST_PATTERN_COLOR_RAMP; 1163 break; 1164 case LINK_TEST_PATTERN_VERTICAL_BARS: 1165 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS; 1166 break; /* black and white */ 1167 case LINK_TEST_PATTERN_COLOR_SQUARES: 1168 test_pattern = (dpcd_test_params.bits.DYN_RANGE == 1169 TEST_DYN_RANGE_VESA ? 1170 DP_TEST_PATTERN_COLOR_SQUARES : 1171 DP_TEST_PATTERN_COLOR_SQUARES_CEA); 1172 break; 1173 default: 1174 test_pattern = DP_TEST_PATTERN_VIDEO_MODE; 1175 break; 1176 } 1177 1178 if (dpcd_test_params.bits.CLR_FORMAT == 0) 1179 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB; 1180 else 1181 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ? 1182 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 : 1183 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601; 1184 1185 switch (dpcd_test_params.bits.BPC) { 1186 case 0: // 6 bits 1187 requestColorDepth = COLOR_DEPTH_666; 1188 break; 1189 case 1: // 8 bits 1190 requestColorDepth = COLOR_DEPTH_888; 1191 break; 1192 case 2: // 10 bits 1193 requestColorDepth = COLOR_DEPTH_101010; 1194 break; 1195 case 3: // 12 bits 1196 requestColorDepth = COLOR_DEPTH_121212; 1197 break; 1198 default: 1199 break; 1200 } 1201 1202 switch (dpcd_test_params.bits.CLR_FORMAT) { 1203 case 0: 1204 requestPixelEncoding = PIXEL_ENCODING_RGB; 1205 break; 1206 case 1: 1207 requestPixelEncoding = PIXEL_ENCODING_YCBCR422; 1208 break; 1209 case 2: 1210 requestPixelEncoding = PIXEL_ENCODING_YCBCR444; 1211 break; 1212 default: 1213 requestPixelEncoding = PIXEL_ENCODING_RGB; 1214 break; 1215 } 1216 1217 if ((requestColorDepth != COLOR_DEPTH_UNDEFINED 1218 && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) 1219 || (requestPixelEncoding != PIXEL_ENCODING_UNDEFINED 1220 && pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) { 1221 drm_dbg(dev, 1222 "original bpc %d pix encoding %d, changing to %d %d\n", 1223 pipe_ctx->stream->timing.display_color_depth, 1224 pipe_ctx->stream->timing.pixel_encoding, 1225 requestColorDepth, 1226 requestPixelEncoding); 1227 pipe_ctx->stream->timing.display_color_depth = requestColorDepth; 1228 pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding; 1229 1230 dc_link_update_dsc_config(pipe_ctx); 1231 1232 aconnector->timing_changed = true; 1233 /* store current timing */ 1234 if (aconnector->timing_requested) 1235 *aconnector->timing_requested = pipe_ctx->stream->timing; 1236 else 1237 drm_err(dev, "timing storage failed\n"); 1238 1239 } 1240 1241 pipe_ctx->stream->test_pattern.type = test_pattern; 1242 pipe_ctx->stream->test_pattern.color_space = test_pattern_color_space; 1243 1244 dc_link_dp_set_test_pattern( 1245 (struct dc_link *) link, 1246 test_pattern, 1247 test_pattern_color_space, 1248 NULL, 1249 NULL, 1250 0); 1251 1252 return false; 1253 } 1254 1255 void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz) 1256 { 1257 // TODO 1258 } 1259 1260 void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable) 1261 { 1262 /* TODO: add periodic detection implementation */ 1263 } 1264 1265 void dm_helpers_dp_mst_update_branch_bandwidth( 1266 struct dc_context *ctx, 1267 struct dc_link *link) 1268 { 1269 // TODO 1270 } 1271 1272 static bool dm_is_freesync_pcon_whitelist(const uint32_t branch_dev_id) 1273 { 1274 bool ret_val = false; 1275 1276 switch (branch_dev_id) { 1277 case DP_BRANCH_DEVICE_ID_0060AD: 1278 case DP_BRANCH_DEVICE_ID_00E04C: 1279 case DP_BRANCH_DEVICE_ID_90CC24: 1280 ret_val = true; 1281 break; 1282 default: 1283 break; 1284 } 1285 1286 return ret_val; 1287 } 1288 1289 enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link) 1290 { 1291 struct dpcd_caps *dpcd_caps = &link->dpcd_caps; 1292 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; 1293 1294 switch (dpcd_caps->dongle_type) { 1295 case DISPLAY_DONGLE_DP_HDMI_CONVERTER: 1296 if (dpcd_caps->adaptive_sync_caps.dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT == true && 1297 dpcd_caps->allow_invalid_MSA_timing_param == true && 1298 dm_is_freesync_pcon_whitelist(dpcd_caps->branch_dev_id)) 1299 as_type = FREESYNC_TYPE_PCON_IN_WHITELIST; 1300 break; 1301 default: 1302 break; 1303 } 1304 1305 return as_type; 1306 } 1307