1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string.h> 27 #include <linux/acpi.h> 28 #include <linux/i2c.h> 29 30 #include <drm/drm_atomic.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/amdgpu_drm.h> 33 #include <drm/drm_edid.h> 34 35 #include "dm_services.h" 36 #include "amdgpu.h" 37 #include "dc.h" 38 #include "amdgpu_dm.h" 39 #include "amdgpu_dm_irq.h" 40 #include "amdgpu_dm_mst_types.h" 41 #include "dpcd_defs.h" 42 #include "dc/inc/core_types.h" 43 44 #include "dm_helpers.h" 45 #include "ddc_service_types.h" 46 47 static u32 edid_extract_panel_id(struct edid *edid) 48 { 49 return (u32)edid->mfg_id[0] << 24 | 50 (u32)edid->mfg_id[1] << 16 | 51 (u32)EDID_PRODUCT_ID(edid); 52 } 53 54 static void apply_edid_quirks(struct edid *edid, struct dc_edid_caps *edid_caps) 55 { 56 uint32_t panel_id = edid_extract_panel_id(edid); 57 58 switch (panel_id) { 59 /* Workaround for some monitors which does not work well with FAMS */ 60 case drm_edid_encode_panel_id('S', 'A', 'M', 0x0E5E): 61 case drm_edid_encode_panel_id('S', 'A', 'M', 0x7053): 62 case drm_edid_encode_panel_id('S', 'A', 'M', 0x71AC): 63 DRM_DEBUG_DRIVER("Disabling FAMS on monitor with panel id %X\n", panel_id); 64 edid_caps->panel_patch.disable_fams = true; 65 break; 66 default: 67 return; 68 } 69 } 70 71 /** 72 * dm_helpers_parse_edid_caps() - Parse edid caps 73 * 74 * @link: current detected link 75 * @edid: [in] pointer to edid 76 * @edid_caps: [in] pointer to edid caps 77 * 78 * Return: void 79 */ 80 enum dc_edid_status dm_helpers_parse_edid_caps( 81 struct dc_link *link, 82 const struct dc_edid *edid, 83 struct dc_edid_caps *edid_caps) 84 { 85 struct amdgpu_dm_connector *aconnector = link->priv; 86 struct drm_connector *connector = &aconnector->base; 87 struct edid *edid_buf = edid ? (struct edid *) edid->raw_edid : NULL; 88 struct cea_sad *sads; 89 int sad_count = -1; 90 int sadb_count = -1; 91 int i = 0; 92 uint8_t *sadb = NULL; 93 94 enum dc_edid_status result = EDID_OK; 95 96 if (!edid_caps || !edid) 97 return EDID_BAD_INPUT; 98 99 if (!drm_edid_is_valid(edid_buf)) 100 result = EDID_BAD_CHECKSUM; 101 102 edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] | 103 ((uint16_t) edid_buf->mfg_id[1])<<8; 104 edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] | 105 ((uint16_t) edid_buf->prod_code[1])<<8; 106 edid_caps->serial_number = edid_buf->serial; 107 edid_caps->manufacture_week = edid_buf->mfg_week; 108 edid_caps->manufacture_year = edid_buf->mfg_year; 109 110 drm_edid_get_monitor_name(edid_buf, 111 edid_caps->display_name, 112 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 113 114 edid_caps->edid_hdmi = connector->display_info.is_hdmi; 115 116 sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads); 117 if (sad_count <= 0) 118 return result; 119 120 edid_caps->audio_mode_count = min(sad_count, DC_MAX_AUDIO_DESC_COUNT); 121 for (i = 0; i < edid_caps->audio_mode_count; ++i) { 122 struct cea_sad *sad = &sads[i]; 123 124 edid_caps->audio_modes[i].format_code = sad->format; 125 edid_caps->audio_modes[i].channel_count = sad->channels + 1; 126 edid_caps->audio_modes[i].sample_rate = sad->freq; 127 edid_caps->audio_modes[i].sample_size = sad->byte2; 128 } 129 130 sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb); 131 132 if (sadb_count < 0) { 133 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count); 134 sadb_count = 0; 135 } 136 137 if (sadb_count) 138 edid_caps->speaker_flags = sadb[0]; 139 else 140 edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION; 141 142 apply_edid_quirks(edid_buf, edid_caps); 143 144 kfree(sads); 145 kfree(sadb); 146 147 return result; 148 } 149 150 static void 151 fill_dc_mst_payload_table_from_drm(struct dc_link *link, 152 bool enable, 153 struct drm_dp_mst_atomic_payload *target_payload, 154 struct dc_dp_mst_stream_allocation_table *table) 155 { 156 struct dc_dp_mst_stream_allocation_table new_table = { 0 }; 157 struct dc_dp_mst_stream_allocation *sa; 158 struct link_mst_stream_allocation_table copy_of_link_table = 159 link->mst_stream_alloc_table; 160 161 int i; 162 int current_hw_table_stream_cnt = copy_of_link_table.stream_count; 163 struct link_mst_stream_allocation *dc_alloc; 164 165 /* TODO: refactor to set link->mst_stream_alloc_table directly if possible.*/ 166 if (enable) { 167 dc_alloc = 168 ©_of_link_table.stream_allocations[current_hw_table_stream_cnt]; 169 dc_alloc->vcp_id = target_payload->vcpi; 170 dc_alloc->slot_count = target_payload->time_slots; 171 } else { 172 for (i = 0; i < copy_of_link_table.stream_count; i++) { 173 dc_alloc = 174 ©_of_link_table.stream_allocations[i]; 175 176 if (dc_alloc->vcp_id == target_payload->vcpi) { 177 dc_alloc->vcp_id = 0; 178 dc_alloc->slot_count = 0; 179 break; 180 } 181 } 182 ASSERT(i != copy_of_link_table.stream_count); 183 } 184 185 /* Fill payload info*/ 186 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 187 dc_alloc = 188 ©_of_link_table.stream_allocations[i]; 189 if (dc_alloc->vcp_id > 0 && dc_alloc->slot_count > 0) { 190 sa = &new_table.stream_allocations[new_table.stream_count]; 191 sa->slot_count = dc_alloc->slot_count; 192 sa->vcp_id = dc_alloc->vcp_id; 193 new_table.stream_count++; 194 } 195 } 196 197 /* Overwrite the old table */ 198 *table = new_table; 199 } 200 201 void dm_helpers_dp_update_branch_info( 202 struct dc_context *ctx, 203 const struct dc_link *link) 204 {} 205 206 static void dm_helpers_construct_old_payload( 207 struct drm_dp_mst_topology_mgr *mgr, 208 struct drm_dp_mst_topology_state *mst_state, 209 struct drm_dp_mst_atomic_payload *new_payload, 210 struct drm_dp_mst_atomic_payload *old_payload) 211 { 212 struct drm_dp_mst_atomic_payload *pos; 213 int pbn_per_slot = mst_state->pbn_div; 214 u8 next_payload_vc_start = mgr->next_start_slot; 215 u8 payload_vc_start = new_payload->vc_start_slot; 216 u8 allocated_time_slots; 217 218 *old_payload = *new_payload; 219 220 /* Set correct time_slots/PBN of old payload. 221 * other fields (delete & dsc_enabled) in 222 * struct drm_dp_mst_atomic_payload are don't care fields 223 * while calling drm_dp_remove_payload_part2() 224 */ 225 list_for_each_entry(pos, &mst_state->payloads, next) { 226 if (pos != new_payload && 227 pos->vc_start_slot > payload_vc_start && 228 pos->vc_start_slot < next_payload_vc_start) 229 next_payload_vc_start = pos->vc_start_slot; 230 } 231 232 allocated_time_slots = next_payload_vc_start - payload_vc_start; 233 234 old_payload->time_slots = allocated_time_slots; 235 old_payload->pbn = allocated_time_slots * pbn_per_slot; 236 } 237 238 /* 239 * Writes payload allocation table in immediate downstream device. 240 */ 241 bool dm_helpers_dp_mst_write_payload_allocation_table( 242 struct dc_context *ctx, 243 const struct dc_stream_state *stream, 244 struct dc_dp_mst_stream_allocation_table *proposed_table, 245 bool enable) 246 { 247 struct amdgpu_dm_connector *aconnector; 248 struct drm_dp_mst_topology_state *mst_state; 249 struct drm_dp_mst_atomic_payload *target_payload, *new_payload, old_payload; 250 struct drm_dp_mst_topology_mgr *mst_mgr; 251 252 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 253 /* Accessing the connector state is required for vcpi_slots allocation 254 * and directly relies on behaviour in commit check 255 * that blocks before commit guaranteeing that the state 256 * is not gonna be swapped while still in use in commit tail 257 */ 258 259 if (!aconnector || !aconnector->mst_root) 260 return false; 261 262 mst_mgr = &aconnector->mst_root->mst_mgr; 263 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); 264 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); 265 266 if (enable) { 267 target_payload = new_payload; 268 269 /* It's OK for this to fail */ 270 drm_dp_add_payload_part1(mst_mgr, mst_state, new_payload); 271 } else { 272 /* construct old payload by VCPI*/ 273 dm_helpers_construct_old_payload(mst_mgr, mst_state, 274 new_payload, &old_payload); 275 target_payload = &old_payload; 276 277 drm_dp_remove_payload_part1(mst_mgr, mst_state, new_payload); 278 } 279 280 /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or 281 * AUX message. The sequence is slot 1-63 allocated sequence for each 282 * stream. AMD ASIC stream slot allocation should follow the same 283 * sequence. copy DRM MST allocation to dc 284 */ 285 fill_dc_mst_payload_table_from_drm(stream->link, enable, target_payload, proposed_table); 286 287 return true; 288 } 289 290 /* 291 * poll pending down reply 292 */ 293 void dm_helpers_dp_mst_poll_pending_down_reply( 294 struct dc_context *ctx, 295 const struct dc_link *link) 296 {} 297 298 /* 299 * Clear payload allocation table before enable MST DP link. 300 */ 301 void dm_helpers_dp_mst_clear_payload_allocation_table( 302 struct dc_context *ctx, 303 const struct dc_link *link) 304 {} 305 306 /* 307 * Polls for ACT (allocation change trigger) handled and sends 308 * ALLOCATE_PAYLOAD message. 309 */ 310 enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger( 311 struct dc_context *ctx, 312 const struct dc_stream_state *stream) 313 { 314 struct amdgpu_dm_connector *aconnector; 315 struct drm_dp_mst_topology_mgr *mst_mgr; 316 int ret; 317 318 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 319 320 if (!aconnector || !aconnector->mst_root) 321 return ACT_FAILED; 322 323 mst_mgr = &aconnector->mst_root->mst_mgr; 324 325 if (!mst_mgr->mst_state) 326 return ACT_FAILED; 327 328 ret = drm_dp_check_act_status(mst_mgr); 329 330 if (ret) 331 return ACT_FAILED; 332 333 return ACT_SUCCESS; 334 } 335 336 bool dm_helpers_dp_mst_send_payload_allocation( 337 struct dc_context *ctx, 338 const struct dc_stream_state *stream, 339 bool enable) 340 { 341 struct amdgpu_dm_connector *aconnector; 342 struct drm_dp_mst_topology_state *mst_state; 343 struct drm_dp_mst_topology_mgr *mst_mgr; 344 struct drm_dp_mst_atomic_payload *new_payload, old_payload; 345 enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD; 346 enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD; 347 int ret = 0; 348 349 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 350 351 if (!aconnector || !aconnector->mst_root) 352 return false; 353 354 mst_mgr = &aconnector->mst_root->mst_mgr; 355 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); 356 357 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); 358 359 if (!enable) { 360 set_flag = MST_CLEAR_ALLOCATED_PAYLOAD; 361 clr_flag = MST_ALLOCATE_NEW_PAYLOAD; 362 } 363 364 if (enable) { 365 ret = drm_dp_add_payload_part2(mst_mgr, mst_state->base.state, new_payload); 366 } else { 367 dm_helpers_construct_old_payload(mst_mgr, mst_state, 368 new_payload, &old_payload); 369 drm_dp_remove_payload_part2(mst_mgr, mst_state, &old_payload, new_payload); 370 } 371 372 if (ret) { 373 amdgpu_dm_set_mst_status(&aconnector->mst_status, 374 set_flag, false); 375 } else { 376 amdgpu_dm_set_mst_status(&aconnector->mst_status, 377 set_flag, true); 378 amdgpu_dm_set_mst_status(&aconnector->mst_status, 379 clr_flag, false); 380 } 381 382 return true; 383 } 384 385 void dm_dtn_log_begin(struct dc_context *ctx, 386 struct dc_log_buffer_ctx *log_ctx) 387 { 388 static const char msg[] = "[dtn begin]\n"; 389 390 if (!log_ctx) { 391 pr_info("%s", msg); 392 return; 393 } 394 395 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); 396 } 397 398 __printf(3, 4) 399 void dm_dtn_log_append_v(struct dc_context *ctx, 400 struct dc_log_buffer_ctx *log_ctx, 401 const char *msg, ...) 402 { 403 va_list args; 404 size_t total; 405 int n; 406 407 if (!log_ctx) { 408 /* No context, redirect to dmesg. */ 409 struct va_format vaf; 410 411 vaf.fmt = msg; 412 vaf.va = &args; 413 414 va_start(args, msg); 415 pr_info("%pV", &vaf); 416 va_end(args); 417 418 return; 419 } 420 421 /* Measure the output. */ 422 va_start(args, msg); 423 n = vsnprintf(NULL, 0, msg, args); 424 va_end(args); 425 426 if (n <= 0) 427 return; 428 429 /* Reallocate the string buffer as needed. */ 430 total = log_ctx->pos + n + 1; 431 432 if (total > log_ctx->size) { 433 char *buf = kvcalloc(total, sizeof(char), GFP_KERNEL); 434 435 if (buf) { 436 memcpy(buf, log_ctx->buf, log_ctx->pos); 437 kfree(log_ctx->buf); 438 439 log_ctx->buf = buf; 440 log_ctx->size = total; 441 } 442 } 443 444 if (!log_ctx->buf) 445 return; 446 447 /* Write the formatted string to the log buffer. */ 448 va_start(args, msg); 449 n = vscnprintf( 450 log_ctx->buf + log_ctx->pos, 451 log_ctx->size - log_ctx->pos, 452 msg, 453 args); 454 va_end(args); 455 456 if (n > 0) 457 log_ctx->pos += n; 458 } 459 460 void dm_dtn_log_end(struct dc_context *ctx, 461 struct dc_log_buffer_ctx *log_ctx) 462 { 463 static const char msg[] = "[dtn end]\n"; 464 465 if (!log_ctx) { 466 pr_info("%s", msg); 467 return; 468 } 469 470 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); 471 } 472 473 bool dm_helpers_dp_mst_start_top_mgr( 474 struct dc_context *ctx, 475 const struct dc_link *link, 476 bool boot) 477 { 478 struct amdgpu_dm_connector *aconnector = link->priv; 479 int ret; 480 481 if (!aconnector) { 482 DRM_ERROR("Failed to find connector for link!"); 483 return false; 484 } 485 486 if (boot) { 487 DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n", 488 aconnector, aconnector->base.base.id); 489 return true; 490 } 491 492 DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n", 493 aconnector, aconnector->base.base.id); 494 495 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 496 if (ret < 0) { 497 DRM_ERROR("DM_MST: Failed to set the device into MST mode!"); 498 return false; 499 } 500 501 DRM_INFO("DM_MST: DP%x, %d-lane link detected\n", aconnector->mst_mgr.dpcd[0], 502 aconnector->mst_mgr.dpcd[2] & DP_MAX_LANE_COUNT_MASK); 503 504 return true; 505 } 506 507 bool dm_helpers_dp_mst_stop_top_mgr( 508 struct dc_context *ctx, 509 struct dc_link *link) 510 { 511 struct amdgpu_dm_connector *aconnector = link->priv; 512 513 if (!aconnector) { 514 DRM_ERROR("Failed to find connector for link!"); 515 return false; 516 } 517 518 DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n", 519 aconnector, aconnector->base.base.id); 520 521 if (aconnector->mst_mgr.mst_state == true) { 522 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false); 523 link->cur_link_settings.lane_count = 0; 524 } 525 526 return false; 527 } 528 529 bool dm_helpers_dp_read_dpcd( 530 struct dc_context *ctx, 531 const struct dc_link *link, 532 uint32_t address, 533 uint8_t *data, 534 uint32_t size) 535 { 536 537 struct amdgpu_dm_connector *aconnector = link->priv; 538 539 if (!aconnector) 540 return false; 541 542 return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address, data, 543 size) == size; 544 } 545 546 bool dm_helpers_dp_write_dpcd( 547 struct dc_context *ctx, 548 const struct dc_link *link, 549 uint32_t address, 550 const uint8_t *data, 551 uint32_t size) 552 { 553 struct amdgpu_dm_connector *aconnector = link->priv; 554 555 if (!aconnector) { 556 DRM_ERROR("Failed to find connector for link!"); 557 return false; 558 } 559 560 return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux, 561 address, (uint8_t *)data, size) > 0; 562 } 563 564 bool dm_helpers_submit_i2c( 565 struct dc_context *ctx, 566 const struct dc_link *link, 567 struct i2c_command *cmd) 568 { 569 struct amdgpu_dm_connector *aconnector = link->priv; 570 struct i2c_msg *msgs; 571 int i = 0; 572 int num = cmd->number_of_payloads; 573 bool result; 574 575 if (!aconnector) { 576 DRM_ERROR("Failed to find connector for link!"); 577 return false; 578 } 579 580 msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL); 581 582 if (!msgs) 583 return false; 584 585 for (i = 0; i < num; i++) { 586 msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD; 587 msgs[i].addr = cmd->payloads[i].address; 588 msgs[i].len = cmd->payloads[i].length; 589 msgs[i].buf = cmd->payloads[i].data; 590 } 591 592 result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num; 593 594 kfree(msgs); 595 596 return result; 597 } 598 599 static bool execute_synaptics_rc_command(struct drm_dp_aux *aux, 600 bool is_write_cmd, 601 unsigned char cmd, 602 unsigned int length, 603 unsigned int offset, 604 unsigned char *data) 605 { 606 bool success = false; 607 unsigned char rc_data[16] = {0}; 608 unsigned char rc_offset[4] = {0}; 609 unsigned char rc_length[2] = {0}; 610 unsigned char rc_cmd = 0; 611 unsigned char rc_result = 0xFF; 612 unsigned char i = 0; 613 int ret; 614 615 if (is_write_cmd) { 616 // write rc data 617 memmove(rc_data, data, length); 618 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_DATA, rc_data, sizeof(rc_data)); 619 } 620 621 // write rc offset 622 rc_offset[0] = (unsigned char) offset & 0xFF; 623 rc_offset[1] = (unsigned char) (offset >> 8) & 0xFF; 624 rc_offset[2] = (unsigned char) (offset >> 16) & 0xFF; 625 rc_offset[3] = (unsigned char) (offset >> 24) & 0xFF; 626 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_OFFSET, rc_offset, sizeof(rc_offset)); 627 628 // write rc length 629 rc_length[0] = (unsigned char) length & 0xFF; 630 rc_length[1] = (unsigned char) (length >> 8) & 0xFF; 631 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_LENGTH, rc_length, sizeof(rc_length)); 632 633 // write rc cmd 634 rc_cmd = cmd | 0x80; 635 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd)); 636 637 if (ret < 0) { 638 DRM_ERROR("%s: write cmd ..., err = %d\n", __func__, ret); 639 return false; 640 } 641 642 // poll until active is 0 643 for (i = 0; i < 10; i++) { 644 drm_dp_dpcd_read(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd)); 645 if (rc_cmd == cmd) 646 // active is 0 647 break; 648 msleep(10); 649 } 650 651 // read rc result 652 drm_dp_dpcd_read(aux, SYNAPTICS_RC_RESULT, &rc_result, sizeof(rc_result)); 653 success = (rc_result == 0); 654 655 if (success && !is_write_cmd) { 656 // read rc data 657 drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length); 658 } 659 660 drm_dbg_dp(aux->drm_dev, "success = %d\n", success); 661 662 return success; 663 } 664 665 static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux) 666 { 667 unsigned char data[16] = {0}; 668 669 drm_dbg_dp(aux->drm_dev, "Start\n"); 670 671 // Step 2 672 data[0] = 'P'; 673 data[1] = 'R'; 674 data[2] = 'I'; 675 data[3] = 'U'; 676 data[4] = 'S'; 677 678 if (!execute_synaptics_rc_command(aux, true, 0x01, 5, 0, data)) 679 return; 680 681 // Step 3 and 4 682 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data)) 683 return; 684 685 data[0] &= (~(1 << 1)); // set bit 1 to 0 686 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data)) 687 return; 688 689 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data)) 690 return; 691 692 data[0] &= (~(1 << 1)); // set bit 1 to 0 693 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220D98, data)) 694 return; 695 696 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data)) 697 return; 698 699 data[0] &= (~(1 << 1)); // set bit 1 to 0 700 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data)) 701 return; 702 703 // Step 3 and 5 704 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data)) 705 return; 706 707 data[0] |= (1 << 1); // set bit 1 to 1 708 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data)) 709 return; 710 711 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data)) 712 return; 713 714 data[0] |= (1 << 1); // set bit 1 to 1 715 716 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data)) 717 return; 718 719 data[0] |= (1 << 1); // set bit 1 to 1 720 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data)) 721 return; 722 723 // Step 6 724 if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL)) 725 return; 726 727 drm_dbg_dp(aux->drm_dev, "Done\n"); 728 } 729 730 /* MST Dock */ 731 static const uint8_t SYNAPTICS_DEVICE_ID[] = "SYNA"; 732 733 static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst( 734 struct drm_dp_aux *aux, 735 const struct dc_stream_state *stream, 736 bool enable) 737 { 738 uint8_t ret = 0; 739 740 drm_dbg_dp(aux->drm_dev, 741 "Configure DSC to non-virtual dpcd synaptics\n"); 742 743 if (enable) { 744 /* When DSC is enabled on previous boot and reboot with the hub, 745 * there is a chance that Synaptics hub gets stuck during reboot sequence. 746 * Applying a workaround to reset Synaptics SDP fifo before enabling the first stream 747 */ 748 if (!stream->link->link_status.link_active && 749 memcmp(stream->link->dpcd_caps.branch_dev_name, 750 (int8_t *)SYNAPTICS_DEVICE_ID, 4) == 0) 751 apply_synaptics_fifo_reset_wa(aux); 752 753 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1); 754 DRM_INFO("Send DSC enable to synaptics\n"); 755 756 } else { 757 /* Synaptics hub not support virtual dpcd, 758 * external monitor occur garbage while disable DSC, 759 * Disable DSC only when entire link status turn to false, 760 */ 761 if (!stream->link->link_status.link_active) { 762 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1); 763 DRM_INFO("Send DSC disable to synaptics\n"); 764 } 765 } 766 767 return ret; 768 } 769 770 bool dm_helpers_dp_write_dsc_enable( 771 struct dc_context *ctx, 772 const struct dc_stream_state *stream, 773 bool enable) 774 { 775 static const uint8_t DSC_DISABLE; 776 static const uint8_t DSC_DECODING = 0x01; 777 static const uint8_t DSC_PASSTHROUGH = 0x02; 778 779 struct amdgpu_dm_connector *aconnector = 780 (struct amdgpu_dm_connector *)stream->dm_stream_context; 781 struct drm_device *dev = aconnector->base.dev; 782 struct drm_dp_mst_port *port; 783 uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE; 784 uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE; 785 uint8_t ret = 0; 786 787 if (!stream) 788 return false; 789 790 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 791 if (!aconnector->dsc_aux) 792 return false; 793 794 // apply w/a to synaptics 795 if (needs_dsc_aux_workaround(aconnector->dc_link) && 796 (aconnector->mst_downstream_port_present.byte & 0x7) != 0x3) 797 return write_dsc_enable_synaptics_non_virtual_dpcd_mst( 798 aconnector->dsc_aux, stream, enable_dsc); 799 800 port = aconnector->mst_output_port; 801 802 if (enable) { 803 if (port->passthrough_aux) { 804 ret = drm_dp_dpcd_write(port->passthrough_aux, 805 DP_DSC_ENABLE, 806 &enable_passthrough, 1); 807 drm_dbg_dp(dev, 808 "Sent DSC pass-through enable to virtual dpcd port, ret = %u\n", 809 ret); 810 } 811 812 ret = drm_dp_dpcd_write(aconnector->dsc_aux, 813 DP_DSC_ENABLE, &enable_dsc, 1); 814 drm_dbg_dp(dev, 815 "Sent DSC decoding enable to %s port, ret = %u\n", 816 (port->passthrough_aux) ? "remote RX" : 817 "virtual dpcd", 818 ret); 819 } else { 820 ret = drm_dp_dpcd_write(aconnector->dsc_aux, 821 DP_DSC_ENABLE, &enable_dsc, 1); 822 drm_dbg_dp(dev, 823 "Sent DSC decoding disable to %s port, ret = %u\n", 824 (port->passthrough_aux) ? "remote RX" : 825 "virtual dpcd", 826 ret); 827 828 if (port->passthrough_aux) { 829 ret = drm_dp_dpcd_write(port->passthrough_aux, 830 DP_DSC_ENABLE, 831 &enable_passthrough, 1); 832 drm_dbg_dp(dev, 833 "Sent DSC pass-through disable to virtual dpcd port, ret = %u\n", 834 ret); 835 } 836 } 837 } 838 839 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) { 840 if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { 841 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); 842 drm_dbg_dp(dev, 843 "Send DSC %s to SST RX\n", 844 enable_dsc ? "enable" : "disable"); 845 } else if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { 846 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); 847 drm_dbg_dp(dev, 848 "Send DSC %s to DP-HDMI PCON\n", 849 enable_dsc ? "enable" : "disable"); 850 } 851 } 852 853 return ret; 854 } 855 856 bool dm_helpers_is_dp_sink_present(struct dc_link *link) 857 { 858 bool dp_sink_present; 859 struct amdgpu_dm_connector *aconnector = link->priv; 860 861 if (!aconnector) { 862 BUG_ON("Failed to find connector for link!"); 863 return true; 864 } 865 866 mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex); 867 dp_sink_present = dc_link_is_dp_sink_present(link); 868 mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex); 869 return dp_sink_present; 870 } 871 872 enum dc_edid_status dm_helpers_read_local_edid( 873 struct dc_context *ctx, 874 struct dc_link *link, 875 struct dc_sink *sink) 876 { 877 struct amdgpu_dm_connector *aconnector = link->priv; 878 struct drm_connector *connector = &aconnector->base; 879 struct i2c_adapter *ddc; 880 int retry = 3; 881 enum dc_edid_status edid_status; 882 struct edid *edid; 883 884 if (link->aux_mode) 885 ddc = &aconnector->dm_dp_aux.aux.ddc; 886 else 887 ddc = &aconnector->i2c->base; 888 889 /* some dongles read edid incorrectly the first time, 890 * do check sum and retry to make sure read correct edid. 891 */ 892 do { 893 894 edid = drm_get_edid(&aconnector->base, ddc); 895 896 /* DP Compliance Test 4.2.2.6 */ 897 if (link->aux_mode && connector->edid_corrupt) 898 drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum); 899 900 if (!edid && connector->edid_corrupt) { 901 connector->edid_corrupt = false; 902 return EDID_BAD_CHECKSUM; 903 } 904 905 if (!edid) 906 return EDID_NO_RESPONSE; 907 908 sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1); 909 memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length); 910 911 /* We don't need the original edid anymore */ 912 kfree(edid); 913 914 edid_status = dm_helpers_parse_edid_caps( 915 link, 916 &sink->dc_edid, 917 &sink->edid_caps); 918 919 } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0); 920 921 if (edid_status != EDID_OK) 922 DRM_ERROR("EDID err: %d, on connector: %s", 923 edid_status, 924 aconnector->base.name); 925 if (link->aux_mode) { 926 union test_request test_request = {0}; 927 union test_response test_response = {0}; 928 929 dm_helpers_dp_read_dpcd(ctx, 930 link, 931 DP_TEST_REQUEST, 932 &test_request.raw, 933 sizeof(union test_request)); 934 935 if (!test_request.bits.EDID_READ) 936 return edid_status; 937 938 test_response.bits.EDID_CHECKSUM_WRITE = 1; 939 940 dm_helpers_dp_write_dpcd(ctx, 941 link, 942 DP_TEST_EDID_CHECKSUM, 943 &sink->dc_edid.raw_edid[sink->dc_edid.length-1], 944 1); 945 946 dm_helpers_dp_write_dpcd(ctx, 947 link, 948 DP_TEST_RESPONSE, 949 &test_response.raw, 950 sizeof(test_response)); 951 952 } 953 954 return edid_status; 955 } 956 int dm_helper_dmub_aux_transfer_sync( 957 struct dc_context *ctx, 958 const struct dc_link *link, 959 struct aux_payload *payload, 960 enum aux_return_code_type *operation_result) 961 { 962 return amdgpu_dm_process_dmub_aux_transfer_sync(ctx, link->link_index, payload, 963 operation_result); 964 } 965 966 int dm_helpers_dmub_set_config_sync(struct dc_context *ctx, 967 const struct dc_link *link, 968 struct set_config_cmd_payload *payload, 969 enum set_config_status *operation_result) 970 { 971 return amdgpu_dm_process_dmub_set_config_sync(ctx, link->link_index, payload, 972 operation_result); 973 } 974 975 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks) 976 { 977 /* TODO: something */ 978 } 979 980 void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us) 981 { 982 // TODO: 983 //amdgpu_device_gpu_recover(dc_context->driver-context, NULL); 984 } 985 986 void dm_helpers_init_panel_settings( 987 struct dc_context *ctx, 988 struct dc_panel_config *panel_config, 989 struct dc_sink *sink) 990 { 991 // Extra Panel Power Sequence 992 panel_config->pps.extra_t3_ms = sink->edid_caps.panel_patch.extra_t3_ms; 993 panel_config->pps.extra_t7_ms = sink->edid_caps.panel_patch.extra_t7_ms; 994 panel_config->pps.extra_delay_backlight_off = sink->edid_caps.panel_patch.extra_delay_backlight_off; 995 panel_config->pps.extra_post_t7_ms = 0; 996 panel_config->pps.extra_pre_t11_ms = 0; 997 panel_config->pps.extra_t12_ms = sink->edid_caps.panel_patch.extra_t12_ms; 998 panel_config->pps.extra_post_OUI_ms = 0; 999 // Feature DSC 1000 panel_config->dsc.disable_dsc_edp = false; 1001 panel_config->dsc.force_dsc_edp_policy = 0; 1002 } 1003 1004 void dm_helpers_override_panel_settings( 1005 struct dc_context *ctx, 1006 struct dc_panel_config *panel_config) 1007 { 1008 // Feature DSC 1009 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) 1010 panel_config->dsc.disable_dsc_edp = true; 1011 } 1012 1013 void *dm_helpers_allocate_gpu_mem( 1014 struct dc_context *ctx, 1015 enum dc_gpu_mem_alloc_type type, 1016 size_t size, 1017 long long *addr) 1018 { 1019 struct amdgpu_device *adev = ctx->driver_context; 1020 struct dal_allocation *da; 1021 u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ? 1022 AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM; 1023 int ret; 1024 1025 da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL); 1026 if (!da) 1027 return NULL; 1028 1029 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 1030 domain, &da->bo, 1031 &da->gpu_addr, &da->cpu_ptr); 1032 1033 *addr = da->gpu_addr; 1034 1035 if (ret) { 1036 kfree(da); 1037 return NULL; 1038 } 1039 1040 /* add da to list in dm */ 1041 list_add(&da->list, &adev->dm.da_list); 1042 1043 return da->cpu_ptr; 1044 } 1045 1046 void dm_helpers_free_gpu_mem( 1047 struct dc_context *ctx, 1048 enum dc_gpu_mem_alloc_type type, 1049 void *pvMem) 1050 { 1051 struct amdgpu_device *adev = ctx->driver_context; 1052 struct dal_allocation *da; 1053 1054 /* walk the da list in DM */ 1055 list_for_each_entry(da, &adev->dm.da_list, list) { 1056 if (pvMem == da->cpu_ptr) { 1057 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); 1058 list_del(&da->list); 1059 kfree(da); 1060 break; 1061 } 1062 } 1063 } 1064 1065 bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable) 1066 { 1067 enum dc_irq_source irq_source; 1068 bool ret; 1069 1070 irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX; 1071 1072 ret = dc_interrupt_set(ctx->dc, irq_source, enable); 1073 1074 DRM_DEBUG_DRIVER("Dmub trace irq %sabling: r=%d\n", 1075 enable ? "en" : "dis", ret); 1076 return ret; 1077 } 1078 1079 void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream) 1080 { 1081 /* TODO: virtual DPCD */ 1082 struct dc_link *link = stream->link; 1083 union down_spread_ctrl old_downspread; 1084 union down_spread_ctrl new_downspread; 1085 1086 if (link->aux_access_disabled) 1087 return; 1088 1089 if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL, 1090 &old_downspread.raw, 1091 sizeof(old_downspread))) 1092 return; 1093 1094 new_downspread.raw = old_downspread.raw; 1095 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 1096 (stream->ignore_msa_timing_param) ? 1 : 0; 1097 1098 if (new_downspread.raw != old_downspread.raw) 1099 dm_helpers_dp_write_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL, 1100 &new_downspread.raw, 1101 sizeof(new_downspread)); 1102 } 1103 1104 bool dm_helpers_dp_handle_test_pattern_request( 1105 struct dc_context *ctx, 1106 const struct dc_link *link, 1107 union link_test_pattern dpcd_test_pattern, 1108 union test_misc dpcd_test_params) 1109 { 1110 enum dp_test_pattern test_pattern; 1111 enum dp_test_pattern_color_space test_pattern_color_space = 1112 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED; 1113 enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED; 1114 enum dc_pixel_encoding requestPixelEncoding = PIXEL_ENCODING_UNDEFINED; 1115 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; 1116 struct pipe_ctx *pipe_ctx = NULL; 1117 struct amdgpu_dm_connector *aconnector = link->priv; 1118 struct drm_device *dev = aconnector->base.dev; 1119 int i; 1120 1121 for (i = 0; i < MAX_PIPES; i++) { 1122 if (pipes[i].stream == NULL) 1123 continue; 1124 1125 if (pipes[i].stream->link == link && !pipes[i].top_pipe && 1126 !pipes[i].prev_odm_pipe) { 1127 pipe_ctx = &pipes[i]; 1128 break; 1129 } 1130 } 1131 1132 if (pipe_ctx == NULL) 1133 return false; 1134 1135 switch (dpcd_test_pattern.bits.PATTERN) { 1136 case LINK_TEST_PATTERN_COLOR_RAMP: 1137 test_pattern = DP_TEST_PATTERN_COLOR_RAMP; 1138 break; 1139 case LINK_TEST_PATTERN_VERTICAL_BARS: 1140 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS; 1141 break; /* black and white */ 1142 case LINK_TEST_PATTERN_COLOR_SQUARES: 1143 test_pattern = (dpcd_test_params.bits.DYN_RANGE == 1144 TEST_DYN_RANGE_VESA ? 1145 DP_TEST_PATTERN_COLOR_SQUARES : 1146 DP_TEST_PATTERN_COLOR_SQUARES_CEA); 1147 break; 1148 default: 1149 test_pattern = DP_TEST_PATTERN_VIDEO_MODE; 1150 break; 1151 } 1152 1153 if (dpcd_test_params.bits.CLR_FORMAT == 0) 1154 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB; 1155 else 1156 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ? 1157 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 : 1158 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601; 1159 1160 switch (dpcd_test_params.bits.BPC) { 1161 case 0: // 6 bits 1162 requestColorDepth = COLOR_DEPTH_666; 1163 break; 1164 case 1: // 8 bits 1165 requestColorDepth = COLOR_DEPTH_888; 1166 break; 1167 case 2: // 10 bits 1168 requestColorDepth = COLOR_DEPTH_101010; 1169 break; 1170 case 3: // 12 bits 1171 requestColorDepth = COLOR_DEPTH_121212; 1172 break; 1173 default: 1174 break; 1175 } 1176 1177 switch (dpcd_test_params.bits.CLR_FORMAT) { 1178 case 0: 1179 requestPixelEncoding = PIXEL_ENCODING_RGB; 1180 break; 1181 case 1: 1182 requestPixelEncoding = PIXEL_ENCODING_YCBCR422; 1183 break; 1184 case 2: 1185 requestPixelEncoding = PIXEL_ENCODING_YCBCR444; 1186 break; 1187 default: 1188 requestPixelEncoding = PIXEL_ENCODING_RGB; 1189 break; 1190 } 1191 1192 if ((requestColorDepth != COLOR_DEPTH_UNDEFINED 1193 && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) 1194 || (requestPixelEncoding != PIXEL_ENCODING_UNDEFINED 1195 && pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) { 1196 drm_dbg(dev, 1197 "original bpc %d pix encoding %d, changing to %d %d\n", 1198 pipe_ctx->stream->timing.display_color_depth, 1199 pipe_ctx->stream->timing.pixel_encoding, 1200 requestColorDepth, 1201 requestPixelEncoding); 1202 pipe_ctx->stream->timing.display_color_depth = requestColorDepth; 1203 pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding; 1204 1205 dc_link_update_dsc_config(pipe_ctx); 1206 1207 aconnector->timing_changed = true; 1208 /* store current timing */ 1209 if (aconnector->timing_requested) 1210 *aconnector->timing_requested = pipe_ctx->stream->timing; 1211 else 1212 drm_err(dev, "timing storage failed\n"); 1213 1214 } 1215 1216 pipe_ctx->stream->test_pattern.type = test_pattern; 1217 pipe_ctx->stream->test_pattern.color_space = test_pattern_color_space; 1218 1219 dc_link_dp_set_test_pattern( 1220 (struct dc_link *) link, 1221 test_pattern, 1222 test_pattern_color_space, 1223 NULL, 1224 NULL, 1225 0); 1226 1227 return false; 1228 } 1229 1230 void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz) 1231 { 1232 // TODO 1233 } 1234 1235 void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable) 1236 { 1237 /* TODO: add periodic detection implementation */ 1238 } 1239 1240 void dm_helpers_dp_mst_update_branch_bandwidth( 1241 struct dc_context *ctx, 1242 struct dc_link *link) 1243 { 1244 // TODO 1245 } 1246 1247 static bool dm_is_freesync_pcon_whitelist(const uint32_t branch_dev_id) 1248 { 1249 bool ret_val = false; 1250 1251 switch (branch_dev_id) { 1252 case DP_BRANCH_DEVICE_ID_0060AD: 1253 case DP_BRANCH_DEVICE_ID_00E04C: 1254 case DP_BRANCH_DEVICE_ID_90CC24: 1255 ret_val = true; 1256 break; 1257 default: 1258 break; 1259 } 1260 1261 return ret_val; 1262 } 1263 1264 enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link) 1265 { 1266 struct dpcd_caps *dpcd_caps = &link->dpcd_caps; 1267 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; 1268 1269 switch (dpcd_caps->dongle_type) { 1270 case DISPLAY_DONGLE_DP_HDMI_CONVERTER: 1271 if (dpcd_caps->adaptive_sync_caps.dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT == true && 1272 dpcd_caps->allow_invalid_MSA_timing_param == true && 1273 dm_is_freesync_pcon_whitelist(dpcd_caps->branch_dev_id)) 1274 as_type = FREESYNC_TYPE_PCON_IN_WHITELIST; 1275 break; 1276 default: 1277 break; 1278 } 1279 1280 return as_type; 1281 } 1282