1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string.h> 27 #include <linux/acpi.h> 28 #include <linux/i2c.h> 29 30 #include <drm/drm_atomic.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/amdgpu_drm.h> 33 #include <drm/drm_edid.h> 34 35 #include "dm_services.h" 36 #include "amdgpu.h" 37 #include "dc.h" 38 #include "amdgpu_dm.h" 39 #include "amdgpu_dm_irq.h" 40 #include "amdgpu_dm_mst_types.h" 41 #include "dpcd_defs.h" 42 #include "dc/inc/core_types.h" 43 44 #include "dm_helpers.h" 45 #include "ddc_service_types.h" 46 47 static u32 edid_extract_panel_id(struct edid *edid) 48 { 49 return (u32)edid->mfg_id[0] << 24 | 50 (u32)edid->mfg_id[1] << 16 | 51 (u32)EDID_PRODUCT_ID(edid); 52 } 53 54 static void apply_edid_quirks(struct edid *edid, struct dc_edid_caps *edid_caps) 55 { 56 uint32_t panel_id = edid_extract_panel_id(edid); 57 58 switch (panel_id) { 59 /* Workaround for some monitors which does not work well with FAMS */ 60 case drm_edid_encode_panel_id('S', 'A', 'M', 0x0E5E): 61 case drm_edid_encode_panel_id('S', 'A', 'M', 0x7053): 62 case drm_edid_encode_panel_id('S', 'A', 'M', 0x71AC): 63 DRM_DEBUG_DRIVER("Disabling FAMS on monitor with panel id %X\n", panel_id); 64 edid_caps->panel_patch.disable_fams = true; 65 break; 66 default: 67 return; 68 } 69 } 70 71 /** 72 * dm_helpers_parse_edid_caps() - Parse edid caps 73 * 74 * @link: current detected link 75 * @edid: [in] pointer to edid 76 * @edid_caps: [in] pointer to edid caps 77 * 78 * Return: void 79 */ 80 enum dc_edid_status dm_helpers_parse_edid_caps( 81 struct dc_link *link, 82 const struct dc_edid *edid, 83 struct dc_edid_caps *edid_caps) 84 { 85 struct amdgpu_dm_connector *aconnector = link->priv; 86 struct drm_connector *connector = &aconnector->base; 87 struct edid *edid_buf = edid ? (struct edid *) edid->raw_edid : NULL; 88 struct cea_sad *sads; 89 int sad_count = -1; 90 int sadb_count = -1; 91 int i = 0; 92 uint8_t *sadb = NULL; 93 94 enum dc_edid_status result = EDID_OK; 95 96 if (!edid_caps || !edid) 97 return EDID_BAD_INPUT; 98 99 if (!drm_edid_is_valid(edid_buf)) 100 result = EDID_BAD_CHECKSUM; 101 102 edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] | 103 ((uint16_t) edid_buf->mfg_id[1])<<8; 104 edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] | 105 ((uint16_t) edid_buf->prod_code[1])<<8; 106 edid_caps->serial_number = edid_buf->serial; 107 edid_caps->manufacture_week = edid_buf->mfg_week; 108 edid_caps->manufacture_year = edid_buf->mfg_year; 109 110 drm_edid_get_monitor_name(edid_buf, 111 edid_caps->display_name, 112 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 113 114 edid_caps->edid_hdmi = connector->display_info.is_hdmi; 115 116 sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads); 117 if (sad_count <= 0) 118 return result; 119 120 edid_caps->audio_mode_count = min(sad_count, DC_MAX_AUDIO_DESC_COUNT); 121 for (i = 0; i < edid_caps->audio_mode_count; ++i) { 122 struct cea_sad *sad = &sads[i]; 123 124 edid_caps->audio_modes[i].format_code = sad->format; 125 edid_caps->audio_modes[i].channel_count = sad->channels + 1; 126 edid_caps->audio_modes[i].sample_rate = sad->freq; 127 edid_caps->audio_modes[i].sample_size = sad->byte2; 128 } 129 130 sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb); 131 132 if (sadb_count < 0) { 133 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count); 134 sadb_count = 0; 135 } 136 137 if (sadb_count) 138 edid_caps->speaker_flags = sadb[0]; 139 else 140 edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION; 141 142 apply_edid_quirks(edid_buf, edid_caps); 143 144 kfree(sads); 145 kfree(sadb); 146 147 return result; 148 } 149 150 static void 151 fill_dc_mst_payload_table_from_drm(struct dc_link *link, 152 bool enable, 153 struct drm_dp_mst_atomic_payload *target_payload, 154 struct dc_dp_mst_stream_allocation_table *table) 155 { 156 struct dc_dp_mst_stream_allocation_table new_table = { 0 }; 157 struct dc_dp_mst_stream_allocation *sa; 158 struct link_mst_stream_allocation_table copy_of_link_table = 159 link->mst_stream_alloc_table; 160 161 int i; 162 int current_hw_table_stream_cnt = copy_of_link_table.stream_count; 163 struct link_mst_stream_allocation *dc_alloc; 164 165 /* TODO: refactor to set link->mst_stream_alloc_table directly if possible.*/ 166 if (enable) { 167 dc_alloc = 168 ©_of_link_table.stream_allocations[current_hw_table_stream_cnt]; 169 dc_alloc->vcp_id = target_payload->vcpi; 170 dc_alloc->slot_count = target_payload->time_slots; 171 } else { 172 for (i = 0; i < copy_of_link_table.stream_count; i++) { 173 dc_alloc = 174 ©_of_link_table.stream_allocations[i]; 175 176 if (dc_alloc->vcp_id == target_payload->vcpi) { 177 dc_alloc->vcp_id = 0; 178 dc_alloc->slot_count = 0; 179 break; 180 } 181 } 182 ASSERT(i != copy_of_link_table.stream_count); 183 } 184 185 /* Fill payload info*/ 186 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 187 dc_alloc = 188 ©_of_link_table.stream_allocations[i]; 189 if (dc_alloc->vcp_id > 0 && dc_alloc->slot_count > 0) { 190 sa = &new_table.stream_allocations[new_table.stream_count]; 191 sa->slot_count = dc_alloc->slot_count; 192 sa->vcp_id = dc_alloc->vcp_id; 193 new_table.stream_count++; 194 } 195 } 196 197 /* Overwrite the old table */ 198 *table = new_table; 199 } 200 201 void dm_helpers_dp_update_branch_info( 202 struct dc_context *ctx, 203 const struct dc_link *link) 204 {} 205 206 static void dm_helpers_construct_old_payload( 207 struct drm_dp_mst_topology_mgr *mgr, 208 struct drm_dp_mst_topology_state *mst_state, 209 struct drm_dp_mst_atomic_payload *new_payload, 210 struct drm_dp_mst_atomic_payload *old_payload) 211 { 212 struct drm_dp_mst_atomic_payload *pos; 213 int pbn_per_slot = mst_state->pbn_div; 214 u8 next_payload_vc_start = mgr->next_start_slot; 215 u8 payload_vc_start = new_payload->vc_start_slot; 216 u8 allocated_time_slots; 217 218 *old_payload = *new_payload; 219 220 /* Set correct time_slots/PBN of old payload. 221 * other fields (delete & dsc_enabled) in 222 * struct drm_dp_mst_atomic_payload are don't care fields 223 * while calling drm_dp_remove_payload_part2() 224 */ 225 list_for_each_entry(pos, &mst_state->payloads, next) { 226 if (pos != new_payload && 227 pos->vc_start_slot > payload_vc_start && 228 pos->vc_start_slot < next_payload_vc_start) 229 next_payload_vc_start = pos->vc_start_slot; 230 } 231 232 allocated_time_slots = next_payload_vc_start - payload_vc_start; 233 234 old_payload->time_slots = allocated_time_slots; 235 old_payload->pbn = allocated_time_slots * pbn_per_slot; 236 } 237 238 /* 239 * Writes payload allocation table in immediate downstream device. 240 */ 241 bool dm_helpers_dp_mst_write_payload_allocation_table( 242 struct dc_context *ctx, 243 const struct dc_stream_state *stream, 244 struct dc_dp_mst_stream_allocation_table *proposed_table, 245 bool enable) 246 { 247 struct amdgpu_dm_connector *aconnector; 248 struct drm_dp_mst_topology_state *mst_state; 249 struct drm_dp_mst_atomic_payload *target_payload, *new_payload, old_payload; 250 struct drm_dp_mst_topology_mgr *mst_mgr; 251 252 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 253 /* Accessing the connector state is required for vcpi_slots allocation 254 * and directly relies on behaviour in commit check 255 * that blocks before commit guaranteeing that the state 256 * is not gonna be swapped while still in use in commit tail 257 */ 258 259 if (!aconnector || !aconnector->mst_root) 260 return false; 261 262 mst_mgr = &aconnector->mst_root->mst_mgr; 263 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); 264 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); 265 266 if (enable) { 267 target_payload = new_payload; 268 269 /* It's OK for this to fail */ 270 drm_dp_add_payload_part1(mst_mgr, mst_state, new_payload); 271 } else { 272 /* construct old payload by VCPI*/ 273 dm_helpers_construct_old_payload(mst_mgr, mst_state, 274 new_payload, &old_payload); 275 target_payload = &old_payload; 276 277 drm_dp_remove_payload_part1(mst_mgr, mst_state, new_payload); 278 } 279 280 /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or 281 * AUX message. The sequence is slot 1-63 allocated sequence for each 282 * stream. AMD ASIC stream slot allocation should follow the same 283 * sequence. copy DRM MST allocation to dc 284 */ 285 fill_dc_mst_payload_table_from_drm(stream->link, enable, target_payload, proposed_table); 286 287 return true; 288 } 289 290 /* 291 * poll pending down reply 292 */ 293 void dm_helpers_dp_mst_poll_pending_down_reply( 294 struct dc_context *ctx, 295 const struct dc_link *link) 296 {} 297 298 /* 299 * Clear payload allocation table before enable MST DP link. 300 */ 301 void dm_helpers_dp_mst_clear_payload_allocation_table( 302 struct dc_context *ctx, 303 const struct dc_link *link) 304 {} 305 306 /* 307 * Polls for ACT (allocation change trigger) handled and sends 308 * ALLOCATE_PAYLOAD message. 309 */ 310 enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger( 311 struct dc_context *ctx, 312 const struct dc_stream_state *stream) 313 { 314 struct amdgpu_dm_connector *aconnector; 315 struct drm_dp_mst_topology_mgr *mst_mgr; 316 int ret; 317 318 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 319 320 if (!aconnector || !aconnector->mst_root) 321 return ACT_FAILED; 322 323 mst_mgr = &aconnector->mst_root->mst_mgr; 324 325 if (!mst_mgr->mst_state) 326 return ACT_FAILED; 327 328 ret = drm_dp_check_act_status(mst_mgr); 329 330 if (ret) 331 return ACT_FAILED; 332 333 return ACT_SUCCESS; 334 } 335 336 bool dm_helpers_dp_mst_send_payload_allocation( 337 struct dc_context *ctx, 338 const struct dc_stream_state *stream, 339 bool enable) 340 { 341 struct amdgpu_dm_connector *aconnector; 342 struct drm_dp_mst_topology_state *mst_state; 343 struct drm_dp_mst_topology_mgr *mst_mgr; 344 struct drm_dp_mst_atomic_payload *new_payload, old_payload; 345 enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD; 346 enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD; 347 int ret = 0; 348 349 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 350 351 if (!aconnector || !aconnector->mst_root) 352 return false; 353 354 mst_mgr = &aconnector->mst_root->mst_mgr; 355 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); 356 357 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); 358 359 if (!enable) { 360 set_flag = MST_CLEAR_ALLOCATED_PAYLOAD; 361 clr_flag = MST_ALLOCATE_NEW_PAYLOAD; 362 } 363 364 if (enable) { 365 ret = drm_dp_add_payload_part2(mst_mgr, mst_state->base.state, new_payload); 366 } else { 367 dm_helpers_construct_old_payload(mst_mgr, mst_state, 368 new_payload, &old_payload); 369 drm_dp_remove_payload_part2(mst_mgr, mst_state, &old_payload, new_payload); 370 } 371 372 if (ret) { 373 amdgpu_dm_set_mst_status(&aconnector->mst_status, 374 set_flag, false); 375 } else { 376 amdgpu_dm_set_mst_status(&aconnector->mst_status, 377 set_flag, true); 378 amdgpu_dm_set_mst_status(&aconnector->mst_status, 379 clr_flag, false); 380 } 381 382 return true; 383 } 384 385 void dm_dtn_log_begin(struct dc_context *ctx, 386 struct dc_log_buffer_ctx *log_ctx) 387 { 388 static const char msg[] = "[dtn begin]\n"; 389 390 if (!log_ctx) { 391 pr_info("%s", msg); 392 return; 393 } 394 395 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); 396 } 397 398 __printf(3, 4) 399 void dm_dtn_log_append_v(struct dc_context *ctx, 400 struct dc_log_buffer_ctx *log_ctx, 401 const char *msg, ...) 402 { 403 va_list args; 404 size_t total; 405 int n; 406 407 if (!log_ctx) { 408 /* No context, redirect to dmesg. */ 409 struct va_format vaf; 410 411 vaf.fmt = msg; 412 vaf.va = &args; 413 414 va_start(args, msg); 415 pr_info("%pV", &vaf); 416 va_end(args); 417 418 return; 419 } 420 421 /* Measure the output. */ 422 va_start(args, msg); 423 n = vsnprintf(NULL, 0, msg, args); 424 va_end(args); 425 426 if (n <= 0) 427 return; 428 429 /* Reallocate the string buffer as needed. */ 430 total = log_ctx->pos + n + 1; 431 432 if (total > log_ctx->size) { 433 char *buf = kvcalloc(total, sizeof(char), GFP_KERNEL); 434 435 if (buf) { 436 memcpy(buf, log_ctx->buf, log_ctx->pos); 437 kfree(log_ctx->buf); 438 439 log_ctx->buf = buf; 440 log_ctx->size = total; 441 } 442 } 443 444 if (!log_ctx->buf) 445 return; 446 447 /* Write the formatted string to the log buffer. */ 448 va_start(args, msg); 449 n = vscnprintf( 450 log_ctx->buf + log_ctx->pos, 451 log_ctx->size - log_ctx->pos, 452 msg, 453 args); 454 va_end(args); 455 456 if (n > 0) 457 log_ctx->pos += n; 458 } 459 460 void dm_dtn_log_end(struct dc_context *ctx, 461 struct dc_log_buffer_ctx *log_ctx) 462 { 463 static const char msg[] = "[dtn end]\n"; 464 465 if (!log_ctx) { 466 pr_info("%s", msg); 467 return; 468 } 469 470 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); 471 } 472 473 bool dm_helpers_dp_mst_start_top_mgr( 474 struct dc_context *ctx, 475 const struct dc_link *link, 476 bool boot) 477 { 478 struct amdgpu_dm_connector *aconnector = link->priv; 479 int ret; 480 481 if (!aconnector) { 482 DRM_ERROR("Failed to find connector for link!"); 483 return false; 484 } 485 486 if (boot) { 487 DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n", 488 aconnector, aconnector->base.base.id); 489 return true; 490 } 491 492 DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n", 493 aconnector, aconnector->base.base.id); 494 495 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 496 if (ret < 0) { 497 DRM_ERROR("DM_MST: Failed to set the device into MST mode!"); 498 return false; 499 } 500 501 DRM_INFO("DM_MST: DP%x, %d-lane link detected\n", aconnector->mst_mgr.dpcd[0], 502 aconnector->mst_mgr.dpcd[2] & DP_MAX_LANE_COUNT_MASK); 503 504 return true; 505 } 506 507 bool dm_helpers_dp_mst_stop_top_mgr( 508 struct dc_context *ctx, 509 struct dc_link *link) 510 { 511 struct amdgpu_dm_connector *aconnector = link->priv; 512 513 if (!aconnector) { 514 DRM_ERROR("Failed to find connector for link!"); 515 return false; 516 } 517 518 DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n", 519 aconnector, aconnector->base.base.id); 520 521 if (aconnector->mst_mgr.mst_state == true) { 522 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false); 523 link->cur_link_settings.lane_count = 0; 524 } 525 526 return false; 527 } 528 529 bool dm_helpers_dp_read_dpcd( 530 struct dc_context *ctx, 531 const struct dc_link *link, 532 uint32_t address, 533 uint8_t *data, 534 uint32_t size) 535 { 536 537 struct amdgpu_dm_connector *aconnector = link->priv; 538 539 if (!aconnector) { 540 drm_dbg_dp(aconnector->base.dev, 541 "Failed to find connector for link!\n"); 542 return false; 543 } 544 545 return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address, data, 546 size) == size; 547 } 548 549 bool dm_helpers_dp_write_dpcd( 550 struct dc_context *ctx, 551 const struct dc_link *link, 552 uint32_t address, 553 const uint8_t *data, 554 uint32_t size) 555 { 556 struct amdgpu_dm_connector *aconnector = link->priv; 557 558 if (!aconnector) { 559 DRM_ERROR("Failed to find connector for link!"); 560 return false; 561 } 562 563 return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux, 564 address, (uint8_t *)data, size) > 0; 565 } 566 567 bool dm_helpers_submit_i2c( 568 struct dc_context *ctx, 569 const struct dc_link *link, 570 struct i2c_command *cmd) 571 { 572 struct amdgpu_dm_connector *aconnector = link->priv; 573 struct i2c_msg *msgs; 574 int i = 0; 575 int num = cmd->number_of_payloads; 576 bool result; 577 578 if (!aconnector) { 579 DRM_ERROR("Failed to find connector for link!"); 580 return false; 581 } 582 583 msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL); 584 585 if (!msgs) 586 return false; 587 588 for (i = 0; i < num; i++) { 589 msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD; 590 msgs[i].addr = cmd->payloads[i].address; 591 msgs[i].len = cmd->payloads[i].length; 592 msgs[i].buf = cmd->payloads[i].data; 593 } 594 595 result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num; 596 597 kfree(msgs); 598 599 return result; 600 } 601 602 static bool execute_synaptics_rc_command(struct drm_dp_aux *aux, 603 bool is_write_cmd, 604 unsigned char cmd, 605 unsigned int length, 606 unsigned int offset, 607 unsigned char *data) 608 { 609 bool success = false; 610 unsigned char rc_data[16] = {0}; 611 unsigned char rc_offset[4] = {0}; 612 unsigned char rc_length[2] = {0}; 613 unsigned char rc_cmd = 0; 614 unsigned char rc_result = 0xFF; 615 unsigned char i = 0; 616 int ret; 617 618 if (is_write_cmd) { 619 // write rc data 620 memmove(rc_data, data, length); 621 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_DATA, rc_data, sizeof(rc_data)); 622 } 623 624 // write rc offset 625 rc_offset[0] = (unsigned char) offset & 0xFF; 626 rc_offset[1] = (unsigned char) (offset >> 8) & 0xFF; 627 rc_offset[2] = (unsigned char) (offset >> 16) & 0xFF; 628 rc_offset[3] = (unsigned char) (offset >> 24) & 0xFF; 629 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_OFFSET, rc_offset, sizeof(rc_offset)); 630 631 // write rc length 632 rc_length[0] = (unsigned char) length & 0xFF; 633 rc_length[1] = (unsigned char) (length >> 8) & 0xFF; 634 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_LENGTH, rc_length, sizeof(rc_length)); 635 636 // write rc cmd 637 rc_cmd = cmd | 0x80; 638 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd)); 639 640 if (ret < 0) { 641 DRM_ERROR("%s: write cmd ..., err = %d\n", __func__, ret); 642 return false; 643 } 644 645 // poll until active is 0 646 for (i = 0; i < 10; i++) { 647 drm_dp_dpcd_read(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd)); 648 if (rc_cmd == cmd) 649 // active is 0 650 break; 651 msleep(10); 652 } 653 654 // read rc result 655 drm_dp_dpcd_read(aux, SYNAPTICS_RC_RESULT, &rc_result, sizeof(rc_result)); 656 success = (rc_result == 0); 657 658 if (success && !is_write_cmd) { 659 // read rc data 660 drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length); 661 } 662 663 drm_dbg_dp(aux->drm_dev, "success = %d\n", success); 664 665 return success; 666 } 667 668 static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux) 669 { 670 unsigned char data[16] = {0}; 671 672 drm_dbg_dp(aux->drm_dev, "Start\n"); 673 674 // Step 2 675 data[0] = 'P'; 676 data[1] = 'R'; 677 data[2] = 'I'; 678 data[3] = 'U'; 679 data[4] = 'S'; 680 681 if (!execute_synaptics_rc_command(aux, true, 0x01, 5, 0, data)) 682 return; 683 684 // Step 3 and 4 685 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data)) 686 return; 687 688 data[0] &= (~(1 << 1)); // set bit 1 to 0 689 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data)) 690 return; 691 692 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data)) 693 return; 694 695 data[0] &= (~(1 << 1)); // set bit 1 to 0 696 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220D98, data)) 697 return; 698 699 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data)) 700 return; 701 702 data[0] &= (~(1 << 1)); // set bit 1 to 0 703 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data)) 704 return; 705 706 // Step 3 and 5 707 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data)) 708 return; 709 710 data[0] |= (1 << 1); // set bit 1 to 1 711 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data)) 712 return; 713 714 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data)) 715 return; 716 717 data[0] |= (1 << 1); // set bit 1 to 1 718 719 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data)) 720 return; 721 722 data[0] |= (1 << 1); // set bit 1 to 1 723 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data)) 724 return; 725 726 // Step 6 727 if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL)) 728 return; 729 730 drm_dbg_dp(aux->drm_dev, "Done\n"); 731 } 732 733 /* MST Dock */ 734 static const uint8_t SYNAPTICS_DEVICE_ID[] = "SYNA"; 735 736 static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst( 737 struct drm_dp_aux *aux, 738 const struct dc_stream_state *stream, 739 bool enable) 740 { 741 uint8_t ret = 0; 742 743 drm_dbg_dp(aux->drm_dev, 744 "Configure DSC to non-virtual dpcd synaptics\n"); 745 746 if (enable) { 747 /* When DSC is enabled on previous boot and reboot with the hub, 748 * there is a chance that Synaptics hub gets stuck during reboot sequence. 749 * Applying a workaround to reset Synaptics SDP fifo before enabling the first stream 750 */ 751 if (!stream->link->link_status.link_active && 752 memcmp(stream->link->dpcd_caps.branch_dev_name, 753 (int8_t *)SYNAPTICS_DEVICE_ID, 4) == 0) 754 apply_synaptics_fifo_reset_wa(aux); 755 756 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1); 757 DRM_INFO("Send DSC enable to synaptics\n"); 758 759 } else { 760 /* Synaptics hub not support virtual dpcd, 761 * external monitor occur garbage while disable DSC, 762 * Disable DSC only when entire link status turn to false, 763 */ 764 if (!stream->link->link_status.link_active) { 765 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1); 766 DRM_INFO("Send DSC disable to synaptics\n"); 767 } 768 } 769 770 return ret; 771 } 772 773 bool dm_helpers_dp_write_dsc_enable( 774 struct dc_context *ctx, 775 const struct dc_stream_state *stream, 776 bool enable) 777 { 778 static const uint8_t DSC_DISABLE; 779 static const uint8_t DSC_DECODING = 0x01; 780 static const uint8_t DSC_PASSTHROUGH = 0x02; 781 782 struct amdgpu_dm_connector *aconnector = 783 (struct amdgpu_dm_connector *)stream->dm_stream_context; 784 struct drm_device *dev = aconnector->base.dev; 785 struct drm_dp_mst_port *port; 786 uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE; 787 uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE; 788 uint8_t ret = 0; 789 790 if (!stream) 791 return false; 792 793 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 794 if (!aconnector->dsc_aux) 795 return false; 796 797 // apply w/a to synaptics 798 if (needs_dsc_aux_workaround(aconnector->dc_link) && 799 (aconnector->mst_downstream_port_present.byte & 0x7) != 0x3) 800 return write_dsc_enable_synaptics_non_virtual_dpcd_mst( 801 aconnector->dsc_aux, stream, enable_dsc); 802 803 port = aconnector->mst_output_port; 804 805 if (enable) { 806 if (port->passthrough_aux) { 807 ret = drm_dp_dpcd_write(port->passthrough_aux, 808 DP_DSC_ENABLE, 809 &enable_passthrough, 1); 810 drm_dbg_dp(dev, 811 "Sent DSC pass-through enable to virtual dpcd port, ret = %u\n", 812 ret); 813 } 814 815 ret = drm_dp_dpcd_write(aconnector->dsc_aux, 816 DP_DSC_ENABLE, &enable_dsc, 1); 817 drm_dbg_dp(dev, 818 "Sent DSC decoding enable to %s port, ret = %u\n", 819 (port->passthrough_aux) ? "remote RX" : 820 "virtual dpcd", 821 ret); 822 } else { 823 ret = drm_dp_dpcd_write(aconnector->dsc_aux, 824 DP_DSC_ENABLE, &enable_dsc, 1); 825 drm_dbg_dp(dev, 826 "Sent DSC decoding disable to %s port, ret = %u\n", 827 (port->passthrough_aux) ? "remote RX" : 828 "virtual dpcd", 829 ret); 830 831 if (port->passthrough_aux) { 832 ret = drm_dp_dpcd_write(port->passthrough_aux, 833 DP_DSC_ENABLE, 834 &enable_passthrough, 1); 835 drm_dbg_dp(dev, 836 "Sent DSC pass-through disable to virtual dpcd port, ret = %u\n", 837 ret); 838 } 839 } 840 } 841 842 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) { 843 if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { 844 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); 845 drm_dbg_dp(dev, 846 "Send DSC %s to SST RX\n", 847 enable_dsc ? "enable" : "disable"); 848 } else if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { 849 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); 850 drm_dbg_dp(dev, 851 "Send DSC %s to DP-HDMI PCON\n", 852 enable_dsc ? "enable" : "disable"); 853 } 854 } 855 856 return ret; 857 } 858 859 bool dm_helpers_is_dp_sink_present(struct dc_link *link) 860 { 861 bool dp_sink_present; 862 struct amdgpu_dm_connector *aconnector = link->priv; 863 864 if (!aconnector) { 865 BUG_ON("Failed to find connector for link!"); 866 return true; 867 } 868 869 mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex); 870 dp_sink_present = dc_link_is_dp_sink_present(link); 871 mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex); 872 return dp_sink_present; 873 } 874 875 enum dc_edid_status dm_helpers_read_local_edid( 876 struct dc_context *ctx, 877 struct dc_link *link, 878 struct dc_sink *sink) 879 { 880 struct amdgpu_dm_connector *aconnector = link->priv; 881 struct drm_connector *connector = &aconnector->base; 882 struct i2c_adapter *ddc; 883 int retry = 3; 884 enum dc_edid_status edid_status; 885 struct edid *edid; 886 887 if (link->aux_mode) 888 ddc = &aconnector->dm_dp_aux.aux.ddc; 889 else 890 ddc = &aconnector->i2c->base; 891 892 /* some dongles read edid incorrectly the first time, 893 * do check sum and retry to make sure read correct edid. 894 */ 895 do { 896 897 edid = drm_get_edid(&aconnector->base, ddc); 898 899 /* DP Compliance Test 4.2.2.6 */ 900 if (link->aux_mode && connector->edid_corrupt) 901 drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum); 902 903 if (!edid && connector->edid_corrupt) { 904 connector->edid_corrupt = false; 905 return EDID_BAD_CHECKSUM; 906 } 907 908 if (!edid) 909 return EDID_NO_RESPONSE; 910 911 sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1); 912 memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length); 913 914 /* We don't need the original edid anymore */ 915 kfree(edid); 916 917 edid_status = dm_helpers_parse_edid_caps( 918 link, 919 &sink->dc_edid, 920 &sink->edid_caps); 921 922 } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0); 923 924 if (edid_status != EDID_OK) 925 DRM_ERROR("EDID err: %d, on connector: %s", 926 edid_status, 927 aconnector->base.name); 928 if (link->aux_mode) { 929 union test_request test_request = {0}; 930 union test_response test_response = {0}; 931 932 dm_helpers_dp_read_dpcd(ctx, 933 link, 934 DP_TEST_REQUEST, 935 &test_request.raw, 936 sizeof(union test_request)); 937 938 if (!test_request.bits.EDID_READ) 939 return edid_status; 940 941 test_response.bits.EDID_CHECKSUM_WRITE = 1; 942 943 dm_helpers_dp_write_dpcd(ctx, 944 link, 945 DP_TEST_EDID_CHECKSUM, 946 &sink->dc_edid.raw_edid[sink->dc_edid.length-1], 947 1); 948 949 dm_helpers_dp_write_dpcd(ctx, 950 link, 951 DP_TEST_RESPONSE, 952 &test_response.raw, 953 sizeof(test_response)); 954 955 } 956 957 return edid_status; 958 } 959 int dm_helper_dmub_aux_transfer_sync( 960 struct dc_context *ctx, 961 const struct dc_link *link, 962 struct aux_payload *payload, 963 enum aux_return_code_type *operation_result) 964 { 965 return amdgpu_dm_process_dmub_aux_transfer_sync(ctx, link->link_index, payload, 966 operation_result); 967 } 968 969 int dm_helpers_dmub_set_config_sync(struct dc_context *ctx, 970 const struct dc_link *link, 971 struct set_config_cmd_payload *payload, 972 enum set_config_status *operation_result) 973 { 974 return amdgpu_dm_process_dmub_set_config_sync(ctx, link->link_index, payload, 975 operation_result); 976 } 977 978 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks) 979 { 980 /* TODO: something */ 981 } 982 983 void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us) 984 { 985 // TODO: 986 //amdgpu_device_gpu_recover(dc_context->driver-context, NULL); 987 } 988 989 void dm_helpers_init_panel_settings( 990 struct dc_context *ctx, 991 struct dc_panel_config *panel_config, 992 struct dc_sink *sink) 993 { 994 // Extra Panel Power Sequence 995 panel_config->pps.extra_t3_ms = sink->edid_caps.panel_patch.extra_t3_ms; 996 panel_config->pps.extra_t7_ms = sink->edid_caps.panel_patch.extra_t7_ms; 997 panel_config->pps.extra_delay_backlight_off = sink->edid_caps.panel_patch.extra_delay_backlight_off; 998 panel_config->pps.extra_post_t7_ms = 0; 999 panel_config->pps.extra_pre_t11_ms = 0; 1000 panel_config->pps.extra_t12_ms = sink->edid_caps.panel_patch.extra_t12_ms; 1001 panel_config->pps.extra_post_OUI_ms = 0; 1002 // Feature DSC 1003 panel_config->dsc.disable_dsc_edp = false; 1004 panel_config->dsc.force_dsc_edp_policy = 0; 1005 } 1006 1007 void dm_helpers_override_panel_settings( 1008 struct dc_context *ctx, 1009 struct dc_panel_config *panel_config) 1010 { 1011 // Feature DSC 1012 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) 1013 panel_config->dsc.disable_dsc_edp = true; 1014 } 1015 1016 void *dm_helpers_allocate_gpu_mem( 1017 struct dc_context *ctx, 1018 enum dc_gpu_mem_alloc_type type, 1019 size_t size, 1020 long long *addr) 1021 { 1022 struct amdgpu_device *adev = ctx->driver_context; 1023 struct dal_allocation *da; 1024 u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ? 1025 AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM; 1026 int ret; 1027 1028 da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL); 1029 if (!da) 1030 return NULL; 1031 1032 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 1033 domain, &da->bo, 1034 &da->gpu_addr, &da->cpu_ptr); 1035 1036 *addr = da->gpu_addr; 1037 1038 if (ret) { 1039 kfree(da); 1040 return NULL; 1041 } 1042 1043 /* add da to list in dm */ 1044 list_add(&da->list, &adev->dm.da_list); 1045 1046 return da->cpu_ptr; 1047 } 1048 1049 void dm_helpers_free_gpu_mem( 1050 struct dc_context *ctx, 1051 enum dc_gpu_mem_alloc_type type, 1052 void *pvMem) 1053 { 1054 struct amdgpu_device *adev = ctx->driver_context; 1055 struct dal_allocation *da; 1056 1057 /* walk the da list in DM */ 1058 list_for_each_entry(da, &adev->dm.da_list, list) { 1059 if (pvMem == da->cpu_ptr) { 1060 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); 1061 list_del(&da->list); 1062 kfree(da); 1063 break; 1064 } 1065 } 1066 } 1067 1068 bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable) 1069 { 1070 enum dc_irq_source irq_source; 1071 bool ret; 1072 1073 irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX; 1074 1075 ret = dc_interrupt_set(ctx->dc, irq_source, enable); 1076 1077 DRM_DEBUG_DRIVER("Dmub trace irq %sabling: r=%d\n", 1078 enable ? "en" : "dis", ret); 1079 return ret; 1080 } 1081 1082 void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream) 1083 { 1084 /* TODO: virtual DPCD */ 1085 struct dc_link *link = stream->link; 1086 union down_spread_ctrl old_downspread; 1087 union down_spread_ctrl new_downspread; 1088 1089 if (link->aux_access_disabled) 1090 return; 1091 1092 if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL, 1093 &old_downspread.raw, 1094 sizeof(old_downspread))) 1095 return; 1096 1097 new_downspread.raw = old_downspread.raw; 1098 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 1099 (stream->ignore_msa_timing_param) ? 1 : 0; 1100 1101 if (new_downspread.raw != old_downspread.raw) 1102 dm_helpers_dp_write_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL, 1103 &new_downspread.raw, 1104 sizeof(new_downspread)); 1105 } 1106 1107 bool dm_helpers_dp_handle_test_pattern_request( 1108 struct dc_context *ctx, 1109 const struct dc_link *link, 1110 union link_test_pattern dpcd_test_pattern, 1111 union test_misc dpcd_test_params) 1112 { 1113 enum dp_test_pattern test_pattern; 1114 enum dp_test_pattern_color_space test_pattern_color_space = 1115 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED; 1116 enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED; 1117 enum dc_pixel_encoding requestPixelEncoding = PIXEL_ENCODING_UNDEFINED; 1118 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; 1119 struct pipe_ctx *pipe_ctx = NULL; 1120 struct amdgpu_dm_connector *aconnector = link->priv; 1121 struct drm_device *dev = aconnector->base.dev; 1122 int i; 1123 1124 for (i = 0; i < MAX_PIPES; i++) { 1125 if (pipes[i].stream == NULL) 1126 continue; 1127 1128 if (pipes[i].stream->link == link && !pipes[i].top_pipe && 1129 !pipes[i].prev_odm_pipe) { 1130 pipe_ctx = &pipes[i]; 1131 break; 1132 } 1133 } 1134 1135 if (pipe_ctx == NULL) 1136 return false; 1137 1138 switch (dpcd_test_pattern.bits.PATTERN) { 1139 case LINK_TEST_PATTERN_COLOR_RAMP: 1140 test_pattern = DP_TEST_PATTERN_COLOR_RAMP; 1141 break; 1142 case LINK_TEST_PATTERN_VERTICAL_BARS: 1143 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS; 1144 break; /* black and white */ 1145 case LINK_TEST_PATTERN_COLOR_SQUARES: 1146 test_pattern = (dpcd_test_params.bits.DYN_RANGE == 1147 TEST_DYN_RANGE_VESA ? 1148 DP_TEST_PATTERN_COLOR_SQUARES : 1149 DP_TEST_PATTERN_COLOR_SQUARES_CEA); 1150 break; 1151 default: 1152 test_pattern = DP_TEST_PATTERN_VIDEO_MODE; 1153 break; 1154 } 1155 1156 if (dpcd_test_params.bits.CLR_FORMAT == 0) 1157 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB; 1158 else 1159 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ? 1160 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 : 1161 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601; 1162 1163 switch (dpcd_test_params.bits.BPC) { 1164 case 0: // 6 bits 1165 requestColorDepth = COLOR_DEPTH_666; 1166 break; 1167 case 1: // 8 bits 1168 requestColorDepth = COLOR_DEPTH_888; 1169 break; 1170 case 2: // 10 bits 1171 requestColorDepth = COLOR_DEPTH_101010; 1172 break; 1173 case 3: // 12 bits 1174 requestColorDepth = COLOR_DEPTH_121212; 1175 break; 1176 default: 1177 break; 1178 } 1179 1180 switch (dpcd_test_params.bits.CLR_FORMAT) { 1181 case 0: 1182 requestPixelEncoding = PIXEL_ENCODING_RGB; 1183 break; 1184 case 1: 1185 requestPixelEncoding = PIXEL_ENCODING_YCBCR422; 1186 break; 1187 case 2: 1188 requestPixelEncoding = PIXEL_ENCODING_YCBCR444; 1189 break; 1190 default: 1191 requestPixelEncoding = PIXEL_ENCODING_RGB; 1192 break; 1193 } 1194 1195 if ((requestColorDepth != COLOR_DEPTH_UNDEFINED 1196 && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) 1197 || (requestPixelEncoding != PIXEL_ENCODING_UNDEFINED 1198 && pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) { 1199 drm_dbg(dev, 1200 "original bpc %d pix encoding %d, changing to %d %d\n", 1201 pipe_ctx->stream->timing.display_color_depth, 1202 pipe_ctx->stream->timing.pixel_encoding, 1203 requestColorDepth, 1204 requestPixelEncoding); 1205 pipe_ctx->stream->timing.display_color_depth = requestColorDepth; 1206 pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding; 1207 1208 dc_link_update_dsc_config(pipe_ctx); 1209 1210 aconnector->timing_changed = true; 1211 /* store current timing */ 1212 if (aconnector->timing_requested) 1213 *aconnector->timing_requested = pipe_ctx->stream->timing; 1214 else 1215 drm_err(dev, "timing storage failed\n"); 1216 1217 } 1218 1219 pipe_ctx->stream->test_pattern.type = test_pattern; 1220 pipe_ctx->stream->test_pattern.color_space = test_pattern_color_space; 1221 1222 dc_link_dp_set_test_pattern( 1223 (struct dc_link *) link, 1224 test_pattern, 1225 test_pattern_color_space, 1226 NULL, 1227 NULL, 1228 0); 1229 1230 return false; 1231 } 1232 1233 void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz) 1234 { 1235 // TODO 1236 } 1237 1238 void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable) 1239 { 1240 /* TODO: add periodic detection implementation */ 1241 } 1242 1243 void dm_helpers_dp_mst_update_branch_bandwidth( 1244 struct dc_context *ctx, 1245 struct dc_link *link) 1246 { 1247 // TODO 1248 } 1249 1250 static bool dm_is_freesync_pcon_whitelist(const uint32_t branch_dev_id) 1251 { 1252 bool ret_val = false; 1253 1254 switch (branch_dev_id) { 1255 case DP_BRANCH_DEVICE_ID_0060AD: 1256 case DP_BRANCH_DEVICE_ID_00E04C: 1257 case DP_BRANCH_DEVICE_ID_90CC24: 1258 ret_val = true; 1259 break; 1260 default: 1261 break; 1262 } 1263 1264 return ret_val; 1265 } 1266 1267 enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link) 1268 { 1269 struct dpcd_caps *dpcd_caps = &link->dpcd_caps; 1270 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; 1271 1272 switch (dpcd_caps->dongle_type) { 1273 case DISPLAY_DONGLE_DP_HDMI_CONVERTER: 1274 if (dpcd_caps->adaptive_sync_caps.dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT == true && 1275 dpcd_caps->allow_invalid_MSA_timing_param == true && 1276 dm_is_freesync_pcon_whitelist(dpcd_caps->branch_dev_id)) 1277 as_type = FREESYNC_TYPE_PCON_IN_WHITELIST; 1278 break; 1279 default: 1280 break; 1281 } 1282 1283 return as_type; 1284 } 1285