1# SPDX-License-Identifier: GPL-2.0 2# 3# For a description of the syntax of this configuration file, 4# see Documentation/kbuild/kconfig-language.rst. 5# 6 7config OPENRISC 8 def_bool y 9 select ARCH_32BIT_OFF_T 10 select ARCH_HAS_DMA_SET_UNCACHED 11 select ARCH_HAS_DMA_CLEAR_UNCACHED 12 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 13 select ARCH_HAS_VM_GET_PAGE_PROT 14 select COMMON_CLK 15 select OF 16 select OF_EARLY_FLATTREE 17 select IRQ_DOMAIN 18 select GPIOLIB 19 select HAVE_ARCH_TRACEHOOK 20 select SPARSE_IRQ 21 select GENERIC_IRQ_CHIP 22 select GENERIC_IRQ_PROBE 23 select GENERIC_IRQ_SHOW 24 select GENERIC_IOMAP 25 select GENERIC_CPU_DEVICES 26 select HAVE_UID16 27 select GENERIC_ATOMIC64 28 select GENERIC_CLOCKEVENTS_BROADCAST 29 select GENERIC_SMP_IDLE_THREAD 30 select MODULES_USE_ELF_RELA 31 select HAVE_DEBUG_STACKOVERFLOW 32 select OR1K_PIC 33 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 34 select ARCH_USE_QUEUED_RWLOCKS 35 select OMPIC if SMP 36 select ARCH_WANT_FRAME_POINTERS 37 select GENERIC_IRQ_MULTI_HANDLER 38 select MMU_GATHER_NO_RANGE if MMU 39 select TRACE_IRQFLAGS_SUPPORT 40 41config CPU_BIG_ENDIAN 42 def_bool y 43 44config MMU 45 def_bool y 46 47config GENERIC_HWEIGHT 48 def_bool y 49 50config NO_IOPORT_MAP 51 def_bool y 52 53# For now, use generic checksum functions 54#These can be reimplemented in assembly later if so inclined 55config GENERIC_CSUM 56 def_bool y 57 58config STACKTRACE_SUPPORT 59 def_bool y 60 61config LOCKDEP_SUPPORT 62 def_bool y 63 64menu "Processor type and features" 65 66choice 67 prompt "Subarchitecture" 68 default OR1K_1200 69 70config OR1K_1200 71 bool "OR1200" 72 help 73 Generic OpenRISC 1200 architecture 74 75endchoice 76 77config DCACHE_WRITETHROUGH 78 bool "Have write through data caches" 79 default n 80 help 81 Select this if your implementation features write through data caches. 82 Selecting 'N' here will allow the kernel to force flushing of data 83 caches at relevant times. Most OpenRISC implementations support write- 84 through data caches. 85 86 If unsure say N here 87 88config OPENRISC_BUILTIN_DTB 89 string "Builtin DTB" 90 default "" 91 92menu "Class II Instructions" 93 94config OPENRISC_HAVE_INST_FF1 95 bool "Have instruction l.ff1" 96 default y 97 help 98 Select this if your implementation has the Class II instruction l.ff1 99 100config OPENRISC_HAVE_INST_FL1 101 bool "Have instruction l.fl1" 102 default y 103 help 104 Select this if your implementation has the Class II instruction l.fl1 105 106config OPENRISC_HAVE_INST_MUL 107 bool "Have instruction l.mul for hardware multiply" 108 default y 109 help 110 Select this if your implementation has a hardware multiply instruction 111 112config OPENRISC_HAVE_INST_DIV 113 bool "Have instruction l.div for hardware divide" 114 default y 115 help 116 Select this if your implementation has a hardware divide instruction 117 118config OPENRISC_HAVE_INST_CMOV 119 bool "Have instruction l.cmov for conditional move" 120 default n 121 help 122 This config enables gcc to generate l.cmov instructions when compiling 123 the kernel which in general will improve performance and reduce the 124 binary size. 125 126 Select this if your implementation has support for the Class II 127 l.cmov conistional move instruction. 128 129 Say N if you are unsure. 130 131config OPENRISC_HAVE_INST_ROR 132 bool "Have instruction l.ror for rotate right" 133 default n 134 help 135 This config enables gcc to generate l.ror instructions when compiling 136 the kernel which in general will improve performance and reduce the 137 binary size. 138 139 Select this if your implementation has support for the Class II 140 l.ror rotate right instruction. 141 142 Say N if you are unsure. 143 144config OPENRISC_HAVE_INST_RORI 145 bool "Have instruction l.rori for rotate right with immediate" 146 default n 147 help 148 This config enables gcc to generate l.rori instructions when compiling 149 the kernel which in general will improve performance and reduce the 150 binary size. 151 152 Select this if your implementation has support for the Class II 153 l.rori rotate right with immediate instruction. 154 155 Say N if you are unsure. 156 157config OPENRISC_HAVE_INST_SEXT 158 bool "Have instructions l.ext* for sign extension" 159 default n 160 help 161 This config enables gcc to generate l.ext* instructions when compiling 162 the kernel which in general will improve performance and reduce the 163 binary size. 164 165 Select this if your implementation has support for the Class II 166 l.exths, l.extbs, l.exthz and l.extbz size extend instructions. 167 168 Say N if you are unsure. 169 170endmenu 171 172config NR_CPUS 173 int "Maximum number of CPUs (2-32)" 174 range 2 32 175 depends on SMP 176 default "2" 177 178config SMP 179 bool "Symmetric Multi-Processing support" 180 help 181 This enables support for systems with more than one CPU. If you have 182 a system with only one CPU, say N. If you have a system with more 183 than one CPU, say Y. 184 185 If you don't know what to do here, say N. 186 187source "kernel/Kconfig.hz" 188 189config OPENRISC_NO_SPR_SR_DSX 190 bool "use SPR_SR_DSX software emulation" if OR1K_1200 191 default y 192 help 193 SPR_SR_DSX bit is status register bit indicating whether 194 the last exception has happened in delay slot. 195 196 OpenRISC architecture makes it optional to have it implemented 197 in hardware and the OR1200 does not have it. 198 199 Say N here if you know that your OpenRISC processor has 200 SPR_SR_DSX bit implemented. Say Y if you are unsure. 201 202config OPENRISC_HAVE_SHADOW_GPRS 203 bool "Support for shadow gpr files" if !SMP 204 default y if SMP 205 help 206 Say Y here if your OpenRISC processor features shadowed 207 register files. They will in such case be used as a 208 scratch reg storage on exception entry. 209 210 On SMP systems, this feature is mandatory. 211 On a unicore system it's safe to say N here if you are unsure. 212 213config CMDLINE 214 string "Default kernel command string" 215 default "" 216 help 217 On some architectures there is currently no way for the boot loader 218 to pass arguments to the kernel. For these architectures, you should 219 supply some command-line options at build time by entering them 220 here. 221 222menu "Debugging options" 223 224config JUMP_UPON_UNHANDLED_EXCEPTION 225 bool "Try to die gracefully" 226 default y 227 help 228 Now this puts kernel into infinite loop after first oops. Till 229 your kernel crashes this doesn't have any influence. 230 231 Say Y if you are unsure. 232 233config OPENRISC_ESR_EXCEPTION_BUG_CHECK 234 bool "Check for possible ESR exception bug" 235 default n 236 help 237 This option enables some checks that might expose some problems 238 in kernel. 239 240 Say N if you are unsure. 241 242endmenu 243 244endmenu 245