1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 1999, 2000 by Ralf Baechle and others. 7 * Copyright (C) 2005, 2006 by Ralf Baechle ([email protected]) 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 9 * Copyright (C) 2004 Thiemo Seufer 10 * Copyright (C) 2013 Imagination Technologies Ltd. 11 */ 12 #include <linux/errno.h> 13 #include <linux/sched.h> 14 #include <linux/sched/debug.h> 15 #include <linux/sched/task.h> 16 #include <linux/sched/task_stack.h> 17 #include <linux/tick.h> 18 #include <linux/kernel.h> 19 #include <linux/mm.h> 20 #include <linux/stddef.h> 21 #include <linux/unistd.h> 22 #include <linux/export.h> 23 #include <linux/ptrace.h> 24 #include <linux/mman.h> 25 #include <linux/personality.h> 26 #include <linux/sys.h> 27 #include <linux/init.h> 28 #include <linux/completion.h> 29 #include <linux/kallsyms.h> 30 #include <linux/random.h> 31 #include <linux/prctl.h> 32 #include <linux/nmi.h> 33 #include <linux/cpu.h> 34 35 #include <asm/abi.h> 36 #include <asm/asm.h> 37 #include <asm/bootinfo.h> 38 #include <asm/cpu.h> 39 #include <asm/dsemul.h> 40 #include <asm/dsp.h> 41 #include <asm/fpu.h> 42 #include <asm/irq.h> 43 #include <asm/mips-cps.h> 44 #include <asm/msa.h> 45 #include <asm/mipsregs.h> 46 #include <asm/processor.h> 47 #include <asm/reg.h> 48 #include <linux/uaccess.h> 49 #include <asm/io.h> 50 #include <asm/elf.h> 51 #include <asm/isadep.h> 52 #include <asm/inst.h> 53 #include <asm/stacktrace.h> 54 #include <asm/irq_regs.h> 55 56 #ifdef CONFIG_HOTPLUG_CPU 57 void arch_cpu_idle_dead(void) 58 { 59 play_dead(); 60 } 61 #endif 62 63 asmlinkage void ret_from_fork(void); 64 asmlinkage void ret_from_kernel_thread(void); 65 66 void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) 67 { 68 unsigned long status; 69 70 /* New thread loses kernel privileges. */ 71 status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_CU2|ST0_FR|KU_MASK); 72 status |= KU_USER; 73 regs->cp0_status = status; 74 lose_fpu(0); 75 clear_thread_flag(TIF_MSA_CTX_LIVE); 76 clear_used_math(); 77 #ifdef CONFIG_MIPS_FP_SUPPORT 78 atomic_set(¤t->thread.bd_emu_frame, BD_EMUFRAME_NONE); 79 #endif 80 init_dsp(); 81 regs->cp0_epc = pc; 82 regs->regs[29] = sp; 83 } 84 85 void exit_thread(struct task_struct *tsk) 86 { 87 /* 88 * User threads may have allocated a delay slot emulation frame. 89 * If so, clean up that allocation. 90 */ 91 if (!(current->flags & PF_KTHREAD)) 92 dsemul_thread_cleanup(tsk); 93 } 94 95 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 96 { 97 /* 98 * Save any process state which is live in hardware registers to the 99 * parent context prior to duplication. This prevents the new child 100 * state becoming stale if the parent is preempted before copy_thread() 101 * gets a chance to save the parent's live hardware registers to the 102 * child context. 103 */ 104 preempt_disable(); 105 106 if (is_msa_enabled()) 107 save_msa(current); 108 else if (is_fpu_owner()) 109 _save_fp(current); 110 111 save_dsp(current); 112 113 preempt_enable(); 114 115 *dst = *src; 116 return 0; 117 } 118 119 /* 120 * Copy architecture-specific thread state 121 */ 122 int copy_thread(unsigned long clone_flags, unsigned long usp, 123 unsigned long kthread_arg, struct task_struct *p, 124 unsigned long tls) 125 { 126 struct thread_info *ti = task_thread_info(p); 127 struct pt_regs *childregs, *regs = current_pt_regs(); 128 unsigned long childksp; 129 130 childksp = (unsigned long)task_stack_page(p) + THREAD_SIZE - 32; 131 132 /* set up new TSS. */ 133 childregs = (struct pt_regs *) childksp - 1; 134 /* Put the stack after the struct pt_regs. */ 135 childksp = (unsigned long) childregs; 136 p->thread.cp0_status = (read_c0_status() & ~(ST0_CU2|ST0_CU1)) | ST0_KERNEL_CUMASK; 137 if (unlikely(p->flags & PF_KTHREAD)) { 138 /* kernel thread */ 139 unsigned long status = p->thread.cp0_status; 140 memset(childregs, 0, sizeof(struct pt_regs)); 141 ti->addr_limit = KERNEL_DS; 142 p->thread.reg16 = usp; /* fn */ 143 p->thread.reg17 = kthread_arg; 144 p->thread.reg29 = childksp; 145 p->thread.reg31 = (unsigned long) ret_from_kernel_thread; 146 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 147 status = (status & ~(ST0_KUP | ST0_IEP | ST0_IEC)) | 148 ((status & (ST0_KUC | ST0_IEC)) << 2); 149 #else 150 status |= ST0_EXL; 151 #endif 152 childregs->cp0_status = status; 153 return 0; 154 } 155 156 /* user thread */ 157 *childregs = *regs; 158 childregs->regs[7] = 0; /* Clear error flag */ 159 childregs->regs[2] = 0; /* Child gets zero as return value */ 160 if (usp) 161 childregs->regs[29] = usp; 162 ti->addr_limit = USER_DS; 163 164 p->thread.reg29 = (unsigned long) childregs; 165 p->thread.reg31 = (unsigned long) ret_from_fork; 166 167 /* 168 * New tasks lose permission to use the fpu. This accelerates context 169 * switching for most programs since they don't use the fpu. 170 */ 171 childregs->cp0_status &= ~(ST0_CU2|ST0_CU1); 172 173 clear_tsk_thread_flag(p, TIF_USEDFPU); 174 clear_tsk_thread_flag(p, TIF_USEDMSA); 175 clear_tsk_thread_flag(p, TIF_MSA_CTX_LIVE); 176 177 #ifdef CONFIG_MIPS_MT_FPAFF 178 clear_tsk_thread_flag(p, TIF_FPUBOUND); 179 #endif /* CONFIG_MIPS_MT_FPAFF */ 180 181 #ifdef CONFIG_MIPS_FP_SUPPORT 182 atomic_set(&p->thread.bd_emu_frame, BD_EMUFRAME_NONE); 183 #endif 184 185 if (clone_flags & CLONE_SETTLS) 186 ti->tp_value = tls; 187 188 return 0; 189 } 190 191 #ifdef CONFIG_STACKPROTECTOR 192 #include <linux/stackprotector.h> 193 unsigned long __stack_chk_guard __read_mostly; 194 EXPORT_SYMBOL(__stack_chk_guard); 195 #endif 196 197 struct mips_frame_info { 198 void *func; 199 unsigned long func_size; 200 int frame_size; 201 int pc_offset; 202 }; 203 204 #define J_TARGET(pc,target) \ 205 (((unsigned long)(pc) & 0xf0000000) | ((target) << 2)) 206 207 static inline int is_ra_save_ins(union mips_instruction *ip, int *poff) 208 { 209 #ifdef CONFIG_CPU_MICROMIPS 210 /* 211 * swsp ra,offset 212 * swm16 reglist,offset(sp) 213 * swm32 reglist,offset(sp) 214 * sw32 ra,offset(sp) 215 * jradiussp - NOT SUPPORTED 216 * 217 * microMIPS is way more fun... 218 */ 219 if (mm_insn_16bit(ip->word >> 16)) { 220 switch (ip->mm16_r5_format.opcode) { 221 case mm_swsp16_op: 222 if (ip->mm16_r5_format.rt != 31) 223 return 0; 224 225 *poff = ip->mm16_r5_format.imm; 226 *poff = (*poff << 2) / sizeof(ulong); 227 return 1; 228 229 case mm_pool16c_op: 230 switch (ip->mm16_m_format.func) { 231 case mm_swm16_op: 232 *poff = ip->mm16_m_format.imm; 233 *poff += 1 + ip->mm16_m_format.rlist; 234 *poff = (*poff << 2) / sizeof(ulong); 235 return 1; 236 237 default: 238 return 0; 239 } 240 241 default: 242 return 0; 243 } 244 } 245 246 switch (ip->i_format.opcode) { 247 case mm_sw32_op: 248 if (ip->i_format.rs != 29) 249 return 0; 250 if (ip->i_format.rt != 31) 251 return 0; 252 253 *poff = ip->i_format.simmediate / sizeof(ulong); 254 return 1; 255 256 case mm_pool32b_op: 257 switch (ip->mm_m_format.func) { 258 case mm_swm32_func: 259 if (ip->mm_m_format.rd < 0x10) 260 return 0; 261 if (ip->mm_m_format.base != 29) 262 return 0; 263 264 *poff = ip->mm_m_format.simmediate; 265 *poff += (ip->mm_m_format.rd & 0xf) * sizeof(u32); 266 *poff /= sizeof(ulong); 267 return 1; 268 default: 269 return 0; 270 } 271 272 default: 273 return 0; 274 } 275 #else 276 /* sw / sd $ra, offset($sp) */ 277 if ((ip->i_format.opcode == sw_op || ip->i_format.opcode == sd_op) && 278 ip->i_format.rs == 29 && ip->i_format.rt == 31) { 279 *poff = ip->i_format.simmediate / sizeof(ulong); 280 return 1; 281 } 282 #ifdef CONFIG_CPU_LOONGSON64 283 if ((ip->loongson3_lswc2_format.opcode == swc2_op) && 284 (ip->loongson3_lswc2_format.ls == 1) && 285 (ip->loongson3_lswc2_format.fr == 0) && 286 (ip->loongson3_lswc2_format.base == 29)) { 287 if (ip->loongson3_lswc2_format.rt == 31) { 288 *poff = ip->loongson3_lswc2_format.offset << 1; 289 return 1; 290 } 291 if (ip->loongson3_lswc2_format.rq == 31) { 292 *poff = (ip->loongson3_lswc2_format.offset << 1) + 1; 293 return 1; 294 } 295 } 296 #endif 297 return 0; 298 #endif 299 } 300 301 static inline int is_jump_ins(union mips_instruction *ip) 302 { 303 #ifdef CONFIG_CPU_MICROMIPS 304 /* 305 * jr16,jrc,jalr16,jalr16 306 * jal 307 * jalr/jr,jalr.hb/jr.hb,jalrs,jalrs.hb 308 * jraddiusp - NOT SUPPORTED 309 * 310 * microMIPS is kind of more fun... 311 */ 312 if (mm_insn_16bit(ip->word >> 16)) { 313 if ((ip->mm16_r5_format.opcode == mm_pool16c_op && 314 (ip->mm16_r5_format.rt & mm_jr16_op) == mm_jr16_op)) 315 return 1; 316 return 0; 317 } 318 319 if (ip->j_format.opcode == mm_j32_op) 320 return 1; 321 if (ip->j_format.opcode == mm_jal32_op) 322 return 1; 323 if (ip->r_format.opcode != mm_pool32a_op || 324 ip->r_format.func != mm_pool32axf_op) 325 return 0; 326 return ((ip->u_format.uimmediate >> 6) & mm_jalr_op) == mm_jalr_op; 327 #else 328 if (ip->j_format.opcode == j_op) 329 return 1; 330 if (ip->j_format.opcode == jal_op) 331 return 1; 332 if (ip->r_format.opcode != spec_op) 333 return 0; 334 return ip->r_format.func == jalr_op || ip->r_format.func == jr_op; 335 #endif 336 } 337 338 static inline int is_sp_move_ins(union mips_instruction *ip, int *frame_size) 339 { 340 #ifdef CONFIG_CPU_MICROMIPS 341 unsigned short tmp; 342 343 /* 344 * addiusp -imm 345 * addius5 sp,-imm 346 * addiu32 sp,sp,-imm 347 * jradiussp - NOT SUPPORTED 348 * 349 * microMIPS is not more fun... 350 */ 351 if (mm_insn_16bit(ip->word >> 16)) { 352 if (ip->mm16_r3_format.opcode == mm_pool16d_op && 353 ip->mm16_r3_format.simmediate & mm_addiusp_func) { 354 tmp = ip->mm_b0_format.simmediate >> 1; 355 tmp = ((tmp & 0x1ff) ^ 0x100) - 0x100; 356 if ((tmp + 2) < 4) /* 0x0,0x1,0x1fe,0x1ff are special */ 357 tmp ^= 0x100; 358 *frame_size = -(signed short)(tmp << 2); 359 return 1; 360 } 361 if (ip->mm16_r5_format.opcode == mm_pool16d_op && 362 ip->mm16_r5_format.rt == 29) { 363 tmp = ip->mm16_r5_format.imm >> 1; 364 *frame_size = -(signed short)(tmp & 0xf); 365 return 1; 366 } 367 return 0; 368 } 369 370 if (ip->mm_i_format.opcode == mm_addiu32_op && 371 ip->mm_i_format.rt == 29 && ip->mm_i_format.rs == 29) { 372 *frame_size = -ip->i_format.simmediate; 373 return 1; 374 } 375 #else 376 /* addiu/daddiu sp,sp,-imm */ 377 if (ip->i_format.rs != 29 || ip->i_format.rt != 29) 378 return 0; 379 380 if (ip->i_format.opcode == addiu_op || 381 ip->i_format.opcode == daddiu_op) { 382 *frame_size = -ip->i_format.simmediate; 383 return 1; 384 } 385 #endif 386 return 0; 387 } 388 389 static int get_frame_info(struct mips_frame_info *info) 390 { 391 bool is_mmips = IS_ENABLED(CONFIG_CPU_MICROMIPS); 392 union mips_instruction insn, *ip; 393 const unsigned int max_insns = 128; 394 unsigned int last_insn_size = 0; 395 unsigned int i; 396 bool saw_jump = false; 397 398 info->pc_offset = -1; 399 info->frame_size = 0; 400 401 ip = (void *)msk_isa16_mode((ulong)info->func); 402 if (!ip) 403 goto err; 404 405 for (i = 0; i < max_insns; i++) { 406 ip = (void *)ip + last_insn_size; 407 408 if (is_mmips && mm_insn_16bit(ip->halfword[0])) { 409 insn.word = ip->halfword[0] << 16; 410 last_insn_size = 2; 411 } else if (is_mmips) { 412 insn.word = ip->halfword[0] << 16 | ip->halfword[1]; 413 last_insn_size = 4; 414 } else { 415 insn.word = ip->word; 416 last_insn_size = 4; 417 } 418 419 if (!info->frame_size) { 420 is_sp_move_ins(&insn, &info->frame_size); 421 continue; 422 } else if (!saw_jump && is_jump_ins(ip)) { 423 /* 424 * If we see a jump instruction, we are finished 425 * with the frame save. 426 * 427 * Some functions can have a shortcut return at 428 * the beginning of the function, so don't start 429 * looking for jump instruction until we see the 430 * frame setup. 431 * 432 * The RA save instruction can get put into the 433 * delay slot of the jump instruction, so look 434 * at the next instruction, too. 435 */ 436 saw_jump = true; 437 continue; 438 } 439 if (info->pc_offset == -1 && 440 is_ra_save_ins(&insn, &info->pc_offset)) 441 break; 442 if (saw_jump) 443 break; 444 } 445 if (info->frame_size && info->pc_offset >= 0) /* nested */ 446 return 0; 447 if (info->pc_offset < 0) /* leaf */ 448 return 1; 449 /* prologue seems bogus... */ 450 err: 451 return -1; 452 } 453 454 static struct mips_frame_info schedule_mfi __read_mostly; 455 456 #ifdef CONFIG_KALLSYMS 457 static unsigned long get___schedule_addr(void) 458 { 459 return kallsyms_lookup_name("__schedule"); 460 } 461 #else 462 static unsigned long get___schedule_addr(void) 463 { 464 union mips_instruction *ip = (void *)schedule; 465 int max_insns = 8; 466 int i; 467 468 for (i = 0; i < max_insns; i++, ip++) { 469 if (ip->j_format.opcode == j_op) 470 return J_TARGET(ip, ip->j_format.target); 471 } 472 return 0; 473 } 474 #endif 475 476 static int __init frame_info_init(void) 477 { 478 unsigned long size = 0; 479 #ifdef CONFIG_KALLSYMS 480 unsigned long ofs; 481 #endif 482 unsigned long addr; 483 484 addr = get___schedule_addr(); 485 if (!addr) 486 addr = (unsigned long)schedule; 487 488 #ifdef CONFIG_KALLSYMS 489 kallsyms_lookup_size_offset(addr, &size, &ofs); 490 #endif 491 schedule_mfi.func = (void *)addr; 492 schedule_mfi.func_size = size; 493 494 get_frame_info(&schedule_mfi); 495 496 /* 497 * Without schedule() frame info, result given by 498 * thread_saved_pc() and get_wchan() are not reliable. 499 */ 500 if (schedule_mfi.pc_offset < 0) 501 printk("Can't analyze schedule() prologue at %p\n", schedule); 502 503 return 0; 504 } 505 506 arch_initcall(frame_info_init); 507 508 /* 509 * Return saved PC of a blocked thread. 510 */ 511 static unsigned long thread_saved_pc(struct task_struct *tsk) 512 { 513 struct thread_struct *t = &tsk->thread; 514 515 /* New born processes are a special case */ 516 if (t->reg31 == (unsigned long) ret_from_fork) 517 return t->reg31; 518 if (schedule_mfi.pc_offset < 0) 519 return 0; 520 return ((unsigned long *)t->reg29)[schedule_mfi.pc_offset]; 521 } 522 523 524 #ifdef CONFIG_KALLSYMS 525 /* generic stack unwinding function */ 526 unsigned long notrace unwind_stack_by_address(unsigned long stack_page, 527 unsigned long *sp, 528 unsigned long pc, 529 unsigned long *ra) 530 { 531 unsigned long low, high, irq_stack_high; 532 struct mips_frame_info info; 533 unsigned long size, ofs; 534 struct pt_regs *regs; 535 int leaf; 536 537 if (!stack_page) 538 return 0; 539 540 /* 541 * IRQ stacks start at IRQ_STACK_START 542 * task stacks at THREAD_SIZE - 32 543 */ 544 low = stack_page; 545 if (!preemptible() && on_irq_stack(raw_smp_processor_id(), *sp)) { 546 high = stack_page + IRQ_STACK_START; 547 irq_stack_high = high; 548 } else { 549 high = stack_page + THREAD_SIZE - 32; 550 irq_stack_high = 0; 551 } 552 553 /* 554 * If we reached the top of the interrupt stack, start unwinding 555 * the interrupted task stack. 556 */ 557 if (unlikely(*sp == irq_stack_high)) { 558 unsigned long task_sp = *(unsigned long *)*sp; 559 560 /* 561 * Check that the pointer saved in the IRQ stack head points to 562 * something within the stack of the current task 563 */ 564 if (!object_is_on_stack((void *)task_sp)) 565 return 0; 566 567 /* 568 * Follow pointer to tasks kernel stack frame where interrupted 569 * state was saved. 570 */ 571 regs = (struct pt_regs *)task_sp; 572 pc = regs->cp0_epc; 573 if (!user_mode(regs) && __kernel_text_address(pc)) { 574 *sp = regs->regs[29]; 575 *ra = regs->regs[31]; 576 return pc; 577 } 578 return 0; 579 } 580 if (!kallsyms_lookup_size_offset(pc, &size, &ofs)) 581 return 0; 582 /* 583 * Return ra if an exception occurred at the first instruction 584 */ 585 if (unlikely(ofs == 0)) { 586 pc = *ra; 587 *ra = 0; 588 return pc; 589 } 590 591 info.func = (void *)(pc - ofs); 592 info.func_size = ofs; /* analyze from start to ofs */ 593 leaf = get_frame_info(&info); 594 if (leaf < 0) 595 return 0; 596 597 if (*sp < low || *sp + info.frame_size > high) 598 return 0; 599 600 if (leaf) 601 /* 602 * For some extreme cases, get_frame_info() can 603 * consider wrongly a nested function as a leaf 604 * one. In that cases avoid to return always the 605 * same value. 606 */ 607 pc = pc != *ra ? *ra : 0; 608 else 609 pc = ((unsigned long *)(*sp))[info.pc_offset]; 610 611 *sp += info.frame_size; 612 *ra = 0; 613 return __kernel_text_address(pc) ? pc : 0; 614 } 615 EXPORT_SYMBOL(unwind_stack_by_address); 616 617 /* used by show_backtrace() */ 618 unsigned long unwind_stack(struct task_struct *task, unsigned long *sp, 619 unsigned long pc, unsigned long *ra) 620 { 621 unsigned long stack_page = 0; 622 int cpu; 623 624 for_each_possible_cpu(cpu) { 625 if (on_irq_stack(cpu, *sp)) { 626 stack_page = (unsigned long)irq_stack[cpu]; 627 break; 628 } 629 } 630 631 if (!stack_page) 632 stack_page = (unsigned long)task_stack_page(task); 633 634 return unwind_stack_by_address(stack_page, sp, pc, ra); 635 } 636 #endif 637 638 /* 639 * get_wchan - a maintenance nightmare^W^Wpain in the ass ... 640 */ 641 unsigned long get_wchan(struct task_struct *task) 642 { 643 unsigned long pc = 0; 644 #ifdef CONFIG_KALLSYMS 645 unsigned long sp; 646 unsigned long ra = 0; 647 #endif 648 649 if (!task || task == current || task->state == TASK_RUNNING) 650 goto out; 651 if (!task_stack_page(task)) 652 goto out; 653 654 pc = thread_saved_pc(task); 655 656 #ifdef CONFIG_KALLSYMS 657 sp = task->thread.reg29 + schedule_mfi.frame_size; 658 659 while (in_sched_functions(pc)) 660 pc = unwind_stack(task, &sp, pc, &ra); 661 #endif 662 663 out: 664 return pc; 665 } 666 667 unsigned long mips_stack_top(void) 668 { 669 unsigned long top = TASK_SIZE & PAGE_MASK; 670 671 if (IS_ENABLED(CONFIG_MIPS_FP_SUPPORT)) { 672 /* One page for branch delay slot "emulation" */ 673 top -= PAGE_SIZE; 674 } 675 676 /* Space for the VDSO, data page & GIC user page */ 677 top -= PAGE_ALIGN(current->thread.abi->vdso->size); 678 top -= PAGE_SIZE; 679 top -= mips_gic_present() ? PAGE_SIZE : 0; 680 681 /* Space for cache colour alignment */ 682 if (cpu_has_dc_aliases) 683 top -= shm_align_mask + 1; 684 685 /* Space to randomize the VDSO base */ 686 if (current->flags & PF_RANDOMIZE) 687 top -= VDSO_RANDOMIZE_SIZE; 688 689 return top; 690 } 691 692 /* 693 * Don't forget that the stack pointer must be aligned on a 8 bytes 694 * boundary for 32-bits ABI and 16 bytes for 64-bits ABI. 695 */ 696 unsigned long arch_align_stack(unsigned long sp) 697 { 698 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) 699 sp -= get_random_int() & ~PAGE_MASK; 700 701 return sp & ALMASK; 702 } 703 704 static DEFINE_PER_CPU(call_single_data_t, backtrace_csd); 705 static struct cpumask backtrace_csd_busy; 706 707 static void handle_backtrace(void *info) 708 { 709 nmi_cpu_backtrace(get_irq_regs()); 710 cpumask_clear_cpu(smp_processor_id(), &backtrace_csd_busy); 711 } 712 713 static void raise_backtrace(cpumask_t *mask) 714 { 715 call_single_data_t *csd; 716 int cpu; 717 718 for_each_cpu(cpu, mask) { 719 /* 720 * If we previously sent an IPI to the target CPU & it hasn't 721 * cleared its bit in the busy cpumask then it didn't handle 722 * our previous IPI & it's not safe for us to reuse the 723 * call_single_data_t. 724 */ 725 if (cpumask_test_and_set_cpu(cpu, &backtrace_csd_busy)) { 726 pr_warn("Unable to send backtrace IPI to CPU%u - perhaps it hung?\n", 727 cpu); 728 continue; 729 } 730 731 csd = &per_cpu(backtrace_csd, cpu); 732 csd->func = handle_backtrace; 733 smp_call_function_single_async(cpu, csd); 734 } 735 } 736 737 void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) 738 { 739 nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_backtrace); 740 } 741 742 int mips_get_process_fp_mode(struct task_struct *task) 743 { 744 int value = 0; 745 746 if (!test_tsk_thread_flag(task, TIF_32BIT_FPREGS)) 747 value |= PR_FP_MODE_FR; 748 if (test_tsk_thread_flag(task, TIF_HYBRID_FPREGS)) 749 value |= PR_FP_MODE_FRE; 750 751 return value; 752 } 753 754 static long prepare_for_fp_mode_switch(void *unused) 755 { 756 /* 757 * This is icky, but we use this to simply ensure that all CPUs have 758 * context switched, regardless of whether they were previously running 759 * kernel or user code. This ensures that no CPU that a mode-switching 760 * program may execute on keeps its FPU enabled (& in the old mode) 761 * throughout the mode switch. 762 */ 763 return 0; 764 } 765 766 int mips_set_process_fp_mode(struct task_struct *task, unsigned int value) 767 { 768 const unsigned int known_bits = PR_FP_MODE_FR | PR_FP_MODE_FRE; 769 struct task_struct *t; 770 struct cpumask process_cpus; 771 int cpu; 772 773 /* If nothing to change, return right away, successfully. */ 774 if (value == mips_get_process_fp_mode(task)) 775 return 0; 776 777 /* Only accept a mode change if 64-bit FP enabled for o32. */ 778 if (!IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT)) 779 return -EOPNOTSUPP; 780 781 /* And only for o32 tasks. */ 782 if (IS_ENABLED(CONFIG_64BIT) && !test_thread_flag(TIF_32BIT_REGS)) 783 return -EOPNOTSUPP; 784 785 /* Check the value is valid */ 786 if (value & ~known_bits) 787 return -EOPNOTSUPP; 788 789 /* Setting FRE without FR is not supported. */ 790 if ((value & (PR_FP_MODE_FR | PR_FP_MODE_FRE)) == PR_FP_MODE_FRE) 791 return -EOPNOTSUPP; 792 793 /* Avoid inadvertently triggering emulation */ 794 if ((value & PR_FP_MODE_FR) && raw_cpu_has_fpu && 795 !(raw_current_cpu_data.fpu_id & MIPS_FPIR_F64)) 796 return -EOPNOTSUPP; 797 if ((value & PR_FP_MODE_FRE) && raw_cpu_has_fpu && !cpu_has_fre) 798 return -EOPNOTSUPP; 799 800 /* FR = 0 not supported in MIPS R6 */ 801 if (!(value & PR_FP_MODE_FR) && raw_cpu_has_fpu && cpu_has_mips_r6) 802 return -EOPNOTSUPP; 803 804 /* Indicate the new FP mode in each thread */ 805 for_each_thread(task, t) { 806 /* Update desired FP register width */ 807 if (value & PR_FP_MODE_FR) { 808 clear_tsk_thread_flag(t, TIF_32BIT_FPREGS); 809 } else { 810 set_tsk_thread_flag(t, TIF_32BIT_FPREGS); 811 clear_tsk_thread_flag(t, TIF_MSA_CTX_LIVE); 812 } 813 814 /* Update desired FP single layout */ 815 if (value & PR_FP_MODE_FRE) 816 set_tsk_thread_flag(t, TIF_HYBRID_FPREGS); 817 else 818 clear_tsk_thread_flag(t, TIF_HYBRID_FPREGS); 819 } 820 821 /* 822 * We need to ensure that all threads in the process have switched mode 823 * before returning, in order to allow userland to not worry about 824 * races. We can do this by forcing all CPUs that any thread in the 825 * process may be running on to schedule something else - in this case 826 * prepare_for_fp_mode_switch(). 827 * 828 * We begin by generating a mask of all CPUs that any thread in the 829 * process may be running on. 830 */ 831 cpumask_clear(&process_cpus); 832 for_each_thread(task, t) 833 cpumask_set_cpu(task_cpu(t), &process_cpus); 834 835 /* 836 * Now we schedule prepare_for_fp_mode_switch() on each of those CPUs. 837 * 838 * The CPUs may have rescheduled already since we switched mode or 839 * generated the cpumask, but that doesn't matter. If the task in this 840 * process is scheduled out then our scheduling 841 * prepare_for_fp_mode_switch() will simply be redundant. If it's 842 * scheduled in then it will already have picked up the new FP mode 843 * whilst doing so. 844 */ 845 get_online_cpus(); 846 for_each_cpu_and(cpu, &process_cpus, cpu_online_mask) 847 work_on_cpu(cpu, prepare_for_fp_mode_switch, NULL); 848 put_online_cpus(); 849 850 return 0; 851 } 852 853 #if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32) 854 void mips_dump_regs32(u32 *uregs, const struct pt_regs *regs) 855 { 856 unsigned int i; 857 858 for (i = MIPS32_EF_R1; i <= MIPS32_EF_R31; i++) { 859 /* k0/k1 are copied as zero. */ 860 if (i == MIPS32_EF_R26 || i == MIPS32_EF_R27) 861 uregs[i] = 0; 862 else 863 uregs[i] = regs->regs[i - MIPS32_EF_R0]; 864 } 865 866 uregs[MIPS32_EF_LO] = regs->lo; 867 uregs[MIPS32_EF_HI] = regs->hi; 868 uregs[MIPS32_EF_CP0_EPC] = regs->cp0_epc; 869 uregs[MIPS32_EF_CP0_BADVADDR] = regs->cp0_badvaddr; 870 uregs[MIPS32_EF_CP0_STATUS] = regs->cp0_status; 871 uregs[MIPS32_EF_CP0_CAUSE] = regs->cp0_cause; 872 } 873 #endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */ 874 875 #ifdef CONFIG_64BIT 876 void mips_dump_regs64(u64 *uregs, const struct pt_regs *regs) 877 { 878 unsigned int i; 879 880 for (i = MIPS64_EF_R1; i <= MIPS64_EF_R31; i++) { 881 /* k0/k1 are copied as zero. */ 882 if (i == MIPS64_EF_R26 || i == MIPS64_EF_R27) 883 uregs[i] = 0; 884 else 885 uregs[i] = regs->regs[i - MIPS64_EF_R0]; 886 } 887 888 uregs[MIPS64_EF_LO] = regs->lo; 889 uregs[MIPS64_EF_HI] = regs->hi; 890 uregs[MIPS64_EF_CP0_EPC] = regs->cp0_epc; 891 uregs[MIPS64_EF_CP0_BADVADDR] = regs->cp0_badvaddr; 892 uregs[MIPS64_EF_CP0_STATUS] = regs->cp0_status; 893 uregs[MIPS64_EF_CP0_CAUSE] = regs->cp0_cause; 894 } 895 #endif /* CONFIG_64BIT */ 896