1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Based on arch/arm/kernel/traps.c 4 * 5 * Copyright (C) 1995-2009 Russell King 6 * Copyright (C) 2012 ARM Ltd. 7 */ 8 9 #include <linux/bug.h> 10 #include <linux/context_tracking.h> 11 #include <linux/signal.h> 12 #include <linux/kallsyms.h> 13 #include <linux/kprobes.h> 14 #include <linux/spinlock.h> 15 #include <linux/uaccess.h> 16 #include <linux/hardirq.h> 17 #include <linux/kdebug.h> 18 #include <linux/module.h> 19 #include <linux/kexec.h> 20 #include <linux/delay.h> 21 #include <linux/init.h> 22 #include <linux/sched/signal.h> 23 #include <linux/sched/debug.h> 24 #include <linux/sched/task_stack.h> 25 #include <linux/sizes.h> 26 #include <linux/syscalls.h> 27 #include <linux/mm_types.h> 28 #include <linux/kasan.h> 29 #include <linux/cfi.h> 30 31 #include <asm/atomic.h> 32 #include <asm/bug.h> 33 #include <asm/cpufeature.h> 34 #include <asm/daifflags.h> 35 #include <asm/debug-monitors.h> 36 #include <asm/esr.h> 37 #include <asm/exception.h> 38 #include <asm/extable.h> 39 #include <asm/insn.h> 40 #include <asm/kprobes.h> 41 #include <asm/patching.h> 42 #include <asm/traps.h> 43 #include <asm/smp.h> 44 #include <asm/stack_pointer.h> 45 #include <asm/stacktrace.h> 46 #include <asm/system_misc.h> 47 #include <asm/sysreg.h> 48 49 static bool __kprobes __check_eq(unsigned long pstate) 50 { 51 return (pstate & PSR_Z_BIT) != 0; 52 } 53 54 static bool __kprobes __check_ne(unsigned long pstate) 55 { 56 return (pstate & PSR_Z_BIT) == 0; 57 } 58 59 static bool __kprobes __check_cs(unsigned long pstate) 60 { 61 return (pstate & PSR_C_BIT) != 0; 62 } 63 64 static bool __kprobes __check_cc(unsigned long pstate) 65 { 66 return (pstate & PSR_C_BIT) == 0; 67 } 68 69 static bool __kprobes __check_mi(unsigned long pstate) 70 { 71 return (pstate & PSR_N_BIT) != 0; 72 } 73 74 static bool __kprobes __check_pl(unsigned long pstate) 75 { 76 return (pstate & PSR_N_BIT) == 0; 77 } 78 79 static bool __kprobes __check_vs(unsigned long pstate) 80 { 81 return (pstate & PSR_V_BIT) != 0; 82 } 83 84 static bool __kprobes __check_vc(unsigned long pstate) 85 { 86 return (pstate & PSR_V_BIT) == 0; 87 } 88 89 static bool __kprobes __check_hi(unsigned long pstate) 90 { 91 pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ 92 return (pstate & PSR_C_BIT) != 0; 93 } 94 95 static bool __kprobes __check_ls(unsigned long pstate) 96 { 97 pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ 98 return (pstate & PSR_C_BIT) == 0; 99 } 100 101 static bool __kprobes __check_ge(unsigned long pstate) 102 { 103 pstate ^= (pstate << 3); /* PSR_N_BIT ^= PSR_V_BIT */ 104 return (pstate & PSR_N_BIT) == 0; 105 } 106 107 static bool __kprobes __check_lt(unsigned long pstate) 108 { 109 pstate ^= (pstate << 3); /* PSR_N_BIT ^= PSR_V_BIT */ 110 return (pstate & PSR_N_BIT) != 0; 111 } 112 113 static bool __kprobes __check_gt(unsigned long pstate) 114 { 115 /*PSR_N_BIT ^= PSR_V_BIT */ 116 unsigned long temp = pstate ^ (pstate << 3); 117 118 temp |= (pstate << 1); /*PSR_N_BIT |= PSR_Z_BIT */ 119 return (temp & PSR_N_BIT) == 0; 120 } 121 122 static bool __kprobes __check_le(unsigned long pstate) 123 { 124 /*PSR_N_BIT ^= PSR_V_BIT */ 125 unsigned long temp = pstate ^ (pstate << 3); 126 127 temp |= (pstate << 1); /*PSR_N_BIT |= PSR_Z_BIT */ 128 return (temp & PSR_N_BIT) != 0; 129 } 130 131 static bool __kprobes __check_al(unsigned long pstate) 132 { 133 return true; 134 } 135 136 /* 137 * Note that the ARMv8 ARM calls condition code 0b1111 "nv", but states that 138 * it behaves identically to 0b1110 ("al"). 139 */ 140 pstate_check_t * const aarch32_opcode_cond_checks[16] = { 141 __check_eq, __check_ne, __check_cs, __check_cc, 142 __check_mi, __check_pl, __check_vs, __check_vc, 143 __check_hi, __check_ls, __check_ge, __check_lt, 144 __check_gt, __check_le, __check_al, __check_al 145 }; 146 147 int show_unhandled_signals = 0; 148 149 static void dump_kernel_instr(const char *lvl, struct pt_regs *regs) 150 { 151 unsigned long addr = instruction_pointer(regs); 152 char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str; 153 int i; 154 155 if (user_mode(regs)) 156 return; 157 158 for (i = -4; i < 1; i++) { 159 unsigned int val, bad; 160 161 bad = aarch64_insn_read(&((u32 *)addr)[i], &val); 162 163 if (!bad) 164 p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val); 165 else { 166 p += sprintf(p, "bad PC value"); 167 break; 168 } 169 } 170 171 printk("%sCode: %s\n", lvl, str); 172 } 173 174 #ifdef CONFIG_PREEMPT 175 #define S_PREEMPT " PREEMPT" 176 #elif defined(CONFIG_PREEMPT_RT) 177 #define S_PREEMPT " PREEMPT_RT" 178 #else 179 #define S_PREEMPT "" 180 #endif 181 182 #define S_SMP " SMP" 183 184 static int __die(const char *str, long err, struct pt_regs *regs) 185 { 186 static int die_counter; 187 int ret; 188 189 pr_emerg("Internal error: %s: %016lx [#%d]" S_PREEMPT S_SMP "\n", 190 str, err, ++die_counter); 191 192 /* trap and error numbers are mostly meaningless on ARM */ 193 ret = notify_die(DIE_OOPS, str, regs, err, 0, SIGSEGV); 194 if (ret == NOTIFY_STOP) 195 return ret; 196 197 print_modules(); 198 show_regs(regs); 199 200 dump_kernel_instr(KERN_EMERG, regs); 201 202 return ret; 203 } 204 205 static DEFINE_RAW_SPINLOCK(die_lock); 206 207 /* 208 * This function is protected against re-entrancy. 209 */ 210 void die(const char *str, struct pt_regs *regs, long err) 211 { 212 int ret; 213 unsigned long flags; 214 215 raw_spin_lock_irqsave(&die_lock, flags); 216 217 oops_enter(); 218 219 console_verbose(); 220 bust_spinlocks(1); 221 ret = __die(str, err, regs); 222 223 if (regs && kexec_should_crash(current)) 224 crash_kexec(regs); 225 226 bust_spinlocks(0); 227 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 228 oops_exit(); 229 230 if (in_interrupt()) 231 panic("%s: Fatal exception in interrupt", str); 232 if (panic_on_oops) 233 panic("%s: Fatal exception", str); 234 235 raw_spin_unlock_irqrestore(&die_lock, flags); 236 237 if (ret != NOTIFY_STOP) 238 make_task_dead(SIGSEGV); 239 } 240 241 static void arm64_show_signal(int signo, const char *str) 242 { 243 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, 244 DEFAULT_RATELIMIT_BURST); 245 struct task_struct *tsk = current; 246 unsigned long esr = tsk->thread.fault_code; 247 struct pt_regs *regs = task_pt_regs(tsk); 248 249 /* Leave if the signal won't be shown */ 250 if (!show_unhandled_signals || 251 !unhandled_signal(tsk, signo) || 252 !__ratelimit(&rs)) 253 return; 254 255 pr_info("%s[%d]: unhandled exception: ", tsk->comm, task_pid_nr(tsk)); 256 if (esr) 257 pr_cont("%s, ESR 0x%016lx, ", esr_get_class_string(esr), esr); 258 259 pr_cont("%s", str); 260 print_vma_addr(KERN_CONT " in ", regs->pc); 261 pr_cont("\n"); 262 __show_regs(regs); 263 } 264 265 void arm64_force_sig_fault(int signo, int code, unsigned long far, 266 const char *str) 267 { 268 arm64_show_signal(signo, str); 269 if (signo == SIGKILL) 270 force_sig(SIGKILL); 271 else 272 force_sig_fault(signo, code, (void __user *)far); 273 } 274 275 void arm64_force_sig_mceerr(int code, unsigned long far, short lsb, 276 const char *str) 277 { 278 arm64_show_signal(SIGBUS, str); 279 force_sig_mceerr(code, (void __user *)far, lsb); 280 } 281 282 void arm64_force_sig_ptrace_errno_trap(int errno, unsigned long far, 283 const char *str) 284 { 285 arm64_show_signal(SIGTRAP, str); 286 force_sig_ptrace_errno_trap(errno, (void __user *)far); 287 } 288 289 void arm64_notify_die(const char *str, struct pt_regs *regs, 290 int signo, int sicode, unsigned long far, 291 unsigned long err) 292 { 293 if (user_mode(regs)) { 294 WARN_ON(regs != current_pt_regs()); 295 current->thread.fault_address = 0; 296 current->thread.fault_code = err; 297 298 arm64_force_sig_fault(signo, sicode, far, str); 299 } else { 300 die(str, regs, err); 301 } 302 } 303 304 #ifdef CONFIG_COMPAT 305 #define PSTATE_IT_1_0_SHIFT 25 306 #define PSTATE_IT_1_0_MASK (0x3 << PSTATE_IT_1_0_SHIFT) 307 #define PSTATE_IT_7_2_SHIFT 10 308 #define PSTATE_IT_7_2_MASK (0x3f << PSTATE_IT_7_2_SHIFT) 309 310 static u32 compat_get_it_state(struct pt_regs *regs) 311 { 312 u32 it, pstate = regs->pstate; 313 314 it = (pstate & PSTATE_IT_1_0_MASK) >> PSTATE_IT_1_0_SHIFT; 315 it |= ((pstate & PSTATE_IT_7_2_MASK) >> PSTATE_IT_7_2_SHIFT) << 2; 316 317 return it; 318 } 319 320 static void compat_set_it_state(struct pt_regs *regs, u32 it) 321 { 322 u32 pstate_it; 323 324 pstate_it = (it << PSTATE_IT_1_0_SHIFT) & PSTATE_IT_1_0_MASK; 325 pstate_it |= ((it >> 2) << PSTATE_IT_7_2_SHIFT) & PSTATE_IT_7_2_MASK; 326 327 regs->pstate &= ~PSR_AA32_IT_MASK; 328 regs->pstate |= pstate_it; 329 } 330 331 static void advance_itstate(struct pt_regs *regs) 332 { 333 u32 it; 334 335 /* ARM mode */ 336 if (!(regs->pstate & PSR_AA32_T_BIT) || 337 !(regs->pstate & PSR_AA32_IT_MASK)) 338 return; 339 340 it = compat_get_it_state(regs); 341 342 /* 343 * If this is the last instruction of the block, wipe the IT 344 * state. Otherwise advance it. 345 */ 346 if (!(it & 7)) 347 it = 0; 348 else 349 it = (it & 0xe0) | ((it << 1) & 0x1f); 350 351 compat_set_it_state(regs, it); 352 } 353 #else 354 static void advance_itstate(struct pt_regs *regs) 355 { 356 } 357 #endif 358 359 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size) 360 { 361 regs->pc += size; 362 363 /* 364 * If we were single stepping, we want to get the step exception after 365 * we return from the trap. 366 */ 367 if (user_mode(regs)) 368 user_fastforward_single_step(current); 369 370 if (compat_user_mode(regs)) 371 advance_itstate(regs); 372 else 373 regs->pstate &= ~PSR_BTYPE_MASK; 374 } 375 376 static LIST_HEAD(undef_hook); 377 static DEFINE_RAW_SPINLOCK(undef_lock); 378 379 void register_undef_hook(struct undef_hook *hook) 380 { 381 unsigned long flags; 382 383 raw_spin_lock_irqsave(&undef_lock, flags); 384 list_add(&hook->node, &undef_hook); 385 raw_spin_unlock_irqrestore(&undef_lock, flags); 386 } 387 388 void unregister_undef_hook(struct undef_hook *hook) 389 { 390 unsigned long flags; 391 392 raw_spin_lock_irqsave(&undef_lock, flags); 393 list_del(&hook->node); 394 raw_spin_unlock_irqrestore(&undef_lock, flags); 395 } 396 397 static int user_insn_read(struct pt_regs *regs, u32 *insnp) 398 { 399 u32 instr; 400 unsigned long pc = instruction_pointer(regs); 401 402 if (compat_thumb_mode(regs)) { 403 /* 16-bit Thumb instruction */ 404 __le16 instr_le; 405 if (get_user(instr_le, (__le16 __user *)pc)) 406 return -EFAULT; 407 instr = le16_to_cpu(instr_le); 408 if (aarch32_insn_is_wide(instr)) { 409 u32 instr2; 410 411 if (get_user(instr_le, (__le16 __user *)(pc + 2))) 412 return -EFAULT; 413 instr2 = le16_to_cpu(instr_le); 414 instr = (instr << 16) | instr2; 415 } 416 } else { 417 /* 32-bit ARM instruction */ 418 __le32 instr_le; 419 if (get_user(instr_le, (__le32 __user *)pc)) 420 return -EFAULT; 421 instr = le32_to_cpu(instr_le); 422 } 423 424 *insnp = instr; 425 return 0; 426 } 427 428 static int call_undef_hook(struct pt_regs *regs, u32 instr) 429 { 430 struct undef_hook *hook; 431 unsigned long flags; 432 int (*fn)(struct pt_regs *regs, u32 instr) = NULL; 433 434 raw_spin_lock_irqsave(&undef_lock, flags); 435 list_for_each_entry(hook, &undef_hook, node) 436 if ((instr & hook->instr_mask) == hook->instr_val && 437 (regs->pstate & hook->pstate_mask) == hook->pstate_val) 438 fn = hook->fn; 439 440 raw_spin_unlock_irqrestore(&undef_lock, flags); 441 442 return fn ? fn(regs, instr) : 1; 443 } 444 445 void force_signal_inject(int signal, int code, unsigned long address, unsigned long err) 446 { 447 const char *desc; 448 struct pt_regs *regs = current_pt_regs(); 449 450 if (WARN_ON(!user_mode(regs))) 451 return; 452 453 switch (signal) { 454 case SIGILL: 455 desc = "undefined instruction"; 456 break; 457 case SIGSEGV: 458 desc = "illegal memory access"; 459 break; 460 default: 461 desc = "unknown or unrecoverable error"; 462 break; 463 } 464 465 /* Force signals we don't understand to SIGKILL */ 466 if (WARN_ON(signal != SIGKILL && 467 siginfo_layout(signal, code) != SIL_FAULT)) { 468 signal = SIGKILL; 469 } 470 471 arm64_notify_die(desc, regs, signal, code, address, err); 472 } 473 474 /* 475 * Set up process info to signal segmentation fault - called on access error. 476 */ 477 void arm64_notify_segfault(unsigned long addr) 478 { 479 int code; 480 481 mmap_read_lock(current->mm); 482 if (find_vma(current->mm, untagged_addr(addr)) == NULL) 483 code = SEGV_MAPERR; 484 else 485 code = SEGV_ACCERR; 486 mmap_read_unlock(current->mm); 487 488 force_signal_inject(SIGSEGV, code, addr, 0); 489 } 490 491 void do_el0_undef(struct pt_regs *regs, unsigned long esr) 492 { 493 u32 insn; 494 495 /* check for AArch32 breakpoint instructions */ 496 if (!aarch32_break_handler(regs)) 497 return; 498 499 if (user_insn_read(regs, &insn)) 500 goto out_err; 501 502 if (try_emulate_mrs(regs, insn)) 503 return; 504 505 if (call_undef_hook(regs, insn) == 0) 506 return; 507 508 out_err: 509 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 510 } 511 512 void do_el1_undef(struct pt_regs *regs, unsigned long esr) 513 { 514 u32 insn; 515 516 if (aarch64_insn_read((void *)regs->pc, &insn)) 517 goto out_err; 518 519 if (try_emulate_el1_ssbs(regs, insn)) 520 return; 521 522 out_err: 523 die("Oops - Undefined instruction", regs, esr); 524 } 525 526 void do_el0_bti(struct pt_regs *regs) 527 { 528 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 529 } 530 531 void do_el1_bti(struct pt_regs *regs, unsigned long esr) 532 { 533 die("Oops - BTI", regs, esr); 534 } 535 536 void do_el0_fpac(struct pt_regs *regs, unsigned long esr) 537 { 538 force_signal_inject(SIGILL, ILL_ILLOPN, regs->pc, esr); 539 } 540 541 void do_el1_fpac(struct pt_regs *regs, unsigned long esr) 542 { 543 /* 544 * Unexpected FPAC exception in the kernel: kill the task before it 545 * does any more harm. 546 */ 547 die("Oops - FPAC", regs, esr); 548 } 549 550 #define __user_cache_maint(insn, address, res) \ 551 if (address >= TASK_SIZE_MAX) { \ 552 res = -EFAULT; \ 553 } else { \ 554 uaccess_ttbr0_enable(); \ 555 asm volatile ( \ 556 "1: " insn ", %1\n" \ 557 " mov %w0, #0\n" \ 558 "2:\n" \ 559 _ASM_EXTABLE_UACCESS_ERR(1b, 2b, %w0) \ 560 : "=r" (res) \ 561 : "r" (address)); \ 562 uaccess_ttbr0_disable(); \ 563 } 564 565 static void user_cache_maint_handler(unsigned long esr, struct pt_regs *regs) 566 { 567 unsigned long tagged_address, address; 568 int rt = ESR_ELx_SYS64_ISS_RT(esr); 569 int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT; 570 int ret = 0; 571 572 tagged_address = pt_regs_read_reg(regs, rt); 573 address = untagged_addr(tagged_address); 574 575 switch (crm) { 576 case ESR_ELx_SYS64_ISS_CRM_DC_CVAU: /* DC CVAU, gets promoted */ 577 __user_cache_maint("dc civac", address, ret); 578 break; 579 case ESR_ELx_SYS64_ISS_CRM_DC_CVAC: /* DC CVAC, gets promoted */ 580 __user_cache_maint("dc civac", address, ret); 581 break; 582 case ESR_ELx_SYS64_ISS_CRM_DC_CVADP: /* DC CVADP */ 583 __user_cache_maint("sys 3, c7, c13, 1", address, ret); 584 break; 585 case ESR_ELx_SYS64_ISS_CRM_DC_CVAP: /* DC CVAP */ 586 __user_cache_maint("sys 3, c7, c12, 1", address, ret); 587 break; 588 case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC: /* DC CIVAC */ 589 __user_cache_maint("dc civac", address, ret); 590 break; 591 case ESR_ELx_SYS64_ISS_CRM_IC_IVAU: /* IC IVAU */ 592 __user_cache_maint("ic ivau", address, ret); 593 break; 594 default: 595 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 596 return; 597 } 598 599 if (ret) 600 arm64_notify_segfault(tagged_address); 601 else 602 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 603 } 604 605 static void ctr_read_handler(unsigned long esr, struct pt_regs *regs) 606 { 607 int rt = ESR_ELx_SYS64_ISS_RT(esr); 608 unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0); 609 610 if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) { 611 /* Hide DIC so that we can trap the unnecessary maintenance...*/ 612 val &= ~BIT(CTR_EL0_DIC_SHIFT); 613 614 /* ... and fake IminLine to reduce the number of traps. */ 615 val &= ~CTR_EL0_IminLine_MASK; 616 val |= (PAGE_SHIFT - 2) & CTR_EL0_IminLine_MASK; 617 } 618 619 pt_regs_write_reg(regs, rt, val); 620 621 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 622 } 623 624 static void cntvct_read_handler(unsigned long esr, struct pt_regs *regs) 625 { 626 int rt = ESR_ELx_SYS64_ISS_RT(esr); 627 628 pt_regs_write_reg(regs, rt, arch_timer_read_counter()); 629 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 630 } 631 632 static void cntfrq_read_handler(unsigned long esr, struct pt_regs *regs) 633 { 634 int rt = ESR_ELx_SYS64_ISS_RT(esr); 635 636 pt_regs_write_reg(regs, rt, arch_timer_get_rate()); 637 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 638 } 639 640 static void mrs_handler(unsigned long esr, struct pt_regs *regs) 641 { 642 u32 sysreg, rt; 643 644 rt = ESR_ELx_SYS64_ISS_RT(esr); 645 sysreg = esr_sys64_to_sysreg(esr); 646 647 if (do_emulate_mrs(regs, sysreg, rt) != 0) 648 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 649 } 650 651 static void wfi_handler(unsigned long esr, struct pt_regs *regs) 652 { 653 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 654 } 655 656 struct sys64_hook { 657 unsigned long esr_mask; 658 unsigned long esr_val; 659 void (*handler)(unsigned long esr, struct pt_regs *regs); 660 }; 661 662 static const struct sys64_hook sys64_hooks[] = { 663 { 664 .esr_mask = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK, 665 .esr_val = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL, 666 .handler = user_cache_maint_handler, 667 }, 668 { 669 /* Trap read access to CTR_EL0 */ 670 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 671 .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ, 672 .handler = ctr_read_handler, 673 }, 674 { 675 /* Trap read access to CNTVCT_EL0 */ 676 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 677 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT, 678 .handler = cntvct_read_handler, 679 }, 680 { 681 /* Trap read access to CNTVCTSS_EL0 */ 682 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 683 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCTSS, 684 .handler = cntvct_read_handler, 685 }, 686 { 687 /* Trap read access to CNTFRQ_EL0 */ 688 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 689 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTFRQ, 690 .handler = cntfrq_read_handler, 691 }, 692 { 693 /* Trap read access to CPUID registers */ 694 .esr_mask = ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK, 695 .esr_val = ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL, 696 .handler = mrs_handler, 697 }, 698 { 699 /* Trap WFI instructions executed in userspace */ 700 .esr_mask = ESR_ELx_WFx_MASK, 701 .esr_val = ESR_ELx_WFx_WFI_VAL, 702 .handler = wfi_handler, 703 }, 704 {}, 705 }; 706 707 #ifdef CONFIG_COMPAT 708 static bool cp15_cond_valid(unsigned long esr, struct pt_regs *regs) 709 { 710 int cond; 711 712 /* Only a T32 instruction can trap without CV being set */ 713 if (!(esr & ESR_ELx_CV)) { 714 u32 it; 715 716 it = compat_get_it_state(regs); 717 if (!it) 718 return true; 719 720 cond = it >> 4; 721 } else { 722 cond = (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT; 723 } 724 725 return aarch32_opcode_cond_checks[cond](regs->pstate); 726 } 727 728 static void compat_cntfrq_read_handler(unsigned long esr, struct pt_regs *regs) 729 { 730 int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT; 731 732 pt_regs_write_reg(regs, reg, arch_timer_get_rate()); 733 arm64_skip_faulting_instruction(regs, 4); 734 } 735 736 static const struct sys64_hook cp15_32_hooks[] = { 737 { 738 .esr_mask = ESR_ELx_CP15_32_ISS_SYS_MASK, 739 .esr_val = ESR_ELx_CP15_32_ISS_SYS_CNTFRQ, 740 .handler = compat_cntfrq_read_handler, 741 }, 742 {}, 743 }; 744 745 static void compat_cntvct_read_handler(unsigned long esr, struct pt_regs *regs) 746 { 747 int rt = (esr & ESR_ELx_CP15_64_ISS_RT_MASK) >> ESR_ELx_CP15_64_ISS_RT_SHIFT; 748 int rt2 = (esr & ESR_ELx_CP15_64_ISS_RT2_MASK) >> ESR_ELx_CP15_64_ISS_RT2_SHIFT; 749 u64 val = arch_timer_read_counter(); 750 751 pt_regs_write_reg(regs, rt, lower_32_bits(val)); 752 pt_regs_write_reg(regs, rt2, upper_32_bits(val)); 753 arm64_skip_faulting_instruction(regs, 4); 754 } 755 756 static const struct sys64_hook cp15_64_hooks[] = { 757 { 758 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK, 759 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCT, 760 .handler = compat_cntvct_read_handler, 761 }, 762 { 763 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK, 764 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS, 765 .handler = compat_cntvct_read_handler, 766 }, 767 {}, 768 }; 769 770 void do_el0_cp15(unsigned long esr, struct pt_regs *regs) 771 { 772 const struct sys64_hook *hook, *hook_base; 773 774 if (!cp15_cond_valid(esr, regs)) { 775 /* 776 * There is no T16 variant of a CP access, so we 777 * always advance PC by 4 bytes. 778 */ 779 arm64_skip_faulting_instruction(regs, 4); 780 return; 781 } 782 783 switch (ESR_ELx_EC(esr)) { 784 case ESR_ELx_EC_CP15_32: 785 hook_base = cp15_32_hooks; 786 break; 787 case ESR_ELx_EC_CP15_64: 788 hook_base = cp15_64_hooks; 789 break; 790 default: 791 do_el0_undef(regs, esr); 792 return; 793 } 794 795 for (hook = hook_base; hook->handler; hook++) 796 if ((hook->esr_mask & esr) == hook->esr_val) { 797 hook->handler(esr, regs); 798 return; 799 } 800 801 /* 802 * New cp15 instructions may previously have been undefined at 803 * EL0. Fall back to our usual undefined instruction handler 804 * so that we handle these consistently. 805 */ 806 do_el0_undef(regs, esr); 807 } 808 #endif 809 810 void do_el0_sys(unsigned long esr, struct pt_regs *regs) 811 { 812 const struct sys64_hook *hook; 813 814 for (hook = sys64_hooks; hook->handler; hook++) 815 if ((hook->esr_mask & esr) == hook->esr_val) { 816 hook->handler(esr, regs); 817 return; 818 } 819 820 /* 821 * New SYS instructions may previously have been undefined at EL0. Fall 822 * back to our usual undefined instruction handler so that we handle 823 * these consistently. 824 */ 825 do_el0_undef(regs, esr); 826 } 827 828 static const char *esr_class_str[] = { 829 [0 ... ESR_ELx_EC_MAX] = "UNRECOGNIZED EC", 830 [ESR_ELx_EC_UNKNOWN] = "Unknown/Uncategorized", 831 [ESR_ELx_EC_WFx] = "WFI/WFE", 832 [ESR_ELx_EC_CP15_32] = "CP15 MCR/MRC", 833 [ESR_ELx_EC_CP15_64] = "CP15 MCRR/MRRC", 834 [ESR_ELx_EC_CP14_MR] = "CP14 MCR/MRC", 835 [ESR_ELx_EC_CP14_LS] = "CP14 LDC/STC", 836 [ESR_ELx_EC_FP_ASIMD] = "ASIMD", 837 [ESR_ELx_EC_CP10_ID] = "CP10 MRC/VMRS", 838 [ESR_ELx_EC_PAC] = "PAC", 839 [ESR_ELx_EC_CP14_64] = "CP14 MCRR/MRRC", 840 [ESR_ELx_EC_BTI] = "BTI", 841 [ESR_ELx_EC_ILL] = "PSTATE.IL", 842 [ESR_ELx_EC_SVC32] = "SVC (AArch32)", 843 [ESR_ELx_EC_HVC32] = "HVC (AArch32)", 844 [ESR_ELx_EC_SMC32] = "SMC (AArch32)", 845 [ESR_ELx_EC_SVC64] = "SVC (AArch64)", 846 [ESR_ELx_EC_HVC64] = "HVC (AArch64)", 847 [ESR_ELx_EC_SMC64] = "SMC (AArch64)", 848 [ESR_ELx_EC_SYS64] = "MSR/MRS (AArch64)", 849 [ESR_ELx_EC_SVE] = "SVE", 850 [ESR_ELx_EC_ERET] = "ERET/ERETAA/ERETAB", 851 [ESR_ELx_EC_FPAC] = "FPAC", 852 [ESR_ELx_EC_SME] = "SME", 853 [ESR_ELx_EC_IMP_DEF] = "EL3 IMP DEF", 854 [ESR_ELx_EC_IABT_LOW] = "IABT (lower EL)", 855 [ESR_ELx_EC_IABT_CUR] = "IABT (current EL)", 856 [ESR_ELx_EC_PC_ALIGN] = "PC Alignment", 857 [ESR_ELx_EC_DABT_LOW] = "DABT (lower EL)", 858 [ESR_ELx_EC_DABT_CUR] = "DABT (current EL)", 859 [ESR_ELx_EC_SP_ALIGN] = "SP Alignment", 860 [ESR_ELx_EC_FP_EXC32] = "FP (AArch32)", 861 [ESR_ELx_EC_FP_EXC64] = "FP (AArch64)", 862 [ESR_ELx_EC_SERROR] = "SError", 863 [ESR_ELx_EC_BREAKPT_LOW] = "Breakpoint (lower EL)", 864 [ESR_ELx_EC_BREAKPT_CUR] = "Breakpoint (current EL)", 865 [ESR_ELx_EC_SOFTSTP_LOW] = "Software Step (lower EL)", 866 [ESR_ELx_EC_SOFTSTP_CUR] = "Software Step (current EL)", 867 [ESR_ELx_EC_WATCHPT_LOW] = "Watchpoint (lower EL)", 868 [ESR_ELx_EC_WATCHPT_CUR] = "Watchpoint (current EL)", 869 [ESR_ELx_EC_BKPT32] = "BKPT (AArch32)", 870 [ESR_ELx_EC_VECTOR32] = "Vector catch (AArch32)", 871 [ESR_ELx_EC_BRK64] = "BRK (AArch64)", 872 }; 873 874 const char *esr_get_class_string(unsigned long esr) 875 { 876 return esr_class_str[ESR_ELx_EC(esr)]; 877 } 878 879 /* 880 * bad_el0_sync handles unexpected, but potentially recoverable synchronous 881 * exceptions taken from EL0. 882 */ 883 void bad_el0_sync(struct pt_regs *regs, int reason, unsigned long esr) 884 { 885 unsigned long pc = instruction_pointer(regs); 886 887 current->thread.fault_address = 0; 888 current->thread.fault_code = esr; 889 890 arm64_force_sig_fault(SIGILL, ILL_ILLOPC, pc, 891 "Bad EL0 synchronous exception"); 892 } 893 894 #ifdef CONFIG_VMAP_STACK 895 896 DEFINE_PER_CPU(unsigned long [OVERFLOW_STACK_SIZE/sizeof(long)], overflow_stack) 897 __aligned(16); 898 899 void panic_bad_stack(struct pt_regs *regs, unsigned long esr, unsigned long far) 900 { 901 unsigned long tsk_stk = (unsigned long)current->stack; 902 unsigned long irq_stk = (unsigned long)this_cpu_read(irq_stack_ptr); 903 unsigned long ovf_stk = (unsigned long)this_cpu_ptr(overflow_stack); 904 905 console_verbose(); 906 pr_emerg("Insufficient stack space to handle exception!"); 907 908 pr_emerg("ESR: 0x%016lx -- %s\n", esr, esr_get_class_string(esr)); 909 pr_emerg("FAR: 0x%016lx\n", far); 910 911 pr_emerg("Task stack: [0x%016lx..0x%016lx]\n", 912 tsk_stk, tsk_stk + THREAD_SIZE); 913 pr_emerg("IRQ stack: [0x%016lx..0x%016lx]\n", 914 irq_stk, irq_stk + IRQ_STACK_SIZE); 915 pr_emerg("Overflow stack: [0x%016lx..0x%016lx]\n", 916 ovf_stk, ovf_stk + OVERFLOW_STACK_SIZE); 917 918 __show_regs(regs); 919 920 /* 921 * We use nmi_panic to limit the potential for recusive overflows, and 922 * to get a better stack trace. 923 */ 924 nmi_panic(NULL, "kernel stack overflow"); 925 cpu_park_loop(); 926 } 927 #endif 928 929 void __noreturn arm64_serror_panic(struct pt_regs *regs, unsigned long esr) 930 { 931 console_verbose(); 932 933 pr_crit("SError Interrupt on CPU%d, code 0x%016lx -- %s\n", 934 smp_processor_id(), esr, esr_get_class_string(esr)); 935 if (regs) 936 __show_regs(regs); 937 938 nmi_panic(regs, "Asynchronous SError Interrupt"); 939 940 cpu_park_loop(); 941 unreachable(); 942 } 943 944 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned long esr) 945 { 946 unsigned long aet = arm64_ras_serror_get_severity(esr); 947 948 switch (aet) { 949 case ESR_ELx_AET_CE: /* corrected error */ 950 case ESR_ELx_AET_UEO: /* restartable, not yet consumed */ 951 /* 952 * The CPU can make progress. We may take UEO again as 953 * a more severe error. 954 */ 955 return false; 956 957 case ESR_ELx_AET_UEU: /* Uncorrected Unrecoverable */ 958 case ESR_ELx_AET_UER: /* Uncorrected Recoverable */ 959 /* 960 * The CPU can't make progress. The exception may have 961 * been imprecise. 962 * 963 * Neoverse-N1 #1349291 means a non-KVM SError reported as 964 * Unrecoverable should be treated as Uncontainable. We 965 * call arm64_serror_panic() in both cases. 966 */ 967 return true; 968 969 case ESR_ELx_AET_UC: /* Uncontainable or Uncategorized error */ 970 default: 971 /* Error has been silently propagated */ 972 arm64_serror_panic(regs, esr); 973 } 974 } 975 976 void do_serror(struct pt_regs *regs, unsigned long esr) 977 { 978 /* non-RAS errors are not containable */ 979 if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(regs, esr)) 980 arm64_serror_panic(regs, esr); 981 } 982 983 /* GENERIC_BUG traps */ 984 985 int is_valid_bugaddr(unsigned long addr) 986 { 987 /* 988 * bug_handler() only called for BRK #BUG_BRK_IMM. 989 * So the answer is trivial -- any spurious instances with no 990 * bug table entry will be rejected by report_bug() and passed 991 * back to the debug-monitors code and handled as a fatal 992 * unexpected debug exception. 993 */ 994 return 1; 995 } 996 997 static int bug_handler(struct pt_regs *regs, unsigned long esr) 998 { 999 switch (report_bug(regs->pc, regs)) { 1000 case BUG_TRAP_TYPE_BUG: 1001 die("Oops - BUG", regs, esr); 1002 break; 1003 1004 case BUG_TRAP_TYPE_WARN: 1005 break; 1006 1007 default: 1008 /* unknown/unrecognised bug trap type */ 1009 return DBG_HOOK_ERROR; 1010 } 1011 1012 /* If thread survives, skip over the BUG instruction and continue: */ 1013 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 1014 return DBG_HOOK_HANDLED; 1015 } 1016 1017 static struct break_hook bug_break_hook = { 1018 .fn = bug_handler, 1019 .imm = BUG_BRK_IMM, 1020 }; 1021 1022 #ifdef CONFIG_CFI_CLANG 1023 static int cfi_handler(struct pt_regs *regs, unsigned long esr) 1024 { 1025 unsigned long target; 1026 u32 type; 1027 1028 target = pt_regs_read_reg(regs, FIELD_GET(CFI_BRK_IMM_TARGET, esr)); 1029 type = (u32)pt_regs_read_reg(regs, FIELD_GET(CFI_BRK_IMM_TYPE, esr)); 1030 1031 switch (report_cfi_failure(regs, regs->pc, &target, type)) { 1032 case BUG_TRAP_TYPE_BUG: 1033 die("Oops - CFI", regs, 0); 1034 break; 1035 1036 case BUG_TRAP_TYPE_WARN: 1037 break; 1038 1039 default: 1040 return DBG_HOOK_ERROR; 1041 } 1042 1043 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 1044 return DBG_HOOK_HANDLED; 1045 } 1046 1047 static struct break_hook cfi_break_hook = { 1048 .fn = cfi_handler, 1049 .imm = CFI_BRK_IMM_BASE, 1050 .mask = CFI_BRK_IMM_MASK, 1051 }; 1052 #endif /* CONFIG_CFI_CLANG */ 1053 1054 static int reserved_fault_handler(struct pt_regs *regs, unsigned long esr) 1055 { 1056 pr_err("%s generated an invalid instruction at %pS!\n", 1057 "Kernel text patching", 1058 (void *)instruction_pointer(regs)); 1059 1060 /* We cannot handle this */ 1061 return DBG_HOOK_ERROR; 1062 } 1063 1064 static struct break_hook fault_break_hook = { 1065 .fn = reserved_fault_handler, 1066 .imm = FAULT_BRK_IMM, 1067 }; 1068 1069 #ifdef CONFIG_KASAN_SW_TAGS 1070 1071 #define KASAN_ESR_RECOVER 0x20 1072 #define KASAN_ESR_WRITE 0x10 1073 #define KASAN_ESR_SIZE_MASK 0x0f 1074 #define KASAN_ESR_SIZE(esr) (1 << ((esr) & KASAN_ESR_SIZE_MASK)) 1075 1076 static int kasan_handler(struct pt_regs *regs, unsigned long esr) 1077 { 1078 bool recover = esr & KASAN_ESR_RECOVER; 1079 bool write = esr & KASAN_ESR_WRITE; 1080 size_t size = KASAN_ESR_SIZE(esr); 1081 u64 addr = regs->regs[0]; 1082 u64 pc = regs->pc; 1083 1084 kasan_report(addr, size, write, pc); 1085 1086 /* 1087 * The instrumentation allows to control whether we can proceed after 1088 * a crash was detected. This is done by passing the -recover flag to 1089 * the compiler. Disabling recovery allows to generate more compact 1090 * code. 1091 * 1092 * Unfortunately disabling recovery doesn't work for the kernel right 1093 * now. KASAN reporting is disabled in some contexts (for example when 1094 * the allocator accesses slab object metadata; this is controlled by 1095 * current->kasan_depth). All these accesses are detected by the tool, 1096 * even though the reports for them are not printed. 1097 * 1098 * This is something that might be fixed at some point in the future. 1099 */ 1100 if (!recover) 1101 die("Oops - KASAN", regs, esr); 1102 1103 /* If thread survives, skip over the brk instruction and continue: */ 1104 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 1105 return DBG_HOOK_HANDLED; 1106 } 1107 1108 static struct break_hook kasan_break_hook = { 1109 .fn = kasan_handler, 1110 .imm = KASAN_BRK_IMM, 1111 .mask = KASAN_BRK_MASK, 1112 }; 1113 #endif 1114 1115 1116 #define esr_comment(esr) ((esr) & ESR_ELx_BRK64_ISS_COMMENT_MASK) 1117 1118 /* 1119 * Initial handler for AArch64 BRK exceptions 1120 * This handler only used until debug_traps_init(). 1121 */ 1122 int __init early_brk64(unsigned long addr, unsigned long esr, 1123 struct pt_regs *regs) 1124 { 1125 #ifdef CONFIG_CFI_CLANG 1126 if ((esr_comment(esr) & ~CFI_BRK_IMM_MASK) == CFI_BRK_IMM_BASE) 1127 return cfi_handler(regs, esr) != DBG_HOOK_HANDLED; 1128 #endif 1129 #ifdef CONFIG_KASAN_SW_TAGS 1130 if ((esr_comment(esr) & ~KASAN_BRK_MASK) == KASAN_BRK_IMM) 1131 return kasan_handler(regs, esr) != DBG_HOOK_HANDLED; 1132 #endif 1133 return bug_handler(regs, esr) != DBG_HOOK_HANDLED; 1134 } 1135 1136 void __init trap_init(void) 1137 { 1138 register_kernel_break_hook(&bug_break_hook); 1139 #ifdef CONFIG_CFI_CLANG 1140 register_kernel_break_hook(&cfi_break_hook); 1141 #endif 1142 register_kernel_break_hook(&fault_break_hook); 1143 #ifdef CONFIG_KASAN_SW_TAGS 1144 register_kernel_break_hook(&kasan_break_hook); 1145 #endif 1146 debug_traps_init(); 1147 } 1148