1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Based on arch/arm/kernel/traps.c 4 * 5 * Copyright (C) 1995-2009 Russell King 6 * Copyright (C) 2012 ARM Ltd. 7 */ 8 9 #include <linux/bug.h> 10 #include <linux/context_tracking.h> 11 #include <linux/signal.h> 12 #include <linux/kallsyms.h> 13 #include <linux/kprobes.h> 14 #include <linux/spinlock.h> 15 #include <linux/uaccess.h> 16 #include <linux/hardirq.h> 17 #include <linux/kdebug.h> 18 #include <linux/module.h> 19 #include <linux/kexec.h> 20 #include <linux/delay.h> 21 #include <linux/init.h> 22 #include <linux/sched/signal.h> 23 #include <linux/sched/debug.h> 24 #include <linux/sched/task_stack.h> 25 #include <linux/sizes.h> 26 #include <linux/syscalls.h> 27 #include <linux/mm_types.h> 28 #include <linux/kasan.h> 29 #include <linux/ubsan.h> 30 #include <linux/cfi.h> 31 32 #include <asm/atomic.h> 33 #include <asm/bug.h> 34 #include <asm/cpufeature.h> 35 #include <asm/daifflags.h> 36 #include <asm/debug-monitors.h> 37 #include <asm/esr.h> 38 #include <asm/exception.h> 39 #include <asm/extable.h> 40 #include <asm/insn.h> 41 #include <asm/kprobes.h> 42 #include <asm/patching.h> 43 #include <asm/traps.h> 44 #include <asm/smp.h> 45 #include <asm/stack_pointer.h> 46 #include <asm/stacktrace.h> 47 #include <asm/system_misc.h> 48 #include <asm/sysreg.h> 49 50 static bool __kprobes __check_eq(unsigned long pstate) 51 { 52 return (pstate & PSR_Z_BIT) != 0; 53 } 54 55 static bool __kprobes __check_ne(unsigned long pstate) 56 { 57 return (pstate & PSR_Z_BIT) == 0; 58 } 59 60 static bool __kprobes __check_cs(unsigned long pstate) 61 { 62 return (pstate & PSR_C_BIT) != 0; 63 } 64 65 static bool __kprobes __check_cc(unsigned long pstate) 66 { 67 return (pstate & PSR_C_BIT) == 0; 68 } 69 70 static bool __kprobes __check_mi(unsigned long pstate) 71 { 72 return (pstate & PSR_N_BIT) != 0; 73 } 74 75 static bool __kprobes __check_pl(unsigned long pstate) 76 { 77 return (pstate & PSR_N_BIT) == 0; 78 } 79 80 static bool __kprobes __check_vs(unsigned long pstate) 81 { 82 return (pstate & PSR_V_BIT) != 0; 83 } 84 85 static bool __kprobes __check_vc(unsigned long pstate) 86 { 87 return (pstate & PSR_V_BIT) == 0; 88 } 89 90 static bool __kprobes __check_hi(unsigned long pstate) 91 { 92 pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ 93 return (pstate & PSR_C_BIT) != 0; 94 } 95 96 static bool __kprobes __check_ls(unsigned long pstate) 97 { 98 pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ 99 return (pstate & PSR_C_BIT) == 0; 100 } 101 102 static bool __kprobes __check_ge(unsigned long pstate) 103 { 104 pstate ^= (pstate << 3); /* PSR_N_BIT ^= PSR_V_BIT */ 105 return (pstate & PSR_N_BIT) == 0; 106 } 107 108 static bool __kprobes __check_lt(unsigned long pstate) 109 { 110 pstate ^= (pstate << 3); /* PSR_N_BIT ^= PSR_V_BIT */ 111 return (pstate & PSR_N_BIT) != 0; 112 } 113 114 static bool __kprobes __check_gt(unsigned long pstate) 115 { 116 /*PSR_N_BIT ^= PSR_V_BIT */ 117 unsigned long temp = pstate ^ (pstate << 3); 118 119 temp |= (pstate << 1); /*PSR_N_BIT |= PSR_Z_BIT */ 120 return (temp & PSR_N_BIT) == 0; 121 } 122 123 static bool __kprobes __check_le(unsigned long pstate) 124 { 125 /*PSR_N_BIT ^= PSR_V_BIT */ 126 unsigned long temp = pstate ^ (pstate << 3); 127 128 temp |= (pstate << 1); /*PSR_N_BIT |= PSR_Z_BIT */ 129 return (temp & PSR_N_BIT) != 0; 130 } 131 132 static bool __kprobes __check_al(unsigned long pstate) 133 { 134 return true; 135 } 136 137 /* 138 * Note that the ARMv8 ARM calls condition code 0b1111 "nv", but states that 139 * it behaves identically to 0b1110 ("al"). 140 */ 141 pstate_check_t * const aarch32_opcode_cond_checks[16] = { 142 __check_eq, __check_ne, __check_cs, __check_cc, 143 __check_mi, __check_pl, __check_vs, __check_vc, 144 __check_hi, __check_ls, __check_ge, __check_lt, 145 __check_gt, __check_le, __check_al, __check_al 146 }; 147 148 int show_unhandled_signals = 0; 149 150 static void dump_kernel_instr(const char *lvl, struct pt_regs *regs) 151 { 152 unsigned long addr = instruction_pointer(regs); 153 char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str; 154 int i; 155 156 if (user_mode(regs)) 157 return; 158 159 for (i = -4; i < 1; i++) { 160 unsigned int val, bad; 161 162 bad = aarch64_insn_read(&((u32 *)addr)[i], &val); 163 164 if (!bad) 165 p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val); 166 else { 167 p += sprintf(p, "bad PC value"); 168 break; 169 } 170 } 171 172 printk("%sCode: %s\n", lvl, str); 173 } 174 175 #ifdef CONFIG_PREEMPT 176 #define S_PREEMPT " PREEMPT" 177 #elif defined(CONFIG_PREEMPT_RT) 178 #define S_PREEMPT " PREEMPT_RT" 179 #else 180 #define S_PREEMPT "" 181 #endif 182 183 #define S_SMP " SMP" 184 185 static int __die(const char *str, long err, struct pt_regs *regs) 186 { 187 static int die_counter; 188 int ret; 189 190 pr_emerg("Internal error: %s: %016lx [#%d]" S_PREEMPT S_SMP "\n", 191 str, err, ++die_counter); 192 193 /* trap and error numbers are mostly meaningless on ARM */ 194 ret = notify_die(DIE_OOPS, str, regs, err, 0, SIGSEGV); 195 if (ret == NOTIFY_STOP) 196 return ret; 197 198 print_modules(); 199 show_regs(regs); 200 201 dump_kernel_instr(KERN_EMERG, regs); 202 203 return ret; 204 } 205 206 static DEFINE_RAW_SPINLOCK(die_lock); 207 208 /* 209 * This function is protected against re-entrancy. 210 */ 211 void die(const char *str, struct pt_regs *regs, long err) 212 { 213 int ret; 214 unsigned long flags; 215 216 raw_spin_lock_irqsave(&die_lock, flags); 217 218 oops_enter(); 219 220 console_verbose(); 221 bust_spinlocks(1); 222 ret = __die(str, err, regs); 223 224 if (regs && kexec_should_crash(current)) 225 crash_kexec(regs); 226 227 bust_spinlocks(0); 228 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 229 oops_exit(); 230 231 if (in_interrupt()) 232 panic("%s: Fatal exception in interrupt", str); 233 if (panic_on_oops) 234 panic("%s: Fatal exception", str); 235 236 raw_spin_unlock_irqrestore(&die_lock, flags); 237 238 if (ret != NOTIFY_STOP) 239 make_task_dead(SIGSEGV); 240 } 241 242 static void arm64_show_signal(int signo, const char *str) 243 { 244 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, 245 DEFAULT_RATELIMIT_BURST); 246 struct task_struct *tsk = current; 247 unsigned long esr = tsk->thread.fault_code; 248 struct pt_regs *regs = task_pt_regs(tsk); 249 250 /* Leave if the signal won't be shown */ 251 if (!show_unhandled_signals || 252 !unhandled_signal(tsk, signo) || 253 !__ratelimit(&rs)) 254 return; 255 256 pr_info("%s[%d]: unhandled exception: ", tsk->comm, task_pid_nr(tsk)); 257 if (esr) 258 pr_cont("%s, ESR 0x%016lx, ", esr_get_class_string(esr), esr); 259 260 pr_cont("%s", str); 261 print_vma_addr(KERN_CONT " in ", regs->pc); 262 pr_cont("\n"); 263 __show_regs(regs); 264 } 265 266 void arm64_force_sig_fault(int signo, int code, unsigned long far, 267 const char *str) 268 { 269 arm64_show_signal(signo, str); 270 if (signo == SIGKILL) 271 force_sig(SIGKILL); 272 else 273 force_sig_fault(signo, code, (void __user *)far); 274 } 275 276 void arm64_force_sig_mceerr(int code, unsigned long far, short lsb, 277 const char *str) 278 { 279 arm64_show_signal(SIGBUS, str); 280 force_sig_mceerr(code, (void __user *)far, lsb); 281 } 282 283 void arm64_force_sig_ptrace_errno_trap(int errno, unsigned long far, 284 const char *str) 285 { 286 arm64_show_signal(SIGTRAP, str); 287 force_sig_ptrace_errno_trap(errno, (void __user *)far); 288 } 289 290 void arm64_notify_die(const char *str, struct pt_regs *regs, 291 int signo, int sicode, unsigned long far, 292 unsigned long err) 293 { 294 if (user_mode(regs)) { 295 WARN_ON(regs != current_pt_regs()); 296 current->thread.fault_address = 0; 297 current->thread.fault_code = err; 298 299 arm64_force_sig_fault(signo, sicode, far, str); 300 } else { 301 die(str, regs, err); 302 } 303 } 304 305 #ifdef CONFIG_COMPAT 306 #define PSTATE_IT_1_0_SHIFT 25 307 #define PSTATE_IT_1_0_MASK (0x3 << PSTATE_IT_1_0_SHIFT) 308 #define PSTATE_IT_7_2_SHIFT 10 309 #define PSTATE_IT_7_2_MASK (0x3f << PSTATE_IT_7_2_SHIFT) 310 311 static u32 compat_get_it_state(struct pt_regs *regs) 312 { 313 u32 it, pstate = regs->pstate; 314 315 it = (pstate & PSTATE_IT_1_0_MASK) >> PSTATE_IT_1_0_SHIFT; 316 it |= ((pstate & PSTATE_IT_7_2_MASK) >> PSTATE_IT_7_2_SHIFT) << 2; 317 318 return it; 319 } 320 321 static void compat_set_it_state(struct pt_regs *regs, u32 it) 322 { 323 u32 pstate_it; 324 325 pstate_it = (it << PSTATE_IT_1_0_SHIFT) & PSTATE_IT_1_0_MASK; 326 pstate_it |= ((it >> 2) << PSTATE_IT_7_2_SHIFT) & PSTATE_IT_7_2_MASK; 327 328 regs->pstate &= ~PSR_AA32_IT_MASK; 329 regs->pstate |= pstate_it; 330 } 331 332 static void advance_itstate(struct pt_regs *regs) 333 { 334 u32 it; 335 336 /* ARM mode */ 337 if (!(regs->pstate & PSR_AA32_T_BIT) || 338 !(regs->pstate & PSR_AA32_IT_MASK)) 339 return; 340 341 it = compat_get_it_state(regs); 342 343 /* 344 * If this is the last instruction of the block, wipe the IT 345 * state. Otherwise advance it. 346 */ 347 if (!(it & 7)) 348 it = 0; 349 else 350 it = (it & 0xe0) | ((it << 1) & 0x1f); 351 352 compat_set_it_state(regs, it); 353 } 354 #else 355 static void advance_itstate(struct pt_regs *regs) 356 { 357 } 358 #endif 359 360 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size) 361 { 362 regs->pc += size; 363 364 /* 365 * If we were single stepping, we want to get the step exception after 366 * we return from the trap. 367 */ 368 if (user_mode(regs)) 369 user_fastforward_single_step(current); 370 371 if (compat_user_mode(regs)) 372 advance_itstate(regs); 373 else 374 regs->pstate &= ~PSR_BTYPE_MASK; 375 } 376 377 static int user_insn_read(struct pt_regs *regs, u32 *insnp) 378 { 379 u32 instr; 380 unsigned long pc = instruction_pointer(regs); 381 382 if (compat_thumb_mode(regs)) { 383 /* 16-bit Thumb instruction */ 384 __le16 instr_le; 385 if (get_user(instr_le, (__le16 __user *)pc)) 386 return -EFAULT; 387 instr = le16_to_cpu(instr_le); 388 if (aarch32_insn_is_wide(instr)) { 389 u32 instr2; 390 391 if (get_user(instr_le, (__le16 __user *)(pc + 2))) 392 return -EFAULT; 393 instr2 = le16_to_cpu(instr_le); 394 instr = (instr << 16) | instr2; 395 } 396 } else { 397 /* 32-bit ARM instruction */ 398 __le32 instr_le; 399 if (get_user(instr_le, (__le32 __user *)pc)) 400 return -EFAULT; 401 instr = le32_to_cpu(instr_le); 402 } 403 404 *insnp = instr; 405 return 0; 406 } 407 408 void force_signal_inject(int signal, int code, unsigned long address, unsigned long err) 409 { 410 const char *desc; 411 struct pt_regs *regs = current_pt_regs(); 412 413 if (WARN_ON(!user_mode(regs))) 414 return; 415 416 switch (signal) { 417 case SIGILL: 418 desc = "undefined instruction"; 419 break; 420 case SIGSEGV: 421 desc = "illegal memory access"; 422 break; 423 default: 424 desc = "unknown or unrecoverable error"; 425 break; 426 } 427 428 /* Force signals we don't understand to SIGKILL */ 429 if (WARN_ON(signal != SIGKILL && 430 siginfo_layout(signal, code) != SIL_FAULT)) { 431 signal = SIGKILL; 432 } 433 434 arm64_notify_die(desc, regs, signal, code, address, err); 435 } 436 437 /* 438 * Set up process info to signal segmentation fault - called on access error. 439 */ 440 void arm64_notify_segfault(unsigned long addr) 441 { 442 int code; 443 444 mmap_read_lock(current->mm); 445 if (find_vma(current->mm, untagged_addr(addr)) == NULL) 446 code = SEGV_MAPERR; 447 else 448 code = SEGV_ACCERR; 449 mmap_read_unlock(current->mm); 450 451 force_signal_inject(SIGSEGV, code, addr, 0); 452 } 453 454 void do_el0_undef(struct pt_regs *regs, unsigned long esr) 455 { 456 u32 insn; 457 458 /* check for AArch32 breakpoint instructions */ 459 if (!aarch32_break_handler(regs)) 460 return; 461 462 if (user_insn_read(regs, &insn)) 463 goto out_err; 464 465 if (try_emulate_mrs(regs, insn)) 466 return; 467 468 if (try_emulate_armv8_deprecated(regs, insn)) 469 return; 470 471 out_err: 472 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 473 } 474 475 void do_el1_undef(struct pt_regs *regs, unsigned long esr) 476 { 477 u32 insn; 478 479 if (aarch64_insn_read((void *)regs->pc, &insn)) 480 goto out_err; 481 482 if (try_emulate_el1_ssbs(regs, insn)) 483 return; 484 485 out_err: 486 die("Oops - Undefined instruction", regs, esr); 487 } 488 489 void do_el0_bti(struct pt_regs *regs) 490 { 491 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 492 } 493 494 void do_el1_bti(struct pt_regs *regs, unsigned long esr) 495 { 496 die("Oops - BTI", regs, esr); 497 } 498 499 void do_el0_fpac(struct pt_regs *regs, unsigned long esr) 500 { 501 force_signal_inject(SIGILL, ILL_ILLOPN, regs->pc, esr); 502 } 503 504 void do_el1_fpac(struct pt_regs *regs, unsigned long esr) 505 { 506 /* 507 * Unexpected FPAC exception in the kernel: kill the task before it 508 * does any more harm. 509 */ 510 die("Oops - FPAC", regs, esr); 511 } 512 513 #define __user_cache_maint(insn, address, res) \ 514 if (address >= TASK_SIZE_MAX) { \ 515 res = -EFAULT; \ 516 } else { \ 517 uaccess_ttbr0_enable(); \ 518 asm volatile ( \ 519 "1: " insn ", %1\n" \ 520 " mov %w0, #0\n" \ 521 "2:\n" \ 522 _ASM_EXTABLE_UACCESS_ERR(1b, 2b, %w0) \ 523 : "=r" (res) \ 524 : "r" (address)); \ 525 uaccess_ttbr0_disable(); \ 526 } 527 528 static void user_cache_maint_handler(unsigned long esr, struct pt_regs *regs) 529 { 530 unsigned long tagged_address, address; 531 int rt = ESR_ELx_SYS64_ISS_RT(esr); 532 int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT; 533 int ret = 0; 534 535 tagged_address = pt_regs_read_reg(regs, rt); 536 address = untagged_addr(tagged_address); 537 538 switch (crm) { 539 case ESR_ELx_SYS64_ISS_CRM_DC_CVAU: /* DC CVAU, gets promoted */ 540 __user_cache_maint("dc civac", address, ret); 541 break; 542 case ESR_ELx_SYS64_ISS_CRM_DC_CVAC: /* DC CVAC, gets promoted */ 543 __user_cache_maint("dc civac", address, ret); 544 break; 545 case ESR_ELx_SYS64_ISS_CRM_DC_CVADP: /* DC CVADP */ 546 __user_cache_maint("sys 3, c7, c13, 1", address, ret); 547 break; 548 case ESR_ELx_SYS64_ISS_CRM_DC_CVAP: /* DC CVAP */ 549 __user_cache_maint("sys 3, c7, c12, 1", address, ret); 550 break; 551 case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC: /* DC CIVAC */ 552 __user_cache_maint("dc civac", address, ret); 553 break; 554 case ESR_ELx_SYS64_ISS_CRM_IC_IVAU: /* IC IVAU */ 555 __user_cache_maint("ic ivau", address, ret); 556 break; 557 default: 558 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 559 return; 560 } 561 562 if (ret) 563 arm64_notify_segfault(tagged_address); 564 else 565 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 566 } 567 568 static void ctr_read_handler(unsigned long esr, struct pt_regs *regs) 569 { 570 int rt = ESR_ELx_SYS64_ISS_RT(esr); 571 unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0); 572 573 if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) { 574 /* Hide DIC so that we can trap the unnecessary maintenance...*/ 575 val &= ~BIT(CTR_EL0_DIC_SHIFT); 576 577 /* ... and fake IminLine to reduce the number of traps. */ 578 val &= ~CTR_EL0_IminLine_MASK; 579 val |= (PAGE_SHIFT - 2) & CTR_EL0_IminLine_MASK; 580 } 581 582 pt_regs_write_reg(regs, rt, val); 583 584 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 585 } 586 587 static void cntvct_read_handler(unsigned long esr, struct pt_regs *regs) 588 { 589 int rt = ESR_ELx_SYS64_ISS_RT(esr); 590 591 pt_regs_write_reg(regs, rt, arch_timer_read_counter()); 592 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 593 } 594 595 static void cntfrq_read_handler(unsigned long esr, struct pt_regs *regs) 596 { 597 int rt = ESR_ELx_SYS64_ISS_RT(esr); 598 599 pt_regs_write_reg(regs, rt, arch_timer_get_rate()); 600 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 601 } 602 603 static void mrs_handler(unsigned long esr, struct pt_regs *regs) 604 { 605 u32 sysreg, rt; 606 607 rt = ESR_ELx_SYS64_ISS_RT(esr); 608 sysreg = esr_sys64_to_sysreg(esr); 609 610 if (do_emulate_mrs(regs, sysreg, rt) != 0) 611 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 612 } 613 614 static void wfi_handler(unsigned long esr, struct pt_regs *regs) 615 { 616 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 617 } 618 619 struct sys64_hook { 620 unsigned long esr_mask; 621 unsigned long esr_val; 622 void (*handler)(unsigned long esr, struct pt_regs *regs); 623 }; 624 625 static const struct sys64_hook sys64_hooks[] = { 626 { 627 .esr_mask = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK, 628 .esr_val = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL, 629 .handler = user_cache_maint_handler, 630 }, 631 { 632 /* Trap read access to CTR_EL0 */ 633 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 634 .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ, 635 .handler = ctr_read_handler, 636 }, 637 { 638 /* Trap read access to CNTVCT_EL0 */ 639 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 640 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT, 641 .handler = cntvct_read_handler, 642 }, 643 { 644 /* Trap read access to CNTVCTSS_EL0 */ 645 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 646 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCTSS, 647 .handler = cntvct_read_handler, 648 }, 649 { 650 /* Trap read access to CNTFRQ_EL0 */ 651 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 652 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTFRQ, 653 .handler = cntfrq_read_handler, 654 }, 655 { 656 /* Trap read access to CPUID registers */ 657 .esr_mask = ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK, 658 .esr_val = ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL, 659 .handler = mrs_handler, 660 }, 661 { 662 /* Trap WFI instructions executed in userspace */ 663 .esr_mask = ESR_ELx_WFx_MASK, 664 .esr_val = ESR_ELx_WFx_WFI_VAL, 665 .handler = wfi_handler, 666 }, 667 {}, 668 }; 669 670 #ifdef CONFIG_COMPAT 671 static bool cp15_cond_valid(unsigned long esr, struct pt_regs *regs) 672 { 673 int cond; 674 675 /* Only a T32 instruction can trap without CV being set */ 676 if (!(esr & ESR_ELx_CV)) { 677 u32 it; 678 679 it = compat_get_it_state(regs); 680 if (!it) 681 return true; 682 683 cond = it >> 4; 684 } else { 685 cond = (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT; 686 } 687 688 return aarch32_opcode_cond_checks[cond](regs->pstate); 689 } 690 691 static void compat_cntfrq_read_handler(unsigned long esr, struct pt_regs *regs) 692 { 693 int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT; 694 695 pt_regs_write_reg(regs, reg, arch_timer_get_rate()); 696 arm64_skip_faulting_instruction(regs, 4); 697 } 698 699 static const struct sys64_hook cp15_32_hooks[] = { 700 { 701 .esr_mask = ESR_ELx_CP15_32_ISS_SYS_MASK, 702 .esr_val = ESR_ELx_CP15_32_ISS_SYS_CNTFRQ, 703 .handler = compat_cntfrq_read_handler, 704 }, 705 {}, 706 }; 707 708 static void compat_cntvct_read_handler(unsigned long esr, struct pt_regs *regs) 709 { 710 int rt = (esr & ESR_ELx_CP15_64_ISS_RT_MASK) >> ESR_ELx_CP15_64_ISS_RT_SHIFT; 711 int rt2 = (esr & ESR_ELx_CP15_64_ISS_RT2_MASK) >> ESR_ELx_CP15_64_ISS_RT2_SHIFT; 712 u64 val = arch_timer_read_counter(); 713 714 pt_regs_write_reg(regs, rt, lower_32_bits(val)); 715 pt_regs_write_reg(regs, rt2, upper_32_bits(val)); 716 arm64_skip_faulting_instruction(regs, 4); 717 } 718 719 static const struct sys64_hook cp15_64_hooks[] = { 720 { 721 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK, 722 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCT, 723 .handler = compat_cntvct_read_handler, 724 }, 725 { 726 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK, 727 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS, 728 .handler = compat_cntvct_read_handler, 729 }, 730 {}, 731 }; 732 733 void do_el0_cp15(unsigned long esr, struct pt_regs *regs) 734 { 735 const struct sys64_hook *hook, *hook_base; 736 737 if (!cp15_cond_valid(esr, regs)) { 738 /* 739 * There is no T16 variant of a CP access, so we 740 * always advance PC by 4 bytes. 741 */ 742 arm64_skip_faulting_instruction(regs, 4); 743 return; 744 } 745 746 switch (ESR_ELx_EC(esr)) { 747 case ESR_ELx_EC_CP15_32: 748 hook_base = cp15_32_hooks; 749 break; 750 case ESR_ELx_EC_CP15_64: 751 hook_base = cp15_64_hooks; 752 break; 753 default: 754 do_el0_undef(regs, esr); 755 return; 756 } 757 758 for (hook = hook_base; hook->handler; hook++) 759 if ((hook->esr_mask & esr) == hook->esr_val) { 760 hook->handler(esr, regs); 761 return; 762 } 763 764 /* 765 * New cp15 instructions may previously have been undefined at 766 * EL0. Fall back to our usual undefined instruction handler 767 * so that we handle these consistently. 768 */ 769 do_el0_undef(regs, esr); 770 } 771 #endif 772 773 void do_el0_sys(unsigned long esr, struct pt_regs *regs) 774 { 775 const struct sys64_hook *hook; 776 777 for (hook = sys64_hooks; hook->handler; hook++) 778 if ((hook->esr_mask & esr) == hook->esr_val) { 779 hook->handler(esr, regs); 780 return; 781 } 782 783 /* 784 * New SYS instructions may previously have been undefined at EL0. Fall 785 * back to our usual undefined instruction handler so that we handle 786 * these consistently. 787 */ 788 do_el0_undef(regs, esr); 789 } 790 791 static const char *esr_class_str[] = { 792 [0 ... ESR_ELx_EC_MAX] = "UNRECOGNIZED EC", 793 [ESR_ELx_EC_UNKNOWN] = "Unknown/Uncategorized", 794 [ESR_ELx_EC_WFx] = "WFI/WFE", 795 [ESR_ELx_EC_CP15_32] = "CP15 MCR/MRC", 796 [ESR_ELx_EC_CP15_64] = "CP15 MCRR/MRRC", 797 [ESR_ELx_EC_CP14_MR] = "CP14 MCR/MRC", 798 [ESR_ELx_EC_CP14_LS] = "CP14 LDC/STC", 799 [ESR_ELx_EC_FP_ASIMD] = "ASIMD", 800 [ESR_ELx_EC_CP10_ID] = "CP10 MRC/VMRS", 801 [ESR_ELx_EC_PAC] = "PAC", 802 [ESR_ELx_EC_CP14_64] = "CP14 MCRR/MRRC", 803 [ESR_ELx_EC_BTI] = "BTI", 804 [ESR_ELx_EC_ILL] = "PSTATE.IL", 805 [ESR_ELx_EC_SVC32] = "SVC (AArch32)", 806 [ESR_ELx_EC_HVC32] = "HVC (AArch32)", 807 [ESR_ELx_EC_SMC32] = "SMC (AArch32)", 808 [ESR_ELx_EC_SVC64] = "SVC (AArch64)", 809 [ESR_ELx_EC_HVC64] = "HVC (AArch64)", 810 [ESR_ELx_EC_SMC64] = "SMC (AArch64)", 811 [ESR_ELx_EC_SYS64] = "MSR/MRS (AArch64)", 812 [ESR_ELx_EC_SVE] = "SVE", 813 [ESR_ELx_EC_ERET] = "ERET/ERETAA/ERETAB", 814 [ESR_ELx_EC_FPAC] = "FPAC", 815 [ESR_ELx_EC_SME] = "SME", 816 [ESR_ELx_EC_IMP_DEF] = "EL3 IMP DEF", 817 [ESR_ELx_EC_IABT_LOW] = "IABT (lower EL)", 818 [ESR_ELx_EC_IABT_CUR] = "IABT (current EL)", 819 [ESR_ELx_EC_PC_ALIGN] = "PC Alignment", 820 [ESR_ELx_EC_DABT_LOW] = "DABT (lower EL)", 821 [ESR_ELx_EC_DABT_CUR] = "DABT (current EL)", 822 [ESR_ELx_EC_SP_ALIGN] = "SP Alignment", 823 [ESR_ELx_EC_FP_EXC32] = "FP (AArch32)", 824 [ESR_ELx_EC_FP_EXC64] = "FP (AArch64)", 825 [ESR_ELx_EC_SERROR] = "SError", 826 [ESR_ELx_EC_BREAKPT_LOW] = "Breakpoint (lower EL)", 827 [ESR_ELx_EC_BREAKPT_CUR] = "Breakpoint (current EL)", 828 [ESR_ELx_EC_SOFTSTP_LOW] = "Software Step (lower EL)", 829 [ESR_ELx_EC_SOFTSTP_CUR] = "Software Step (current EL)", 830 [ESR_ELx_EC_WATCHPT_LOW] = "Watchpoint (lower EL)", 831 [ESR_ELx_EC_WATCHPT_CUR] = "Watchpoint (current EL)", 832 [ESR_ELx_EC_BKPT32] = "BKPT (AArch32)", 833 [ESR_ELx_EC_VECTOR32] = "Vector catch (AArch32)", 834 [ESR_ELx_EC_BRK64] = "BRK (AArch64)", 835 }; 836 837 const char *esr_get_class_string(unsigned long esr) 838 { 839 return esr_class_str[ESR_ELx_EC(esr)]; 840 } 841 842 /* 843 * bad_el0_sync handles unexpected, but potentially recoverable synchronous 844 * exceptions taken from EL0. 845 */ 846 void bad_el0_sync(struct pt_regs *regs, int reason, unsigned long esr) 847 { 848 unsigned long pc = instruction_pointer(regs); 849 850 current->thread.fault_address = 0; 851 current->thread.fault_code = esr; 852 853 arm64_force_sig_fault(SIGILL, ILL_ILLOPC, pc, 854 "Bad EL0 synchronous exception"); 855 } 856 857 #ifdef CONFIG_VMAP_STACK 858 859 DEFINE_PER_CPU(unsigned long [OVERFLOW_STACK_SIZE/sizeof(long)], overflow_stack) 860 __aligned(16); 861 862 void panic_bad_stack(struct pt_regs *regs, unsigned long esr, unsigned long far) 863 { 864 unsigned long tsk_stk = (unsigned long)current->stack; 865 unsigned long irq_stk = (unsigned long)this_cpu_read(irq_stack_ptr); 866 unsigned long ovf_stk = (unsigned long)this_cpu_ptr(overflow_stack); 867 868 console_verbose(); 869 pr_emerg("Insufficient stack space to handle exception!"); 870 871 pr_emerg("ESR: 0x%016lx -- %s\n", esr, esr_get_class_string(esr)); 872 pr_emerg("FAR: 0x%016lx\n", far); 873 874 pr_emerg("Task stack: [0x%016lx..0x%016lx]\n", 875 tsk_stk, tsk_stk + THREAD_SIZE); 876 pr_emerg("IRQ stack: [0x%016lx..0x%016lx]\n", 877 irq_stk, irq_stk + IRQ_STACK_SIZE); 878 pr_emerg("Overflow stack: [0x%016lx..0x%016lx]\n", 879 ovf_stk, ovf_stk + OVERFLOW_STACK_SIZE); 880 881 __show_regs(regs); 882 883 /* 884 * We use nmi_panic to limit the potential for recusive overflows, and 885 * to get a better stack trace. 886 */ 887 nmi_panic(NULL, "kernel stack overflow"); 888 cpu_park_loop(); 889 } 890 #endif 891 892 void __noreturn arm64_serror_panic(struct pt_regs *regs, unsigned long esr) 893 { 894 console_verbose(); 895 896 pr_crit("SError Interrupt on CPU%d, code 0x%016lx -- %s\n", 897 smp_processor_id(), esr, esr_get_class_string(esr)); 898 if (regs) 899 __show_regs(regs); 900 901 nmi_panic(regs, "Asynchronous SError Interrupt"); 902 903 cpu_park_loop(); 904 unreachable(); 905 } 906 907 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned long esr) 908 { 909 unsigned long aet = arm64_ras_serror_get_severity(esr); 910 911 switch (aet) { 912 case ESR_ELx_AET_CE: /* corrected error */ 913 case ESR_ELx_AET_UEO: /* restartable, not yet consumed */ 914 /* 915 * The CPU can make progress. We may take UEO again as 916 * a more severe error. 917 */ 918 return false; 919 920 case ESR_ELx_AET_UEU: /* Uncorrected Unrecoverable */ 921 case ESR_ELx_AET_UER: /* Uncorrected Recoverable */ 922 /* 923 * The CPU can't make progress. The exception may have 924 * been imprecise. 925 * 926 * Neoverse-N1 #1349291 means a non-KVM SError reported as 927 * Unrecoverable should be treated as Uncontainable. We 928 * call arm64_serror_panic() in both cases. 929 */ 930 return true; 931 932 case ESR_ELx_AET_UC: /* Uncontainable or Uncategorized error */ 933 default: 934 /* Error has been silently propagated */ 935 arm64_serror_panic(regs, esr); 936 } 937 } 938 939 void do_serror(struct pt_regs *regs, unsigned long esr) 940 { 941 /* non-RAS errors are not containable */ 942 if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(regs, esr)) 943 arm64_serror_panic(regs, esr); 944 } 945 946 /* GENERIC_BUG traps */ 947 948 int is_valid_bugaddr(unsigned long addr) 949 { 950 /* 951 * bug_handler() only called for BRK #BUG_BRK_IMM. 952 * So the answer is trivial -- any spurious instances with no 953 * bug table entry will be rejected by report_bug() and passed 954 * back to the debug-monitors code and handled as a fatal 955 * unexpected debug exception. 956 */ 957 return 1; 958 } 959 960 static int bug_handler(struct pt_regs *regs, unsigned long esr) 961 { 962 switch (report_bug(regs->pc, regs)) { 963 case BUG_TRAP_TYPE_BUG: 964 die("Oops - BUG", regs, esr); 965 break; 966 967 case BUG_TRAP_TYPE_WARN: 968 break; 969 970 default: 971 /* unknown/unrecognised bug trap type */ 972 return DBG_HOOK_ERROR; 973 } 974 975 /* If thread survives, skip over the BUG instruction and continue: */ 976 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 977 return DBG_HOOK_HANDLED; 978 } 979 980 static struct break_hook bug_break_hook = { 981 .fn = bug_handler, 982 .imm = BUG_BRK_IMM, 983 }; 984 985 #ifdef CONFIG_CFI_CLANG 986 static int cfi_handler(struct pt_regs *regs, unsigned long esr) 987 { 988 unsigned long target; 989 u32 type; 990 991 target = pt_regs_read_reg(regs, FIELD_GET(CFI_BRK_IMM_TARGET, esr)); 992 type = (u32)pt_regs_read_reg(regs, FIELD_GET(CFI_BRK_IMM_TYPE, esr)); 993 994 switch (report_cfi_failure(regs, regs->pc, &target, type)) { 995 case BUG_TRAP_TYPE_BUG: 996 die("Oops - CFI", regs, 0); 997 break; 998 999 case BUG_TRAP_TYPE_WARN: 1000 break; 1001 1002 default: 1003 return DBG_HOOK_ERROR; 1004 } 1005 1006 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 1007 return DBG_HOOK_HANDLED; 1008 } 1009 1010 static struct break_hook cfi_break_hook = { 1011 .fn = cfi_handler, 1012 .imm = CFI_BRK_IMM_BASE, 1013 .mask = CFI_BRK_IMM_MASK, 1014 }; 1015 #endif /* CONFIG_CFI_CLANG */ 1016 1017 static int reserved_fault_handler(struct pt_regs *regs, unsigned long esr) 1018 { 1019 pr_err("%s generated an invalid instruction at %pS!\n", 1020 "Kernel text patching", 1021 (void *)instruction_pointer(regs)); 1022 1023 /* We cannot handle this */ 1024 return DBG_HOOK_ERROR; 1025 } 1026 1027 static struct break_hook fault_break_hook = { 1028 .fn = reserved_fault_handler, 1029 .imm = FAULT_BRK_IMM, 1030 }; 1031 1032 #ifdef CONFIG_KASAN_SW_TAGS 1033 1034 #define KASAN_ESR_RECOVER 0x20 1035 #define KASAN_ESR_WRITE 0x10 1036 #define KASAN_ESR_SIZE_MASK 0x0f 1037 #define KASAN_ESR_SIZE(esr) (1 << ((esr) & KASAN_ESR_SIZE_MASK)) 1038 1039 static int kasan_handler(struct pt_regs *regs, unsigned long esr) 1040 { 1041 bool recover = esr & KASAN_ESR_RECOVER; 1042 bool write = esr & KASAN_ESR_WRITE; 1043 size_t size = KASAN_ESR_SIZE(esr); 1044 u64 addr = regs->regs[0]; 1045 u64 pc = regs->pc; 1046 1047 kasan_report(addr, size, write, pc); 1048 1049 /* 1050 * The instrumentation allows to control whether we can proceed after 1051 * a crash was detected. This is done by passing the -recover flag to 1052 * the compiler. Disabling recovery allows to generate more compact 1053 * code. 1054 * 1055 * Unfortunately disabling recovery doesn't work for the kernel right 1056 * now. KASAN reporting is disabled in some contexts (for example when 1057 * the allocator accesses slab object metadata; this is controlled by 1058 * current->kasan_depth). All these accesses are detected by the tool, 1059 * even though the reports for them are not printed. 1060 * 1061 * This is something that might be fixed at some point in the future. 1062 */ 1063 if (!recover) 1064 die("Oops - KASAN", regs, esr); 1065 1066 /* If thread survives, skip over the brk instruction and continue: */ 1067 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 1068 return DBG_HOOK_HANDLED; 1069 } 1070 1071 static struct break_hook kasan_break_hook = { 1072 .fn = kasan_handler, 1073 .imm = KASAN_BRK_IMM, 1074 .mask = KASAN_BRK_MASK, 1075 }; 1076 #endif 1077 1078 #ifdef CONFIG_UBSAN_TRAP 1079 static int ubsan_handler(struct pt_regs *regs, unsigned long esr) 1080 { 1081 die(report_ubsan_failure(regs, esr & UBSAN_BRK_MASK), regs, esr); 1082 return DBG_HOOK_HANDLED; 1083 } 1084 1085 static struct break_hook ubsan_break_hook = { 1086 .fn = ubsan_handler, 1087 .imm = UBSAN_BRK_IMM, 1088 .mask = UBSAN_BRK_MASK, 1089 }; 1090 #endif 1091 1092 #define esr_comment(esr) ((esr) & ESR_ELx_BRK64_ISS_COMMENT_MASK) 1093 1094 /* 1095 * Initial handler for AArch64 BRK exceptions 1096 * This handler only used until debug_traps_init(). 1097 */ 1098 int __init early_brk64(unsigned long addr, unsigned long esr, 1099 struct pt_regs *regs) 1100 { 1101 #ifdef CONFIG_CFI_CLANG 1102 if ((esr_comment(esr) & ~CFI_BRK_IMM_MASK) == CFI_BRK_IMM_BASE) 1103 return cfi_handler(regs, esr) != DBG_HOOK_HANDLED; 1104 #endif 1105 #ifdef CONFIG_KASAN_SW_TAGS 1106 if ((esr_comment(esr) & ~KASAN_BRK_MASK) == KASAN_BRK_IMM) 1107 return kasan_handler(regs, esr) != DBG_HOOK_HANDLED; 1108 #endif 1109 #ifdef CONFIG_UBSAN_TRAP 1110 if ((esr_comment(esr) & ~UBSAN_BRK_MASK) == UBSAN_BRK_IMM) 1111 return ubsan_handler(regs, esr) != DBG_HOOK_HANDLED; 1112 #endif 1113 return bug_handler(regs, esr) != DBG_HOOK_HANDLED; 1114 } 1115 1116 void __init trap_init(void) 1117 { 1118 register_kernel_break_hook(&bug_break_hook); 1119 #ifdef CONFIG_CFI_CLANG 1120 register_kernel_break_hook(&cfi_break_hook); 1121 #endif 1122 register_kernel_break_hook(&fault_break_hook); 1123 #ifdef CONFIG_KASAN_SW_TAGS 1124 register_kernel_break_hook(&kasan_break_hook); 1125 #endif 1126 #ifdef CONFIG_UBSAN_TRAP 1127 register_kernel_break_hook(&ubsan_break_hook); 1128 #endif 1129 debug_traps_init(); 1130 } 1131