1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Based on arch/arm/kernel/traps.c 4 * 5 * Copyright (C) 1995-2009 Russell King 6 * Copyright (C) 2012 ARM Ltd. 7 */ 8 9 #include <linux/bug.h> 10 #include <linux/context_tracking.h> 11 #include <linux/signal.h> 12 #include <linux/kallsyms.h> 13 #include <linux/kprobes.h> 14 #include <linux/spinlock.h> 15 #include <linux/uaccess.h> 16 #include <linux/hardirq.h> 17 #include <linux/kdebug.h> 18 #include <linux/module.h> 19 #include <linux/kexec.h> 20 #include <linux/delay.h> 21 #include <linux/efi.h> 22 #include <linux/init.h> 23 #include <linux/sched/signal.h> 24 #include <linux/sched/debug.h> 25 #include <linux/sched/task_stack.h> 26 #include <linux/sizes.h> 27 #include <linux/syscalls.h> 28 #include <linux/mm_types.h> 29 #include <linux/kasan.h> 30 #include <linux/cfi.h> 31 32 #include <asm/atomic.h> 33 #include <asm/bug.h> 34 #include <asm/cpufeature.h> 35 #include <asm/daifflags.h> 36 #include <asm/debug-monitors.h> 37 #include <asm/efi.h> 38 #include <asm/esr.h> 39 #include <asm/exception.h> 40 #include <asm/extable.h> 41 #include <asm/insn.h> 42 #include <asm/kprobes.h> 43 #include <asm/patching.h> 44 #include <asm/traps.h> 45 #include <asm/smp.h> 46 #include <asm/stack_pointer.h> 47 #include <asm/stacktrace.h> 48 #include <asm/system_misc.h> 49 #include <asm/sysreg.h> 50 51 static bool __kprobes __check_eq(unsigned long pstate) 52 { 53 return (pstate & PSR_Z_BIT) != 0; 54 } 55 56 static bool __kprobes __check_ne(unsigned long pstate) 57 { 58 return (pstate & PSR_Z_BIT) == 0; 59 } 60 61 static bool __kprobes __check_cs(unsigned long pstate) 62 { 63 return (pstate & PSR_C_BIT) != 0; 64 } 65 66 static bool __kprobes __check_cc(unsigned long pstate) 67 { 68 return (pstate & PSR_C_BIT) == 0; 69 } 70 71 static bool __kprobes __check_mi(unsigned long pstate) 72 { 73 return (pstate & PSR_N_BIT) != 0; 74 } 75 76 static bool __kprobes __check_pl(unsigned long pstate) 77 { 78 return (pstate & PSR_N_BIT) == 0; 79 } 80 81 static bool __kprobes __check_vs(unsigned long pstate) 82 { 83 return (pstate & PSR_V_BIT) != 0; 84 } 85 86 static bool __kprobes __check_vc(unsigned long pstate) 87 { 88 return (pstate & PSR_V_BIT) == 0; 89 } 90 91 static bool __kprobes __check_hi(unsigned long pstate) 92 { 93 pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ 94 return (pstate & PSR_C_BIT) != 0; 95 } 96 97 static bool __kprobes __check_ls(unsigned long pstate) 98 { 99 pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ 100 return (pstate & PSR_C_BIT) == 0; 101 } 102 103 static bool __kprobes __check_ge(unsigned long pstate) 104 { 105 pstate ^= (pstate << 3); /* PSR_N_BIT ^= PSR_V_BIT */ 106 return (pstate & PSR_N_BIT) == 0; 107 } 108 109 static bool __kprobes __check_lt(unsigned long pstate) 110 { 111 pstate ^= (pstate << 3); /* PSR_N_BIT ^= PSR_V_BIT */ 112 return (pstate & PSR_N_BIT) != 0; 113 } 114 115 static bool __kprobes __check_gt(unsigned long pstate) 116 { 117 /*PSR_N_BIT ^= PSR_V_BIT */ 118 unsigned long temp = pstate ^ (pstate << 3); 119 120 temp |= (pstate << 1); /*PSR_N_BIT |= PSR_Z_BIT */ 121 return (temp & PSR_N_BIT) == 0; 122 } 123 124 static bool __kprobes __check_le(unsigned long pstate) 125 { 126 /*PSR_N_BIT ^= PSR_V_BIT */ 127 unsigned long temp = pstate ^ (pstate << 3); 128 129 temp |= (pstate << 1); /*PSR_N_BIT |= PSR_Z_BIT */ 130 return (temp & PSR_N_BIT) != 0; 131 } 132 133 static bool __kprobes __check_al(unsigned long pstate) 134 { 135 return true; 136 } 137 138 /* 139 * Note that the ARMv8 ARM calls condition code 0b1111 "nv", but states that 140 * it behaves identically to 0b1110 ("al"). 141 */ 142 pstate_check_t * const aarch32_opcode_cond_checks[16] = { 143 __check_eq, __check_ne, __check_cs, __check_cc, 144 __check_mi, __check_pl, __check_vs, __check_vc, 145 __check_hi, __check_ls, __check_ge, __check_lt, 146 __check_gt, __check_le, __check_al, __check_al 147 }; 148 149 int show_unhandled_signals = 0; 150 151 static void dump_kernel_instr(const char *lvl, struct pt_regs *regs) 152 { 153 unsigned long addr = instruction_pointer(regs); 154 char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str; 155 int i; 156 157 if (user_mode(regs)) 158 return; 159 160 for (i = -4; i < 1; i++) { 161 unsigned int val, bad; 162 163 bad = aarch64_insn_read(&((u32 *)addr)[i], &val); 164 165 if (!bad) 166 p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val); 167 else { 168 p += sprintf(p, "bad PC value"); 169 break; 170 } 171 } 172 173 printk("%sCode: %s\n", lvl, str); 174 } 175 176 #ifdef CONFIG_PREEMPT 177 #define S_PREEMPT " PREEMPT" 178 #elif defined(CONFIG_PREEMPT_RT) 179 #define S_PREEMPT " PREEMPT_RT" 180 #else 181 #define S_PREEMPT "" 182 #endif 183 184 #define S_SMP " SMP" 185 186 static int __die(const char *str, long err, struct pt_regs *regs) 187 { 188 static int die_counter; 189 int ret; 190 191 pr_emerg("Internal error: %s: %016lx [#%d]" S_PREEMPT S_SMP "\n", 192 str, err, ++die_counter); 193 194 /* trap and error numbers are mostly meaningless on ARM */ 195 ret = notify_die(DIE_OOPS, str, regs, err, 0, SIGSEGV); 196 if (ret == NOTIFY_STOP) 197 return ret; 198 199 print_modules(); 200 show_regs(regs); 201 202 dump_kernel_instr(KERN_EMERG, regs); 203 204 return ret; 205 } 206 207 static DEFINE_RAW_SPINLOCK(die_lock); 208 209 /* 210 * This function is protected against re-entrancy. 211 */ 212 void die(const char *str, struct pt_regs *regs, long err) 213 { 214 int ret; 215 unsigned long flags; 216 217 raw_spin_lock_irqsave(&die_lock, flags); 218 219 oops_enter(); 220 221 console_verbose(); 222 bust_spinlocks(1); 223 ret = __die(str, err, regs); 224 225 if (regs && kexec_should_crash(current)) 226 crash_kexec(regs); 227 228 bust_spinlocks(0); 229 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 230 oops_exit(); 231 232 if (in_interrupt()) 233 panic("%s: Fatal exception in interrupt", str); 234 if (panic_on_oops) 235 panic("%s: Fatal exception", str); 236 237 raw_spin_unlock_irqrestore(&die_lock, flags); 238 239 if (ret != NOTIFY_STOP) 240 make_task_dead(SIGSEGV); 241 } 242 243 static void arm64_show_signal(int signo, const char *str) 244 { 245 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, 246 DEFAULT_RATELIMIT_BURST); 247 struct task_struct *tsk = current; 248 unsigned long esr = tsk->thread.fault_code; 249 struct pt_regs *regs = task_pt_regs(tsk); 250 251 /* Leave if the signal won't be shown */ 252 if (!show_unhandled_signals || 253 !unhandled_signal(tsk, signo) || 254 !__ratelimit(&rs)) 255 return; 256 257 pr_info("%s[%d]: unhandled exception: ", tsk->comm, task_pid_nr(tsk)); 258 if (esr) 259 pr_cont("%s, ESR 0x%016lx, ", esr_get_class_string(esr), esr); 260 261 pr_cont("%s", str); 262 print_vma_addr(KERN_CONT " in ", regs->pc); 263 pr_cont("\n"); 264 __show_regs(regs); 265 } 266 267 void arm64_force_sig_fault(int signo, int code, unsigned long far, 268 const char *str) 269 { 270 arm64_show_signal(signo, str); 271 if (signo == SIGKILL) 272 force_sig(SIGKILL); 273 else 274 force_sig_fault(signo, code, (void __user *)far); 275 } 276 277 void arm64_force_sig_mceerr(int code, unsigned long far, short lsb, 278 const char *str) 279 { 280 arm64_show_signal(SIGBUS, str); 281 force_sig_mceerr(code, (void __user *)far, lsb); 282 } 283 284 void arm64_force_sig_ptrace_errno_trap(int errno, unsigned long far, 285 const char *str) 286 { 287 arm64_show_signal(SIGTRAP, str); 288 force_sig_ptrace_errno_trap(errno, (void __user *)far); 289 } 290 291 void arm64_notify_die(const char *str, struct pt_regs *regs, 292 int signo, int sicode, unsigned long far, 293 unsigned long err) 294 { 295 if (user_mode(regs)) { 296 WARN_ON(regs != current_pt_regs()); 297 current->thread.fault_address = 0; 298 current->thread.fault_code = err; 299 300 arm64_force_sig_fault(signo, sicode, far, str); 301 } else { 302 die(str, regs, err); 303 } 304 } 305 306 #ifdef CONFIG_COMPAT 307 #define PSTATE_IT_1_0_SHIFT 25 308 #define PSTATE_IT_1_0_MASK (0x3 << PSTATE_IT_1_0_SHIFT) 309 #define PSTATE_IT_7_2_SHIFT 10 310 #define PSTATE_IT_7_2_MASK (0x3f << PSTATE_IT_7_2_SHIFT) 311 312 static u32 compat_get_it_state(struct pt_regs *regs) 313 { 314 u32 it, pstate = regs->pstate; 315 316 it = (pstate & PSTATE_IT_1_0_MASK) >> PSTATE_IT_1_0_SHIFT; 317 it |= ((pstate & PSTATE_IT_7_2_MASK) >> PSTATE_IT_7_2_SHIFT) << 2; 318 319 return it; 320 } 321 322 static void compat_set_it_state(struct pt_regs *regs, u32 it) 323 { 324 u32 pstate_it; 325 326 pstate_it = (it << PSTATE_IT_1_0_SHIFT) & PSTATE_IT_1_0_MASK; 327 pstate_it |= ((it >> 2) << PSTATE_IT_7_2_SHIFT) & PSTATE_IT_7_2_MASK; 328 329 regs->pstate &= ~PSR_AA32_IT_MASK; 330 regs->pstate |= pstate_it; 331 } 332 333 static void advance_itstate(struct pt_regs *regs) 334 { 335 u32 it; 336 337 /* ARM mode */ 338 if (!(regs->pstate & PSR_AA32_T_BIT) || 339 !(regs->pstate & PSR_AA32_IT_MASK)) 340 return; 341 342 it = compat_get_it_state(regs); 343 344 /* 345 * If this is the last instruction of the block, wipe the IT 346 * state. Otherwise advance it. 347 */ 348 if (!(it & 7)) 349 it = 0; 350 else 351 it = (it & 0xe0) | ((it << 1) & 0x1f); 352 353 compat_set_it_state(regs, it); 354 } 355 #else 356 static void advance_itstate(struct pt_regs *regs) 357 { 358 } 359 #endif 360 361 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size) 362 { 363 regs->pc += size; 364 365 /* 366 * If we were single stepping, we want to get the step exception after 367 * we return from the trap. 368 */ 369 if (user_mode(regs)) 370 user_fastforward_single_step(current); 371 372 if (compat_user_mode(regs)) 373 advance_itstate(regs); 374 else 375 regs->pstate &= ~PSR_BTYPE_MASK; 376 } 377 378 static int user_insn_read(struct pt_regs *regs, u32 *insnp) 379 { 380 u32 instr; 381 unsigned long pc = instruction_pointer(regs); 382 383 if (compat_thumb_mode(regs)) { 384 /* 16-bit Thumb instruction */ 385 __le16 instr_le; 386 if (get_user(instr_le, (__le16 __user *)pc)) 387 return -EFAULT; 388 instr = le16_to_cpu(instr_le); 389 if (aarch32_insn_is_wide(instr)) { 390 u32 instr2; 391 392 if (get_user(instr_le, (__le16 __user *)(pc + 2))) 393 return -EFAULT; 394 instr2 = le16_to_cpu(instr_le); 395 instr = (instr << 16) | instr2; 396 } 397 } else { 398 /* 32-bit ARM instruction */ 399 __le32 instr_le; 400 if (get_user(instr_le, (__le32 __user *)pc)) 401 return -EFAULT; 402 instr = le32_to_cpu(instr_le); 403 } 404 405 *insnp = instr; 406 return 0; 407 } 408 409 void force_signal_inject(int signal, int code, unsigned long address, unsigned long err) 410 { 411 const char *desc; 412 struct pt_regs *regs = current_pt_regs(); 413 414 if (WARN_ON(!user_mode(regs))) 415 return; 416 417 switch (signal) { 418 case SIGILL: 419 desc = "undefined instruction"; 420 break; 421 case SIGSEGV: 422 desc = "illegal memory access"; 423 break; 424 default: 425 desc = "unknown or unrecoverable error"; 426 break; 427 } 428 429 /* Force signals we don't understand to SIGKILL */ 430 if (WARN_ON(signal != SIGKILL && 431 siginfo_layout(signal, code) != SIL_FAULT)) { 432 signal = SIGKILL; 433 } 434 435 arm64_notify_die(desc, regs, signal, code, address, err); 436 } 437 438 /* 439 * Set up process info to signal segmentation fault - called on access error. 440 */ 441 void arm64_notify_segfault(unsigned long addr) 442 { 443 int code; 444 445 mmap_read_lock(current->mm); 446 if (find_vma(current->mm, untagged_addr(addr)) == NULL) 447 code = SEGV_MAPERR; 448 else 449 code = SEGV_ACCERR; 450 mmap_read_unlock(current->mm); 451 452 force_signal_inject(SIGSEGV, code, addr, 0); 453 } 454 455 void do_el0_undef(struct pt_regs *regs, unsigned long esr) 456 { 457 u32 insn; 458 459 /* check for AArch32 breakpoint instructions */ 460 if (!aarch32_break_handler(regs)) 461 return; 462 463 if (user_insn_read(regs, &insn)) 464 goto out_err; 465 466 if (try_emulate_mrs(regs, insn)) 467 return; 468 469 if (try_emulate_armv8_deprecated(regs, insn)) 470 return; 471 472 out_err: 473 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 474 } 475 476 void do_el1_undef(struct pt_regs *regs, unsigned long esr) 477 { 478 u32 insn; 479 480 if (aarch64_insn_read((void *)regs->pc, &insn)) 481 goto out_err; 482 483 if (try_emulate_el1_ssbs(regs, insn)) 484 return; 485 486 out_err: 487 die("Oops - Undefined instruction", regs, esr); 488 } 489 490 void do_el0_bti(struct pt_regs *regs) 491 { 492 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 493 } 494 495 void do_el1_bti(struct pt_regs *regs, unsigned long esr) 496 { 497 if (efi_runtime_fixup_exception(regs, "BTI violation")) { 498 regs->pstate &= ~PSR_BTYPE_MASK; 499 return; 500 } 501 die("Oops - BTI", regs, esr); 502 } 503 504 void do_el0_fpac(struct pt_regs *regs, unsigned long esr) 505 { 506 force_signal_inject(SIGILL, ILL_ILLOPN, regs->pc, esr); 507 } 508 509 void do_el1_fpac(struct pt_regs *regs, unsigned long esr) 510 { 511 /* 512 * Unexpected FPAC exception in the kernel: kill the task before it 513 * does any more harm. 514 */ 515 die("Oops - FPAC", regs, esr); 516 } 517 518 #define __user_cache_maint(insn, address, res) \ 519 if (address >= TASK_SIZE_MAX) { \ 520 res = -EFAULT; \ 521 } else { \ 522 uaccess_ttbr0_enable(); \ 523 asm volatile ( \ 524 "1: " insn ", %1\n" \ 525 " mov %w0, #0\n" \ 526 "2:\n" \ 527 _ASM_EXTABLE_UACCESS_ERR(1b, 2b, %w0) \ 528 : "=r" (res) \ 529 : "r" (address)); \ 530 uaccess_ttbr0_disable(); \ 531 } 532 533 static void user_cache_maint_handler(unsigned long esr, struct pt_regs *regs) 534 { 535 unsigned long tagged_address, address; 536 int rt = ESR_ELx_SYS64_ISS_RT(esr); 537 int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT; 538 int ret = 0; 539 540 tagged_address = pt_regs_read_reg(regs, rt); 541 address = untagged_addr(tagged_address); 542 543 switch (crm) { 544 case ESR_ELx_SYS64_ISS_CRM_DC_CVAU: /* DC CVAU, gets promoted */ 545 __user_cache_maint("dc civac", address, ret); 546 break; 547 case ESR_ELx_SYS64_ISS_CRM_DC_CVAC: /* DC CVAC, gets promoted */ 548 __user_cache_maint("dc civac", address, ret); 549 break; 550 case ESR_ELx_SYS64_ISS_CRM_DC_CVADP: /* DC CVADP */ 551 __user_cache_maint("sys 3, c7, c13, 1", address, ret); 552 break; 553 case ESR_ELx_SYS64_ISS_CRM_DC_CVAP: /* DC CVAP */ 554 __user_cache_maint("sys 3, c7, c12, 1", address, ret); 555 break; 556 case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC: /* DC CIVAC */ 557 __user_cache_maint("dc civac", address, ret); 558 break; 559 case ESR_ELx_SYS64_ISS_CRM_IC_IVAU: /* IC IVAU */ 560 __user_cache_maint("ic ivau", address, ret); 561 break; 562 default: 563 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 564 return; 565 } 566 567 if (ret) 568 arm64_notify_segfault(tagged_address); 569 else 570 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 571 } 572 573 static void ctr_read_handler(unsigned long esr, struct pt_regs *regs) 574 { 575 int rt = ESR_ELx_SYS64_ISS_RT(esr); 576 unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0); 577 578 if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) { 579 /* Hide DIC so that we can trap the unnecessary maintenance...*/ 580 val &= ~BIT(CTR_EL0_DIC_SHIFT); 581 582 /* ... and fake IminLine to reduce the number of traps. */ 583 val &= ~CTR_EL0_IminLine_MASK; 584 val |= (PAGE_SHIFT - 2) & CTR_EL0_IminLine_MASK; 585 } 586 587 pt_regs_write_reg(regs, rt, val); 588 589 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 590 } 591 592 static void cntvct_read_handler(unsigned long esr, struct pt_regs *regs) 593 { 594 int rt = ESR_ELx_SYS64_ISS_RT(esr); 595 596 pt_regs_write_reg(regs, rt, arch_timer_read_counter()); 597 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 598 } 599 600 static void cntfrq_read_handler(unsigned long esr, struct pt_regs *regs) 601 { 602 int rt = ESR_ELx_SYS64_ISS_RT(esr); 603 604 pt_regs_write_reg(regs, rt, arch_timer_get_rate()); 605 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 606 } 607 608 static void mrs_handler(unsigned long esr, struct pt_regs *regs) 609 { 610 u32 sysreg, rt; 611 612 rt = ESR_ELx_SYS64_ISS_RT(esr); 613 sysreg = esr_sys64_to_sysreg(esr); 614 615 if (do_emulate_mrs(regs, sysreg, rt) != 0) 616 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 617 } 618 619 static void wfi_handler(unsigned long esr, struct pt_regs *regs) 620 { 621 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 622 } 623 624 struct sys64_hook { 625 unsigned long esr_mask; 626 unsigned long esr_val; 627 void (*handler)(unsigned long esr, struct pt_regs *regs); 628 }; 629 630 static const struct sys64_hook sys64_hooks[] = { 631 { 632 .esr_mask = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK, 633 .esr_val = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL, 634 .handler = user_cache_maint_handler, 635 }, 636 { 637 /* Trap read access to CTR_EL0 */ 638 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 639 .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ, 640 .handler = ctr_read_handler, 641 }, 642 { 643 /* Trap read access to CNTVCT_EL0 */ 644 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 645 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT, 646 .handler = cntvct_read_handler, 647 }, 648 { 649 /* Trap read access to CNTVCTSS_EL0 */ 650 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 651 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCTSS, 652 .handler = cntvct_read_handler, 653 }, 654 { 655 /* Trap read access to CNTFRQ_EL0 */ 656 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 657 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTFRQ, 658 .handler = cntfrq_read_handler, 659 }, 660 { 661 /* Trap read access to CPUID registers */ 662 .esr_mask = ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK, 663 .esr_val = ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL, 664 .handler = mrs_handler, 665 }, 666 { 667 /* Trap WFI instructions executed in userspace */ 668 .esr_mask = ESR_ELx_WFx_MASK, 669 .esr_val = ESR_ELx_WFx_WFI_VAL, 670 .handler = wfi_handler, 671 }, 672 {}, 673 }; 674 675 #ifdef CONFIG_COMPAT 676 static bool cp15_cond_valid(unsigned long esr, struct pt_regs *regs) 677 { 678 int cond; 679 680 /* Only a T32 instruction can trap without CV being set */ 681 if (!(esr & ESR_ELx_CV)) { 682 u32 it; 683 684 it = compat_get_it_state(regs); 685 if (!it) 686 return true; 687 688 cond = it >> 4; 689 } else { 690 cond = (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT; 691 } 692 693 return aarch32_opcode_cond_checks[cond](regs->pstate); 694 } 695 696 static void compat_cntfrq_read_handler(unsigned long esr, struct pt_regs *regs) 697 { 698 int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT; 699 700 pt_regs_write_reg(regs, reg, arch_timer_get_rate()); 701 arm64_skip_faulting_instruction(regs, 4); 702 } 703 704 static const struct sys64_hook cp15_32_hooks[] = { 705 { 706 .esr_mask = ESR_ELx_CP15_32_ISS_SYS_MASK, 707 .esr_val = ESR_ELx_CP15_32_ISS_SYS_CNTFRQ, 708 .handler = compat_cntfrq_read_handler, 709 }, 710 {}, 711 }; 712 713 static void compat_cntvct_read_handler(unsigned long esr, struct pt_regs *regs) 714 { 715 int rt = (esr & ESR_ELx_CP15_64_ISS_RT_MASK) >> ESR_ELx_CP15_64_ISS_RT_SHIFT; 716 int rt2 = (esr & ESR_ELx_CP15_64_ISS_RT2_MASK) >> ESR_ELx_CP15_64_ISS_RT2_SHIFT; 717 u64 val = arch_timer_read_counter(); 718 719 pt_regs_write_reg(regs, rt, lower_32_bits(val)); 720 pt_regs_write_reg(regs, rt2, upper_32_bits(val)); 721 arm64_skip_faulting_instruction(regs, 4); 722 } 723 724 static const struct sys64_hook cp15_64_hooks[] = { 725 { 726 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK, 727 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCT, 728 .handler = compat_cntvct_read_handler, 729 }, 730 { 731 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK, 732 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS, 733 .handler = compat_cntvct_read_handler, 734 }, 735 {}, 736 }; 737 738 void do_el0_cp15(unsigned long esr, struct pt_regs *regs) 739 { 740 const struct sys64_hook *hook, *hook_base; 741 742 if (!cp15_cond_valid(esr, regs)) { 743 /* 744 * There is no T16 variant of a CP access, so we 745 * always advance PC by 4 bytes. 746 */ 747 arm64_skip_faulting_instruction(regs, 4); 748 return; 749 } 750 751 switch (ESR_ELx_EC(esr)) { 752 case ESR_ELx_EC_CP15_32: 753 hook_base = cp15_32_hooks; 754 break; 755 case ESR_ELx_EC_CP15_64: 756 hook_base = cp15_64_hooks; 757 break; 758 default: 759 do_el0_undef(regs, esr); 760 return; 761 } 762 763 for (hook = hook_base; hook->handler; hook++) 764 if ((hook->esr_mask & esr) == hook->esr_val) { 765 hook->handler(esr, regs); 766 return; 767 } 768 769 /* 770 * New cp15 instructions may previously have been undefined at 771 * EL0. Fall back to our usual undefined instruction handler 772 * so that we handle these consistently. 773 */ 774 do_el0_undef(regs, esr); 775 } 776 #endif 777 778 void do_el0_sys(unsigned long esr, struct pt_regs *regs) 779 { 780 const struct sys64_hook *hook; 781 782 for (hook = sys64_hooks; hook->handler; hook++) 783 if ((hook->esr_mask & esr) == hook->esr_val) { 784 hook->handler(esr, regs); 785 return; 786 } 787 788 /* 789 * New SYS instructions may previously have been undefined at EL0. Fall 790 * back to our usual undefined instruction handler so that we handle 791 * these consistently. 792 */ 793 do_el0_undef(regs, esr); 794 } 795 796 static const char *esr_class_str[] = { 797 [0 ... ESR_ELx_EC_MAX] = "UNRECOGNIZED EC", 798 [ESR_ELx_EC_UNKNOWN] = "Unknown/Uncategorized", 799 [ESR_ELx_EC_WFx] = "WFI/WFE", 800 [ESR_ELx_EC_CP15_32] = "CP15 MCR/MRC", 801 [ESR_ELx_EC_CP15_64] = "CP15 MCRR/MRRC", 802 [ESR_ELx_EC_CP14_MR] = "CP14 MCR/MRC", 803 [ESR_ELx_EC_CP14_LS] = "CP14 LDC/STC", 804 [ESR_ELx_EC_FP_ASIMD] = "ASIMD", 805 [ESR_ELx_EC_CP10_ID] = "CP10 MRC/VMRS", 806 [ESR_ELx_EC_PAC] = "PAC", 807 [ESR_ELx_EC_CP14_64] = "CP14 MCRR/MRRC", 808 [ESR_ELx_EC_BTI] = "BTI", 809 [ESR_ELx_EC_ILL] = "PSTATE.IL", 810 [ESR_ELx_EC_SVC32] = "SVC (AArch32)", 811 [ESR_ELx_EC_HVC32] = "HVC (AArch32)", 812 [ESR_ELx_EC_SMC32] = "SMC (AArch32)", 813 [ESR_ELx_EC_SVC64] = "SVC (AArch64)", 814 [ESR_ELx_EC_HVC64] = "HVC (AArch64)", 815 [ESR_ELx_EC_SMC64] = "SMC (AArch64)", 816 [ESR_ELx_EC_SYS64] = "MSR/MRS (AArch64)", 817 [ESR_ELx_EC_SVE] = "SVE", 818 [ESR_ELx_EC_ERET] = "ERET/ERETAA/ERETAB", 819 [ESR_ELx_EC_FPAC] = "FPAC", 820 [ESR_ELx_EC_SME] = "SME", 821 [ESR_ELx_EC_IMP_DEF] = "EL3 IMP DEF", 822 [ESR_ELx_EC_IABT_LOW] = "IABT (lower EL)", 823 [ESR_ELx_EC_IABT_CUR] = "IABT (current EL)", 824 [ESR_ELx_EC_PC_ALIGN] = "PC Alignment", 825 [ESR_ELx_EC_DABT_LOW] = "DABT (lower EL)", 826 [ESR_ELx_EC_DABT_CUR] = "DABT (current EL)", 827 [ESR_ELx_EC_SP_ALIGN] = "SP Alignment", 828 [ESR_ELx_EC_FP_EXC32] = "FP (AArch32)", 829 [ESR_ELx_EC_FP_EXC64] = "FP (AArch64)", 830 [ESR_ELx_EC_SERROR] = "SError", 831 [ESR_ELx_EC_BREAKPT_LOW] = "Breakpoint (lower EL)", 832 [ESR_ELx_EC_BREAKPT_CUR] = "Breakpoint (current EL)", 833 [ESR_ELx_EC_SOFTSTP_LOW] = "Software Step (lower EL)", 834 [ESR_ELx_EC_SOFTSTP_CUR] = "Software Step (current EL)", 835 [ESR_ELx_EC_WATCHPT_LOW] = "Watchpoint (lower EL)", 836 [ESR_ELx_EC_WATCHPT_CUR] = "Watchpoint (current EL)", 837 [ESR_ELx_EC_BKPT32] = "BKPT (AArch32)", 838 [ESR_ELx_EC_VECTOR32] = "Vector catch (AArch32)", 839 [ESR_ELx_EC_BRK64] = "BRK (AArch64)", 840 }; 841 842 const char *esr_get_class_string(unsigned long esr) 843 { 844 return esr_class_str[ESR_ELx_EC(esr)]; 845 } 846 847 /* 848 * bad_el0_sync handles unexpected, but potentially recoverable synchronous 849 * exceptions taken from EL0. 850 */ 851 void bad_el0_sync(struct pt_regs *regs, int reason, unsigned long esr) 852 { 853 unsigned long pc = instruction_pointer(regs); 854 855 current->thread.fault_address = 0; 856 current->thread.fault_code = esr; 857 858 arm64_force_sig_fault(SIGILL, ILL_ILLOPC, pc, 859 "Bad EL0 synchronous exception"); 860 } 861 862 #ifdef CONFIG_VMAP_STACK 863 864 DEFINE_PER_CPU(unsigned long [OVERFLOW_STACK_SIZE/sizeof(long)], overflow_stack) 865 __aligned(16); 866 867 void panic_bad_stack(struct pt_regs *regs, unsigned long esr, unsigned long far) 868 { 869 unsigned long tsk_stk = (unsigned long)current->stack; 870 unsigned long irq_stk = (unsigned long)this_cpu_read(irq_stack_ptr); 871 unsigned long ovf_stk = (unsigned long)this_cpu_ptr(overflow_stack); 872 873 console_verbose(); 874 pr_emerg("Insufficient stack space to handle exception!"); 875 876 pr_emerg("ESR: 0x%016lx -- %s\n", esr, esr_get_class_string(esr)); 877 pr_emerg("FAR: 0x%016lx\n", far); 878 879 pr_emerg("Task stack: [0x%016lx..0x%016lx]\n", 880 tsk_stk, tsk_stk + THREAD_SIZE); 881 pr_emerg("IRQ stack: [0x%016lx..0x%016lx]\n", 882 irq_stk, irq_stk + IRQ_STACK_SIZE); 883 pr_emerg("Overflow stack: [0x%016lx..0x%016lx]\n", 884 ovf_stk, ovf_stk + OVERFLOW_STACK_SIZE); 885 886 __show_regs(regs); 887 888 /* 889 * We use nmi_panic to limit the potential for recusive overflows, and 890 * to get a better stack trace. 891 */ 892 nmi_panic(NULL, "kernel stack overflow"); 893 cpu_park_loop(); 894 } 895 #endif 896 897 void __noreturn arm64_serror_panic(struct pt_regs *regs, unsigned long esr) 898 { 899 console_verbose(); 900 901 pr_crit("SError Interrupt on CPU%d, code 0x%016lx -- %s\n", 902 smp_processor_id(), esr, esr_get_class_string(esr)); 903 if (regs) 904 __show_regs(regs); 905 906 nmi_panic(regs, "Asynchronous SError Interrupt"); 907 908 cpu_park_loop(); 909 unreachable(); 910 } 911 912 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned long esr) 913 { 914 unsigned long aet = arm64_ras_serror_get_severity(esr); 915 916 switch (aet) { 917 case ESR_ELx_AET_CE: /* corrected error */ 918 case ESR_ELx_AET_UEO: /* restartable, not yet consumed */ 919 /* 920 * The CPU can make progress. We may take UEO again as 921 * a more severe error. 922 */ 923 return false; 924 925 case ESR_ELx_AET_UEU: /* Uncorrected Unrecoverable */ 926 case ESR_ELx_AET_UER: /* Uncorrected Recoverable */ 927 /* 928 * The CPU can't make progress. The exception may have 929 * been imprecise. 930 * 931 * Neoverse-N1 #1349291 means a non-KVM SError reported as 932 * Unrecoverable should be treated as Uncontainable. We 933 * call arm64_serror_panic() in both cases. 934 */ 935 return true; 936 937 case ESR_ELx_AET_UC: /* Uncontainable or Uncategorized error */ 938 default: 939 /* Error has been silently propagated */ 940 arm64_serror_panic(regs, esr); 941 } 942 } 943 944 void do_serror(struct pt_regs *regs, unsigned long esr) 945 { 946 /* non-RAS errors are not containable */ 947 if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(regs, esr)) 948 arm64_serror_panic(regs, esr); 949 } 950 951 /* GENERIC_BUG traps */ 952 953 int is_valid_bugaddr(unsigned long addr) 954 { 955 /* 956 * bug_handler() only called for BRK #BUG_BRK_IMM. 957 * So the answer is trivial -- any spurious instances with no 958 * bug table entry will be rejected by report_bug() and passed 959 * back to the debug-monitors code and handled as a fatal 960 * unexpected debug exception. 961 */ 962 return 1; 963 } 964 965 static int bug_handler(struct pt_regs *regs, unsigned long esr) 966 { 967 switch (report_bug(regs->pc, regs)) { 968 case BUG_TRAP_TYPE_BUG: 969 die("Oops - BUG", regs, esr); 970 break; 971 972 case BUG_TRAP_TYPE_WARN: 973 break; 974 975 default: 976 /* unknown/unrecognised bug trap type */ 977 return DBG_HOOK_ERROR; 978 } 979 980 /* If thread survives, skip over the BUG instruction and continue: */ 981 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 982 return DBG_HOOK_HANDLED; 983 } 984 985 static struct break_hook bug_break_hook = { 986 .fn = bug_handler, 987 .imm = BUG_BRK_IMM, 988 }; 989 990 #ifdef CONFIG_CFI_CLANG 991 static int cfi_handler(struct pt_regs *regs, unsigned long esr) 992 { 993 unsigned long target; 994 u32 type; 995 996 target = pt_regs_read_reg(regs, FIELD_GET(CFI_BRK_IMM_TARGET, esr)); 997 type = (u32)pt_regs_read_reg(regs, FIELD_GET(CFI_BRK_IMM_TYPE, esr)); 998 999 switch (report_cfi_failure(regs, regs->pc, &target, type)) { 1000 case BUG_TRAP_TYPE_BUG: 1001 die("Oops - CFI", regs, 0); 1002 break; 1003 1004 case BUG_TRAP_TYPE_WARN: 1005 break; 1006 1007 default: 1008 return DBG_HOOK_ERROR; 1009 } 1010 1011 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 1012 return DBG_HOOK_HANDLED; 1013 } 1014 1015 static struct break_hook cfi_break_hook = { 1016 .fn = cfi_handler, 1017 .imm = CFI_BRK_IMM_BASE, 1018 .mask = CFI_BRK_IMM_MASK, 1019 }; 1020 #endif /* CONFIG_CFI_CLANG */ 1021 1022 static int reserved_fault_handler(struct pt_regs *regs, unsigned long esr) 1023 { 1024 pr_err("%s generated an invalid instruction at %pS!\n", 1025 "Kernel text patching", 1026 (void *)instruction_pointer(regs)); 1027 1028 /* We cannot handle this */ 1029 return DBG_HOOK_ERROR; 1030 } 1031 1032 static struct break_hook fault_break_hook = { 1033 .fn = reserved_fault_handler, 1034 .imm = FAULT_BRK_IMM, 1035 }; 1036 1037 #ifdef CONFIG_KASAN_SW_TAGS 1038 1039 #define KASAN_ESR_RECOVER 0x20 1040 #define KASAN_ESR_WRITE 0x10 1041 #define KASAN_ESR_SIZE_MASK 0x0f 1042 #define KASAN_ESR_SIZE(esr) (1 << ((esr) & KASAN_ESR_SIZE_MASK)) 1043 1044 static int kasan_handler(struct pt_regs *regs, unsigned long esr) 1045 { 1046 bool recover = esr & KASAN_ESR_RECOVER; 1047 bool write = esr & KASAN_ESR_WRITE; 1048 size_t size = KASAN_ESR_SIZE(esr); 1049 u64 addr = regs->regs[0]; 1050 u64 pc = regs->pc; 1051 1052 kasan_report(addr, size, write, pc); 1053 1054 /* 1055 * The instrumentation allows to control whether we can proceed after 1056 * a crash was detected. This is done by passing the -recover flag to 1057 * the compiler. Disabling recovery allows to generate more compact 1058 * code. 1059 * 1060 * Unfortunately disabling recovery doesn't work for the kernel right 1061 * now. KASAN reporting is disabled in some contexts (for example when 1062 * the allocator accesses slab object metadata; this is controlled by 1063 * current->kasan_depth). All these accesses are detected by the tool, 1064 * even though the reports for them are not printed. 1065 * 1066 * This is something that might be fixed at some point in the future. 1067 */ 1068 if (!recover) 1069 die("Oops - KASAN", regs, esr); 1070 1071 /* If thread survives, skip over the brk instruction and continue: */ 1072 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 1073 return DBG_HOOK_HANDLED; 1074 } 1075 1076 static struct break_hook kasan_break_hook = { 1077 .fn = kasan_handler, 1078 .imm = KASAN_BRK_IMM, 1079 .mask = KASAN_BRK_MASK, 1080 }; 1081 #endif 1082 1083 1084 #define esr_comment(esr) ((esr) & ESR_ELx_BRK64_ISS_COMMENT_MASK) 1085 1086 /* 1087 * Initial handler for AArch64 BRK exceptions 1088 * This handler only used until debug_traps_init(). 1089 */ 1090 int __init early_brk64(unsigned long addr, unsigned long esr, 1091 struct pt_regs *regs) 1092 { 1093 #ifdef CONFIG_CFI_CLANG 1094 if ((esr_comment(esr) & ~CFI_BRK_IMM_MASK) == CFI_BRK_IMM_BASE) 1095 return cfi_handler(regs, esr) != DBG_HOOK_HANDLED; 1096 #endif 1097 #ifdef CONFIG_KASAN_SW_TAGS 1098 if ((esr_comment(esr) & ~KASAN_BRK_MASK) == KASAN_BRK_IMM) 1099 return kasan_handler(regs, esr) != DBG_HOOK_HANDLED; 1100 #endif 1101 return bug_handler(regs, esr) != DBG_HOOK_HANDLED; 1102 } 1103 1104 void __init trap_init(void) 1105 { 1106 register_kernel_break_hook(&bug_break_hook); 1107 #ifdef CONFIG_CFI_CLANG 1108 register_kernel_break_hook(&cfi_break_hook); 1109 #endif 1110 register_kernel_break_hook(&fault_break_hook); 1111 #ifdef CONFIG_KASAN_SW_TAGS 1112 register_kernel_break_hook(&kasan_break_hook); 1113 #endif 1114 debug_traps_init(); 1115 } 1116