1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Based on arch/arm/kernel/traps.c 4 * 5 * Copyright (C) 1995-2009 Russell King 6 * Copyright (C) 2012 ARM Ltd. 7 */ 8 9 #include <linux/bug.h> 10 #include <linux/context_tracking.h> 11 #include <linux/signal.h> 12 #include <linux/kallsyms.h> 13 #include <linux/kprobes.h> 14 #include <linux/spinlock.h> 15 #include <linux/uaccess.h> 16 #include <linux/hardirq.h> 17 #include <linux/kdebug.h> 18 #include <linux/module.h> 19 #include <linux/kexec.h> 20 #include <linux/delay.h> 21 #include <linux/efi.h> 22 #include <linux/init.h> 23 #include <linux/sched/signal.h> 24 #include <linux/sched/debug.h> 25 #include <linux/sched/task_stack.h> 26 #include <linux/sizes.h> 27 #include <linux/syscalls.h> 28 #include <linux/mm_types.h> 29 #include <linux/kasan.h> 30 #include <linux/ubsan.h> 31 #include <linux/cfi.h> 32 33 #include <asm/atomic.h> 34 #include <asm/bug.h> 35 #include <asm/cpufeature.h> 36 #include <asm/daifflags.h> 37 #include <asm/debug-monitors.h> 38 #include <asm/efi.h> 39 #include <asm/esr.h> 40 #include <asm/exception.h> 41 #include <asm/extable.h> 42 #include <asm/insn.h> 43 #include <asm/kprobes.h> 44 #include <asm/patching.h> 45 #include <asm/traps.h> 46 #include <asm/smp.h> 47 #include <asm/stack_pointer.h> 48 #include <asm/stacktrace.h> 49 #include <asm/system_misc.h> 50 #include <asm/sysreg.h> 51 52 static bool __kprobes __check_eq(unsigned long pstate) 53 { 54 return (pstate & PSR_Z_BIT) != 0; 55 } 56 57 static bool __kprobes __check_ne(unsigned long pstate) 58 { 59 return (pstate & PSR_Z_BIT) == 0; 60 } 61 62 static bool __kprobes __check_cs(unsigned long pstate) 63 { 64 return (pstate & PSR_C_BIT) != 0; 65 } 66 67 static bool __kprobes __check_cc(unsigned long pstate) 68 { 69 return (pstate & PSR_C_BIT) == 0; 70 } 71 72 static bool __kprobes __check_mi(unsigned long pstate) 73 { 74 return (pstate & PSR_N_BIT) != 0; 75 } 76 77 static bool __kprobes __check_pl(unsigned long pstate) 78 { 79 return (pstate & PSR_N_BIT) == 0; 80 } 81 82 static bool __kprobes __check_vs(unsigned long pstate) 83 { 84 return (pstate & PSR_V_BIT) != 0; 85 } 86 87 static bool __kprobes __check_vc(unsigned long pstate) 88 { 89 return (pstate & PSR_V_BIT) == 0; 90 } 91 92 static bool __kprobes __check_hi(unsigned long pstate) 93 { 94 pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ 95 return (pstate & PSR_C_BIT) != 0; 96 } 97 98 static bool __kprobes __check_ls(unsigned long pstate) 99 { 100 pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ 101 return (pstate & PSR_C_BIT) == 0; 102 } 103 104 static bool __kprobes __check_ge(unsigned long pstate) 105 { 106 pstate ^= (pstate << 3); /* PSR_N_BIT ^= PSR_V_BIT */ 107 return (pstate & PSR_N_BIT) == 0; 108 } 109 110 static bool __kprobes __check_lt(unsigned long pstate) 111 { 112 pstate ^= (pstate << 3); /* PSR_N_BIT ^= PSR_V_BIT */ 113 return (pstate & PSR_N_BIT) != 0; 114 } 115 116 static bool __kprobes __check_gt(unsigned long pstate) 117 { 118 /*PSR_N_BIT ^= PSR_V_BIT */ 119 unsigned long temp = pstate ^ (pstate << 3); 120 121 temp |= (pstate << 1); /*PSR_N_BIT |= PSR_Z_BIT */ 122 return (temp & PSR_N_BIT) == 0; 123 } 124 125 static bool __kprobes __check_le(unsigned long pstate) 126 { 127 /*PSR_N_BIT ^= PSR_V_BIT */ 128 unsigned long temp = pstate ^ (pstate << 3); 129 130 temp |= (pstate << 1); /*PSR_N_BIT |= PSR_Z_BIT */ 131 return (temp & PSR_N_BIT) != 0; 132 } 133 134 static bool __kprobes __check_al(unsigned long pstate) 135 { 136 return true; 137 } 138 139 /* 140 * Note that the ARMv8 ARM calls condition code 0b1111 "nv", but states that 141 * it behaves identically to 0b1110 ("al"). 142 */ 143 pstate_check_t * const aarch32_opcode_cond_checks[16] = { 144 __check_eq, __check_ne, __check_cs, __check_cc, 145 __check_mi, __check_pl, __check_vs, __check_vc, 146 __check_hi, __check_ls, __check_ge, __check_lt, 147 __check_gt, __check_le, __check_al, __check_al 148 }; 149 150 int show_unhandled_signals = 0; 151 152 static void dump_kernel_instr(const char *lvl, struct pt_regs *regs) 153 { 154 unsigned long addr = instruction_pointer(regs); 155 char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str; 156 int i; 157 158 if (user_mode(regs)) 159 return; 160 161 for (i = -4; i < 1; i++) { 162 unsigned int val, bad; 163 164 bad = aarch64_insn_read(&((u32 *)addr)[i], &val); 165 166 if (!bad) 167 p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val); 168 else 169 p += sprintf(p, i == 0 ? "(????????) " : "???????? "); 170 } 171 172 printk("%sCode: %s\n", lvl, str); 173 } 174 175 #ifdef CONFIG_PREEMPT 176 #define S_PREEMPT " PREEMPT" 177 #elif defined(CONFIG_PREEMPT_RT) 178 #define S_PREEMPT " PREEMPT_RT" 179 #else 180 #define S_PREEMPT "" 181 #endif 182 183 #define S_SMP " SMP" 184 185 static int __die(const char *str, long err, struct pt_regs *regs) 186 { 187 static int die_counter; 188 int ret; 189 190 pr_emerg("Internal error: %s: %016lx [#%d]" S_PREEMPT S_SMP "\n", 191 str, err, ++die_counter); 192 193 /* trap and error numbers are mostly meaningless on ARM */ 194 ret = notify_die(DIE_OOPS, str, regs, err, 0, SIGSEGV); 195 if (ret == NOTIFY_STOP) 196 return ret; 197 198 print_modules(); 199 show_regs(regs); 200 201 dump_kernel_instr(KERN_EMERG, regs); 202 203 return ret; 204 } 205 206 static DEFINE_RAW_SPINLOCK(die_lock); 207 208 /* 209 * This function is protected against re-entrancy. 210 */ 211 void die(const char *str, struct pt_regs *regs, long err) 212 { 213 int ret; 214 unsigned long flags; 215 216 raw_spin_lock_irqsave(&die_lock, flags); 217 218 oops_enter(); 219 220 console_verbose(); 221 bust_spinlocks(1); 222 ret = __die(str, err, regs); 223 224 if (regs && kexec_should_crash(current)) 225 crash_kexec(regs); 226 227 bust_spinlocks(0); 228 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 229 oops_exit(); 230 231 if (in_interrupt()) 232 panic("%s: Fatal exception in interrupt", str); 233 if (panic_on_oops) 234 panic("%s: Fatal exception", str); 235 236 raw_spin_unlock_irqrestore(&die_lock, flags); 237 238 if (ret != NOTIFY_STOP) 239 make_task_dead(SIGSEGV); 240 } 241 242 static void arm64_show_signal(int signo, const char *str) 243 { 244 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, 245 DEFAULT_RATELIMIT_BURST); 246 struct task_struct *tsk = current; 247 unsigned long esr = tsk->thread.fault_code; 248 struct pt_regs *regs = task_pt_regs(tsk); 249 250 /* Leave if the signal won't be shown */ 251 if (!show_unhandled_signals || 252 !unhandled_signal(tsk, signo) || 253 !__ratelimit(&rs)) 254 return; 255 256 pr_info("%s[%d]: unhandled exception: ", tsk->comm, task_pid_nr(tsk)); 257 if (esr) 258 pr_cont("%s, ESR 0x%016lx, ", esr_get_class_string(esr), esr); 259 260 pr_cont("%s", str); 261 print_vma_addr(KERN_CONT " in ", regs->pc); 262 pr_cont("\n"); 263 __show_regs(regs); 264 } 265 266 void arm64_force_sig_fault(int signo, int code, unsigned long far, 267 const char *str) 268 { 269 arm64_show_signal(signo, str); 270 if (signo == SIGKILL) 271 force_sig(SIGKILL); 272 else 273 force_sig_fault(signo, code, (void __user *)far); 274 } 275 276 void arm64_force_sig_fault_pkey(unsigned long far, const char *str, int pkey) 277 { 278 arm64_show_signal(SIGSEGV, str); 279 force_sig_pkuerr((void __user *)far, pkey); 280 } 281 282 void arm64_force_sig_mceerr(int code, unsigned long far, short lsb, 283 const char *str) 284 { 285 arm64_show_signal(SIGBUS, str); 286 force_sig_mceerr(code, (void __user *)far, lsb); 287 } 288 289 void arm64_force_sig_ptrace_errno_trap(int errno, unsigned long far, 290 const char *str) 291 { 292 arm64_show_signal(SIGTRAP, str); 293 force_sig_ptrace_errno_trap(errno, (void __user *)far); 294 } 295 296 void arm64_notify_die(const char *str, struct pt_regs *regs, 297 int signo, int sicode, unsigned long far, 298 unsigned long err) 299 { 300 if (user_mode(regs)) { 301 WARN_ON(regs != current_pt_regs()); 302 current->thread.fault_address = 0; 303 current->thread.fault_code = err; 304 305 arm64_force_sig_fault(signo, sicode, far, str); 306 } else { 307 die(str, regs, err); 308 } 309 } 310 311 #ifdef CONFIG_COMPAT 312 #define PSTATE_IT_1_0_SHIFT 25 313 #define PSTATE_IT_1_0_MASK (0x3 << PSTATE_IT_1_0_SHIFT) 314 #define PSTATE_IT_7_2_SHIFT 10 315 #define PSTATE_IT_7_2_MASK (0x3f << PSTATE_IT_7_2_SHIFT) 316 317 static u32 compat_get_it_state(struct pt_regs *regs) 318 { 319 u32 it, pstate = regs->pstate; 320 321 it = (pstate & PSTATE_IT_1_0_MASK) >> PSTATE_IT_1_0_SHIFT; 322 it |= ((pstate & PSTATE_IT_7_2_MASK) >> PSTATE_IT_7_2_SHIFT) << 2; 323 324 return it; 325 } 326 327 static void compat_set_it_state(struct pt_regs *regs, u32 it) 328 { 329 u32 pstate_it; 330 331 pstate_it = (it << PSTATE_IT_1_0_SHIFT) & PSTATE_IT_1_0_MASK; 332 pstate_it |= ((it >> 2) << PSTATE_IT_7_2_SHIFT) & PSTATE_IT_7_2_MASK; 333 334 regs->pstate &= ~PSR_AA32_IT_MASK; 335 regs->pstate |= pstate_it; 336 } 337 338 static void advance_itstate(struct pt_regs *regs) 339 { 340 u32 it; 341 342 /* ARM mode */ 343 if (!(regs->pstate & PSR_AA32_T_BIT) || 344 !(regs->pstate & PSR_AA32_IT_MASK)) 345 return; 346 347 it = compat_get_it_state(regs); 348 349 /* 350 * If this is the last instruction of the block, wipe the IT 351 * state. Otherwise advance it. 352 */ 353 if (!(it & 7)) 354 it = 0; 355 else 356 it = (it & 0xe0) | ((it << 1) & 0x1f); 357 358 compat_set_it_state(regs, it); 359 } 360 #else 361 static void advance_itstate(struct pt_regs *regs) 362 { 363 } 364 #endif 365 366 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size) 367 { 368 regs->pc += size; 369 370 /* 371 * If we were single stepping, we want to get the step exception after 372 * we return from the trap. 373 */ 374 if (user_mode(regs)) 375 user_fastforward_single_step(current); 376 377 if (compat_user_mode(regs)) 378 advance_itstate(regs); 379 else 380 regs->pstate &= ~PSR_BTYPE_MASK; 381 } 382 383 static int user_insn_read(struct pt_regs *regs, u32 *insnp) 384 { 385 u32 instr; 386 unsigned long pc = instruction_pointer(regs); 387 388 if (compat_thumb_mode(regs)) { 389 /* 16-bit Thumb instruction */ 390 __le16 instr_le; 391 if (get_user(instr_le, (__le16 __user *)pc)) 392 return -EFAULT; 393 instr = le16_to_cpu(instr_le); 394 if (aarch32_insn_is_wide(instr)) { 395 u32 instr2; 396 397 if (get_user(instr_le, (__le16 __user *)(pc + 2))) 398 return -EFAULT; 399 instr2 = le16_to_cpu(instr_le); 400 instr = (instr << 16) | instr2; 401 } 402 } else { 403 /* 32-bit ARM instruction */ 404 __le32 instr_le; 405 if (get_user(instr_le, (__le32 __user *)pc)) 406 return -EFAULT; 407 instr = le32_to_cpu(instr_le); 408 } 409 410 *insnp = instr; 411 return 0; 412 } 413 414 void force_signal_inject(int signal, int code, unsigned long address, unsigned long err) 415 { 416 const char *desc; 417 struct pt_regs *regs = current_pt_regs(); 418 419 if (WARN_ON(!user_mode(regs))) 420 return; 421 422 switch (signal) { 423 case SIGILL: 424 desc = "undefined instruction"; 425 break; 426 case SIGSEGV: 427 desc = "illegal memory access"; 428 break; 429 default: 430 desc = "unknown or unrecoverable error"; 431 break; 432 } 433 434 /* Force signals we don't understand to SIGKILL */ 435 if (WARN_ON(signal != SIGKILL && 436 siginfo_layout(signal, code) != SIL_FAULT)) { 437 signal = SIGKILL; 438 } 439 440 arm64_notify_die(desc, regs, signal, code, address, err); 441 } 442 443 /* 444 * Set up process info to signal segmentation fault - called on access error. 445 */ 446 void arm64_notify_segfault(unsigned long addr) 447 { 448 int code; 449 450 mmap_read_lock(current->mm); 451 if (find_vma(current->mm, untagged_addr(addr)) == NULL) 452 code = SEGV_MAPERR; 453 else 454 code = SEGV_ACCERR; 455 mmap_read_unlock(current->mm); 456 457 force_signal_inject(SIGSEGV, code, addr, 0); 458 } 459 460 void do_el0_undef(struct pt_regs *regs, unsigned long esr) 461 { 462 u32 insn; 463 464 /* check for AArch32 breakpoint instructions */ 465 if (!aarch32_break_handler(regs)) 466 return; 467 468 if (user_insn_read(regs, &insn)) 469 goto out_err; 470 471 if (try_emulate_mrs(regs, insn)) 472 return; 473 474 if (try_emulate_armv8_deprecated(regs, insn)) 475 return; 476 477 out_err: 478 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 479 } 480 481 void do_el1_undef(struct pt_regs *regs, unsigned long esr) 482 { 483 u32 insn; 484 485 if (aarch64_insn_read((void *)regs->pc, &insn)) 486 goto out_err; 487 488 if (try_emulate_el1_ssbs(regs, insn)) 489 return; 490 491 out_err: 492 die("Oops - Undefined instruction", regs, esr); 493 } 494 495 void do_el0_bti(struct pt_regs *regs) 496 { 497 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 498 } 499 500 void do_el1_bti(struct pt_regs *regs, unsigned long esr) 501 { 502 if (efi_runtime_fixup_exception(regs, "BTI violation")) { 503 regs->pstate &= ~PSR_BTYPE_MASK; 504 return; 505 } 506 die("Oops - BTI", regs, esr); 507 } 508 509 void do_el0_fpac(struct pt_regs *regs, unsigned long esr) 510 { 511 force_signal_inject(SIGILL, ILL_ILLOPN, regs->pc, esr); 512 } 513 514 void do_el1_fpac(struct pt_regs *regs, unsigned long esr) 515 { 516 /* 517 * Unexpected FPAC exception in the kernel: kill the task before it 518 * does any more harm. 519 */ 520 die("Oops - FPAC", regs, esr); 521 } 522 523 void do_el0_mops(struct pt_regs *regs, unsigned long esr) 524 { 525 arm64_mops_reset_regs(®s->user_regs, esr); 526 527 /* 528 * If single stepping then finish the step before executing the 529 * prologue instruction. 530 */ 531 user_fastforward_single_step(current); 532 } 533 534 void do_el1_mops(struct pt_regs *regs, unsigned long esr) 535 { 536 arm64_mops_reset_regs(®s->user_regs, esr); 537 538 kernel_fastforward_single_step(regs); 539 } 540 541 #define __user_cache_maint(insn, address, res) \ 542 if (address >= TASK_SIZE_MAX) { \ 543 res = -EFAULT; \ 544 } else { \ 545 uaccess_ttbr0_enable(); \ 546 asm volatile ( \ 547 "1: " insn ", %1\n" \ 548 " mov %w0, #0\n" \ 549 "2:\n" \ 550 _ASM_EXTABLE_UACCESS_ERR(1b, 2b, %w0) \ 551 : "=r" (res) \ 552 : "r" (address)); \ 553 uaccess_ttbr0_disable(); \ 554 } 555 556 static void user_cache_maint_handler(unsigned long esr, struct pt_regs *regs) 557 { 558 unsigned long tagged_address, address; 559 int rt = ESR_ELx_SYS64_ISS_RT(esr); 560 int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT; 561 int ret = 0; 562 563 tagged_address = pt_regs_read_reg(regs, rt); 564 address = untagged_addr(tagged_address); 565 566 switch (crm) { 567 case ESR_ELx_SYS64_ISS_CRM_DC_CVAU: /* DC CVAU, gets promoted */ 568 __user_cache_maint("dc civac", address, ret); 569 break; 570 case ESR_ELx_SYS64_ISS_CRM_DC_CVAC: /* DC CVAC, gets promoted */ 571 __user_cache_maint("dc civac", address, ret); 572 break; 573 case ESR_ELx_SYS64_ISS_CRM_DC_CVADP: /* DC CVADP */ 574 __user_cache_maint("sys 3, c7, c13, 1", address, ret); 575 break; 576 case ESR_ELx_SYS64_ISS_CRM_DC_CVAP: /* DC CVAP */ 577 __user_cache_maint("sys 3, c7, c12, 1", address, ret); 578 break; 579 case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC: /* DC CIVAC */ 580 __user_cache_maint("dc civac", address, ret); 581 break; 582 case ESR_ELx_SYS64_ISS_CRM_IC_IVAU: /* IC IVAU */ 583 __user_cache_maint("ic ivau", address, ret); 584 break; 585 default: 586 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 587 return; 588 } 589 590 if (ret) 591 arm64_notify_segfault(tagged_address); 592 else 593 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 594 } 595 596 static void ctr_read_handler(unsigned long esr, struct pt_regs *regs) 597 { 598 int rt = ESR_ELx_SYS64_ISS_RT(esr); 599 unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0); 600 601 if (cpus_have_final_cap(ARM64_WORKAROUND_1542419)) { 602 /* Hide DIC so that we can trap the unnecessary maintenance...*/ 603 val &= ~BIT(CTR_EL0_DIC_SHIFT); 604 605 /* ... and fake IminLine to reduce the number of traps. */ 606 val &= ~CTR_EL0_IminLine_MASK; 607 val |= (PAGE_SHIFT - 2) & CTR_EL0_IminLine_MASK; 608 } 609 610 pt_regs_write_reg(regs, rt, val); 611 612 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 613 } 614 615 static void cntvct_read_handler(unsigned long esr, struct pt_regs *regs) 616 { 617 if (test_thread_flag(TIF_TSC_SIGSEGV)) { 618 force_sig(SIGSEGV); 619 } else { 620 int rt = ESR_ELx_SYS64_ISS_RT(esr); 621 622 pt_regs_write_reg(regs, rt, arch_timer_read_counter()); 623 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 624 } 625 } 626 627 static void cntfrq_read_handler(unsigned long esr, struct pt_regs *regs) 628 { 629 if (test_thread_flag(TIF_TSC_SIGSEGV)) { 630 force_sig(SIGSEGV); 631 } else { 632 int rt = ESR_ELx_SYS64_ISS_RT(esr); 633 634 pt_regs_write_reg(regs, rt, arch_timer_get_rate()); 635 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 636 } 637 } 638 639 static void mrs_handler(unsigned long esr, struct pt_regs *regs) 640 { 641 u32 sysreg, rt; 642 643 rt = ESR_ELx_SYS64_ISS_RT(esr); 644 sysreg = esr_sys64_to_sysreg(esr); 645 646 if (do_emulate_mrs(regs, sysreg, rt) != 0) 647 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 648 } 649 650 static void wfi_handler(unsigned long esr, struct pt_regs *regs) 651 { 652 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 653 } 654 655 struct sys64_hook { 656 unsigned long esr_mask; 657 unsigned long esr_val; 658 void (*handler)(unsigned long esr, struct pt_regs *regs); 659 }; 660 661 static const struct sys64_hook sys64_hooks[] = { 662 { 663 .esr_mask = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK, 664 .esr_val = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL, 665 .handler = user_cache_maint_handler, 666 }, 667 { 668 /* Trap read access to CTR_EL0 */ 669 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 670 .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ, 671 .handler = ctr_read_handler, 672 }, 673 { 674 /* Trap read access to CNTVCT_EL0 */ 675 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 676 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT, 677 .handler = cntvct_read_handler, 678 }, 679 { 680 /* Trap read access to CNTVCTSS_EL0 */ 681 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 682 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCTSS, 683 .handler = cntvct_read_handler, 684 }, 685 { 686 /* Trap read access to CNTFRQ_EL0 */ 687 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, 688 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTFRQ, 689 .handler = cntfrq_read_handler, 690 }, 691 { 692 /* Trap read access to CPUID registers */ 693 .esr_mask = ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK, 694 .esr_val = ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL, 695 .handler = mrs_handler, 696 }, 697 { 698 /* Trap WFI instructions executed in userspace */ 699 .esr_mask = ESR_ELx_WFx_MASK, 700 .esr_val = ESR_ELx_WFx_WFI_VAL, 701 .handler = wfi_handler, 702 }, 703 {}, 704 }; 705 706 #ifdef CONFIG_COMPAT 707 static bool cp15_cond_valid(unsigned long esr, struct pt_regs *regs) 708 { 709 int cond; 710 711 /* Only a T32 instruction can trap without CV being set */ 712 if (!(esr & ESR_ELx_CV)) { 713 u32 it; 714 715 it = compat_get_it_state(regs); 716 if (!it) 717 return true; 718 719 cond = it >> 4; 720 } else { 721 cond = (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT; 722 } 723 724 return aarch32_opcode_cond_checks[cond](regs->pstate); 725 } 726 727 static void compat_cntfrq_read_handler(unsigned long esr, struct pt_regs *regs) 728 { 729 int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT; 730 731 pt_regs_write_reg(regs, reg, arch_timer_get_rate()); 732 arm64_skip_faulting_instruction(regs, 4); 733 } 734 735 static const struct sys64_hook cp15_32_hooks[] = { 736 { 737 .esr_mask = ESR_ELx_CP15_32_ISS_SYS_MASK, 738 .esr_val = ESR_ELx_CP15_32_ISS_SYS_CNTFRQ, 739 .handler = compat_cntfrq_read_handler, 740 }, 741 {}, 742 }; 743 744 static void compat_cntvct_read_handler(unsigned long esr, struct pt_regs *regs) 745 { 746 int rt = (esr & ESR_ELx_CP15_64_ISS_RT_MASK) >> ESR_ELx_CP15_64_ISS_RT_SHIFT; 747 int rt2 = (esr & ESR_ELx_CP15_64_ISS_RT2_MASK) >> ESR_ELx_CP15_64_ISS_RT2_SHIFT; 748 u64 val = arch_timer_read_counter(); 749 750 pt_regs_write_reg(regs, rt, lower_32_bits(val)); 751 pt_regs_write_reg(regs, rt2, upper_32_bits(val)); 752 arm64_skip_faulting_instruction(regs, 4); 753 } 754 755 static const struct sys64_hook cp15_64_hooks[] = { 756 { 757 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK, 758 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCT, 759 .handler = compat_cntvct_read_handler, 760 }, 761 { 762 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK, 763 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS, 764 .handler = compat_cntvct_read_handler, 765 }, 766 {}, 767 }; 768 769 void do_el0_cp15(unsigned long esr, struct pt_regs *regs) 770 { 771 const struct sys64_hook *hook, *hook_base; 772 773 if (!cp15_cond_valid(esr, regs)) { 774 /* 775 * There is no T16 variant of a CP access, so we 776 * always advance PC by 4 bytes. 777 */ 778 arm64_skip_faulting_instruction(regs, 4); 779 return; 780 } 781 782 switch (ESR_ELx_EC(esr)) { 783 case ESR_ELx_EC_CP15_32: 784 hook_base = cp15_32_hooks; 785 break; 786 case ESR_ELx_EC_CP15_64: 787 hook_base = cp15_64_hooks; 788 break; 789 default: 790 do_el0_undef(regs, esr); 791 return; 792 } 793 794 for (hook = hook_base; hook->handler; hook++) 795 if ((hook->esr_mask & esr) == hook->esr_val) { 796 hook->handler(esr, regs); 797 return; 798 } 799 800 /* 801 * New cp15 instructions may previously have been undefined at 802 * EL0. Fall back to our usual undefined instruction handler 803 * so that we handle these consistently. 804 */ 805 do_el0_undef(regs, esr); 806 } 807 #endif 808 809 void do_el0_sys(unsigned long esr, struct pt_regs *regs) 810 { 811 const struct sys64_hook *hook; 812 813 for (hook = sys64_hooks; hook->handler; hook++) 814 if ((hook->esr_mask & esr) == hook->esr_val) { 815 hook->handler(esr, regs); 816 return; 817 } 818 819 /* 820 * New SYS instructions may previously have been undefined at EL0. Fall 821 * back to our usual undefined instruction handler so that we handle 822 * these consistently. 823 */ 824 do_el0_undef(regs, esr); 825 } 826 827 static const char *esr_class_str[] = { 828 [0 ... ESR_ELx_EC_MAX] = "UNRECOGNIZED EC", 829 [ESR_ELx_EC_UNKNOWN] = "Unknown/Uncategorized", 830 [ESR_ELx_EC_WFx] = "WFI/WFE", 831 [ESR_ELx_EC_CP15_32] = "CP15 MCR/MRC", 832 [ESR_ELx_EC_CP15_64] = "CP15 MCRR/MRRC", 833 [ESR_ELx_EC_CP14_MR] = "CP14 MCR/MRC", 834 [ESR_ELx_EC_CP14_LS] = "CP14 LDC/STC", 835 [ESR_ELx_EC_FP_ASIMD] = "ASIMD", 836 [ESR_ELx_EC_CP10_ID] = "CP10 MRC/VMRS", 837 [ESR_ELx_EC_PAC] = "PAC", 838 [ESR_ELx_EC_CP14_64] = "CP14 MCRR/MRRC", 839 [ESR_ELx_EC_BTI] = "BTI", 840 [ESR_ELx_EC_ILL] = "PSTATE.IL", 841 [ESR_ELx_EC_SVC32] = "SVC (AArch32)", 842 [ESR_ELx_EC_HVC32] = "HVC (AArch32)", 843 [ESR_ELx_EC_SMC32] = "SMC (AArch32)", 844 [ESR_ELx_EC_SVC64] = "SVC (AArch64)", 845 [ESR_ELx_EC_HVC64] = "HVC (AArch64)", 846 [ESR_ELx_EC_SMC64] = "SMC (AArch64)", 847 [ESR_ELx_EC_SYS64] = "MSR/MRS (AArch64)", 848 [ESR_ELx_EC_SVE] = "SVE", 849 [ESR_ELx_EC_ERET] = "ERET/ERETAA/ERETAB", 850 [ESR_ELx_EC_FPAC] = "FPAC", 851 [ESR_ELx_EC_SME] = "SME", 852 [ESR_ELx_EC_IMP_DEF] = "EL3 IMP DEF", 853 [ESR_ELx_EC_IABT_LOW] = "IABT (lower EL)", 854 [ESR_ELx_EC_IABT_CUR] = "IABT (current EL)", 855 [ESR_ELx_EC_PC_ALIGN] = "PC Alignment", 856 [ESR_ELx_EC_DABT_LOW] = "DABT (lower EL)", 857 [ESR_ELx_EC_DABT_CUR] = "DABT (current EL)", 858 [ESR_ELx_EC_SP_ALIGN] = "SP Alignment", 859 [ESR_ELx_EC_MOPS] = "MOPS", 860 [ESR_ELx_EC_FP_EXC32] = "FP (AArch32)", 861 [ESR_ELx_EC_FP_EXC64] = "FP (AArch64)", 862 [ESR_ELx_EC_SERROR] = "SError", 863 [ESR_ELx_EC_BREAKPT_LOW] = "Breakpoint (lower EL)", 864 [ESR_ELx_EC_BREAKPT_CUR] = "Breakpoint (current EL)", 865 [ESR_ELx_EC_SOFTSTP_LOW] = "Software Step (lower EL)", 866 [ESR_ELx_EC_SOFTSTP_CUR] = "Software Step (current EL)", 867 [ESR_ELx_EC_WATCHPT_LOW] = "Watchpoint (lower EL)", 868 [ESR_ELx_EC_WATCHPT_CUR] = "Watchpoint (current EL)", 869 [ESR_ELx_EC_BKPT32] = "BKPT (AArch32)", 870 [ESR_ELx_EC_VECTOR32] = "Vector catch (AArch32)", 871 [ESR_ELx_EC_BRK64] = "BRK (AArch64)", 872 }; 873 874 const char *esr_get_class_string(unsigned long esr) 875 { 876 return esr_class_str[ESR_ELx_EC(esr)]; 877 } 878 879 /* 880 * bad_el0_sync handles unexpected, but potentially recoverable synchronous 881 * exceptions taken from EL0. 882 */ 883 void bad_el0_sync(struct pt_regs *regs, int reason, unsigned long esr) 884 { 885 unsigned long pc = instruction_pointer(regs); 886 887 current->thread.fault_address = 0; 888 current->thread.fault_code = esr; 889 890 arm64_force_sig_fault(SIGILL, ILL_ILLOPC, pc, 891 "Bad EL0 synchronous exception"); 892 } 893 894 #ifdef CONFIG_VMAP_STACK 895 896 DEFINE_PER_CPU(unsigned long [OVERFLOW_STACK_SIZE/sizeof(long)], overflow_stack) 897 __aligned(16); 898 899 void __noreturn panic_bad_stack(struct pt_regs *regs, unsigned long esr, unsigned long far) 900 { 901 unsigned long tsk_stk = (unsigned long)current->stack; 902 unsigned long irq_stk = (unsigned long)this_cpu_read(irq_stack_ptr); 903 unsigned long ovf_stk = (unsigned long)this_cpu_ptr(overflow_stack); 904 905 console_verbose(); 906 pr_emerg("Insufficient stack space to handle exception!"); 907 908 pr_emerg("ESR: 0x%016lx -- %s\n", esr, esr_get_class_string(esr)); 909 pr_emerg("FAR: 0x%016lx\n", far); 910 911 pr_emerg("Task stack: [0x%016lx..0x%016lx]\n", 912 tsk_stk, tsk_stk + THREAD_SIZE); 913 pr_emerg("IRQ stack: [0x%016lx..0x%016lx]\n", 914 irq_stk, irq_stk + IRQ_STACK_SIZE); 915 pr_emerg("Overflow stack: [0x%016lx..0x%016lx]\n", 916 ovf_stk, ovf_stk + OVERFLOW_STACK_SIZE); 917 918 __show_regs(regs); 919 920 /* 921 * We use nmi_panic to limit the potential for recusive overflows, and 922 * to get a better stack trace. 923 */ 924 nmi_panic(NULL, "kernel stack overflow"); 925 cpu_park_loop(); 926 } 927 #endif 928 929 void __noreturn arm64_serror_panic(struct pt_regs *regs, unsigned long esr) 930 { 931 console_verbose(); 932 933 pr_crit("SError Interrupt on CPU%d, code 0x%016lx -- %s\n", 934 smp_processor_id(), esr, esr_get_class_string(esr)); 935 if (regs) 936 __show_regs(regs); 937 938 nmi_panic(regs, "Asynchronous SError Interrupt"); 939 940 cpu_park_loop(); 941 } 942 943 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned long esr) 944 { 945 unsigned long aet = arm64_ras_serror_get_severity(esr); 946 947 switch (aet) { 948 case ESR_ELx_AET_CE: /* corrected error */ 949 case ESR_ELx_AET_UEO: /* restartable, not yet consumed */ 950 /* 951 * The CPU can make progress. We may take UEO again as 952 * a more severe error. 953 */ 954 return false; 955 956 case ESR_ELx_AET_UEU: /* Uncorrected Unrecoverable */ 957 case ESR_ELx_AET_UER: /* Uncorrected Recoverable */ 958 /* 959 * The CPU can't make progress. The exception may have 960 * been imprecise. 961 * 962 * Neoverse-N1 #1349291 means a non-KVM SError reported as 963 * Unrecoverable should be treated as Uncontainable. We 964 * call arm64_serror_panic() in both cases. 965 */ 966 return true; 967 968 case ESR_ELx_AET_UC: /* Uncontainable or Uncategorized error */ 969 default: 970 /* Error has been silently propagated */ 971 arm64_serror_panic(regs, esr); 972 } 973 } 974 975 void do_serror(struct pt_regs *regs, unsigned long esr) 976 { 977 /* non-RAS errors are not containable */ 978 if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(regs, esr)) 979 arm64_serror_panic(regs, esr); 980 } 981 982 /* GENERIC_BUG traps */ 983 #ifdef CONFIG_GENERIC_BUG 984 int is_valid_bugaddr(unsigned long addr) 985 { 986 /* 987 * bug_handler() only called for BRK #BUG_BRK_IMM. 988 * So the answer is trivial -- any spurious instances with no 989 * bug table entry will be rejected by report_bug() and passed 990 * back to the debug-monitors code and handled as a fatal 991 * unexpected debug exception. 992 */ 993 return 1; 994 } 995 #endif 996 997 static int bug_handler(struct pt_regs *regs, unsigned long esr) 998 { 999 switch (report_bug(regs->pc, regs)) { 1000 case BUG_TRAP_TYPE_BUG: 1001 die("Oops - BUG", regs, esr); 1002 break; 1003 1004 case BUG_TRAP_TYPE_WARN: 1005 break; 1006 1007 default: 1008 /* unknown/unrecognised bug trap type */ 1009 return DBG_HOOK_ERROR; 1010 } 1011 1012 /* If thread survives, skip over the BUG instruction and continue: */ 1013 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 1014 return DBG_HOOK_HANDLED; 1015 } 1016 1017 static struct break_hook bug_break_hook = { 1018 .fn = bug_handler, 1019 .imm = BUG_BRK_IMM, 1020 }; 1021 1022 #ifdef CONFIG_CFI_CLANG 1023 static int cfi_handler(struct pt_regs *regs, unsigned long esr) 1024 { 1025 unsigned long target; 1026 u32 type; 1027 1028 target = pt_regs_read_reg(regs, FIELD_GET(CFI_BRK_IMM_TARGET, esr)); 1029 type = (u32)pt_regs_read_reg(regs, FIELD_GET(CFI_BRK_IMM_TYPE, esr)); 1030 1031 switch (report_cfi_failure(regs, regs->pc, &target, type)) { 1032 case BUG_TRAP_TYPE_BUG: 1033 die("Oops - CFI", regs, esr); 1034 break; 1035 1036 case BUG_TRAP_TYPE_WARN: 1037 break; 1038 1039 default: 1040 return DBG_HOOK_ERROR; 1041 } 1042 1043 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 1044 return DBG_HOOK_HANDLED; 1045 } 1046 1047 static struct break_hook cfi_break_hook = { 1048 .fn = cfi_handler, 1049 .imm = CFI_BRK_IMM_BASE, 1050 .mask = CFI_BRK_IMM_MASK, 1051 }; 1052 #endif /* CONFIG_CFI_CLANG */ 1053 1054 static int reserved_fault_handler(struct pt_regs *regs, unsigned long esr) 1055 { 1056 pr_err("%s generated an invalid instruction at %pS!\n", 1057 "Kernel text patching", 1058 (void *)instruction_pointer(regs)); 1059 1060 /* We cannot handle this */ 1061 return DBG_HOOK_ERROR; 1062 } 1063 1064 static struct break_hook fault_break_hook = { 1065 .fn = reserved_fault_handler, 1066 .imm = FAULT_BRK_IMM, 1067 }; 1068 1069 #ifdef CONFIG_KASAN_SW_TAGS 1070 1071 #define KASAN_ESR_RECOVER 0x20 1072 #define KASAN_ESR_WRITE 0x10 1073 #define KASAN_ESR_SIZE_MASK 0x0f 1074 #define KASAN_ESR_SIZE(esr) (1 << ((esr) & KASAN_ESR_SIZE_MASK)) 1075 1076 static int kasan_handler(struct pt_regs *regs, unsigned long esr) 1077 { 1078 bool recover = esr & KASAN_ESR_RECOVER; 1079 bool write = esr & KASAN_ESR_WRITE; 1080 size_t size = KASAN_ESR_SIZE(esr); 1081 void *addr = (void *)regs->regs[0]; 1082 u64 pc = regs->pc; 1083 1084 kasan_report(addr, size, write, pc); 1085 1086 /* 1087 * The instrumentation allows to control whether we can proceed after 1088 * a crash was detected. This is done by passing the -recover flag to 1089 * the compiler. Disabling recovery allows to generate more compact 1090 * code. 1091 * 1092 * Unfortunately disabling recovery doesn't work for the kernel right 1093 * now. KASAN reporting is disabled in some contexts (for example when 1094 * the allocator accesses slab object metadata; this is controlled by 1095 * current->kasan_depth). All these accesses are detected by the tool, 1096 * even though the reports for them are not printed. 1097 * 1098 * This is something that might be fixed at some point in the future. 1099 */ 1100 if (!recover) 1101 die("Oops - KASAN", regs, esr); 1102 1103 /* If thread survives, skip over the brk instruction and continue: */ 1104 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 1105 return DBG_HOOK_HANDLED; 1106 } 1107 1108 static struct break_hook kasan_break_hook = { 1109 .fn = kasan_handler, 1110 .imm = KASAN_BRK_IMM, 1111 .mask = KASAN_BRK_MASK, 1112 }; 1113 #endif 1114 1115 #ifdef CONFIG_UBSAN_TRAP 1116 static int ubsan_handler(struct pt_regs *regs, unsigned long esr) 1117 { 1118 die(report_ubsan_failure(regs, esr & UBSAN_BRK_MASK), regs, esr); 1119 return DBG_HOOK_HANDLED; 1120 } 1121 1122 static struct break_hook ubsan_break_hook = { 1123 .fn = ubsan_handler, 1124 .imm = UBSAN_BRK_IMM, 1125 .mask = UBSAN_BRK_MASK, 1126 }; 1127 #endif 1128 1129 /* 1130 * Initial handler for AArch64 BRK exceptions 1131 * This handler only used until debug_traps_init(). 1132 */ 1133 int __init early_brk64(unsigned long addr, unsigned long esr, 1134 struct pt_regs *regs) 1135 { 1136 #ifdef CONFIG_CFI_CLANG 1137 if (esr_is_cfi_brk(esr)) 1138 return cfi_handler(regs, esr) != DBG_HOOK_HANDLED; 1139 #endif 1140 #ifdef CONFIG_KASAN_SW_TAGS 1141 if ((esr_brk_comment(esr) & ~KASAN_BRK_MASK) == KASAN_BRK_IMM) 1142 return kasan_handler(regs, esr) != DBG_HOOK_HANDLED; 1143 #endif 1144 #ifdef CONFIG_UBSAN_TRAP 1145 if ((esr_brk_comment(esr) & ~UBSAN_BRK_MASK) == UBSAN_BRK_IMM) 1146 return ubsan_handler(regs, esr) != DBG_HOOK_HANDLED; 1147 #endif 1148 return bug_handler(regs, esr) != DBG_HOOK_HANDLED; 1149 } 1150 1151 void __init trap_init(void) 1152 { 1153 register_kernel_break_hook(&bug_break_hook); 1154 #ifdef CONFIG_CFI_CLANG 1155 register_kernel_break_hook(&cfi_break_hook); 1156 #endif 1157 register_kernel_break_hook(&fault_break_hook); 1158 #ifdef CONFIG_KASAN_SW_TAGS 1159 register_kernel_break_hook(&kasan_break_hook); 1160 #endif 1161 #ifdef CONFIG_UBSAN_TRAP 1162 register_kernel_break_hook(&ubsan_break_hook); 1163 #endif 1164 debug_traps_init(); 1165 } 1166