1 /* 2 * (C) Copyright IBM Corporation 2006 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * IBM AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 */ 24 /* 25 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 26 * 27 * Permission is hereby granted, free of charge, to any person obtaining a 28 * copy of this software and associated documentation files (the 29 * "Software"), to deal in the Software without restriction, including 30 * without limitation the rights to use, copy, modify, merge, publish, 31 * distribute, and/or sell copies of the Software, and to permit persons 32 * to whom the Software is furnished to do so, provided that the above 33 * copyright notice(s) and this permission notice appear in all copies of 34 * the Software and that both the above copyright notice(s) and this 35 * permission notice appear in supporting documentation. 36 * 37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 38 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 39 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT 40 * OF THIRD PARTY RIGHTS. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 41 * HOLDERS INCLUDED IN THIS NOTICE BE LIABLE FOR ANY CLAIM, OR ANY SPECIAL 42 * INDIRECT OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING 43 * FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, 44 * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION 45 * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 46 * 47 * Except as contained in this notice, the name of a copyright holder 48 * shall not be used in advertising or otherwise to promote the sale, use 49 * or other dealings in this Software without prior written authorization 50 * of the copyright holder. 51 */ 52 /* 53 * Solaris devfs interfaces 54 */ 55 56 #include <stdlib.h> 57 #include <strings.h> 58 #include <stdio.h> 59 #include <unistd.h> 60 #include <sys/types.h> 61 #include <fcntl.h> 62 #include <sys/mman.h> 63 #include <errno.h> 64 #include <sys/pci.h> 65 #include <libdevinfo.h> 66 #include "pci_tools.h" 67 68 #include "pciaccess.h" 69 #include "pciaccess_private.h" 70 71 #define MAX_DEVICES 256 72 #define CELL_NUMS_1275 (sizeof(pci_regspec_t) / sizeof(uint_t)) 73 74 typedef union { 75 uint8_t bytes[16 * sizeof (uint32_t)]; 76 uint32_t dwords[16]; 77 } pci_conf_hdr_t; 78 79 typedef struct i_devnode { 80 uint8_t bus; 81 uint8_t dev; 82 uint8_t func; 83 di_node_t node; 84 } i_devnode_t; 85 86 typedef struct nexus { 87 int fd; 88 int domain; 89 struct nexus *next; 90 } nexus_t; 91 92 static nexus_t *nexus_list = NULL; 93 static int num_domains = 0; 94 static int xsvc_fd = -1; 95 96 /* 97 * Read config space in native processor endianness. Endian-neutral 98 * processing can then take place. On big endian machines, MSB and LSB 99 * of little endian data end up switched if read as little endian. 100 * They are in correct order if read as big endian. 101 */ 102 #if defined(__sparc) 103 # define NATIVE_ENDIAN PCITOOL_ACC_ATTR_ENDN_BIG 104 #elif defined(__x86) 105 # define NATIVE_ENDIAN PCITOOL_ACC_ATTR_ENDN_LTL 106 #else 107 # error "ISA is neither __sparc nor __x86" 108 #endif 109 110 /* 111 * Identify problematic southbridges. These have device id 0x5249 and 112 * vendor id 0x10b9. Check for revision ID 0 and class code 060400 as well. 113 * Values are little endian, so they are reversed for SPARC. 114 * 115 * Check for these southbridges on all architectures, as the issue is a 116 * southbridge issue, independent of processor. 117 * 118 * If one of these is found during probing, skip probing other devs/funcs on 119 * the rest of the bus, since the southbridge and all devs underneath will 120 * otherwise disappear. 121 */ 122 #if (NATIVE_ENDIAN == PCITOOL_ACC_ATTR_ENDN_BIG) 123 # define U45_SB_DEVID_VID 0xb9104952 124 # define U45_SB_CLASS_RID 0x00000406 125 #else 126 # define U45_SB_DEVID_VID 0x524910b9 127 # define U45_SB_CLASS_RID 0x06040000 128 #endif 129 130 #define DEBUGON 0 131 132 133 static int pci_device_solx_devfs_map_range(struct pci_device *dev, 134 struct pci_device_mapping *map); 135 136 static int pci_device_solx_devfs_read_rom( struct pci_device * dev, 137 void * buffer ); 138 139 static int pci_device_solx_devfs_probe( struct pci_device * dev ); 140 141 static int pci_device_solx_devfs_read( struct pci_device * dev, void * data, 142 pciaddr_t offset, pciaddr_t size, pciaddr_t * bytes_read ); 143 144 static int pci_device_solx_devfs_write( struct pci_device * dev, 145 const void * data, pciaddr_t offset, pciaddr_t size, 146 pciaddr_t * bytes_written ); 147 148 static int probe_dev(nexus_t *nexus, pcitool_reg_t *prg_p, 149 struct pci_system *pci_sys); 150 151 static int do_probe(nexus_t *nexus, struct pci_system *pci_sys); 152 153 static int probe_nexus_node(di_node_t di_node, di_minor_t minor, void *arg); 154 155 static void pci_system_solx_devfs_destroy( void ); 156 157 static int get_config_header(int fd, uint8_t bus_no, uint8_t dev_no, 158 uint8_t func_no, pci_conf_hdr_t *config_hdr_p); 159 160 int pci_system_solx_devfs_create( void ); 161 162 static const struct pci_system_methods solx_devfs_methods = { 163 .destroy = pci_system_solx_devfs_destroy, 164 .destroy_device = NULL, 165 .read_rom = pci_device_solx_devfs_read_rom, 166 .probe = pci_device_solx_devfs_probe, 167 .map_range = pci_device_solx_devfs_map_range, 168 .unmap_range = pci_device_generic_unmap_range, 169 170 .read = pci_device_solx_devfs_read, 171 .write = pci_device_solx_devfs_write, 172 173 .fill_capabilities = pci_fill_capabilities_generic 174 }; 175 176 static nexus_t * 177 find_nexus_for_domain( int domain ) 178 { 179 nexus_t *nexus; 180 181 for (nexus = nexus_list ; nexus != NULL ; nexus = nexus->next) { 182 if (nexus->domain == domain) { 183 return nexus; 184 } 185 } 186 return NULL; 187 } 188 189 #define GET_CONFIG_VAL_8(offset) (config_hdr.bytes[offset]) 190 #define GET_CONFIG_VAL_16(offset) \ 191 (uint16_t) (GET_CONFIG_VAL_8(offset) + (GET_CONFIG_VAL_8(offset+1) << 8)) 192 #define GET_CONFIG_VAL_32(offset) \ 193 (uint32_t) (GET_CONFIG_VAL_8(offset) + \ 194 (GET_CONFIG_VAL_8(offset+1) << 8) + \ 195 (GET_CONFIG_VAL_8(offset+2) << 16) + \ 196 (GET_CONFIG_VAL_8(offset+3) << 24)) 197 198 /* 199 * Release all the resources 200 * Solaris version 201 */ 202 static void 203 pci_system_solx_devfs_destroy( void ) 204 { 205 /* 206 * The memory allocated for pci_sys & devices in create routines 207 * will be freed in pci_system_cleanup. 208 * Need to free system-specific allocations here. 209 */ 210 nexus_t *nexus, *next; 211 212 for (nexus = nexus_list ; nexus != NULL ; nexus = next) { 213 next = nexus->next; 214 close(nexus->fd); 215 free(nexus); 216 } 217 nexus_list = NULL; 218 219 if (xsvc_fd >= 0) { 220 close(xsvc_fd); 221 xsvc_fd = -1; 222 } 223 } 224 225 /* 226 * Attempt to access PCI subsystem using Solaris's devfs interface. 227 * Solaris version 228 */ 229 _pci_hidden int 230 pci_system_solx_devfs_create( void ) 231 { 232 int err = 0; 233 di_node_t di_node; 234 235 236 if (nexus_list != NULL) { 237 return 0; 238 } 239 240 /* 241 * Only allow MAX_DEVICES exists 242 * I will fix it later to get 243 * the total devices first 244 */ 245 if ((pci_sys = calloc(1, sizeof (struct pci_system))) != NULL) { 246 pci_sys->methods = &solx_devfs_methods; 247 248 if ((pci_sys->devices = 249 calloc(MAX_DEVICES, sizeof (struct pci_device_private))) 250 != NULL) { 251 252 if ((di_node = di_init("/", DINFOCPYALL)) == DI_NODE_NIL) { 253 err = errno; 254 (void) fprintf(stderr, "di_init() failed: %s\n", 255 strerror(errno)); 256 } else { 257 (void) di_walk_minor(di_node, DDI_NT_REGACC, 0, pci_sys, 258 probe_nexus_node); 259 di_fini(di_node); 260 } 261 } 262 else { 263 err = errno; 264 } 265 } else { 266 err = errno; 267 } 268 269 if (err != 0) { 270 if (pci_sys != NULL) { 271 free(pci_sys->devices); 272 free(pci_sys); 273 pci_sys = NULL; 274 } 275 } 276 277 return (err); 278 } 279 280 /* 281 * Retrieve first 16 dwords of device's config header, except for the first 282 * dword. First 16 dwords are defined by the PCI specification. 283 */ 284 static int 285 get_config_header(int fd, uint8_t bus_no, uint8_t dev_no, uint8_t func_no, 286 pci_conf_hdr_t *config_hdr_p) 287 { 288 pcitool_reg_t cfg_prg; 289 int i; 290 int rval = 0; 291 292 /* Prepare a local pcitool_reg_t so as to not disturb the caller's. */ 293 cfg_prg.offset = 0; 294 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN; 295 cfg_prg.bus_no = bus_no; 296 cfg_prg.dev_no = dev_no; 297 cfg_prg.func_no = func_no; 298 cfg_prg.barnum = 0; 299 cfg_prg.user_version = PCITOOL_USER_VERSION; 300 301 /* Get dwords 1-15 of config space. They must be read as uint32_t. */ 302 for (i = 1; i < (sizeof (pci_conf_hdr_t) / sizeof (uint32_t)); i++) { 303 cfg_prg.offset += sizeof (uint32_t); 304 if ((rval = ioctl(fd, PCITOOL_DEVICE_GET_REG, &cfg_prg)) != 0) { 305 break; 306 } 307 config_hdr_p->dwords[i] = (uint32_t)cfg_prg.data; 308 } 309 310 return (rval); 311 } 312 313 314 /* 315 * Probe device's functions. Modifies many fields in the prg_p. 316 */ 317 static int 318 probe_dev(nexus_t *nexus, pcitool_reg_t *prg_p, struct pci_system *pci_sys) 319 { 320 pci_conf_hdr_t config_hdr; 321 boolean_t multi_function_device; 322 int8_t func; 323 int8_t first_func = 0; 324 int8_t last_func = PCI_REG_FUNC_M >> PCI_REG_FUNC_SHIFT; 325 int rval = 0; 326 struct pci_device * pci_base; 327 328 /* 329 * Loop through at least func=first_func. Continue looping through 330 * functions if there are no errors and the device is a multi-function 331 * device. 332 * 333 * (Note, if first_func == 0, header will show whether multifunction 334 * device and set multi_function_device. If first_func != 0, then we 335 * will force the loop as the user wants a specific function to be 336 * checked. 337 */ 338 for (func = first_func, multi_function_device = B_FALSE; 339 ((func <= last_func) && 340 ((func == first_func) || (multi_function_device))); 341 func++) { 342 prg_p->func_no = func; 343 344 /* 345 * Four things can happen here: 346 * 347 * 1) ioctl comes back as EFAULT and prg_p->status is 348 * PCITOOL_INVALID_ADDRESS. There is no device at this location. 349 * 350 * 2) ioctl comes back successful and the data comes back as 351 * zero. Config space is mapped but no device responded. 352 * 353 * 3) ioctl comes back successful and the data comes back as 354 * non-zero. We've found a device. 355 * 356 * 4) Some other error occurs in an ioctl. 357 */ 358 359 prg_p->status = PCITOOL_SUCCESS; 360 prg_p->offset = 0; 361 prg_p->data = 0; 362 prg_p->user_version = PCITOOL_USER_VERSION; 363 364 errno = 0; 365 if (((rval = ioctl(nexus->fd, PCITOOL_DEVICE_GET_REG, prg_p)) != 0) || 366 (prg_p->data == 0xffffffff)) { 367 368 /* 369 * Accept errno == EINVAL along with status of 370 * PCITOOL_OUT_OF_RANGE because some systems 371 * don't implement the full range of config space. 372 * Leave the loop quietly in this case. 373 */ 374 if ((errno == EINVAL) || 375 (prg_p->status == PCITOOL_OUT_OF_RANGE)) { 376 break; 377 } 378 379 /* 380 * Exit silently with ENXIO as this means that there are 381 * no devices under the pci root nexus. 382 */ 383 else if ((errno == ENXIO) && 384 (prg_p->status == PCITOOL_IO_ERROR)) { 385 break; 386 } 387 388 /* 389 * Expect errno == EFAULT along with status of 390 * PCITOOL_INVALID_ADDRESS because there won't be 391 * devices at each stop. Quit on any other error. 392 */ 393 else if (((errno != EFAULT) || 394 (prg_p->status != PCITOOL_INVALID_ADDRESS)) && 395 (prg_p->data != 0xffffffff)) { 396 break; 397 } 398 399 /* 400 * If no function at this location, 401 * just advance to the next function. 402 */ 403 else { 404 rval = 0; 405 } 406 407 /* 408 * Data came back as 0. 409 * Treat as unresponsive device and check next device. 410 */ 411 } else if (prg_p->data == 0) { 412 rval = 0; 413 break; /* Func loop. */ 414 415 /* Found something. */ 416 } else { 417 config_hdr.dwords[0] = (uint32_t)prg_p->data; 418 419 /* Get the rest of the PCI header. */ 420 if ((rval = get_config_header(nexus->fd, prg_p->bus_no, 421 prg_p->dev_no, prg_p->func_no, 422 &config_hdr)) != 0) { 423 break; 424 } 425 426 /* 427 * Special case for the type of Southbridge found on 428 * Ultra-45 and other sun4u fire workstations. 429 */ 430 if ((config_hdr.dwords[0] == U45_SB_DEVID_VID) && 431 (config_hdr.dwords[2] == U45_SB_CLASS_RID)) { 432 rval = ECANCELED; 433 break; 434 } 435 436 /* 437 * Found one device with bus number, device number and 438 * function number. 439 */ 440 441 pci_base = &pci_sys->devices[pci_sys->num_devices].base; 442 443 /* 444 * Domain is peer bus?? 445 */ 446 pci_base->domain = nexus->domain; 447 pci_base->bus = prg_p->bus_no; 448 pci_base->dev = prg_p->dev_no; 449 pci_base->func = func; 450 451 /* 452 * for the format of device_class, see struct pci_device; 453 */ 454 455 pci_base->device_class = 456 (GET_CONFIG_VAL_8(PCI_CONF_BASCLASS) << 16) | 457 (GET_CONFIG_VAL_8(PCI_CONF_SUBCLASS) << 8) | 458 GET_CONFIG_VAL_8(PCI_CONF_PROGCLASS); 459 460 pci_base->revision = GET_CONFIG_VAL_8(PCI_CONF_REVID); 461 pci_base->vendor_id = GET_CONFIG_VAL_16(PCI_CONF_VENID); 462 pci_base->device_id = GET_CONFIG_VAL_16(PCI_CONF_DEVID); 463 pci_base->subvendor_id = GET_CONFIG_VAL_16(PCI_CONF_SUBVENID); 464 pci_base->subdevice_id = GET_CONFIG_VAL_16(PCI_CONF_SUBSYSID); 465 466 pci_sys->devices[pci_sys->num_devices].header_type 467 = GET_CONFIG_VAL_8(PCI_CONF_HEADER); 468 469 #if DEBUGON 470 fprintf(stderr, "busno = %x, devno = %x, funcno = %x\n", 471 prg_p->bus_no, prg_p->dev_no, func); 472 #endif 473 474 pci_sys->num_devices++; 475 476 /* 477 * Accommodate devices which state their 478 * multi-functionality only in their function 0 config 479 * space. Note multi-functionality throughout probing 480 * of all of this device's functions. 481 */ 482 if (config_hdr.bytes[PCI_CONF_HEADER] & PCI_HEADER_MULTI) { 483 multi_function_device = B_TRUE; 484 } 485 } 486 } 487 488 return (rval); 489 } 490 491 /* 492 * This function is called from di_walk_minor() when any PROBE is processed 493 */ 494 static int 495 probe_nexus_node(di_node_t di_node, di_minor_t minor, void *arg) 496 { 497 struct pci_system *pci_sys = (struct pci_system *) arg; 498 char *nexus_name; 499 nexus_t *nexus; 500 int fd; 501 char nexus_path[MAXPATHLEN]; 502 503 nexus = calloc(1, sizeof(nexus_t)); 504 if (nexus == NULL) { 505 (void) fprintf(stderr, "Error allocating memory for nexus: %s\n", 506 strerror(errno)); 507 return DI_WALK_TERMINATE; 508 } 509 510 nexus_name = di_devfs_minor_path(minor); 511 if (nexus_name == NULL) { 512 (void) fprintf(stderr, "Error getting nexus path: %s\n", 513 strerror(errno)); 514 free(nexus); 515 return (DI_WALK_CONTINUE); 516 } 517 518 snprintf(nexus_path, sizeof(nexus_path), "/devices%s", nexus_name); 519 di_devfs_path_free(nexus_name); 520 521 if ((fd = open(nexus_path, O_RDWR)) >= 0) { 522 nexus->fd = fd; 523 nexus->domain = num_domains++; 524 if ((do_probe(nexus, pci_sys) != 0) && (errno != ENXIO)) { 525 (void) fprintf(stderr, "Error probing node %s: %s\n", 526 nexus_path, strerror(errno)); 527 (void) close(fd); 528 free(nexus); 529 } else { 530 nexus->next = nexus_list; 531 nexus_list = nexus; 532 } 533 } else { 534 (void) fprintf(stderr, "Error opening %s: %s\n", 535 nexus_path, strerror(errno)); 536 free(nexus); 537 } 538 539 return DI_WALK_CONTINUE; 540 } 541 542 543 /* 544 * Solaris version 545 * Probe a given nexus config space for devices. 546 * 547 * fd is the file descriptor of the nexus. 548 * input_args contains commandline options as specified by the user. 549 */ 550 static int 551 do_probe(nexus_t *nexus, struct pci_system *pci_sys) 552 { 553 pcitool_reg_t prg; 554 uint32_t bus; 555 uint8_t dev; 556 uint32_t last_bus = PCI_REG_BUS_M >> PCI_REG_BUS_SHIFT; 557 uint8_t last_dev = PCI_REG_DEV_M >> PCI_REG_DEV_SHIFT; 558 uint8_t first_bus = 0; 559 uint8_t first_dev = 0; 560 int rval = 0; 561 562 prg.barnum = 0; /* Config space. */ 563 564 /* Must read in 4-byte quantities. */ 565 prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN; 566 567 prg.data = 0; 568 569 /* 570 * Loop through all valid bus / dev / func combinations to check for 571 * all devices, with the following exceptions: 572 * 573 * When nothing is found at function 0 of a bus / dev combination, skip 574 * the other functions of that bus / dev combination. 575 * 576 * When a found device's function 0 is probed and it is determined that 577 * it is not a multifunction device, skip probing of that device's 578 * other functions. 579 */ 580 for (bus = first_bus; ((bus <= last_bus) && (rval == 0)); bus++) { 581 prg.bus_no = (uint8_t)bus; 582 583 for (dev = first_dev; ((dev <= last_dev) && (rval == 0)); dev++) { 584 prg.dev_no = dev; 585 rval = probe_dev(nexus, &prg, pci_sys); 586 } 587 588 /* 589 * Ultra-45 southbridge workaround: 590 * ECANCELED tells to skip to the next bus. 591 */ 592 if (rval == ECANCELED) { 593 rval = 0; 594 } 595 } 596 if (pci_sys->num_devices > MAX_DEVICES) { 597 (void) fprintf(stderr, "pci devices reach maximum number\n"); 598 } 599 600 return (rval); 601 } 602 603 static int 604 find_target_node(di_node_t node, void *arg) 605 { 606 int *regbuf = NULL; 607 int len = 0; 608 uint32_t busno, funcno, devno; 609 i_devnode_t *devnode; 610 void *prop = DI_PROP_NIL; 611 int i; 612 613 devnode = (i_devnode_t *)arg; 614 615 /* 616 * Test the property functions, only for testing 617 */ 618 /* 619 (void) fprintf(stderr, "start of node 0x%x\n", node->nodeid); 620 while ((prop = di_prop_hw_next(node, prop)) != DI_PROP_NIL) { 621 (void) fprintf(stderr, "name=%s: ", di_prop_name(prop)); 622 len = 0; 623 if (!strcmp(di_prop_name(prop), "reg")) { 624 len = di_prop_ints(prop, ®buf); 625 } 626 for (i = 0; i < len; i++) { 627 fprintf(stderr, "0x%0x.", regbuf[i]); 628 } 629 fprintf(stderr, "\n"); 630 } 631 (void) fprintf(stderr, "end of node 0x%x\n", node->nodeid); 632 */ 633 634 len = di_prop_lookup_ints(DDI_DEV_T_ANY, node, "reg", ®buf); 635 636 if (len <= 0) { 637 #if DEBUGON 638 fprintf(stderr, "error = %x\n", errno); 639 fprintf(stderr, "can not find assigned-address\n"); 640 #endif 641 return (DI_WALK_CONTINUE); 642 } 643 644 busno = PCI_REG_BUS_G(regbuf[0]); 645 devno = PCI_REG_DEV_G(regbuf[0]); 646 funcno = PCI_REG_FUNC_G(regbuf[0]); 647 648 if ((busno == devnode->bus) && 649 (devno == devnode->dev) && 650 (funcno == devnode->func)) { 651 devnode->node = node; 652 653 return (DI_WALK_TERMINATE); 654 } 655 656 return (DI_WALK_CONTINUE); 657 } 658 659 /* 660 * Solaris version 661 */ 662 static int 663 pci_device_solx_devfs_probe( struct pci_device * dev ) 664 { 665 uint8_t config[256]; 666 int err; 667 di_node_t rnode; 668 i_devnode_t args; 669 int *regbuf; 670 pci_regspec_t *reg; 671 int i; 672 pciaddr_t bytes; 673 int len = 0; 674 675 err = pci_device_solx_devfs_read( dev, config, 0, 256, & bytes ); 676 args.node = DI_NODE_NIL; 677 678 if ( bytes >= 64 ) { 679 struct pci_device_private *priv = 680 (struct pci_device_private *) dev; 681 682 dev->vendor_id = (uint16_t)config[0] + ((uint16_t)config[1] << 8); 683 dev->device_id = (uint16_t)config[2] + ((uint16_t)config[3] << 8); 684 dev->device_class = (uint32_t)config[9] + 685 ((uint32_t)config[10] << 8) + 686 ((uint16_t)config[11] << 16); 687 688 /* 689 * device class code is already there. 690 * see probe_dev function. 691 */ 692 dev->revision = config[8]; 693 dev->subvendor_id = (uint16_t)config[44] + ((uint16_t)config[45] << 8); 694 dev->subdevice_id = (uint16_t)config[46] + ((uint16_t)config[47] << 8); 695 dev->irq = config[60]; 696 697 priv->header_type = config[14]; 698 /* 699 * starting to find if it is MEM/MEM64/IO 700 * using libdevinfo 701 */ 702 if ((rnode = di_init("/", DINFOCPYALL)) == DI_NODE_NIL) { 703 err = errno; 704 (void) fprintf(stderr, "di_init failed: %s\n", strerror(errno)); 705 } else { 706 args.bus = dev->bus; 707 args.dev = dev->dev; 708 args.func = dev->func; 709 (void) di_walk_node(rnode, DI_WALK_CLDFIRST, 710 (void *)&args, find_target_node); 711 di_fini(rnode); 712 } 713 } 714 if (args.node != DI_NODE_NIL) { 715 /* 716 * It will succeed for sure, because it was 717 * successfully called in find_target_node 718 */ 719 len = di_prop_lookup_ints(DDI_DEV_T_ANY, args.node, 720 "assigned-addresses", 721 ®buf); 722 723 } 724 725 if (len <= 0) 726 return (err); 727 728 729 /* 730 * how to find the size of rom??? 731 * if the device has expansion rom, 732 * it must be listed in the last 733 * cells because solaris find probe 734 * the base address from offset 0x10 735 * to 0x30h. So only check the last 736 * item. 737 */ 738 reg = (pci_regspec_t *)®buf[len - CELL_NUMS_1275]; 739 if (PCI_REG_REG_G(reg->pci_phys_hi) == PCI_CONF_ROM) { 740 /* 741 * rom can only be 32 bits 742 */ 743 dev->rom_size = reg->pci_size_low; 744 len = len - CELL_NUMS_1275; 745 } 746 else { 747 /* 748 * size default to 64K and base address 749 * default to 0xC0000 750 */ 751 dev->rom_size = 0x10000; 752 } 753 754 /* 755 * solaris has its own BAR index. To be sure that 756 * Xorg has the same BAR number as solaris. ???? 757 */ 758 for (i = 0; i < len; i = i + CELL_NUMS_1275) { 759 int ent = i/CELL_NUMS_1275; 760 761 reg = (pci_regspec_t *)®buf[i]; 762 763 /* 764 * non relocatable resource is excluded 765 * such like 0xa0000, 0x3b0. If it is met, 766 * the loop is broken; 767 */ 768 if (!PCI_REG_REG_G(reg->pci_phys_hi)) 769 break; 770 771 if (reg->pci_phys_hi & PCI_PREFETCH_B) { 772 dev->regions[ent].is_prefetchable = 1; 773 } 774 775 switch (reg->pci_phys_hi & PCI_REG_ADDR_M) { 776 case PCI_ADDR_IO: 777 dev->regions[ent].is_IO = 1; 778 break; 779 case PCI_ADDR_MEM32: 780 break; 781 case PCI_ADDR_MEM64: 782 dev->regions[ent].is_64 = 1; 783 break; 784 } 785 786 /* 787 * We split the shift count 32 into two 16 to 788 * avoid the complaining of the compiler 789 */ 790 dev->regions[ent].base_addr = reg->pci_phys_low + 791 ((reg->pci_phys_mid << 16) << 16); 792 dev->regions[ent].size = reg->pci_size_low + 793 ((reg->pci_size_hi << 16) << 16); 794 } 795 796 return (err); 797 } 798 799 /* 800 * Solaris version: read the VGA ROM data 801 */ 802 static int 803 pci_device_solx_devfs_read_rom( struct pci_device * dev, void * buffer ) 804 { 805 int err; 806 struct pci_device_mapping prom = { 807 .base = 0xC0000, 808 .size = dev->rom_size, 809 .flags = 0 810 }; 811 812 err = pci_device_solx_devfs_map_range(dev, &prom); 813 if (err == 0) { 814 (void) bcopy(prom.memory, buffer, dev->rom_size); 815 816 if (munmap(prom.memory, dev->rom_size) == -1) { 817 err = errno; 818 } 819 } 820 return err; 821 } 822 823 /* 824 * solaris version: Read the configurations space of the devices 825 */ 826 static int 827 pci_device_solx_devfs_read( struct pci_device * dev, void * data, 828 pciaddr_t offset, pciaddr_t size, 829 pciaddr_t * bytes_read ) 830 { 831 pcitool_reg_t cfg_prg; 832 int err = 0; 833 int i = 0; 834 nexus_t *nexus = find_nexus_for_domain(dev->domain); 835 836 *bytes_read = 0; 837 838 if ( nexus == NULL ) { 839 return ENODEV; 840 } 841 842 cfg_prg.offset = offset; 843 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_1 + NATIVE_ENDIAN; 844 cfg_prg.bus_no = dev->bus; 845 cfg_prg.dev_no = dev->dev; 846 cfg_prg.func_no = dev->func; 847 cfg_prg.barnum = 0; 848 cfg_prg.user_version = PCITOOL_USER_VERSION; 849 850 for (i = 0; i < size; i += PCITOOL_ACC_ATTR_SIZE(PCITOOL_ACC_ATTR_SIZE_1)) 851 { 852 cfg_prg.offset = offset + i; 853 854 if ((err = ioctl(nexus->fd, PCITOOL_DEVICE_GET_REG, &cfg_prg)) != 0) { 855 fprintf(stderr, "read bdf<%x,%x,%x,%llx> config space failure\n", 856 cfg_prg.bus_no, 857 cfg_prg.dev_no, 858 cfg_prg.func_no, 859 cfg_prg.offset); 860 fprintf(stderr, "Failure cause = %x\n", err); 861 break; 862 } 863 864 ((uint8_t *)data)[i] = (uint8_t)cfg_prg.data; 865 /* 866 * DWORDS Offset or bytes Offset ?? 867 */ 868 } 869 *bytes_read = i; 870 871 return (err); 872 } 873 874 /* 875 * Solaris version 876 */ 877 static int 878 pci_device_solx_devfs_write( struct pci_device * dev, const void * data, 879 pciaddr_t offset, pciaddr_t size, 880 pciaddr_t * bytes_written ) 881 { 882 pcitool_reg_t cfg_prg; 883 int err = 0; 884 int cmd; 885 nexus_t *nexus = find_nexus_for_domain(dev->domain); 886 887 if ( bytes_written != NULL ) { 888 *bytes_written = 0; 889 } 890 891 if ( nexus == NULL ) { 892 return ENODEV; 893 } 894 895 cfg_prg.offset = offset; 896 switch (size) { 897 case 1: 898 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_1 + NATIVE_ENDIAN; 899 break; 900 case 2: 901 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_2 + NATIVE_ENDIAN; 902 break; 903 case 4: 904 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN; 905 break; 906 case 8: 907 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_8 + NATIVE_ENDIAN; 908 break; 909 default: 910 return EINVAL; 911 } 912 cfg_prg.bus_no = dev->bus; 913 cfg_prg.dev_no = dev->dev; 914 cfg_prg.func_no = dev->func; 915 cfg_prg.barnum = 0; 916 cfg_prg.user_version = PCITOOL_USER_VERSION; 917 cfg_prg.data = *((uint64_t *)data); 918 919 /* 920 * Check if this device is bridge device. 921 * If it is, it is also a nexus node??? 922 * It seems that there is no explicit 923 * PCI nexus device for X86, so not applicable 924 * from pcitool_bus_reg_ops in pci_tools.c 925 */ 926 cmd = PCITOOL_DEVICE_SET_REG; 927 928 if ((err = ioctl(nexus->fd, cmd, &cfg_prg)) != 0) { 929 return (err); 930 } 931 *bytes_written = size; 932 933 return (err); 934 } 935 936 937 /** 938 * Map a memory region for a device using /dev/xsvc. 939 * 940 * \param dev Device whose memory region is to be mapped. 941 * \param map Parameters of the mapping that is to be created. 942 * 943 * \return 944 * Zero on success or an \c errno value on failure. 945 */ 946 static int 947 pci_device_solx_devfs_map_range(struct pci_device *dev, 948 struct pci_device_mapping *map) 949 { 950 const int prot = ((map->flags & PCI_DEV_MAP_FLAG_WRITABLE) != 0) 951 ? (PROT_READ | PROT_WRITE) : PROT_READ; 952 int err = 0; 953 954 /* 955 * Still used xsvc to do the user space mapping 956 */ 957 if (xsvc_fd < 0) { 958 if ((xsvc_fd = open("/dev/xsvc", O_RDWR)) < 0) { 959 err = errno; 960 (void) fprintf(stderr, "can not open /dev/xsvc: %s\n", 961 strerror(errno)); 962 return err; 963 } 964 } 965 966 map->memory = mmap(NULL, map->size, prot, MAP_SHARED, xsvc_fd, map->base); 967 if (map->memory == MAP_FAILED) { 968 err = errno; 969 970 (void) fprintf(stderr, "map rom region =%llx failed: %s\n", 971 map->base, strerror(errno)); 972 } 973 974 return err; 975 } 976