1 /* 2 * (C) Copyright IBM Corporation 2006 3 * Copyright 2007, 2009 Sun Microsystems, Inc. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * on the rights to use, copy, modify, merge, publish, distribute, sub 10 * license, and/or sell copies of the Software, and to permit persons to whom 11 * the Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 20 * IBM AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 */ 25 /* 26 * Solaris devfs interfaces 27 */ 28 29 #include <stdlib.h> 30 #include <strings.h> 31 #include <stdio.h> 32 #include <unistd.h> 33 #include <sys/types.h> 34 #include <fcntl.h> 35 #include <sys/mman.h> 36 #include <errno.h> 37 #include <sys/pci.h> 38 #include <libdevinfo.h> 39 #include "pci_tools.h" 40 41 #include "pciaccess.h" 42 #include "pciaccess_private.h" 43 44 /* #define DEBUG */ 45 46 #define MAX_DEVICES 256 47 #define CELL_NUMS_1275 (sizeof(pci_regspec_t) / sizeof(uint_t)) 48 49 typedef union { 50 uint8_t bytes[16 * sizeof (uint32_t)]; 51 uint32_t dwords[16]; 52 } pci_conf_hdr_t; 53 54 typedef struct i_devnode { 55 uint8_t bus; 56 uint8_t dev; 57 uint8_t func; 58 di_node_t node; 59 } i_devnode_t; 60 61 typedef struct nexus { 62 int fd; 63 int first_bus; 64 int last_bus; 65 char *path; /* for errors/debugging; fd is all we need */ 66 struct nexus *next; 67 } nexus_t; 68 69 static nexus_t *nexus_list = NULL; 70 static int xsvc_fd = -1; 71 72 /* 73 * Read config space in native processor endianness. Endian-neutral 74 * processing can then take place. On big endian machines, MSB and LSB 75 * of little endian data end up switched if read as little endian. 76 * They are in correct order if read as big endian. 77 */ 78 #if defined(__sparc) 79 # define NATIVE_ENDIAN PCITOOL_ACC_ATTR_ENDN_BIG 80 #elif defined(__x86) 81 # define NATIVE_ENDIAN PCITOOL_ACC_ATTR_ENDN_LTL 82 #else 83 # error "ISA is neither __sparc nor __x86" 84 #endif 85 86 /* 87 * Identify problematic southbridges. These have device id 0x5249 and 88 * vendor id 0x10b9. Check for revision ID 0 and class code 060400 as well. 89 * Values are little endian, so they are reversed for SPARC. 90 * 91 * Check for these southbridges on all architectures, as the issue is a 92 * southbridge issue, independent of processor. 93 * 94 * If one of these is found during probing, skip probing other devs/funcs on 95 * the rest of the bus, since the southbridge and all devs underneath will 96 * otherwise disappear. 97 */ 98 #if (NATIVE_ENDIAN == PCITOOL_ACC_ATTR_ENDN_BIG) 99 # define U45_SB_DEVID_VID 0xb9104952 100 # define U45_SB_CLASS_RID 0x00000406 101 #else 102 # define U45_SB_DEVID_VID 0x524910b9 103 # define U45_SB_CLASS_RID 0x06040000 104 #endif 105 106 static int pci_device_solx_devfs_map_range(struct pci_device *dev, 107 struct pci_device_mapping *map); 108 109 static int pci_device_solx_devfs_read_rom( struct pci_device * dev, 110 void * buffer ); 111 112 static int pci_device_solx_devfs_probe( struct pci_device * dev ); 113 114 static int pci_device_solx_devfs_read( struct pci_device * dev, void * data, 115 pciaddr_t offset, pciaddr_t size, pciaddr_t * bytes_read ); 116 117 static int pci_device_solx_devfs_write( struct pci_device * dev, 118 const void * data, pciaddr_t offset, pciaddr_t size, 119 pciaddr_t * bytes_written ); 120 121 static int probe_dev(nexus_t *nexus, pcitool_reg_t *prg_p, 122 struct pci_system *pci_sys); 123 124 static int do_probe(nexus_t *nexus, struct pci_system *pci_sys); 125 126 static int probe_nexus_node(di_node_t di_node, di_minor_t minor, void *arg); 127 128 static void pci_system_solx_devfs_destroy( void ); 129 130 static int get_config_header(int fd, uint8_t bus_no, uint8_t dev_no, 131 uint8_t func_no, pci_conf_hdr_t *config_hdr_p); 132 133 int pci_system_solx_devfs_create( void ); 134 135 static const struct pci_system_methods solx_devfs_methods = { 136 .destroy = pci_system_solx_devfs_destroy, 137 .destroy_device = NULL, 138 .read_rom = pci_device_solx_devfs_read_rom, 139 .probe = pci_device_solx_devfs_probe, 140 .map_range = pci_device_solx_devfs_map_range, 141 .unmap_range = pci_device_generic_unmap_range, 142 143 .read = pci_device_solx_devfs_read, 144 .write = pci_device_solx_devfs_write, 145 146 .fill_capabilities = pci_fill_capabilities_generic 147 }; 148 149 static nexus_t * 150 find_nexus_for_bus( int bus ) 151 { 152 nexus_t *nexus; 153 154 for (nexus = nexus_list ; nexus != NULL ; nexus = nexus->next) { 155 if ((bus >= nexus->first_bus) && (bus <= nexus->last_bus)) { 156 return nexus; 157 } 158 } 159 return NULL; 160 } 161 162 #define GET_CONFIG_VAL_8(offset) (config_hdr.bytes[offset]) 163 #define GET_CONFIG_VAL_16(offset) \ 164 (uint16_t) (GET_CONFIG_VAL_8(offset) + (GET_CONFIG_VAL_8(offset+1) << 8)) 165 #define GET_CONFIG_VAL_32(offset) \ 166 (uint32_t) (GET_CONFIG_VAL_8(offset) + \ 167 (GET_CONFIG_VAL_8(offset+1) << 8) + \ 168 (GET_CONFIG_VAL_8(offset+2) << 16) + \ 169 (GET_CONFIG_VAL_8(offset+3) << 24)) 170 171 /* 172 * Release all the resources 173 * Solaris version 174 */ 175 static void 176 pci_system_solx_devfs_destroy( void ) 177 { 178 /* 179 * The memory allocated for pci_sys & devices in create routines 180 * will be freed in pci_system_cleanup. 181 * Need to free system-specific allocations here. 182 */ 183 nexus_t *nexus, *next; 184 185 for (nexus = nexus_list ; nexus != NULL ; nexus = next) { 186 next = nexus->next; 187 close(nexus->fd); 188 free(nexus->path); 189 free(nexus); 190 } 191 nexus_list = NULL; 192 193 if (xsvc_fd >= 0) { 194 close(xsvc_fd); 195 xsvc_fd = -1; 196 } 197 } 198 199 /* 200 * Attempt to access PCI subsystem using Solaris's devfs interface. 201 * Solaris version 202 */ 203 _pci_hidden int 204 pci_system_solx_devfs_create( void ) 205 { 206 int err = 0; 207 di_node_t di_node; 208 209 210 if (nexus_list != NULL) { 211 return 0; 212 } 213 214 /* 215 * Only allow MAX_DEVICES exists 216 * I will fix it later to get 217 * the total devices first 218 */ 219 if ((pci_sys = calloc(1, sizeof (struct pci_system))) != NULL) { 220 pci_sys->methods = &solx_devfs_methods; 221 222 if ((pci_sys->devices = 223 calloc(MAX_DEVICES, sizeof (struct pci_device_private))) 224 != NULL) { 225 226 if ((di_node = di_init("/", DINFOCPYALL)) == DI_NODE_NIL) { 227 err = errno; 228 (void) fprintf(stderr, "di_init() failed: %s\n", 229 strerror(errno)); 230 } else { 231 (void) di_walk_minor(di_node, DDI_NT_REGACC, 0, pci_sys, 232 probe_nexus_node); 233 di_fini(di_node); 234 } 235 } 236 else { 237 err = errno; 238 } 239 } else { 240 err = errno; 241 } 242 243 if (err != 0) { 244 if (pci_sys != NULL) { 245 free(pci_sys->devices); 246 free(pci_sys); 247 pci_sys = NULL; 248 } 249 } 250 251 return (err); 252 } 253 254 /* 255 * Retrieve first 16 dwords of device's config header, except for the first 256 * dword. First 16 dwords are defined by the PCI specification. 257 */ 258 static int 259 get_config_header(int fd, uint8_t bus_no, uint8_t dev_no, uint8_t func_no, 260 pci_conf_hdr_t *config_hdr_p) 261 { 262 pcitool_reg_t cfg_prg; 263 int i; 264 int rval = 0; 265 266 /* Prepare a local pcitool_reg_t so as to not disturb the caller's. */ 267 cfg_prg.offset = 0; 268 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN; 269 cfg_prg.bus_no = bus_no; 270 cfg_prg.dev_no = dev_no; 271 cfg_prg.func_no = func_no; 272 cfg_prg.barnum = 0; 273 cfg_prg.user_version = PCITOOL_USER_VERSION; 274 275 /* Get dwords 1-15 of config space. They must be read as uint32_t. */ 276 for (i = 1; i < (sizeof (pci_conf_hdr_t) / sizeof (uint32_t)); i++) { 277 cfg_prg.offset += sizeof (uint32_t); 278 if ((rval = ioctl(fd, PCITOOL_DEVICE_GET_REG, &cfg_prg)) != 0) { 279 break; 280 } 281 config_hdr_p->dwords[i] = (uint32_t)cfg_prg.data; 282 } 283 284 return (rval); 285 } 286 287 288 /* 289 * Probe device's functions. Modifies many fields in the prg_p. 290 */ 291 static int 292 probe_dev(nexus_t *nexus, pcitool_reg_t *prg_p, struct pci_system *pci_sys) 293 { 294 pci_conf_hdr_t config_hdr; 295 boolean_t multi_function_device; 296 int8_t func; 297 int8_t first_func = 0; 298 int8_t last_func = PCI_REG_FUNC_M >> PCI_REG_FUNC_SHIFT; 299 int rval = 0; 300 struct pci_device * pci_base; 301 302 /* 303 * Loop through at least func=first_func. Continue looping through 304 * functions if there are no errors and the device is a multi-function 305 * device. 306 * 307 * (Note, if first_func == 0, header will show whether multifunction 308 * device and set multi_function_device. If first_func != 0, then we 309 * will force the loop as the user wants a specific function to be 310 * checked. 311 */ 312 for (func = first_func, multi_function_device = B_FALSE; 313 ((func <= last_func) && 314 ((func == first_func) || (multi_function_device))); 315 func++) { 316 prg_p->func_no = func; 317 318 /* 319 * Four things can happen here: 320 * 321 * 1) ioctl comes back as EFAULT and prg_p->status is 322 * PCITOOL_INVALID_ADDRESS. There is no device at this location. 323 * 324 * 2) ioctl comes back successful and the data comes back as 325 * zero. Config space is mapped but no device responded. 326 * 327 * 3) ioctl comes back successful and the data comes back as 328 * non-zero. We've found a device. 329 * 330 * 4) Some other error occurs in an ioctl. 331 */ 332 333 prg_p->status = PCITOOL_SUCCESS; 334 prg_p->offset = 0; 335 prg_p->data = 0; 336 prg_p->user_version = PCITOOL_USER_VERSION; 337 338 errno = 0; 339 if (((rval = ioctl(nexus->fd, PCITOOL_DEVICE_GET_REG, prg_p)) != 0) || 340 (prg_p->data == 0xffffffff)) { 341 342 /* 343 * Accept errno == EINVAL along with status of 344 * PCITOOL_OUT_OF_RANGE because some systems 345 * don't implement the full range of config space. 346 * Leave the loop quietly in this case. 347 */ 348 if ((errno == EINVAL) || 349 (prg_p->status == PCITOOL_OUT_OF_RANGE)) { 350 break; 351 } 352 353 /* 354 * Exit silently with ENXIO as this means that there are 355 * no devices under the pci root nexus. 356 */ 357 else if ((errno == ENXIO) && 358 (prg_p->status == PCITOOL_IO_ERROR)) { 359 break; 360 } 361 362 /* 363 * Expect errno == EFAULT along with status of 364 * PCITOOL_INVALID_ADDRESS because there won't be 365 * devices at each stop. Quit on any other error. 366 */ 367 else if (((errno != EFAULT) || 368 (prg_p->status != PCITOOL_INVALID_ADDRESS)) && 369 (prg_p->data != 0xffffffff)) { 370 break; 371 } 372 373 /* 374 * If no function at this location, 375 * just advance to the next function. 376 */ 377 else { 378 rval = 0; 379 } 380 381 /* 382 * Data came back as 0. 383 * Treat as unresponsive device and check next device. 384 */ 385 } else if (prg_p->data == 0) { 386 rval = 0; 387 break; /* Func loop. */ 388 389 /* Found something. */ 390 } else { 391 config_hdr.dwords[0] = (uint32_t)prg_p->data; 392 393 /* Get the rest of the PCI header. */ 394 if ((rval = get_config_header(nexus->fd, prg_p->bus_no, 395 prg_p->dev_no, prg_p->func_no, 396 &config_hdr)) != 0) { 397 break; 398 } 399 400 /* 401 * Special case for the type of Southbridge found on 402 * Ultra-45 and other sun4u fire workstations. 403 */ 404 if ((config_hdr.dwords[0] == U45_SB_DEVID_VID) && 405 (config_hdr.dwords[2] == U45_SB_CLASS_RID)) { 406 rval = ECANCELED; 407 break; 408 } 409 410 /* 411 * Found one device with bus number, device number and 412 * function number. 413 */ 414 415 pci_base = &pci_sys->devices[pci_sys->num_devices].base; 416 417 /* 418 * Domain is peer bus?? 419 */ 420 pci_base->domain = 0; 421 pci_base->bus = prg_p->bus_no; 422 pci_base->dev = prg_p->dev_no; 423 pci_base->func = func; 424 425 /* 426 * for the format of device_class, see struct pci_device; 427 */ 428 429 pci_base->device_class = 430 (GET_CONFIG_VAL_8(PCI_CONF_BASCLASS) << 16) | 431 (GET_CONFIG_VAL_8(PCI_CONF_SUBCLASS) << 8) | 432 GET_CONFIG_VAL_8(PCI_CONF_PROGCLASS); 433 434 pci_base->revision = GET_CONFIG_VAL_8(PCI_CONF_REVID); 435 pci_base->vendor_id = GET_CONFIG_VAL_16(PCI_CONF_VENID); 436 pci_base->device_id = GET_CONFIG_VAL_16(PCI_CONF_DEVID); 437 pci_base->subvendor_id = GET_CONFIG_VAL_16(PCI_CONF_SUBVENID); 438 pci_base->subdevice_id = GET_CONFIG_VAL_16(PCI_CONF_SUBSYSID); 439 440 pci_sys->devices[pci_sys->num_devices].header_type 441 = GET_CONFIG_VAL_8(PCI_CONF_HEADER); 442 443 #ifdef DEBUG 444 fprintf(stderr, 445 "nexus = %s, busno = %x, devno = %x, funcno = %x\n", 446 nexus->path, prg_p->bus_no, prg_p->dev_no, func); 447 #endif 448 449 if (pci_sys->num_devices < (MAX_DEVICES - 1)) { 450 pci_sys->num_devices++; 451 } else { 452 (void) fprintf(stderr, 453 "Maximum number of PCI devices found," 454 " discarding additional devices\n"); 455 } 456 457 458 /* 459 * Accommodate devices which state their 460 * multi-functionality only in their function 0 config 461 * space. Note multi-functionality throughout probing 462 * of all of this device's functions. 463 */ 464 if (config_hdr.bytes[PCI_CONF_HEADER] & PCI_HEADER_MULTI) { 465 multi_function_device = B_TRUE; 466 } 467 } 468 } 469 470 return (rval); 471 } 472 473 /* 474 * This function is called from di_walk_minor() when any PROBE is processed 475 */ 476 static int 477 probe_nexus_node(di_node_t di_node, di_minor_t minor, void *arg) 478 { 479 struct pci_system *pci_sys = (struct pci_system *) arg; 480 char *nexus_name; 481 nexus_t *nexus; 482 int fd; 483 char nexus_path[MAXPATHLEN]; 484 485 di_prop_t prop; 486 char *strings; 487 int *ints; 488 int numval; 489 int pci_node = 0; 490 int first_bus = 0, last_bus = PCI_REG_BUS_G(PCI_REG_BUS_M); 491 492 #ifdef DEBUG 493 nexus_name = di_devfs_minor_path(minor); 494 fprintf(stderr, "-- device name: %s\n", nexus_name); 495 #endif 496 497 for (prop = di_prop_next(di_node, NULL); prop != NULL; 498 prop = di_prop_next(di_node, prop)) { 499 500 const char *prop_name = di_prop_name(prop); 501 502 #ifdef DEBUG 503 fprintf(stderr, " property: %s\n", prop_name); 504 #endif 505 506 if (strcmp(prop_name, "device_type") == 0) { 507 numval = di_prop_strings(prop, &strings); 508 if (numval != 1 || strncmp(strings, "pci", 3) != 0) { 509 /* not a PCI node, bail */ 510 return (DI_WALK_CONTINUE); 511 } 512 pci_node = 1; 513 } 514 else if (strcmp(prop_name, "class-code") == 0) { 515 /* not a root bus node, bail */ 516 return (DI_WALK_CONTINUE); 517 } 518 else if (strcmp(prop_name, "bus-range") == 0) { 519 numval = di_prop_ints(prop, &ints); 520 if (numval == 2) { 521 first_bus = ints[0]; 522 last_bus = ints[1]; 523 } 524 } 525 } 526 527 #ifdef __x86 /* sparc pci nodes don't have the device_type set */ 528 if (pci_node != 1) 529 return (DI_WALK_CONTINUE); 530 #endif 531 532 /* we have a PCI root bus node. */ 533 nexus = calloc(1, sizeof(nexus_t)); 534 if (nexus == NULL) { 535 (void) fprintf(stderr, "Error allocating memory for nexus: %s\n", 536 strerror(errno)); 537 return (DI_WALK_TERMINATE); 538 } 539 nexus->first_bus = first_bus; 540 nexus->last_bus = last_bus; 541 542 nexus_name = di_devfs_minor_path(minor); 543 if (nexus_name == NULL) { 544 (void) fprintf(stderr, "Error getting nexus path: %s\n", 545 strerror(errno)); 546 free(nexus); 547 return (DI_WALK_CONTINUE); 548 } 549 550 snprintf(nexus_path, sizeof(nexus_path), "/devices%s", nexus_name); 551 di_devfs_path_free(nexus_name); 552 553 #ifdef DEBUG 554 fprintf(stderr, "nexus = %s, bus-range = %d - %d\n", 555 nexus_path, first_bus, last_bus); 556 #endif 557 558 if ((fd = open(nexus_path, O_RDWR)) >= 0) { 559 nexus->fd = fd; 560 nexus->path = strdup(nexus_path); 561 if ((do_probe(nexus, pci_sys) != 0) && (errno != ENXIO)) { 562 (void) fprintf(stderr, "Error probing node %s: %s\n", 563 nexus_path, strerror(errno)); 564 (void) close(fd); 565 free(nexus->path); 566 free(nexus); 567 } else { 568 nexus->next = nexus_list; 569 nexus_list = nexus; 570 } 571 } else { 572 (void) fprintf(stderr, "Error opening %s: %s\n", 573 nexus_path, strerror(errno)); 574 free(nexus); 575 } 576 577 return DI_WALK_CONTINUE; 578 } 579 580 581 /* 582 * Solaris version 583 * Probe a given nexus config space for devices. 584 * 585 * fd is the file descriptor of the nexus. 586 * input_args contains commandline options as specified by the user. 587 */ 588 static int 589 do_probe(nexus_t *nexus, struct pci_system *pci_sys) 590 { 591 pcitool_reg_t prg; 592 uint32_t bus; 593 uint8_t dev; 594 uint32_t last_bus = nexus->last_bus; 595 uint8_t last_dev = PCI_REG_DEV_M >> PCI_REG_DEV_SHIFT; 596 uint8_t first_bus = nexus->first_bus; 597 uint8_t first_dev = 0; 598 int rval = 0; 599 600 prg.barnum = 0; /* Config space. */ 601 602 /* Must read in 4-byte quantities. */ 603 prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN; 604 605 prg.data = 0; 606 607 /* 608 * Loop through all valid bus / dev / func combinations to check for 609 * all devices, with the following exceptions: 610 * 611 * When nothing is found at function 0 of a bus / dev combination, skip 612 * the other functions of that bus / dev combination. 613 * 614 * When a found device's function 0 is probed and it is determined that 615 * it is not a multifunction device, skip probing of that device's 616 * other functions. 617 */ 618 for (bus = first_bus; ((bus <= last_bus) && (rval == 0)); bus++) { 619 prg.bus_no = (uint8_t)bus; 620 621 for (dev = first_dev; ((dev <= last_dev) && (rval == 0)); dev++) { 622 prg.dev_no = dev; 623 rval = probe_dev(nexus, &prg, pci_sys); 624 } 625 626 /* 627 * Ultra-45 southbridge workaround: 628 * ECANCELED tells to skip to the next bus. 629 */ 630 if (rval == ECANCELED) { 631 rval = 0; 632 } 633 } 634 635 return (rval); 636 } 637 638 static int 639 find_target_node(di_node_t node, void *arg) 640 { 641 int *regbuf = NULL; 642 int len = 0; 643 uint32_t busno, funcno, devno; 644 i_devnode_t *devnode = (i_devnode_t *)arg; 645 646 /* 647 * Test the property functions, only for testing 648 */ 649 /* 650 void *prop = DI_PROP_NIL; 651 652 (void) fprintf(stderr, "start of node 0x%x\n", node->nodeid); 653 while ((prop = di_prop_hw_next(node, prop)) != DI_PROP_NIL) { 654 int i; 655 (void) fprintf(stderr, "name=%s: ", di_prop_name(prop)); 656 len = 0; 657 if (!strcmp(di_prop_name(prop), "reg")) { 658 len = di_prop_ints(prop, ®buf); 659 } 660 for (i = 0; i < len; i++) { 661 fprintf(stderr, "0x%0x.", regbuf[i]); 662 } 663 fprintf(stderr, "\n"); 664 } 665 (void) fprintf(stderr, "end of node 0x%x\n", node->nodeid); 666 */ 667 668 len = di_prop_lookup_ints(DDI_DEV_T_ANY, node, "reg", ®buf); 669 670 if (len <= 0) { 671 #ifdef DEBUG 672 fprintf(stderr, "error = %x\n", errno); 673 fprintf(stderr, "can not find assigned-address\n"); 674 #endif 675 return (DI_WALK_CONTINUE); 676 } 677 678 busno = PCI_REG_BUS_G(regbuf[0]); 679 devno = PCI_REG_DEV_G(regbuf[0]); 680 funcno = PCI_REG_FUNC_G(regbuf[0]); 681 682 if ((busno == devnode->bus) && 683 (devno == devnode->dev) && 684 (funcno == devnode->func)) { 685 devnode->node = node; 686 687 return (DI_WALK_TERMINATE); 688 } 689 690 return (DI_WALK_CONTINUE); 691 } 692 693 /* 694 * Solaris version 695 */ 696 static int 697 pci_device_solx_devfs_probe( struct pci_device * dev ) 698 { 699 uint8_t config[256]; 700 int err; 701 di_node_t rnode = DI_NODE_NIL; 702 i_devnode_t args = { 0, 0, 0, DI_NODE_NIL }; 703 int *regbuf; 704 pci_regspec_t *reg; 705 int i; 706 pciaddr_t bytes; 707 int len = 0; 708 uint ent = 0; 709 710 err = pci_device_solx_devfs_read( dev, config, 0, 256, & bytes ); 711 712 if ( bytes >= 64 ) { 713 struct pci_device_private *priv = 714 (struct pci_device_private *) dev; 715 716 dev->vendor_id = (uint16_t)config[0] + ((uint16_t)config[1] << 8); 717 dev->device_id = (uint16_t)config[2] + ((uint16_t)config[3] << 8); 718 dev->device_class = (uint32_t)config[9] + 719 ((uint32_t)config[10] << 8) + 720 ((uint16_t)config[11] << 16); 721 722 /* 723 * device class code is already there. 724 * see probe_dev function. 725 */ 726 dev->revision = config[8]; 727 dev->subvendor_id = (uint16_t)config[44] + ((uint16_t)config[45] << 8); 728 dev->subdevice_id = (uint16_t)config[46] + ((uint16_t)config[47] << 8); 729 dev->irq = config[60]; 730 731 priv->header_type = config[14]; 732 /* 733 * starting to find if it is MEM/MEM64/IO 734 * using libdevinfo 735 */ 736 if ((rnode = di_init("/", DINFOCPYALL)) == DI_NODE_NIL) { 737 err = errno; 738 (void) fprintf(stderr, "di_init failed: %s\n", strerror(errno)); 739 } else { 740 args.bus = dev->bus; 741 args.dev = dev->dev; 742 args.func = dev->func; 743 (void) di_walk_node(rnode, DI_WALK_CLDFIRST, 744 (void *)&args, find_target_node); 745 } 746 } 747 if (args.node != DI_NODE_NIL) { 748 /* 749 * It will succeed for sure, because it was 750 * successfully called in find_target_node 751 */ 752 len = di_prop_lookup_ints(DDI_DEV_T_ANY, args.node, 753 "assigned-addresses", 754 ®buf); 755 756 } 757 758 if (len <= 0) 759 goto cleanup; 760 761 762 /* 763 * how to find the size of rom??? 764 * if the device has expansion rom, 765 * it must be listed in the last 766 * cells because solaris find probe 767 * the base address from offset 0x10 768 * to 0x30h. So only check the last 769 * item. 770 */ 771 reg = (pci_regspec_t *)®buf[len - CELL_NUMS_1275]; 772 if (PCI_REG_REG_G(reg->pci_phys_hi) == PCI_CONF_ROM) { 773 /* 774 * rom can only be 32 bits 775 */ 776 dev->rom_size = reg->pci_size_low; 777 len = len - CELL_NUMS_1275; 778 } 779 else { 780 /* 781 * size default to 64K and base address 782 * default to 0xC0000 783 */ 784 dev->rom_size = 0x10000; 785 } 786 787 /* 788 * Solaris has its own BAR index. 789 * Linux give two region slot for 64 bit address. 790 */ 791 for (i = 0; i < len; i = i + CELL_NUMS_1275) { 792 793 reg = (pci_regspec_t *)®buf[i]; 794 ent = reg->pci_phys_hi & 0xff; 795 /* 796 * G35 broken in BAR0 797 */ 798 ent = (ent - PCI_CONF_BASE0) >> 2; 799 if (ent >= 6) { 800 fprintf(stderr, "error ent = %d\n", ent); 801 break; 802 } 803 804 /* 805 * non relocatable resource is excluded 806 * such like 0xa0000, 0x3b0. If it is met, 807 * the loop is broken; 808 */ 809 if (!PCI_REG_REG_G(reg->pci_phys_hi)) 810 break; 811 812 if (reg->pci_phys_hi & PCI_PREFETCH_B) { 813 dev->regions[ent].is_prefetchable = 1; 814 } 815 816 817 /* 818 * We split the shift count 32 into two 16 to 819 * avoid the complaining of the compiler 820 */ 821 dev->regions[ent].base_addr = reg->pci_phys_low + 822 ((reg->pci_phys_mid << 16) << 16); 823 dev->regions[ent].size = reg->pci_size_low + 824 ((reg->pci_size_hi << 16) << 16); 825 826 switch (reg->pci_phys_hi & PCI_REG_ADDR_M) { 827 case PCI_ADDR_IO: 828 dev->regions[ent].is_IO = 1; 829 break; 830 case PCI_ADDR_MEM32: 831 break; 832 case PCI_ADDR_MEM64: 833 dev->regions[ent].is_64 = 1; 834 /* 835 * Skip one slot for 64 bit address 836 */ 837 break; 838 } 839 } 840 841 cleanup: 842 if (rnode != DI_NODE_NIL) { 843 di_fini(rnode); 844 } 845 return (err); 846 } 847 848 /* 849 * Solaris version: read the VGA ROM data 850 */ 851 static int 852 pci_device_solx_devfs_read_rom( struct pci_device * dev, void * buffer ) 853 { 854 int err; 855 struct pci_device_mapping prom = { 856 .base = 0xC0000, 857 .size = dev->rom_size, 858 .flags = 0 859 }; 860 861 err = pci_device_solx_devfs_map_range(dev, &prom); 862 if (err == 0) { 863 (void) bcopy(prom.memory, buffer, dev->rom_size); 864 865 if (munmap(prom.memory, dev->rom_size) == -1) { 866 err = errno; 867 } 868 } 869 return err; 870 } 871 872 /* 873 * solaris version: Read the configurations space of the devices 874 */ 875 static int 876 pci_device_solx_devfs_read( struct pci_device * dev, void * data, 877 pciaddr_t offset, pciaddr_t size, 878 pciaddr_t * bytes_read ) 879 { 880 pcitool_reg_t cfg_prg; 881 int err = 0; 882 int i = 0; 883 nexus_t *nexus = find_nexus_for_bus(dev->bus); 884 885 *bytes_read = 0; 886 887 if ( nexus == NULL ) { 888 return ENODEV; 889 } 890 891 cfg_prg.offset = offset; 892 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_1 + NATIVE_ENDIAN; 893 cfg_prg.bus_no = dev->bus; 894 cfg_prg.dev_no = dev->dev; 895 cfg_prg.func_no = dev->func; 896 cfg_prg.barnum = 0; 897 cfg_prg.user_version = PCITOOL_USER_VERSION; 898 899 for (i = 0; i < size; i += PCITOOL_ACC_ATTR_SIZE(PCITOOL_ACC_ATTR_SIZE_1)) 900 { 901 cfg_prg.offset = offset + i; 902 903 if ((err = ioctl(nexus->fd, PCITOOL_DEVICE_GET_REG, &cfg_prg)) != 0) { 904 fprintf(stderr, "read bdf<%s,%x,%x,%x,%llx> config space failure\n", 905 nexus->path, 906 cfg_prg.bus_no, 907 cfg_prg.dev_no, 908 cfg_prg.func_no, 909 cfg_prg.offset); 910 fprintf(stderr, "Failure cause = %x\n", err); 911 break; 912 } 913 914 ((uint8_t *)data)[i] = (uint8_t)cfg_prg.data; 915 /* 916 * DWORDS Offset or bytes Offset ?? 917 */ 918 } 919 *bytes_read = i; 920 921 return (err); 922 } 923 924 /* 925 * Solaris version 926 */ 927 static int 928 pci_device_solx_devfs_write( struct pci_device * dev, const void * data, 929 pciaddr_t offset, pciaddr_t size, 930 pciaddr_t * bytes_written ) 931 { 932 pcitool_reg_t cfg_prg; 933 int err = 0; 934 int cmd; 935 nexus_t *nexus = find_nexus_for_bus(dev->bus); 936 937 if ( bytes_written != NULL ) { 938 *bytes_written = 0; 939 } 940 941 if ( nexus == NULL ) { 942 return ENODEV; 943 } 944 945 cfg_prg.offset = offset; 946 switch (size) { 947 case 1: 948 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_1 + NATIVE_ENDIAN; 949 break; 950 case 2: 951 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_2 + NATIVE_ENDIAN; 952 break; 953 case 4: 954 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN; 955 break; 956 case 8: 957 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_8 + NATIVE_ENDIAN; 958 break; 959 default: 960 return EINVAL; 961 } 962 cfg_prg.bus_no = dev->bus; 963 cfg_prg.dev_no = dev->dev; 964 cfg_prg.func_no = dev->func; 965 cfg_prg.barnum = 0; 966 cfg_prg.user_version = PCITOOL_USER_VERSION; 967 cfg_prg.data = *((uint64_t *)data); 968 969 /* 970 * Check if this device is bridge device. 971 * If it is, it is also a nexus node??? 972 * It seems that there is no explicit 973 * PCI nexus device for X86, so not applicable 974 * from pcitool_bus_reg_ops in pci_tools.c 975 */ 976 cmd = PCITOOL_DEVICE_SET_REG; 977 978 if ((err = ioctl(nexus->fd, cmd, &cfg_prg)) != 0) { 979 return (err); 980 } 981 *bytes_written = size; 982 983 return (err); 984 } 985 986 987 /** 988 * Map a memory region for a device using /dev/xsvc. 989 * 990 * \param dev Device whose memory region is to be mapped. 991 * \param map Parameters of the mapping that is to be created. 992 * 993 * \return 994 * Zero on success or an \c errno value on failure. 995 */ 996 static int 997 pci_device_solx_devfs_map_range(struct pci_device *dev, 998 struct pci_device_mapping *map) 999 { 1000 const int prot = ((map->flags & PCI_DEV_MAP_FLAG_WRITABLE) != 0) 1001 ? (PROT_READ | PROT_WRITE) : PROT_READ; 1002 int err = 0; 1003 1004 /* 1005 * Still used xsvc to do the user space mapping 1006 */ 1007 if (xsvc_fd < 0) { 1008 if ((xsvc_fd = open("/dev/xsvc", O_RDWR)) < 0) { 1009 err = errno; 1010 (void) fprintf(stderr, "can not open /dev/xsvc: %s\n", 1011 strerror(errno)); 1012 return err; 1013 } 1014 } 1015 1016 map->memory = mmap(NULL, map->size, prot, MAP_SHARED, xsvc_fd, map->base); 1017 if (map->memory == MAP_FAILED) { 1018 err = errno; 1019 1020 (void) fprintf(stderr, "map rom region =%llx failed: %s\n", 1021 map->base, strerror(errno)); 1022 } 1023 1024 return err; 1025 } 1026