1 /* 2 * (C) Copyright IBM Corporation 2006 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * IBM AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 */ 24 /* 25 * Copyright 2007, 2009 Sun Microsystems, Inc. All rights reserved. 26 * 27 * Permission is hereby granted, free of charge, to any person obtaining a 28 * copy of this software and associated documentation files (the 29 * "Software"), to deal in the Software without restriction, including 30 * without limitation the rights to use, copy, modify, merge, publish, 31 * distribute, and/or sell copies of the Software, and to permit persons 32 * to whom the Software is furnished to do so, provided that the above 33 * copyright notice(s) and this permission notice appear in all copies of 34 * the Software and that both the above copyright notice(s) and this 35 * permission notice appear in supporting documentation. 36 * 37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 38 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 39 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT 40 * OF THIRD PARTY RIGHTS. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 41 * HOLDERS INCLUDED IN THIS NOTICE BE LIABLE FOR ANY CLAIM, OR ANY SPECIAL 42 * INDIRECT OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING 43 * FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, 44 * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION 45 * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 46 * 47 * Except as contained in this notice, the name of a copyright holder 48 * shall not be used in advertising or otherwise to promote the sale, use 49 * or other dealings in this Software without prior written authorization 50 * of the copyright holder. 51 */ 52 /* 53 * Solaris devfs interfaces 54 */ 55 56 #include <stdlib.h> 57 #include <strings.h> 58 #include <stdio.h> 59 #include <unistd.h> 60 #include <sys/types.h> 61 #include <fcntl.h> 62 #include <sys/mman.h> 63 #include <errno.h> 64 #include <sys/pci.h> 65 #include <libdevinfo.h> 66 #include "pci_tools.h" 67 68 #include "pciaccess.h" 69 #include "pciaccess_private.h" 70 71 /* #define DEBUG */ 72 73 #define MAX_DEVICES 256 74 #define CELL_NUMS_1275 (sizeof(pci_regspec_t) / sizeof(uint_t)) 75 76 typedef union { 77 uint8_t bytes[16 * sizeof (uint32_t)]; 78 uint32_t dwords[16]; 79 } pci_conf_hdr_t; 80 81 typedef struct i_devnode { 82 uint8_t bus; 83 uint8_t dev; 84 uint8_t func; 85 di_node_t node; 86 } i_devnode_t; 87 88 typedef struct nexus { 89 int fd; 90 int first_bus; 91 int last_bus; 92 char *path; /* for errors/debugging; fd is all we need */ 93 struct nexus *next; 94 } nexus_t; 95 96 static nexus_t *nexus_list = NULL; 97 static int xsvc_fd = -1; 98 99 /* 100 * Read config space in native processor endianness. Endian-neutral 101 * processing can then take place. On big endian machines, MSB and LSB 102 * of little endian data end up switched if read as little endian. 103 * They are in correct order if read as big endian. 104 */ 105 #if defined(__sparc) 106 # define NATIVE_ENDIAN PCITOOL_ACC_ATTR_ENDN_BIG 107 #elif defined(__x86) 108 # define NATIVE_ENDIAN PCITOOL_ACC_ATTR_ENDN_LTL 109 #else 110 # error "ISA is neither __sparc nor __x86" 111 #endif 112 113 /* 114 * Identify problematic southbridges. These have device id 0x5249 and 115 * vendor id 0x10b9. Check for revision ID 0 and class code 060400 as well. 116 * Values are little endian, so they are reversed for SPARC. 117 * 118 * Check for these southbridges on all architectures, as the issue is a 119 * southbridge issue, independent of processor. 120 * 121 * If one of these is found during probing, skip probing other devs/funcs on 122 * the rest of the bus, since the southbridge and all devs underneath will 123 * otherwise disappear. 124 */ 125 #if (NATIVE_ENDIAN == PCITOOL_ACC_ATTR_ENDN_BIG) 126 # define U45_SB_DEVID_VID 0xb9104952 127 # define U45_SB_CLASS_RID 0x00000406 128 #else 129 # define U45_SB_DEVID_VID 0x524910b9 130 # define U45_SB_CLASS_RID 0x06040000 131 #endif 132 133 static int pci_device_solx_devfs_map_range(struct pci_device *dev, 134 struct pci_device_mapping *map); 135 136 static int pci_device_solx_devfs_read_rom( struct pci_device * dev, 137 void * buffer ); 138 139 static int pci_device_solx_devfs_probe( struct pci_device * dev ); 140 141 static int pci_device_solx_devfs_read( struct pci_device * dev, void * data, 142 pciaddr_t offset, pciaddr_t size, pciaddr_t * bytes_read ); 143 144 static int pci_device_solx_devfs_write( struct pci_device * dev, 145 const void * data, pciaddr_t offset, pciaddr_t size, 146 pciaddr_t * bytes_written ); 147 148 static int probe_dev(nexus_t *nexus, pcitool_reg_t *prg_p, 149 struct pci_system *pci_sys); 150 151 static int do_probe(nexus_t *nexus, struct pci_system *pci_sys); 152 153 static int probe_nexus_node(di_node_t di_node, di_minor_t minor, void *arg); 154 155 static void pci_system_solx_devfs_destroy( void ); 156 157 static int get_config_header(int fd, uint8_t bus_no, uint8_t dev_no, 158 uint8_t func_no, pci_conf_hdr_t *config_hdr_p); 159 160 int pci_system_solx_devfs_create( void ); 161 162 static const struct pci_system_methods solx_devfs_methods = { 163 .destroy = pci_system_solx_devfs_destroy, 164 .destroy_device = NULL, 165 .read_rom = pci_device_solx_devfs_read_rom, 166 .probe = pci_device_solx_devfs_probe, 167 .map_range = pci_device_solx_devfs_map_range, 168 .unmap_range = pci_device_generic_unmap_range, 169 170 .read = pci_device_solx_devfs_read, 171 .write = pci_device_solx_devfs_write, 172 173 .fill_capabilities = pci_fill_capabilities_generic 174 }; 175 176 static nexus_t * 177 find_nexus_for_bus( int bus ) 178 { 179 nexus_t *nexus; 180 181 for (nexus = nexus_list ; nexus != NULL ; nexus = nexus->next) { 182 if ((bus >= nexus->first_bus) && (bus <= nexus->last_bus)) { 183 return nexus; 184 } 185 } 186 return NULL; 187 } 188 189 #define GET_CONFIG_VAL_8(offset) (config_hdr.bytes[offset]) 190 #define GET_CONFIG_VAL_16(offset) \ 191 (uint16_t) (GET_CONFIG_VAL_8(offset) + (GET_CONFIG_VAL_8(offset+1) << 8)) 192 #define GET_CONFIG_VAL_32(offset) \ 193 (uint32_t) (GET_CONFIG_VAL_8(offset) + \ 194 (GET_CONFIG_VAL_8(offset+1) << 8) + \ 195 (GET_CONFIG_VAL_8(offset+2) << 16) + \ 196 (GET_CONFIG_VAL_8(offset+3) << 24)) 197 198 /* 199 * Release all the resources 200 * Solaris version 201 */ 202 static void 203 pci_system_solx_devfs_destroy( void ) 204 { 205 /* 206 * The memory allocated for pci_sys & devices in create routines 207 * will be freed in pci_system_cleanup. 208 * Need to free system-specific allocations here. 209 */ 210 nexus_t *nexus, *next; 211 212 for (nexus = nexus_list ; nexus != NULL ; nexus = next) { 213 next = nexus->next; 214 close(nexus->fd); 215 free(nexus->path); 216 free(nexus); 217 } 218 nexus_list = NULL; 219 220 if (xsvc_fd >= 0) { 221 close(xsvc_fd); 222 xsvc_fd = -1; 223 } 224 } 225 226 /* 227 * Attempt to access PCI subsystem using Solaris's devfs interface. 228 * Solaris version 229 */ 230 _pci_hidden int 231 pci_system_solx_devfs_create( void ) 232 { 233 int err = 0; 234 di_node_t di_node; 235 236 237 if (nexus_list != NULL) { 238 return 0; 239 } 240 241 /* 242 * Only allow MAX_DEVICES exists 243 * I will fix it later to get 244 * the total devices first 245 */ 246 if ((pci_sys = calloc(1, sizeof (struct pci_system))) != NULL) { 247 pci_sys->methods = &solx_devfs_methods; 248 249 if ((pci_sys->devices = 250 calloc(MAX_DEVICES, sizeof (struct pci_device_private))) 251 != NULL) { 252 253 if ((di_node = di_init("/", DINFOCPYALL)) == DI_NODE_NIL) { 254 err = errno; 255 (void) fprintf(stderr, "di_init() failed: %s\n", 256 strerror(errno)); 257 } else { 258 (void) di_walk_minor(di_node, DDI_NT_REGACC, 0, pci_sys, 259 probe_nexus_node); 260 di_fini(di_node); 261 } 262 } 263 else { 264 err = errno; 265 } 266 } else { 267 err = errno; 268 } 269 270 if (err != 0) { 271 if (pci_sys != NULL) { 272 free(pci_sys->devices); 273 free(pci_sys); 274 pci_sys = NULL; 275 } 276 } 277 278 return (err); 279 } 280 281 /* 282 * Retrieve first 16 dwords of device's config header, except for the first 283 * dword. First 16 dwords are defined by the PCI specification. 284 */ 285 static int 286 get_config_header(int fd, uint8_t bus_no, uint8_t dev_no, uint8_t func_no, 287 pci_conf_hdr_t *config_hdr_p) 288 { 289 pcitool_reg_t cfg_prg; 290 int i; 291 int rval = 0; 292 293 /* Prepare a local pcitool_reg_t so as to not disturb the caller's. */ 294 cfg_prg.offset = 0; 295 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN; 296 cfg_prg.bus_no = bus_no; 297 cfg_prg.dev_no = dev_no; 298 cfg_prg.func_no = func_no; 299 cfg_prg.barnum = 0; 300 cfg_prg.user_version = PCITOOL_USER_VERSION; 301 302 /* Get dwords 1-15 of config space. They must be read as uint32_t. */ 303 for (i = 1; i < (sizeof (pci_conf_hdr_t) / sizeof (uint32_t)); i++) { 304 cfg_prg.offset += sizeof (uint32_t); 305 if ((rval = ioctl(fd, PCITOOL_DEVICE_GET_REG, &cfg_prg)) != 0) { 306 break; 307 } 308 config_hdr_p->dwords[i] = (uint32_t)cfg_prg.data; 309 } 310 311 return (rval); 312 } 313 314 315 /* 316 * Probe device's functions. Modifies many fields in the prg_p. 317 */ 318 static int 319 probe_dev(nexus_t *nexus, pcitool_reg_t *prg_p, struct pci_system *pci_sys) 320 { 321 pci_conf_hdr_t config_hdr; 322 boolean_t multi_function_device; 323 int8_t func; 324 int8_t first_func = 0; 325 int8_t last_func = PCI_REG_FUNC_M >> PCI_REG_FUNC_SHIFT; 326 int rval = 0; 327 struct pci_device * pci_base; 328 329 /* 330 * Loop through at least func=first_func. Continue looping through 331 * functions if there are no errors and the device is a multi-function 332 * device. 333 * 334 * (Note, if first_func == 0, header will show whether multifunction 335 * device and set multi_function_device. If first_func != 0, then we 336 * will force the loop as the user wants a specific function to be 337 * checked. 338 */ 339 for (func = first_func, multi_function_device = B_FALSE; 340 ((func <= last_func) && 341 ((func == first_func) || (multi_function_device))); 342 func++) { 343 prg_p->func_no = func; 344 345 /* 346 * Four things can happen here: 347 * 348 * 1) ioctl comes back as EFAULT and prg_p->status is 349 * PCITOOL_INVALID_ADDRESS. There is no device at this location. 350 * 351 * 2) ioctl comes back successful and the data comes back as 352 * zero. Config space is mapped but no device responded. 353 * 354 * 3) ioctl comes back successful and the data comes back as 355 * non-zero. We've found a device. 356 * 357 * 4) Some other error occurs in an ioctl. 358 */ 359 360 prg_p->status = PCITOOL_SUCCESS; 361 prg_p->offset = 0; 362 prg_p->data = 0; 363 prg_p->user_version = PCITOOL_USER_VERSION; 364 365 errno = 0; 366 if (((rval = ioctl(nexus->fd, PCITOOL_DEVICE_GET_REG, prg_p)) != 0) || 367 (prg_p->data == 0xffffffff)) { 368 369 /* 370 * Accept errno == EINVAL along with status of 371 * PCITOOL_OUT_OF_RANGE because some systems 372 * don't implement the full range of config space. 373 * Leave the loop quietly in this case. 374 */ 375 if ((errno == EINVAL) || 376 (prg_p->status == PCITOOL_OUT_OF_RANGE)) { 377 break; 378 } 379 380 /* 381 * Exit silently with ENXIO as this means that there are 382 * no devices under the pci root nexus. 383 */ 384 else if ((errno == ENXIO) && 385 (prg_p->status == PCITOOL_IO_ERROR)) { 386 break; 387 } 388 389 /* 390 * Expect errno == EFAULT along with status of 391 * PCITOOL_INVALID_ADDRESS because there won't be 392 * devices at each stop. Quit on any other error. 393 */ 394 else if (((errno != EFAULT) || 395 (prg_p->status != PCITOOL_INVALID_ADDRESS)) && 396 (prg_p->data != 0xffffffff)) { 397 break; 398 } 399 400 /* 401 * If no function at this location, 402 * just advance to the next function. 403 */ 404 else { 405 rval = 0; 406 } 407 408 /* 409 * Data came back as 0. 410 * Treat as unresponsive device and check next device. 411 */ 412 } else if (prg_p->data == 0) { 413 rval = 0; 414 break; /* Func loop. */ 415 416 /* Found something. */ 417 } else { 418 config_hdr.dwords[0] = (uint32_t)prg_p->data; 419 420 /* Get the rest of the PCI header. */ 421 if ((rval = get_config_header(nexus->fd, prg_p->bus_no, 422 prg_p->dev_no, prg_p->func_no, 423 &config_hdr)) != 0) { 424 break; 425 } 426 427 /* 428 * Special case for the type of Southbridge found on 429 * Ultra-45 and other sun4u fire workstations. 430 */ 431 if ((config_hdr.dwords[0] == U45_SB_DEVID_VID) && 432 (config_hdr.dwords[2] == U45_SB_CLASS_RID)) { 433 rval = ECANCELED; 434 break; 435 } 436 437 /* 438 * Found one device with bus number, device number and 439 * function number. 440 */ 441 442 pci_base = &pci_sys->devices[pci_sys->num_devices].base; 443 444 /* 445 * Domain is peer bus?? 446 */ 447 pci_base->domain = 0; 448 pci_base->bus = prg_p->bus_no; 449 pci_base->dev = prg_p->dev_no; 450 pci_base->func = func; 451 452 /* 453 * for the format of device_class, see struct pci_device; 454 */ 455 456 pci_base->device_class = 457 (GET_CONFIG_VAL_8(PCI_CONF_BASCLASS) << 16) | 458 (GET_CONFIG_VAL_8(PCI_CONF_SUBCLASS) << 8) | 459 GET_CONFIG_VAL_8(PCI_CONF_PROGCLASS); 460 461 pci_base->revision = GET_CONFIG_VAL_8(PCI_CONF_REVID); 462 pci_base->vendor_id = GET_CONFIG_VAL_16(PCI_CONF_VENID); 463 pci_base->device_id = GET_CONFIG_VAL_16(PCI_CONF_DEVID); 464 pci_base->subvendor_id = GET_CONFIG_VAL_16(PCI_CONF_SUBVENID); 465 pci_base->subdevice_id = GET_CONFIG_VAL_16(PCI_CONF_SUBSYSID); 466 467 pci_sys->devices[pci_sys->num_devices].header_type 468 = GET_CONFIG_VAL_8(PCI_CONF_HEADER); 469 470 #ifdef DEBUG 471 fprintf(stderr, 472 "nexus = %s, busno = %x, devno = %x, funcno = %x\n", 473 nexus->path, prg_p->bus_no, prg_p->dev_no, func); 474 #endif 475 476 if (pci_sys->num_devices < (MAX_DEVICES - 1)) { 477 pci_sys->num_devices++; 478 } else { 479 (void) fprintf(stderr, 480 "Maximum number of PCI devices found," 481 " discarding additional devices\n"); 482 } 483 484 485 /* 486 * Accommodate devices which state their 487 * multi-functionality only in their function 0 config 488 * space. Note multi-functionality throughout probing 489 * of all of this device's functions. 490 */ 491 if (config_hdr.bytes[PCI_CONF_HEADER] & PCI_HEADER_MULTI) { 492 multi_function_device = B_TRUE; 493 } 494 } 495 } 496 497 return (rval); 498 } 499 500 /* 501 * This function is called from di_walk_minor() when any PROBE is processed 502 */ 503 static int 504 probe_nexus_node(di_node_t di_node, di_minor_t minor, void *arg) 505 { 506 struct pci_system *pci_sys = (struct pci_system *) arg; 507 char *nexus_name; 508 nexus_t *nexus; 509 int fd; 510 char nexus_path[MAXPATHLEN]; 511 512 di_prop_t prop; 513 char *strings; 514 int *ints; 515 int numval; 516 int pci_node = 0; 517 int first_bus = 0, last_bus = PCI_REG_BUS_G(PCI_REG_BUS_M); 518 519 #ifdef DEBUG 520 nexus_name = di_devfs_minor_path(minor); 521 fprintf(stderr, "-- device name: %s\n", nexus_name); 522 #endif 523 524 for (prop = di_prop_next(di_node, NULL); prop != NULL; 525 prop = di_prop_next(di_node, prop)) { 526 527 const char *prop_name = di_prop_name(prop); 528 529 #ifdef DEBUG 530 fprintf(stderr, " property: %s\n", prop_name); 531 #endif 532 533 if (strcmp(prop_name, "device_type") == 0) { 534 numval = di_prop_strings(prop, &strings); 535 if (numval != 1 || strncmp(strings, "pci", 3) != 0) { 536 /* not a PCI node, bail */ 537 return (DI_WALK_CONTINUE); 538 } 539 pci_node = 1; 540 } 541 else if (strcmp(prop_name, "class-code") == 0) { 542 /* not a root bus node, bail */ 543 return (DI_WALK_CONTINUE); 544 } 545 else if (strcmp(prop_name, "bus-range") == 0) { 546 numval = di_prop_ints(prop, &ints); 547 if (numval == 2) { 548 first_bus = ints[0]; 549 last_bus = ints[1]; 550 } 551 } 552 } 553 554 #ifdef __x86 /* sparc pci nodes don't have the device_type set */ 555 if (pci_node != 1) 556 return (DI_WALK_CONTINUE); 557 #endif 558 559 /* we have a PCI root bus node. */ 560 nexus = calloc(1, sizeof(nexus_t)); 561 if (nexus == NULL) { 562 (void) fprintf(stderr, "Error allocating memory for nexus: %s\n", 563 strerror(errno)); 564 return (DI_WALK_TERMINATE); 565 } 566 nexus->first_bus = first_bus; 567 nexus->last_bus = last_bus; 568 569 nexus_name = di_devfs_minor_path(minor); 570 if (nexus_name == NULL) { 571 (void) fprintf(stderr, "Error getting nexus path: %s\n", 572 strerror(errno)); 573 free(nexus); 574 return (DI_WALK_CONTINUE); 575 } 576 577 snprintf(nexus_path, sizeof(nexus_path), "/devices%s", nexus_name); 578 di_devfs_path_free(nexus_name); 579 580 #ifdef DEBUG 581 fprintf(stderr, "nexus = %s, bus-range = %d - %d\n", 582 nexus_path, first_bus, last_bus); 583 #endif 584 585 if ((fd = open(nexus_path, O_RDWR)) >= 0) { 586 nexus->fd = fd; 587 nexus->path = strdup(nexus_path); 588 if ((do_probe(nexus, pci_sys) != 0) && (errno != ENXIO)) { 589 (void) fprintf(stderr, "Error probing node %s: %s\n", 590 nexus_path, strerror(errno)); 591 (void) close(fd); 592 free(nexus->path); 593 free(nexus); 594 } else { 595 nexus->next = nexus_list; 596 nexus_list = nexus; 597 } 598 } else { 599 (void) fprintf(stderr, "Error opening %s: %s\n", 600 nexus_path, strerror(errno)); 601 free(nexus); 602 } 603 604 return DI_WALK_CONTINUE; 605 } 606 607 608 /* 609 * Solaris version 610 * Probe a given nexus config space for devices. 611 * 612 * fd is the file descriptor of the nexus. 613 * input_args contains commandline options as specified by the user. 614 */ 615 static int 616 do_probe(nexus_t *nexus, struct pci_system *pci_sys) 617 { 618 pcitool_reg_t prg; 619 uint32_t bus; 620 uint8_t dev; 621 uint32_t last_bus = nexus->last_bus; 622 uint8_t last_dev = PCI_REG_DEV_M >> PCI_REG_DEV_SHIFT; 623 uint8_t first_bus = nexus->first_bus; 624 uint8_t first_dev = 0; 625 int rval = 0; 626 627 prg.barnum = 0; /* Config space. */ 628 629 /* Must read in 4-byte quantities. */ 630 prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN; 631 632 prg.data = 0; 633 634 /* 635 * Loop through all valid bus / dev / func combinations to check for 636 * all devices, with the following exceptions: 637 * 638 * When nothing is found at function 0 of a bus / dev combination, skip 639 * the other functions of that bus / dev combination. 640 * 641 * When a found device's function 0 is probed and it is determined that 642 * it is not a multifunction device, skip probing of that device's 643 * other functions. 644 */ 645 for (bus = first_bus; ((bus <= last_bus) && (rval == 0)); bus++) { 646 prg.bus_no = (uint8_t)bus; 647 648 for (dev = first_dev; ((dev <= last_dev) && (rval == 0)); dev++) { 649 prg.dev_no = dev; 650 rval = probe_dev(nexus, &prg, pci_sys); 651 } 652 653 /* 654 * Ultra-45 southbridge workaround: 655 * ECANCELED tells to skip to the next bus. 656 */ 657 if (rval == ECANCELED) { 658 rval = 0; 659 } 660 } 661 662 return (rval); 663 } 664 665 static int 666 find_target_node(di_node_t node, void *arg) 667 { 668 int *regbuf = NULL; 669 int len = 0; 670 uint32_t busno, funcno, devno; 671 i_devnode_t *devnode = (i_devnode_t *)arg; 672 673 /* 674 * Test the property functions, only for testing 675 */ 676 /* 677 void *prop = DI_PROP_NIL; 678 679 (void) fprintf(stderr, "start of node 0x%x\n", node->nodeid); 680 while ((prop = di_prop_hw_next(node, prop)) != DI_PROP_NIL) { 681 int i; 682 (void) fprintf(stderr, "name=%s: ", di_prop_name(prop)); 683 len = 0; 684 if (!strcmp(di_prop_name(prop), "reg")) { 685 len = di_prop_ints(prop, ®buf); 686 } 687 for (i = 0; i < len; i++) { 688 fprintf(stderr, "0x%0x.", regbuf[i]); 689 } 690 fprintf(stderr, "\n"); 691 } 692 (void) fprintf(stderr, "end of node 0x%x\n", node->nodeid); 693 */ 694 695 len = di_prop_lookup_ints(DDI_DEV_T_ANY, node, "reg", ®buf); 696 697 if (len <= 0) { 698 #ifdef DEBUG 699 fprintf(stderr, "error = %x\n", errno); 700 fprintf(stderr, "can not find assigned-address\n"); 701 #endif 702 return (DI_WALK_CONTINUE); 703 } 704 705 busno = PCI_REG_BUS_G(regbuf[0]); 706 devno = PCI_REG_DEV_G(regbuf[0]); 707 funcno = PCI_REG_FUNC_G(regbuf[0]); 708 709 if ((busno == devnode->bus) && 710 (devno == devnode->dev) && 711 (funcno == devnode->func)) { 712 devnode->node = node; 713 714 return (DI_WALK_TERMINATE); 715 } 716 717 return (DI_WALK_CONTINUE); 718 } 719 720 /* 721 * Solaris version 722 */ 723 static int 724 pci_device_solx_devfs_probe( struct pci_device * dev ) 725 { 726 uint8_t config[256]; 727 int err; 728 di_node_t rnode = DI_NODE_NIL; 729 i_devnode_t args = { 0, 0, 0, DI_NODE_NIL }; 730 int *regbuf; 731 pci_regspec_t *reg; 732 int i; 733 pciaddr_t bytes; 734 int len = 0; 735 uint ent = 0; 736 737 err = pci_device_solx_devfs_read( dev, config, 0, 256, & bytes ); 738 739 if ( bytes >= 64 ) { 740 struct pci_device_private *priv = 741 (struct pci_device_private *) dev; 742 743 dev->vendor_id = (uint16_t)config[0] + ((uint16_t)config[1] << 8); 744 dev->device_id = (uint16_t)config[2] + ((uint16_t)config[3] << 8); 745 dev->device_class = (uint32_t)config[9] + 746 ((uint32_t)config[10] << 8) + 747 ((uint16_t)config[11] << 16); 748 749 /* 750 * device class code is already there. 751 * see probe_dev function. 752 */ 753 dev->revision = config[8]; 754 dev->subvendor_id = (uint16_t)config[44] + ((uint16_t)config[45] << 8); 755 dev->subdevice_id = (uint16_t)config[46] + ((uint16_t)config[47] << 8); 756 dev->irq = config[60]; 757 758 priv->header_type = config[14]; 759 /* 760 * starting to find if it is MEM/MEM64/IO 761 * using libdevinfo 762 */ 763 if ((rnode = di_init("/", DINFOCPYALL)) == DI_NODE_NIL) { 764 err = errno; 765 (void) fprintf(stderr, "di_init failed: %s\n", strerror(errno)); 766 } else { 767 args.bus = dev->bus; 768 args.dev = dev->dev; 769 args.func = dev->func; 770 (void) di_walk_node(rnode, DI_WALK_CLDFIRST, 771 (void *)&args, find_target_node); 772 } 773 } 774 if (args.node != DI_NODE_NIL) { 775 /* 776 * It will succeed for sure, because it was 777 * successfully called in find_target_node 778 */ 779 len = di_prop_lookup_ints(DDI_DEV_T_ANY, args.node, 780 "assigned-addresses", 781 ®buf); 782 783 } 784 785 if (len <= 0) 786 goto cleanup; 787 788 789 /* 790 * how to find the size of rom??? 791 * if the device has expansion rom, 792 * it must be listed in the last 793 * cells because solaris find probe 794 * the base address from offset 0x10 795 * to 0x30h. So only check the last 796 * item. 797 */ 798 reg = (pci_regspec_t *)®buf[len - CELL_NUMS_1275]; 799 if (PCI_REG_REG_G(reg->pci_phys_hi) == PCI_CONF_ROM) { 800 /* 801 * rom can only be 32 bits 802 */ 803 dev->rom_size = reg->pci_size_low; 804 len = len - CELL_NUMS_1275; 805 } 806 else { 807 /* 808 * size default to 64K and base address 809 * default to 0xC0000 810 */ 811 dev->rom_size = 0x10000; 812 } 813 814 /* 815 * Solaris has its own BAR index. 816 * Linux give two region slot for 64 bit address. 817 */ 818 for (i = 0; i < len; i = i + CELL_NUMS_1275) { 819 820 reg = (pci_regspec_t *)®buf[i]; 821 ent = reg->pci_phys_hi & 0xff; 822 /* 823 * G35 broken in BAR0 824 */ 825 ent = (ent - PCI_CONF_BASE0) >> 2; 826 if (ent >= 6) { 827 fprintf(stderr, "error ent = %d\n", ent); 828 break; 829 } 830 831 /* 832 * non relocatable resource is excluded 833 * such like 0xa0000, 0x3b0. If it is met, 834 * the loop is broken; 835 */ 836 if (!PCI_REG_REG_G(reg->pci_phys_hi)) 837 break; 838 839 if (reg->pci_phys_hi & PCI_PREFETCH_B) { 840 dev->regions[ent].is_prefetchable = 1; 841 } 842 843 844 /* 845 * We split the shift count 32 into two 16 to 846 * avoid the complaining of the compiler 847 */ 848 dev->regions[ent].base_addr = reg->pci_phys_low + 849 ((reg->pci_phys_mid << 16) << 16); 850 dev->regions[ent].size = reg->pci_size_low + 851 ((reg->pci_size_hi << 16) << 16); 852 853 switch (reg->pci_phys_hi & PCI_REG_ADDR_M) { 854 case PCI_ADDR_IO: 855 dev->regions[ent].is_IO = 1; 856 break; 857 case PCI_ADDR_MEM32: 858 break; 859 case PCI_ADDR_MEM64: 860 dev->regions[ent].is_64 = 1; 861 /* 862 * Skip one slot for 64 bit address 863 */ 864 break; 865 } 866 } 867 868 cleanup: 869 if (rnode != DI_NODE_NIL) { 870 di_fini(rnode); 871 } 872 return (err); 873 } 874 875 /* 876 * Solaris version: read the VGA ROM data 877 */ 878 static int 879 pci_device_solx_devfs_read_rom( struct pci_device * dev, void * buffer ) 880 { 881 int err; 882 struct pci_device_mapping prom = { 883 .base = 0xC0000, 884 .size = dev->rom_size, 885 .flags = 0 886 }; 887 888 err = pci_device_solx_devfs_map_range(dev, &prom); 889 if (err == 0) { 890 (void) bcopy(prom.memory, buffer, dev->rom_size); 891 892 if (munmap(prom.memory, dev->rom_size) == -1) { 893 err = errno; 894 } 895 } 896 return err; 897 } 898 899 /* 900 * solaris version: Read the configurations space of the devices 901 */ 902 static int 903 pci_device_solx_devfs_read( struct pci_device * dev, void * data, 904 pciaddr_t offset, pciaddr_t size, 905 pciaddr_t * bytes_read ) 906 { 907 pcitool_reg_t cfg_prg; 908 int err = 0; 909 int i = 0; 910 nexus_t *nexus = find_nexus_for_bus(dev->bus); 911 912 *bytes_read = 0; 913 914 if ( nexus == NULL ) { 915 return ENODEV; 916 } 917 918 cfg_prg.offset = offset; 919 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_1 + NATIVE_ENDIAN; 920 cfg_prg.bus_no = dev->bus; 921 cfg_prg.dev_no = dev->dev; 922 cfg_prg.func_no = dev->func; 923 cfg_prg.barnum = 0; 924 cfg_prg.user_version = PCITOOL_USER_VERSION; 925 926 for (i = 0; i < size; i += PCITOOL_ACC_ATTR_SIZE(PCITOOL_ACC_ATTR_SIZE_1)) 927 { 928 cfg_prg.offset = offset + i; 929 930 if ((err = ioctl(nexus->fd, PCITOOL_DEVICE_GET_REG, &cfg_prg)) != 0) { 931 fprintf(stderr, "read bdf<%s,%x,%x,%x,%llx> config space failure\n", 932 nexus->path, 933 cfg_prg.bus_no, 934 cfg_prg.dev_no, 935 cfg_prg.func_no, 936 cfg_prg.offset); 937 fprintf(stderr, "Failure cause = %x\n", err); 938 break; 939 } 940 941 ((uint8_t *)data)[i] = (uint8_t)cfg_prg.data; 942 /* 943 * DWORDS Offset or bytes Offset ?? 944 */ 945 } 946 *bytes_read = i; 947 948 return (err); 949 } 950 951 /* 952 * Solaris version 953 */ 954 static int 955 pci_device_solx_devfs_write( struct pci_device * dev, const void * data, 956 pciaddr_t offset, pciaddr_t size, 957 pciaddr_t * bytes_written ) 958 { 959 pcitool_reg_t cfg_prg; 960 int err = 0; 961 int cmd; 962 nexus_t *nexus = find_nexus_for_bus(dev->bus); 963 964 if ( bytes_written != NULL ) { 965 *bytes_written = 0; 966 } 967 968 if ( nexus == NULL ) { 969 return ENODEV; 970 } 971 972 cfg_prg.offset = offset; 973 switch (size) { 974 case 1: 975 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_1 + NATIVE_ENDIAN; 976 break; 977 case 2: 978 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_2 + NATIVE_ENDIAN; 979 break; 980 case 4: 981 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN; 982 break; 983 case 8: 984 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_8 + NATIVE_ENDIAN; 985 break; 986 default: 987 return EINVAL; 988 } 989 cfg_prg.bus_no = dev->bus; 990 cfg_prg.dev_no = dev->dev; 991 cfg_prg.func_no = dev->func; 992 cfg_prg.barnum = 0; 993 cfg_prg.user_version = PCITOOL_USER_VERSION; 994 cfg_prg.data = *((uint64_t *)data); 995 996 /* 997 * Check if this device is bridge device. 998 * If it is, it is also a nexus node??? 999 * It seems that there is no explicit 1000 * PCI nexus device for X86, so not applicable 1001 * from pcitool_bus_reg_ops in pci_tools.c 1002 */ 1003 cmd = PCITOOL_DEVICE_SET_REG; 1004 1005 if ((err = ioctl(nexus->fd, cmd, &cfg_prg)) != 0) { 1006 return (err); 1007 } 1008 *bytes_written = size; 1009 1010 return (err); 1011 } 1012 1013 1014 /** 1015 * Map a memory region for a device using /dev/xsvc. 1016 * 1017 * \param dev Device whose memory region is to be mapped. 1018 * \param map Parameters of the mapping that is to be created. 1019 * 1020 * \return 1021 * Zero on success or an \c errno value on failure. 1022 */ 1023 static int 1024 pci_device_solx_devfs_map_range(struct pci_device *dev, 1025 struct pci_device_mapping *map) 1026 { 1027 const int prot = ((map->flags & PCI_DEV_MAP_FLAG_WRITABLE) != 0) 1028 ? (PROT_READ | PROT_WRITE) : PROT_READ; 1029 int err = 0; 1030 1031 /* 1032 * Still used xsvc to do the user space mapping 1033 */ 1034 if (xsvc_fd < 0) { 1035 if ((xsvc_fd = open("/dev/xsvc", O_RDWR)) < 0) { 1036 err = errno; 1037 (void) fprintf(stderr, "can not open /dev/xsvc: %s\n", 1038 strerror(errno)); 1039 return err; 1040 } 1041 } 1042 1043 map->memory = mmap(NULL, map->size, prot, MAP_SHARED, xsvc_fd, map->base); 1044 if (map->memory == MAP_FAILED) { 1045 err = errno; 1046 1047 (void) fprintf(stderr, "map rom region =%llx failed: %s\n", 1048 map->base, strerror(errno)); 1049 } 1050 1051 return err; 1052 } 1053