1 /*
2 * (C) Copyright Eric Anholt 2006
3 * (C) Copyright IBM Corporation 2006
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * IBM AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25
26 /**
27 * \file freebsd_pci.c
28 *
29 * Access the kernel PCI support using /dev/pci's ioctl and mmap interface.
30 *
31 * \author Eric Anholt <[email protected]>
32 */
33
34 #include <stdlib.h>
35 #include <stdio.h>
36 #include <string.h>
37 #include <unistd.h>
38 #include <fcntl.h>
39 #include <errno.h>
40 #include <sys/types.h>
41 #include <sys/param.h>
42 #include <sys/pciio.h>
43 #include <sys/mman.h>
44 #include <sys/memrange.h>
45
46 #ifndef ANDROID
47 #include "config.h"
48 #endif
49
50 #include "pciaccess.h"
51 #include "pciaccess_private.h"
52
53 #define PCIC_DISPLAY 0x03
54 #define PCIS_DISPLAY_VGA 0x00
55 #define PCIS_DISPLAY_XGA 0x01
56 #define PCIS_DISPLAY_3D 0x02
57 #define PCIS_DISPLAY_OTHER 0x80
58
59 /* Registers taken from pcireg.h */
60 #define PCIR_COMMAND 0x04
61 #define PCIM_CMD_PORTEN 0x0001
62 #define PCIM_CMD_MEMEN 0x0002
63 #define PCIR_BIOS 0x30
64 #define PCIM_BIOS_ENABLE 0x01
65 #define PCIM_BIOS_ADDR_MASK 0xfffff800
66
67 #define PCIR_BARS 0x10
68 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4)
69 #define PCI_BAR_IO(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE)
70 #define PCI_BAR_MEM(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE)
71 #define PCIM_BAR_MEM_TYPE 0x00000006
72 #define PCIM_BAR_MEM_64 4
73 #define PCIM_BAR_MEM_PREFETCH 0x00000008
74 #define PCIM_BAR_SPACE 0x00000001
75 #define PCIM_BAR_MEM_SPACE 0
76 #define PCIM_BAR_IO_SPACE 1
77
78 /**
79 * FreeBSD private pci_system structure that extends the base pci_system
80 * structure.
81 *
82 * It is initialized once and used as a global, just as pci_system is used.
83 */
84 _pci_hidden
85 struct freebsd_pci_system {
86 /* This must be the first entry in the structure, as pci_system_cleanup()
87 * frees pci_sys.
88 */
89 struct pci_system pci_sys;
90
91 int pcidev; /**< fd for /dev/pci */
92 } *freebsd_pci_sys;
93
94 /**
95 * Map a memory region for a device using /dev/mem.
96 *
97 * \param dev Device whose memory region is to be mapped.
98 * \param map Parameters of the mapping that is to be created.
99 *
100 * \return
101 * Zero on success or an \c errno value on failure.
102 */
103 static int
pci_device_freebsd_map_range(struct pci_device * dev,struct pci_device_mapping * map)104 pci_device_freebsd_map_range(struct pci_device *dev,
105 struct pci_device_mapping *map)
106 {
107 const int prot = ((map->flags & PCI_DEV_MAP_FLAG_WRITABLE) != 0)
108 ? (PROT_READ | PROT_WRITE) : PROT_READ;
109 struct mem_range_desc mrd;
110 struct mem_range_op mro;
111
112 int fd, err = 0;
113
114 fd = open("/dev/mem", O_RDWR);
115 if (fd == -1)
116 return errno;
117
118 map->memory = mmap(NULL, map->size, prot, MAP_SHARED, fd, map->base);
119
120 if (map->memory == MAP_FAILED) {
121 err = errno;
122 }
123
124 mrd.mr_base = map->base;
125 mrd.mr_len = map->size;
126 strncpy(mrd.mr_owner, "pciaccess", sizeof(mrd.mr_owner));
127 if (map->flags & PCI_DEV_MAP_FLAG_CACHABLE)
128 mrd.mr_flags = MDF_WRITEBACK;
129 else if (map->flags & PCI_DEV_MAP_FLAG_WRITE_COMBINE)
130 mrd.mr_flags = MDF_WRITECOMBINE;
131 else
132 mrd.mr_flags = MDF_UNCACHEABLE;
133 mro.mo_desc = &mrd;
134 mro.mo_arg[0] = MEMRANGE_SET_UPDATE;
135
136 /* No need to set an MTRR if it's the default mode. */
137 if (mrd.mr_flags != MDF_UNCACHEABLE) {
138 if (ioctl(fd, MEMRANGE_SET, &mro)) {
139 fprintf(stderr, "failed to set mtrr: %s\n", strerror(errno));
140 }
141 }
142
143 close(fd);
144
145 return err;
146 }
147
148 static int
pci_device_freebsd_unmap_range(struct pci_device * dev,struct pci_device_mapping * map)149 pci_device_freebsd_unmap_range( struct pci_device *dev,
150 struct pci_device_mapping *map )
151 {
152 struct mem_range_desc mrd;
153 struct mem_range_op mro;
154 int fd;
155
156 if ((map->flags & PCI_DEV_MAP_FLAG_CACHABLE) ||
157 (map->flags & PCI_DEV_MAP_FLAG_WRITE_COMBINE))
158 {
159 fd = open("/dev/mem", O_RDWR);
160 if (fd != -1) {
161 mrd.mr_base = map->base;
162 mrd.mr_len = map->size;
163 strncpy(mrd.mr_owner, "pciaccess", sizeof(mrd.mr_owner));
164 mrd.mr_flags = MDF_UNCACHEABLE;
165 mro.mo_desc = &mrd;
166 mro.mo_arg[0] = MEMRANGE_SET_REMOVE;
167
168 if (ioctl(fd, MEMRANGE_SET, &mro)) {
169 fprintf(stderr, "failed to unset mtrr: %s\n", strerror(errno));
170 }
171
172 close(fd);
173 } else {
174 fprintf(stderr, "Failed to open /dev/mem\n");
175 }
176 }
177
178 return pci_device_generic_unmap_range(dev, map);
179 }
180
181 static int
pci_device_freebsd_read(struct pci_device * dev,void * data,pciaddr_t offset,pciaddr_t size,pciaddr_t * bytes_read)182 pci_device_freebsd_read( struct pci_device * dev, void * data,
183 pciaddr_t offset, pciaddr_t size,
184 pciaddr_t * bytes_read )
185 {
186 struct pci_io io;
187
188 #if HAVE_PCI_IO_PC_DOMAIN
189 io.pi_sel.pc_domain = dev->domain;
190 #endif
191 io.pi_sel.pc_bus = dev->bus;
192 io.pi_sel.pc_dev = dev->dev;
193 io.pi_sel.pc_func = dev->func;
194
195 *bytes_read = 0;
196 while ( size > 0 ) {
197 int toread = (size < 4) ? size : 4;
198
199 /* Only power of two allowed. */
200 if (toread == 3)
201 toread = 2;
202
203 io.pi_reg = offset;
204 io.pi_width = toread;
205
206 if ( ioctl( freebsd_pci_sys->pcidev, PCIOCREAD, &io ) < 0 )
207 return errno;
208
209 memcpy(data, &io.pi_data, toread );
210
211 offset += toread;
212 data = (char *)data + toread;
213 size -= toread;
214 *bytes_read += toread;
215 }
216
217 return 0;
218 }
219
220
221 static int
pci_device_freebsd_write(struct pci_device * dev,const void * data,pciaddr_t offset,pciaddr_t size,pciaddr_t * bytes_written)222 pci_device_freebsd_write( struct pci_device * dev, const void * data,
223 pciaddr_t offset, pciaddr_t size,
224 pciaddr_t * bytes_written )
225 {
226 struct pci_io io;
227
228 #if HAVE_PCI_IO_PC_DOMAIN
229 io.pi_sel.pc_domain = dev->domain;
230 #endif
231 io.pi_sel.pc_bus = dev->bus;
232 io.pi_sel.pc_dev = dev->dev;
233 io.pi_sel.pc_func = dev->func;
234
235 *bytes_written = 0;
236 while ( size > 0 ) {
237 int towrite = (size < 4 ? size : 4);
238
239 /* Only power of two allowed. */
240 if (towrite == 3)
241 towrite = 2;
242
243 io.pi_reg = offset;
244 io.pi_width = towrite;
245 memcpy( &io.pi_data, data, towrite );
246
247 if ( ioctl( freebsd_pci_sys->pcidev, PCIOCWRITE, &io ) < 0 )
248 return errno;
249
250 offset += towrite;
251 data = (char *)data + towrite;
252 size -= towrite;
253 *bytes_written += towrite;
254 }
255
256 return 0;
257 }
258
259 /**
260 * Read a VGA rom using the 0xc0000 mapping.
261 *
262 * This function should be extended to handle access through PCI resources,
263 * which should be more reliable when available.
264 */
265 static int
pci_device_freebsd_read_rom(struct pci_device * dev,void * buffer)266 pci_device_freebsd_read_rom( struct pci_device * dev, void * buffer )
267 {
268 struct pci_device_private *priv = (struct pci_device_private *) dev;
269 void *bios;
270 pciaddr_t rom_base;
271 uint32_t rom;
272 uint16_t reg;
273 int pci_rom, memfd;
274
275 if ( ( dev->device_class & 0x00ffff00 ) !=
276 ( ( PCIC_DISPLAY << 16 ) | ( PCIS_DISPLAY_VGA << 8 ) ) )
277 {
278 return ENOSYS;
279 }
280
281 if (priv->rom_base == 0) {
282 #if defined(__amd64__) || defined(__i386__)
283 rom_base = 0xc0000;
284 pci_rom = 0;
285 #else
286 return ENOSYS;
287 #endif
288 } else {
289 rom_base = priv->rom_base;
290 pci_rom = 1;
291
292 pci_device_cfg_read_u16( dev, ®, PCIR_COMMAND );
293 pci_device_cfg_write_u16( dev, reg | PCIM_CMD_MEMEN, PCIR_COMMAND );
294 pci_device_cfg_read_u32( dev, &rom, PCIR_BIOS );
295 pci_device_cfg_write_u32( dev, rom | PCIM_BIOS_ENABLE, PCIR_BIOS );
296 }
297
298 printf("Using rom_base = 0x%lx\n", (long)rom_base);
299 memfd = open( "/dev/mem", O_RDONLY );
300 if ( memfd == -1 )
301 return errno;
302
303 bios = mmap( NULL, dev->rom_size, PROT_READ, 0, memfd, rom_base );
304 if ( bios == MAP_FAILED ) {
305 close( memfd );
306 return errno;
307 }
308
309 memcpy( buffer, bios, dev->rom_size );
310
311 munmap( bios, dev->rom_size );
312 close( memfd );
313
314 if (pci_rom) {
315 pci_device_cfg_write_u32( dev, PCIR_BIOS, rom );
316 pci_device_cfg_write_u16( dev, PCIR_COMMAND, reg );
317 }
318
319 return 0;
320 }
321
322 /** Returns the number of regions (base address registers) the device has */
323
324 static int
pci_device_freebsd_get_num_regions(struct pci_device * dev)325 pci_device_freebsd_get_num_regions( struct pci_device * dev )
326 {
327 struct pci_device_private *priv = (struct pci_device_private *) dev;
328
329 switch (priv->header_type) {
330 case 0:
331 return 6;
332 case 1:
333 return 2;
334 case 2:
335 return 1;
336 default:
337 printf("unknown header type %02x\n", priv->header_type);
338 return 0;
339 }
340 }
341
342 #ifdef PCIOCGETBAR
343
344 static int
pci_device_freebsd_probe(struct pci_device * dev)345 pci_device_freebsd_probe( struct pci_device * dev )
346 {
347 struct pci_device_private *priv = (struct pci_device_private *) dev;
348 struct pci_bar_io bar;
349 uint8_t irq;
350 int err, i;
351
352 #if HAVE_PCI_IO_PC_DOMAIN
353 bar.pbi_sel.pc_domain = dev->domain;
354 #endif
355 bar.pbi_sel.pc_bus = dev->bus;
356 bar.pbi_sel.pc_dev = dev->dev;
357 bar.pbi_sel.pc_func = dev->func;
358
359
360 /* Many of the fields were filled in during initial device enumeration.
361 * At this point, we need to fill in regions, rom_size, and irq.
362 */
363
364 err = pci_device_cfg_read_u8( dev, &irq, 60 );
365 if (err)
366 return errno;
367 dev->irq = irq;
368
369 for (i = 0; i < pci_device_freebsd_get_num_regions( dev ); i++) {
370 bar.pbi_reg = PCIR_BAR(i);
371 if ( ioctl( freebsd_pci_sys->pcidev, PCIOCGETBAR, &bar ) < 0 )
372 continue;
373
374 if (PCI_BAR_IO(bar.pbi_base))
375 dev->regions[i].is_IO = 1;
376
377 if ((bar.pbi_base & PCIM_BAR_MEM_TYPE) == PCIM_BAR_MEM_64)
378 dev->regions[i].is_64 = 1;
379
380 if (bar.pbi_base & PCIM_BAR_MEM_PREFETCH)
381 dev->regions[i].is_prefetchable = 1;
382
383 dev->regions[i].base_addr = bar.pbi_base & ~((uint64_t)0xf);
384 dev->regions[i].size = bar.pbi_length;
385 }
386
387 /* If it's a VGA device, set up the rom size for read_rom using the
388 * 0xc0000 mapping.
389 */
390 if ((dev->device_class & 0x00ffff00) ==
391 ((PCIC_DISPLAY << 16) | (PCIS_DISPLAY_VGA << 8))) {
392 dev->rom_size = 64 * 1024;
393 }
394
395 return 0;
396 }
397
398 #else
399
400 /** Masks out the flag bigs of the base address register value */
401 static uint32_t
get_map_base(uint32_t val)402 get_map_base( uint32_t val )
403 {
404 if (val & 0x01)
405 return val & ~0x03;
406 else
407 return val & ~0x0f;
408 }
409
410 /** Returns the size of a region based on the all-ones test value */
411 static int
get_test_val_size(uint32_t testval)412 get_test_val_size( uint32_t testval )
413 {
414 if (testval == 0)
415 return 0;
416
417 /* Mask out the flag bits */
418 testval = get_map_base( testval );
419
420 return 1 << (ffs(testval) - 1);
421 }
422
423 /**
424 * Sets the address and size information for the region from config space
425 * registers.
426 *
427 * This would be much better provided by a kernel interface.
428 *
429 * \return 0 on success, or an errno value.
430 */
431 static int
pci_device_freebsd_get_region_info(struct pci_device * dev,int region,int bar)432 pci_device_freebsd_get_region_info( struct pci_device * dev, int region,
433 int bar )
434 {
435 uint32_t addr, testval;
436 uint16_t cmd;
437 int err;
438
439 /* Get the base address */
440 err = pci_device_cfg_read_u32( dev, &addr, bar );
441 if (err != 0)
442 return err;
443
444 /*
445 * We are going to be doing evil things to the registers here
446 * so disable them via the command register first.
447 */
448 err = pci_device_cfg_read_u16( dev, &cmd, PCIR_COMMAND );
449 if (err != 0)
450 return err;
451
452 err = pci_device_cfg_write_u16( dev,
453 cmd & ~(PCI_BAR_MEM(addr) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN),
454 PCIR_COMMAND );
455 if (err != 0)
456 return err;
457
458 /* Test write all ones to the register, then restore it. */
459 err = pci_device_cfg_write_u32( dev, 0xffffffff, bar );
460 if (err != 0)
461 return err;
462 err = pci_device_cfg_read_u32( dev, &testval, bar );
463 if (err != 0)
464 return err;
465 err = pci_device_cfg_write_u32( dev, addr, bar );
466 if (err != 0)
467 return err;
468
469 /* Restore the command register */
470 err = pci_device_cfg_write_u16( dev, cmd, PCIR_COMMAND );
471 if (err != 0)
472 return err;
473
474 if (addr & 0x01)
475 dev->regions[region].is_IO = 1;
476 if (addr & 0x04)
477 dev->regions[region].is_64 = 1;
478 if (addr & 0x08)
479 dev->regions[region].is_prefetchable = 1;
480
481 /* Set the size */
482 dev->regions[region].size = get_test_val_size( testval );
483 printf("size = 0x%lx\n", (long)dev->regions[region].size);
484
485 /* Set the base address value */
486 if (dev->regions[region].is_64) {
487 uint32_t top;
488
489 err = pci_device_cfg_read_u32( dev, &top, bar + 4 );
490 if (err != 0)
491 return err;
492
493 dev->regions[region].base_addr = ((uint64_t)top << 32) |
494 get_map_base(addr);
495 } else {
496 dev->regions[region].base_addr = get_map_base(addr);
497 }
498
499 return 0;
500 }
501
502 static int
pci_device_freebsd_probe(struct pci_device * dev)503 pci_device_freebsd_probe( struct pci_device * dev )
504 {
505 struct pci_device_private *priv = (struct pci_device_private *) dev;
506 uint32_t reg, size;
507 uint8_t irq;
508 int err, i, bar;
509
510 /* Many of the fields were filled in during initial device enumeration.
511 * At this point, we need to fill in regions, rom_size, and irq.
512 */
513
514 err = pci_device_cfg_read_u8( dev, &irq, 60 );
515 if (err)
516 return errno;
517 dev->irq = irq;
518
519 bar = 0x10;
520 for (i = 0; i < pci_device_freebsd_get_num_regions( dev ); i++) {
521 pci_device_freebsd_get_region_info( dev, i, bar );
522 if (dev->regions[i].is_64) {
523 bar += 0x08;
524 i++;
525 } else
526 bar += 0x04;
527 }
528
529 /* If it's a VGA device, set up the rom size for read_rom */
530 if ((dev->device_class & 0x00ffff00) ==
531 ((PCIC_DISPLAY << 16) | (PCIS_DISPLAY_VGA << 8)))
532 {
533 err = pci_device_cfg_read_u32( dev, ®, PCIR_BIOS );
534 if (err)
535 return errno;
536
537 if (reg == 0) {
538 dev->rom_size = 0x10000;
539 return 0;
540 }
541
542 err = pci_device_cfg_write_u32( dev, ~PCIM_BIOS_ENABLE, PCIR_BIOS );
543 if (err)
544 return errno;
545 pci_device_cfg_read_u32( dev, &size, PCIR_BIOS );
546 pci_device_cfg_write_u32( dev, reg, PCIR_BIOS );
547
548 if ((reg & PCIM_BIOS_ADDR_MASK) != 0) {
549 priv->rom_base = (reg & PCIM_BIOS_ADDR_MASK);
550 dev->rom_size = -(size & PCIM_BIOS_ADDR_MASK);
551 }
552 }
553
554 return 0;
555 }
556
557 #endif
558
559 static void
pci_system_freebsd_destroy(void)560 pci_system_freebsd_destroy(void)
561 {
562 close(freebsd_pci_sys->pcidev);
563 free(freebsd_pci_sys->pci_sys.devices);
564 freebsd_pci_sys = NULL;
565 }
566
567 static const struct pci_system_methods freebsd_pci_methods = {
568 .destroy = pci_system_freebsd_destroy,
569 .destroy_device = NULL, /* nothing to do for this */
570 .read_rom = pci_device_freebsd_read_rom,
571 .probe = pci_device_freebsd_probe,
572 .map_range = pci_device_freebsd_map_range,
573 .unmap_range = pci_device_freebsd_unmap_range,
574 .read = pci_device_freebsd_read,
575 .write = pci_device_freebsd_write,
576 .fill_capabilities = pci_fill_capabilities_generic,
577 };
578
579 /**
580 * Attempt to access the FreeBSD PCI interface.
581 */
582 _pci_hidden int
pci_system_freebsd_create(void)583 pci_system_freebsd_create( void )
584 {
585 struct pci_conf_io pciconfio;
586 struct pci_conf pciconf[255];
587 int pcidev;
588 int i;
589
590 /* Try to open the PCI device */
591 pcidev = open( "/dev/pci", O_RDWR );
592 if ( pcidev == -1 )
593 return ENXIO;
594
595 freebsd_pci_sys = calloc( 1, sizeof( struct freebsd_pci_system ) );
596 if ( freebsd_pci_sys == NULL ) {
597 close( pcidev );
598 return ENOMEM;
599 }
600 pci_sys = &freebsd_pci_sys->pci_sys;
601
602 pci_sys->methods = & freebsd_pci_methods;
603 freebsd_pci_sys->pcidev = pcidev;
604
605 /* Probe the list of devices known by the system */
606 bzero( &pciconfio, sizeof( struct pci_conf_io ) );
607 pciconfio.match_buf_len = sizeof(pciconf);
608 pciconfio.matches = pciconf;
609
610 if ( ioctl( pcidev, PCIOCGETCONF, &pciconfio ) == -1) {
611 free( pci_sys );
612 close( pcidev );
613 return errno;
614 }
615
616 if (pciconfio.status == PCI_GETCONF_ERROR ) {
617 free( pci_sys );
618 close( pcidev );
619 return EINVAL;
620 }
621
622 /* Translate the list of devices into pciaccess's format. */
623 pci_sys->num_devices = pciconfio.num_matches;
624 pci_sys->devices = calloc( pciconfio.num_matches,
625 sizeof( struct pci_device_private ) );
626
627 for ( i = 0; i < pciconfio.num_matches; i++ ) {
628 struct pci_conf *p = &pciconf[ i ];
629
630 #if HAVE_PCI_IO_PC_DOMAIN
631 pci_sys->devices[ i ].base.domain = p->pc_sel.pc_domain;
632 #else
633 pci_sys->devices[ i ].base.domain = 0;
634 #endif
635 pci_sys->devices[ i ].base.bus = p->pc_sel.pc_bus;
636 pci_sys->devices[ i ].base.dev = p->pc_sel.pc_dev;
637 pci_sys->devices[ i ].base.func = p->pc_sel.pc_func;
638 pci_sys->devices[ i ].base.vendor_id = p->pc_vendor;
639 pci_sys->devices[ i ].base.device_id = p->pc_device;
640 pci_sys->devices[ i ].base.subvendor_id = p->pc_subvendor;
641 pci_sys->devices[ i ].base.subdevice_id = p->pc_subdevice;
642 pci_sys->devices[ i ].base.revision = p->pc_revid;
643 pci_sys->devices[ i ].base.device_class = (uint32_t)p->pc_class << 16 |
644 (uint32_t)p->pc_subclass << 8 | (uint32_t)p->pc_progif;
645 pci_sys->devices[ i ].header_type = p->pc_hdr & 0x7f;
646 }
647
648 return 0;
649 }
650