1 /*-
2 * Copyright (c) 2017-2018 QCM Technologies.
3 * Copyright (c) 2017-2018 Semihalf.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include "opt_platform.h"
29
30 #include <sys/cdefs.h>
31 #include <sys/param.h>
32 #include <sys/endian.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/conf.h>
36 #include <sys/kernel.h>
37 #include <sys/lock.h>
38 #include <sys/mbuf.h>
39 #include <sys/malloc.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
42 #include <sys/rman.h>
43 #include <machine/bus.h>
44
45 #include <vm/vm.h>
46 #include <vm/pmap.h>
47
48 #include <dev/iicbus/iiconf.h>
49 #include <dev/iicbus/iicbus.h>
50 #include "iicbus_if.h"
51
52 #include "opal.h"
53
54 #ifdef FDT
55 #include <dev/ofw/ofw_bus.h>
56 #include <dev/ofw/ofw_bus_subr.h>
57 #endif
58
59 struct opal_i2c_softc
60 {
61 device_t dev;
62 device_t iicbus;
63 uint32_t opal_id;
64 struct mtx sc_mtx;
65 };
66
67 /* OPAL I2C request */
68 struct opal_i2c_request {
69 uint8_t type;
70 #define OPAL_I2C_RAW_READ 0
71 #define OPAL_I2C_RAW_WRITE 1
72 #define OPAL_I2C_SM_READ 2
73 #define OPAL_I2C_SM_WRITE 3
74 uint8_t flags;
75 uint8_t subaddr_sz; /* Max 4 */
76 uint8_t reserved;
77 uint16_t addr; /* 7 or 10 bit address */
78 uint16_t reserved2;
79 uint32_t subaddr; /* Sub-address if any */
80 uint32_t size; /* Data size */
81 uint64_t buffer_pa; /* Buffer real address */
82 };
83
84 static int opal_i2c_attach(device_t);
85 static int opal_i2c_callback(device_t, int, caddr_t);
86 static int opal_i2c_probe(device_t);
87 static int opal_i2c_transfer(device_t, struct iic_msg *, uint32_t);
88 static int i2c_opal_send_request(uint32_t, struct opal_i2c_request *);
89 static phandle_t opal_i2c_get_node(device_t bus, device_t dev);
90
91 static device_method_t opal_i2c_methods[] = {
92 /* Device interface */
93 DEVMETHOD(device_probe, opal_i2c_probe),
94 DEVMETHOD(device_attach, opal_i2c_attach),
95
96 /* iicbus interface */
97 DEVMETHOD(iicbus_callback, opal_i2c_callback),
98 DEVMETHOD(iicbus_transfer, opal_i2c_transfer),
99 DEVMETHOD(ofw_bus_get_node, opal_i2c_get_node),
100 DEVMETHOD_END
101 };
102
103 #define I2C_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
104 #define I2C_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
105 #define I2C_LOCK_INIT(_sc) \
106 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
107 "i2c", MTX_DEF)
108
109 static driver_t opal_i2c_driver = {
110 "iichb",
111 opal_i2c_methods,
112 sizeof(struct opal_i2c_softc),
113 };
114
115 static int
opal_i2c_probe(device_t dev)116 opal_i2c_probe(device_t dev)
117 {
118
119 if (!(ofw_bus_is_compatible(dev, "ibm,opal-i2c")))
120 return (ENXIO);
121
122 device_set_desc(dev, "opal-i2c");
123
124 return (0);
125 }
126
127 static int
opal_i2c_attach(device_t dev)128 opal_i2c_attach(device_t dev)
129 {
130 struct opal_i2c_softc *sc;
131 int len;
132
133 sc = device_get_softc(dev);
134 sc->dev = dev;
135
136 len = OF_getproplen(ofw_bus_get_node(dev), "ibm,opal-id");
137 if (len <= 0)
138 return (EINVAL);
139 OF_getencprop(ofw_bus_get_node(dev), "ibm,opal-id", &sc->opal_id, len);
140
141 if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL) {
142 device_printf(dev, "could not allocate iicbus instance\n");
143 return (EINVAL);
144 }
145
146 I2C_LOCK_INIT(sc);
147
148 return (bus_generic_attach(dev));
149 }
150
151 static int
opal_get_async_rc(struct opal_msg msg)152 opal_get_async_rc(struct opal_msg msg)
153 {
154 if (msg.msg_type != OPAL_MSG_ASYNC_COMP)
155 return OPAL_PARAMETER;
156 else
157 return htobe64(msg.params[1]);
158 }
159
160 static int
i2c_opal_send_request(uint32_t bus_id,struct opal_i2c_request * req)161 i2c_opal_send_request(uint32_t bus_id, struct opal_i2c_request *req)
162 {
163 struct opal_msg msg;
164 uint64_t token;
165 int rc;
166
167 token = opal_alloc_async_token();
168
169 memset(&msg, 0, sizeof(msg));
170
171 rc = opal_call(OPAL_I2C_REQUEST, token, bus_id,
172 vtophys(req));
173 if (rc != OPAL_ASYNC_COMPLETION)
174 goto out;
175
176 rc = opal_wait_completion(&msg, sizeof(msg), token);
177
178 if (rc != OPAL_SUCCESS)
179 goto out;
180
181 rc = opal_get_async_rc(msg);
182
183 out:
184 opal_free_async_token(token);
185
186 return (rc);
187 }
188
189 static int
opal_i2c_transfer(device_t dev,struct iic_msg * msgs,uint32_t nmsgs)190 opal_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
191 {
192 struct opal_i2c_softc *sc;
193 int i, err = 0;
194 struct opal_i2c_request req;
195
196 sc = device_get_softc(dev);
197
198 memset(&req, 0, sizeof(req));
199
200 I2C_LOCK(sc);
201 for (i = 0; i < nmsgs; i++) {
202 req.type = (msgs[i].flags & IIC_M_RD) ?
203 OPAL_I2C_RAW_READ : OPAL_I2C_RAW_WRITE;
204 req.addr = htobe16(msgs[i].slave >> 1);
205 req.size = htobe32(msgs[i].len);
206 req.buffer_pa = htobe64(pmap_kextract((uint64_t)msgs[i].buf));
207
208 err = i2c_opal_send_request(sc->opal_id, &req);
209 }
210 I2C_UNLOCK(sc);
211
212 return (err);
213 }
214
215 static int
opal_i2c_callback(device_t dev,int index,caddr_t data)216 opal_i2c_callback(device_t dev, int index, caddr_t data)
217 {
218 int error = 0;
219
220 switch (index) {
221 case IIC_REQUEST_BUS:
222 break;
223
224 case IIC_RELEASE_BUS:
225 break;
226
227 default:
228 error = EINVAL;
229 }
230
231 return (error);
232 }
233
234 static phandle_t
opal_i2c_get_node(device_t bus,device_t dev)235 opal_i2c_get_node(device_t bus, device_t dev)
236 {
237
238 /* Share controller node with iibus device. */
239 return (ofw_bus_get_node(bus));
240 }
241
242 DRIVER_MODULE(opal_i2c, opal_i2cm, opal_i2c_driver, NULL, NULL);
243 DRIVER_MODULE(iicbus, opal_i2c, iicbus_driver, NULL, NULL);
244 MODULE_DEPEND(opal_i2c, iicbus, 1, 1, 1);
245