1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2010, Pyun YongHyeon <[email protected]> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for DM&P Electronics, Inc, Vortex86 RDC R6040 FastEthernet. */ 31 32 #include <sys/cdefs.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/mbuf.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/rman.h> 44 #include <sys/socket.h> 45 #include <sys/sockio.h> 46 #include <sys/sysctl.h> 47 48 #include <net/bpf.h> 49 #include <net/if.h> 50 #include <net/if_var.h> 51 #include <net/if_arp.h> 52 #include <net/ethernet.h> 53 #include <net/if_dl.h> 54 #include <net/if_llc.h> 55 #include <net/if_media.h> 56 #include <net/if_types.h> 57 #include <net/if_vlan_var.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 62 #include <dev/mii/mii.h> 63 #include <dev/mii/miivar.h> 64 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcivar.h> 67 68 #include <machine/bus.h> 69 70 #include <dev/vte/if_vtereg.h> 71 #include <dev/vte/if_vtevar.h> 72 73 /* "device miibus" required. See GENERIC if you get errors here. */ 74 #include "miibus_if.h" 75 76 MODULE_DEPEND(vte, pci, 1, 1, 1); 77 MODULE_DEPEND(vte, ether, 1, 1, 1); 78 MODULE_DEPEND(vte, miibus, 1, 1, 1); 79 80 /* Tunables. */ 81 static int tx_deep_copy = 1; 82 TUNABLE_INT("hw.vte.tx_deep_copy", &tx_deep_copy); 83 84 /* 85 * Devices supported by this driver. 86 */ 87 static const struct vte_ident vte_ident_table[] = { 88 { VENDORID_RDC, DEVICEID_RDC_R6040, "RDC R6040 FastEthernet"}, 89 { 0, 0, NULL} 90 }; 91 92 static int vte_attach(device_t); 93 static int vte_detach(device_t); 94 static int vte_dma_alloc(struct vte_softc *); 95 static void vte_dma_free(struct vte_softc *); 96 static void vte_dmamap_cb(void *, bus_dma_segment_t *, int, int); 97 static struct vte_txdesc * 98 vte_encap(struct vte_softc *, struct mbuf **); 99 static const struct vte_ident * 100 vte_find_ident(device_t); 101 #ifndef __NO_STRICT_ALIGNMENT 102 static struct mbuf * 103 vte_fixup_rx(if_t, struct mbuf *); 104 #endif 105 static void vte_get_macaddr(struct vte_softc *); 106 static void vte_init(void *); 107 static void vte_init_locked(struct vte_softc *); 108 static int vte_init_rx_ring(struct vte_softc *); 109 static int vte_init_tx_ring(struct vte_softc *); 110 static void vte_intr(void *); 111 static int vte_ioctl(if_t, u_long, caddr_t); 112 static uint64_t vte_get_counter(if_t, ift_counter); 113 static void vte_mac_config(struct vte_softc *); 114 static int vte_miibus_readreg(device_t, int, int); 115 static void vte_miibus_statchg(device_t); 116 static int vte_miibus_writereg(device_t, int, int, int); 117 static int vte_mediachange(if_t); 118 static int vte_mediachange_locked(if_t); 119 static void vte_mediastatus(if_t, struct ifmediareq *); 120 static int vte_newbuf(struct vte_softc *, struct vte_rxdesc *); 121 static int vte_probe(device_t); 122 static void vte_reset(struct vte_softc *); 123 static int vte_resume(device_t); 124 static void vte_rxeof(struct vte_softc *); 125 static void vte_rxfilter(struct vte_softc *); 126 static int vte_shutdown(device_t); 127 static void vte_start(if_t); 128 static void vte_start_locked(struct vte_softc *); 129 static void vte_start_mac(struct vte_softc *); 130 static void vte_stats_clear(struct vte_softc *); 131 static void vte_stats_update(struct vte_softc *); 132 static void vte_stop(struct vte_softc *); 133 static void vte_stop_mac(struct vte_softc *); 134 static int vte_suspend(device_t); 135 static void vte_sysctl_node(struct vte_softc *); 136 static void vte_tick(void *); 137 static void vte_txeof(struct vte_softc *); 138 static void vte_watchdog(struct vte_softc *); 139 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 140 static int sysctl_hw_vte_int_mod(SYSCTL_HANDLER_ARGS); 141 142 static device_method_t vte_methods[] = { 143 /* Device interface. */ 144 DEVMETHOD(device_probe, vte_probe), 145 DEVMETHOD(device_attach, vte_attach), 146 DEVMETHOD(device_detach, vte_detach), 147 DEVMETHOD(device_shutdown, vte_shutdown), 148 DEVMETHOD(device_suspend, vte_suspend), 149 DEVMETHOD(device_resume, vte_resume), 150 151 /* MII interface. */ 152 DEVMETHOD(miibus_readreg, vte_miibus_readreg), 153 DEVMETHOD(miibus_writereg, vte_miibus_writereg), 154 DEVMETHOD(miibus_statchg, vte_miibus_statchg), 155 156 DEVMETHOD_END 157 }; 158 159 static driver_t vte_driver = { 160 "vte", 161 vte_methods, 162 sizeof(struct vte_softc) 163 }; 164 165 DRIVER_MODULE(vte, pci, vte_driver, 0, 0); 166 DRIVER_MODULE(miibus, vte, miibus_driver, 0, 0); 167 168 static int 169 vte_miibus_readreg(device_t dev, int phy, int reg) 170 { 171 struct vte_softc *sc; 172 int i; 173 174 sc = device_get_softc(dev); 175 176 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ | 177 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 178 for (i = VTE_PHY_TIMEOUT; i > 0; i--) { 179 DELAY(5); 180 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_READ) == 0) 181 break; 182 } 183 184 if (i == 0) { 185 device_printf(sc->vte_dev, "phy read timeout : %d\n", reg); 186 return (0); 187 } 188 189 return (CSR_READ_2(sc, VTE_MMRD)); 190 } 191 192 static int 193 vte_miibus_writereg(device_t dev, int phy, int reg, int val) 194 { 195 struct vte_softc *sc; 196 int i; 197 198 sc = device_get_softc(dev); 199 200 CSR_WRITE_2(sc, VTE_MMWD, val); 201 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE | 202 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 203 for (i = VTE_PHY_TIMEOUT; i > 0; i--) { 204 DELAY(5); 205 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_WRITE) == 0) 206 break; 207 } 208 209 if (i == 0) 210 device_printf(sc->vte_dev, "phy write timeout : %d\n", reg); 211 212 return (0); 213 } 214 215 static void 216 vte_miibus_statchg(device_t dev) 217 { 218 struct vte_softc *sc; 219 struct mii_data *mii; 220 if_t ifp; 221 uint16_t val; 222 223 sc = device_get_softc(dev); 224 225 mii = device_get_softc(sc->vte_miibus); 226 ifp = sc->vte_ifp; 227 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 228 return; 229 230 sc->vte_flags &= ~VTE_FLAG_LINK; 231 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 232 (IFM_ACTIVE | IFM_AVALID)) { 233 switch (IFM_SUBTYPE(mii->mii_media_active)) { 234 case IFM_10_T: 235 case IFM_100_TX: 236 sc->vte_flags |= VTE_FLAG_LINK; 237 break; 238 default: 239 break; 240 } 241 } 242 243 /* Stop RX/TX MACs. */ 244 vte_stop_mac(sc); 245 /* Program MACs with resolved duplex and flow control. */ 246 if ((sc->vte_flags & VTE_FLAG_LINK) != 0) { 247 /* 248 * Timer waiting time : (63 + TIMER * 64) MII clock. 249 * MII clock : 25MHz(100Mbps) or 2.5MHz(10Mbps). 250 */ 251 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) 252 val = 18 << VTE_IM_TIMER_SHIFT; 253 else 254 val = 1 << VTE_IM_TIMER_SHIFT; 255 val |= sc->vte_int_rx_mod << VTE_IM_BUNDLE_SHIFT; 256 /* 48.6us for 100Mbps, 50.8us for 10Mbps */ 257 CSR_WRITE_2(sc, VTE_MRICR, val); 258 259 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) 260 val = 18 << VTE_IM_TIMER_SHIFT; 261 else 262 val = 1 << VTE_IM_TIMER_SHIFT; 263 val |= sc->vte_int_tx_mod << VTE_IM_BUNDLE_SHIFT; 264 /* 48.6us for 100Mbps, 50.8us for 10Mbps */ 265 CSR_WRITE_2(sc, VTE_MTICR, val); 266 267 vte_mac_config(sc); 268 vte_start_mac(sc); 269 } 270 } 271 272 static void 273 vte_mediastatus(if_t ifp, struct ifmediareq *ifmr) 274 { 275 struct vte_softc *sc; 276 struct mii_data *mii; 277 278 sc = if_getsoftc(ifp); 279 VTE_LOCK(sc); 280 if ((if_getflags(ifp) & IFF_UP) == 0) { 281 VTE_UNLOCK(sc); 282 return; 283 } 284 mii = device_get_softc(sc->vte_miibus); 285 286 mii_pollstat(mii); 287 ifmr->ifm_status = mii->mii_media_status; 288 ifmr->ifm_active = mii->mii_media_active; 289 VTE_UNLOCK(sc); 290 } 291 292 static int 293 vte_mediachange(if_t ifp) 294 { 295 struct vte_softc *sc; 296 int error; 297 298 sc = if_getsoftc(ifp); 299 VTE_LOCK(sc); 300 error = vte_mediachange_locked(ifp); 301 VTE_UNLOCK(sc); 302 return (error); 303 } 304 305 static int 306 vte_mediachange_locked(if_t ifp) 307 { 308 struct vte_softc *sc; 309 struct mii_data *mii; 310 struct mii_softc *miisc; 311 int error; 312 313 sc = if_getsoftc(ifp); 314 mii = device_get_softc(sc->vte_miibus); 315 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 316 PHY_RESET(miisc); 317 error = mii_mediachg(mii); 318 319 return (error); 320 } 321 322 static const struct vte_ident * 323 vte_find_ident(device_t dev) 324 { 325 const struct vte_ident *ident; 326 uint16_t vendor, devid; 327 328 vendor = pci_get_vendor(dev); 329 devid = pci_get_device(dev); 330 for (ident = vte_ident_table; ident->name != NULL; ident++) { 331 if (vendor == ident->vendorid && devid == ident->deviceid) 332 return (ident); 333 } 334 335 return (NULL); 336 } 337 338 static int 339 vte_probe(device_t dev) 340 { 341 const struct vte_ident *ident; 342 343 ident = vte_find_ident(dev); 344 if (ident != NULL) { 345 device_set_desc(dev, ident->name); 346 return (BUS_PROBE_DEFAULT); 347 } 348 349 return (ENXIO); 350 } 351 352 static void 353 vte_get_macaddr(struct vte_softc *sc) 354 { 355 uint16_t mid; 356 357 /* 358 * It seems there is no way to reload station address and 359 * it is supposed to be set by BIOS. 360 */ 361 mid = CSR_READ_2(sc, VTE_MID0L); 362 sc->vte_eaddr[0] = (mid >> 0) & 0xFF; 363 sc->vte_eaddr[1] = (mid >> 8) & 0xFF; 364 mid = CSR_READ_2(sc, VTE_MID0M); 365 sc->vte_eaddr[2] = (mid >> 0) & 0xFF; 366 sc->vte_eaddr[3] = (mid >> 8) & 0xFF; 367 mid = CSR_READ_2(sc, VTE_MID0H); 368 sc->vte_eaddr[4] = (mid >> 0) & 0xFF; 369 sc->vte_eaddr[5] = (mid >> 8) & 0xFF; 370 } 371 372 static int 373 vte_attach(device_t dev) 374 { 375 struct vte_softc *sc; 376 if_t ifp; 377 uint16_t macid; 378 int error, rid; 379 380 error = 0; 381 sc = device_get_softc(dev); 382 sc->vte_dev = dev; 383 384 mtx_init(&sc->vte_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 385 MTX_DEF); 386 callout_init_mtx(&sc->vte_tick_ch, &sc->vte_mtx, 0); 387 sc->vte_ident = vte_find_ident(dev); 388 389 /* Map the device. */ 390 pci_enable_busmaster(dev); 391 sc->vte_res_id = PCIR_BAR(1); 392 sc->vte_res_type = SYS_RES_MEMORY; 393 sc->vte_res = bus_alloc_resource_any(dev, sc->vte_res_type, 394 &sc->vte_res_id, RF_ACTIVE); 395 if (sc->vte_res == NULL) { 396 sc->vte_res_id = PCIR_BAR(0); 397 sc->vte_res_type = SYS_RES_IOPORT; 398 sc->vte_res = bus_alloc_resource_any(dev, sc->vte_res_type, 399 &sc->vte_res_id, RF_ACTIVE); 400 if (sc->vte_res == NULL) { 401 device_printf(dev, "cannot map memory/ports.\n"); 402 mtx_destroy(&sc->vte_mtx); 403 return (ENXIO); 404 } 405 } 406 if (bootverbose) { 407 device_printf(dev, "using %s space register mapping\n", 408 sc->vte_res_type == SYS_RES_MEMORY ? "memory" : "I/O"); 409 device_printf(dev, "MAC Identifier : 0x%04x\n", 410 CSR_READ_2(sc, VTE_MACID)); 411 macid = CSR_READ_2(sc, VTE_MACID_REV); 412 device_printf(dev, "MAC Id. 0x%02x, Rev. 0x%02x\n", 413 (macid & VTE_MACID_MASK) >> VTE_MACID_SHIFT, 414 (macid & VTE_MACID_REV_MASK) >> VTE_MACID_REV_SHIFT); 415 } 416 417 rid = 0; 418 sc->vte_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 419 RF_SHAREABLE | RF_ACTIVE); 420 if (sc->vte_irq == NULL) { 421 device_printf(dev, "cannot allocate IRQ resources.\n"); 422 error = ENXIO; 423 goto fail; 424 } 425 426 /* Reset the ethernet controller. */ 427 vte_reset(sc); 428 429 if ((error = vte_dma_alloc(sc)) != 0) 430 goto fail; 431 432 /* Create device sysctl node. */ 433 vte_sysctl_node(sc); 434 435 /* Load station address. */ 436 vte_get_macaddr(sc); 437 438 ifp = sc->vte_ifp = if_alloc(IFT_ETHER); 439 if_setsoftc(ifp, sc); 440 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 441 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 442 if_setioctlfn(ifp, vte_ioctl); 443 if_setstartfn(ifp, vte_start); 444 if_setinitfn(ifp, vte_init); 445 if_setgetcounterfn(ifp, vte_get_counter); 446 if_setsendqlen(ifp, VTE_TX_RING_CNT - 1); 447 if_setsendqready(ifp); 448 449 /* 450 * Set up MII bus. 451 * BIOS would have initialized VTE_MPSCCR to catch PHY 452 * status changes so driver may be able to extract 453 * configured PHY address. Since it's common to see BIOS 454 * fails to initialize the register(including the sample 455 * board I have), let mii(4) probe it. This is more 456 * reliable than relying on BIOS's initialization. 457 * 458 * Advertising flow control capability to mii(4) was 459 * intentionally disabled due to severe problems in TX 460 * pause frame generation. See vte_rxeof() for more 461 * details. 462 */ 463 error = mii_attach(dev, &sc->vte_miibus, ifp, vte_mediachange, 464 vte_mediastatus, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 465 if (error != 0) { 466 device_printf(dev, "attaching PHYs failed\n"); 467 goto fail; 468 } 469 470 ether_ifattach(ifp, sc->vte_eaddr); 471 472 /* VLAN capability setup. */ 473 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 474 if_setcapenable(ifp, if_getcapabilities(ifp)); 475 /* Tell the upper layer we support VLAN over-sized frames. */ 476 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 477 478 error = bus_setup_intr(dev, sc->vte_irq, INTR_TYPE_NET | INTR_MPSAFE, 479 NULL, vte_intr, sc, &sc->vte_intrhand); 480 if (error != 0) { 481 device_printf(dev, "could not set up interrupt handler.\n"); 482 ether_ifdetach(ifp); 483 goto fail; 484 } 485 486 fail: 487 if (error != 0) 488 vte_detach(dev); 489 490 return (error); 491 } 492 493 static int 494 vte_detach(device_t dev) 495 { 496 struct vte_softc *sc; 497 if_t ifp; 498 499 sc = device_get_softc(dev); 500 501 ifp = sc->vte_ifp; 502 if (device_is_attached(dev)) { 503 VTE_LOCK(sc); 504 vte_stop(sc); 505 VTE_UNLOCK(sc); 506 callout_drain(&sc->vte_tick_ch); 507 ether_ifdetach(ifp); 508 } 509 510 if (sc->vte_miibus != NULL) { 511 device_delete_child(dev, sc->vte_miibus); 512 sc->vte_miibus = NULL; 513 } 514 bus_generic_detach(dev); 515 516 if (sc->vte_intrhand != NULL) { 517 bus_teardown_intr(dev, sc->vte_irq, sc->vte_intrhand); 518 sc->vte_intrhand = NULL; 519 } 520 if (sc->vte_irq != NULL) { 521 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vte_irq); 522 sc->vte_irq = NULL; 523 } 524 if (sc->vte_res != NULL) { 525 bus_release_resource(dev, sc->vte_res_type, sc->vte_res_id, 526 sc->vte_res); 527 sc->vte_res = NULL; 528 } 529 if (ifp != NULL) { 530 if_free(ifp); 531 sc->vte_ifp = NULL; 532 } 533 vte_dma_free(sc); 534 mtx_destroy(&sc->vte_mtx); 535 536 return (0); 537 } 538 539 #define VTE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 540 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 541 542 static void 543 vte_sysctl_node(struct vte_softc *sc) 544 { 545 struct sysctl_ctx_list *ctx; 546 struct sysctl_oid_list *child, *parent; 547 struct sysctl_oid *tree; 548 struct vte_hw_stats *stats; 549 int error; 550 551 stats = &sc->vte_stats; 552 ctx = device_get_sysctl_ctx(sc->vte_dev); 553 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->vte_dev)); 554 555 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 556 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 557 &sc->vte_int_rx_mod, 0, sysctl_hw_vte_int_mod, "I", 558 "vte RX interrupt moderation"); 559 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 560 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 561 &sc->vte_int_tx_mod, 0, sysctl_hw_vte_int_mod, "I", 562 "vte TX interrupt moderation"); 563 /* Pull in device tunables. */ 564 sc->vte_int_rx_mod = VTE_IM_RX_BUNDLE_DEFAULT; 565 error = resource_int_value(device_get_name(sc->vte_dev), 566 device_get_unit(sc->vte_dev), "int_rx_mod", &sc->vte_int_rx_mod); 567 if (error == 0) { 568 if (sc->vte_int_rx_mod < VTE_IM_BUNDLE_MIN || 569 sc->vte_int_rx_mod > VTE_IM_BUNDLE_MAX) { 570 device_printf(sc->vte_dev, "int_rx_mod value out of " 571 "range; using default: %d\n", 572 VTE_IM_RX_BUNDLE_DEFAULT); 573 sc->vte_int_rx_mod = VTE_IM_RX_BUNDLE_DEFAULT; 574 } 575 } 576 577 sc->vte_int_tx_mod = VTE_IM_TX_BUNDLE_DEFAULT; 578 error = resource_int_value(device_get_name(sc->vte_dev), 579 device_get_unit(sc->vte_dev), "int_tx_mod", &sc->vte_int_tx_mod); 580 if (error == 0) { 581 if (sc->vte_int_tx_mod < VTE_IM_BUNDLE_MIN || 582 sc->vte_int_tx_mod > VTE_IM_BUNDLE_MAX) { 583 device_printf(sc->vte_dev, "int_tx_mod value out of " 584 "range; using default: %d\n", 585 VTE_IM_TX_BUNDLE_DEFAULT); 586 sc->vte_int_tx_mod = VTE_IM_TX_BUNDLE_DEFAULT; 587 } 588 } 589 590 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 591 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "VTE statistics"); 592 parent = SYSCTL_CHILDREN(tree); 593 594 /* RX statistics. */ 595 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 596 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX MAC statistics"); 597 child = SYSCTL_CHILDREN(tree); 598 VTE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 599 &stats->rx_frames, "Good frames"); 600 VTE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 601 &stats->rx_bcast_frames, "Good broadcast frames"); 602 VTE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 603 &stats->rx_mcast_frames, "Good multicast frames"); 604 VTE_SYSCTL_STAT_ADD32(ctx, child, "runt", 605 &stats->rx_runts, "Too short frames"); 606 VTE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 607 &stats->rx_crcerrs, "CRC errors"); 608 VTE_SYSCTL_STAT_ADD32(ctx, child, "long_frames", 609 &stats->rx_long_frames, 610 "Frames that have longer length than maximum packet length"); 611 VTE_SYSCTL_STAT_ADD32(ctx, child, "fifo_full", 612 &stats->rx_fifo_full, "FIFO full"); 613 VTE_SYSCTL_STAT_ADD32(ctx, child, "desc_unavail", 614 &stats->rx_desc_unavail, "Descriptor unavailable frames"); 615 VTE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 616 &stats->rx_pause_frames, "Pause control frames"); 617 618 /* TX statistics. */ 619 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 620 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX MAC statistics"); 621 child = SYSCTL_CHILDREN(tree); 622 VTE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 623 &stats->tx_frames, "Good frames"); 624 VTE_SYSCTL_STAT_ADD32(ctx, child, "underruns", 625 &stats->tx_underruns, "FIFO underruns"); 626 VTE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 627 &stats->tx_late_colls, "Late collisions"); 628 VTE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 629 &stats->tx_pause_frames, "Pause control frames"); 630 } 631 632 #undef VTE_SYSCTL_STAT_ADD32 633 634 struct vte_dmamap_arg { 635 bus_addr_t vte_busaddr; 636 }; 637 638 static void 639 vte_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 640 { 641 struct vte_dmamap_arg *ctx; 642 643 if (error != 0) 644 return; 645 646 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 647 648 ctx = (struct vte_dmamap_arg *)arg; 649 ctx->vte_busaddr = segs[0].ds_addr; 650 } 651 652 static int 653 vte_dma_alloc(struct vte_softc *sc) 654 { 655 struct vte_txdesc *txd; 656 struct vte_rxdesc *rxd; 657 struct vte_dmamap_arg ctx; 658 int error, i; 659 660 /* Create parent DMA tag. */ 661 error = bus_dma_tag_create( 662 bus_get_dma_tag(sc->vte_dev), /* parent */ 663 1, 0, /* alignment, boundary */ 664 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 665 BUS_SPACE_MAXADDR, /* highaddr */ 666 NULL, NULL, /* filter, filterarg */ 667 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 668 0, /* nsegments */ 669 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 670 0, /* flags */ 671 NULL, NULL, /* lockfunc, lockarg */ 672 &sc->vte_cdata.vte_parent_tag); 673 if (error != 0) { 674 device_printf(sc->vte_dev, 675 "could not create parent DMA tag.\n"); 676 goto fail; 677 } 678 679 /* Create DMA tag for TX descriptor ring. */ 680 error = bus_dma_tag_create( 681 sc->vte_cdata.vte_parent_tag, /* parent */ 682 VTE_TX_RING_ALIGN, 0, /* alignment, boundary */ 683 BUS_SPACE_MAXADDR, /* lowaddr */ 684 BUS_SPACE_MAXADDR, /* highaddr */ 685 NULL, NULL, /* filter, filterarg */ 686 VTE_TX_RING_SZ, /* maxsize */ 687 1, /* nsegments */ 688 VTE_TX_RING_SZ, /* maxsegsize */ 689 0, /* flags */ 690 NULL, NULL, /* lockfunc, lockarg */ 691 &sc->vte_cdata.vte_tx_ring_tag); 692 if (error != 0) { 693 device_printf(sc->vte_dev, 694 "could not create TX ring DMA tag.\n"); 695 goto fail; 696 } 697 698 /* Create DMA tag for RX free descriptor ring. */ 699 error = bus_dma_tag_create( 700 sc->vte_cdata.vte_parent_tag, /* parent */ 701 VTE_RX_RING_ALIGN, 0, /* alignment, boundary */ 702 BUS_SPACE_MAXADDR, /* lowaddr */ 703 BUS_SPACE_MAXADDR, /* highaddr */ 704 NULL, NULL, /* filter, filterarg */ 705 VTE_RX_RING_SZ, /* maxsize */ 706 1, /* nsegments */ 707 VTE_RX_RING_SZ, /* maxsegsize */ 708 0, /* flags */ 709 NULL, NULL, /* lockfunc, lockarg */ 710 &sc->vte_cdata.vte_rx_ring_tag); 711 if (error != 0) { 712 device_printf(sc->vte_dev, 713 "could not create RX ring DMA tag.\n"); 714 goto fail; 715 } 716 717 /* Allocate DMA'able memory and load the DMA map for TX ring. */ 718 error = bus_dmamem_alloc(sc->vte_cdata.vte_tx_ring_tag, 719 (void **)&sc->vte_cdata.vte_tx_ring, 720 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 721 &sc->vte_cdata.vte_tx_ring_map); 722 if (error != 0) { 723 device_printf(sc->vte_dev, 724 "could not allocate DMA'able memory for TX ring.\n"); 725 goto fail; 726 } 727 ctx.vte_busaddr = 0; 728 error = bus_dmamap_load(sc->vte_cdata.vte_tx_ring_tag, 729 sc->vte_cdata.vte_tx_ring_map, sc->vte_cdata.vte_tx_ring, 730 VTE_TX_RING_SZ, vte_dmamap_cb, &ctx, 0); 731 if (error != 0 || ctx.vte_busaddr == 0) { 732 device_printf(sc->vte_dev, 733 "could not load DMA'able memory for TX ring.\n"); 734 goto fail; 735 } 736 sc->vte_cdata.vte_tx_ring_paddr = ctx.vte_busaddr; 737 738 /* Allocate DMA'able memory and load the DMA map for RX ring. */ 739 error = bus_dmamem_alloc(sc->vte_cdata.vte_rx_ring_tag, 740 (void **)&sc->vte_cdata.vte_rx_ring, 741 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 742 &sc->vte_cdata.vte_rx_ring_map); 743 if (error != 0) { 744 device_printf(sc->vte_dev, 745 "could not allocate DMA'able memory for RX ring.\n"); 746 goto fail; 747 } 748 ctx.vte_busaddr = 0; 749 error = bus_dmamap_load(sc->vte_cdata.vte_rx_ring_tag, 750 sc->vte_cdata.vte_rx_ring_map, sc->vte_cdata.vte_rx_ring, 751 VTE_RX_RING_SZ, vte_dmamap_cb, &ctx, 0); 752 if (error != 0 || ctx.vte_busaddr == 0) { 753 device_printf(sc->vte_dev, 754 "could not load DMA'able memory for RX ring.\n"); 755 goto fail; 756 } 757 sc->vte_cdata.vte_rx_ring_paddr = ctx.vte_busaddr; 758 759 /* Create TX buffer parent tag. */ 760 error = bus_dma_tag_create( 761 bus_get_dma_tag(sc->vte_dev), /* parent */ 762 1, 0, /* alignment, boundary */ 763 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 764 BUS_SPACE_MAXADDR, /* highaddr */ 765 NULL, NULL, /* filter, filterarg */ 766 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 767 0, /* nsegments */ 768 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 769 0, /* flags */ 770 NULL, NULL, /* lockfunc, lockarg */ 771 &sc->vte_cdata.vte_buffer_tag); 772 if (error != 0) { 773 device_printf(sc->vte_dev, 774 "could not create parent buffer DMA tag.\n"); 775 goto fail; 776 } 777 778 /* Create DMA tag for TX buffers. */ 779 error = bus_dma_tag_create( 780 sc->vte_cdata.vte_buffer_tag, /* parent */ 781 1, 0, /* alignment, boundary */ 782 BUS_SPACE_MAXADDR, /* lowaddr */ 783 BUS_SPACE_MAXADDR, /* highaddr */ 784 NULL, NULL, /* filter, filterarg */ 785 MCLBYTES, /* maxsize */ 786 1, /* nsegments */ 787 MCLBYTES, /* maxsegsize */ 788 0, /* flags */ 789 NULL, NULL, /* lockfunc, lockarg */ 790 &sc->vte_cdata.vte_tx_tag); 791 if (error != 0) { 792 device_printf(sc->vte_dev, "could not create TX DMA tag.\n"); 793 goto fail; 794 } 795 796 /* Create DMA tag for RX buffers. */ 797 error = bus_dma_tag_create( 798 sc->vte_cdata.vte_buffer_tag, /* parent */ 799 VTE_RX_BUF_ALIGN, 0, /* alignment, boundary */ 800 BUS_SPACE_MAXADDR, /* lowaddr */ 801 BUS_SPACE_MAXADDR, /* highaddr */ 802 NULL, NULL, /* filter, filterarg */ 803 MCLBYTES, /* maxsize */ 804 1, /* nsegments */ 805 MCLBYTES, /* maxsegsize */ 806 0, /* flags */ 807 NULL, NULL, /* lockfunc, lockarg */ 808 &sc->vte_cdata.vte_rx_tag); 809 if (error != 0) { 810 device_printf(sc->vte_dev, "could not create RX DMA tag.\n"); 811 goto fail; 812 } 813 /* Create DMA maps for TX buffers. */ 814 for (i = 0; i < VTE_TX_RING_CNT; i++) { 815 txd = &sc->vte_cdata.vte_txdesc[i]; 816 txd->tx_m = NULL; 817 txd->tx_dmamap = NULL; 818 error = bus_dmamap_create(sc->vte_cdata.vte_tx_tag, 0, 819 &txd->tx_dmamap); 820 if (error != 0) { 821 device_printf(sc->vte_dev, 822 "could not create TX dmamap.\n"); 823 goto fail; 824 } 825 } 826 /* Create DMA maps for RX buffers. */ 827 if ((error = bus_dmamap_create(sc->vte_cdata.vte_rx_tag, 0, 828 &sc->vte_cdata.vte_rx_sparemap)) != 0) { 829 device_printf(sc->vte_dev, 830 "could not create spare RX dmamap.\n"); 831 goto fail; 832 } 833 for (i = 0; i < VTE_RX_RING_CNT; i++) { 834 rxd = &sc->vte_cdata.vte_rxdesc[i]; 835 rxd->rx_m = NULL; 836 rxd->rx_dmamap = NULL; 837 error = bus_dmamap_create(sc->vte_cdata.vte_rx_tag, 0, 838 &rxd->rx_dmamap); 839 if (error != 0) { 840 device_printf(sc->vte_dev, 841 "could not create RX dmamap.\n"); 842 goto fail; 843 } 844 } 845 846 fail: 847 return (error); 848 } 849 850 static void 851 vte_dma_free(struct vte_softc *sc) 852 { 853 struct vte_txdesc *txd; 854 struct vte_rxdesc *rxd; 855 int i; 856 857 /* TX buffers. */ 858 if (sc->vte_cdata.vte_tx_tag != NULL) { 859 for (i = 0; i < VTE_TX_RING_CNT; i++) { 860 txd = &sc->vte_cdata.vte_txdesc[i]; 861 if (txd->tx_dmamap != NULL) { 862 bus_dmamap_destroy(sc->vte_cdata.vte_tx_tag, 863 txd->tx_dmamap); 864 txd->tx_dmamap = NULL; 865 } 866 } 867 bus_dma_tag_destroy(sc->vte_cdata.vte_tx_tag); 868 sc->vte_cdata.vte_tx_tag = NULL; 869 } 870 /* RX buffers */ 871 if (sc->vte_cdata.vte_rx_tag != NULL) { 872 for (i = 0; i < VTE_RX_RING_CNT; i++) { 873 rxd = &sc->vte_cdata.vte_rxdesc[i]; 874 if (rxd->rx_dmamap != NULL) { 875 bus_dmamap_destroy(sc->vte_cdata.vte_rx_tag, 876 rxd->rx_dmamap); 877 rxd->rx_dmamap = NULL; 878 } 879 } 880 if (sc->vte_cdata.vte_rx_sparemap != NULL) { 881 bus_dmamap_destroy(sc->vte_cdata.vte_rx_tag, 882 sc->vte_cdata.vte_rx_sparemap); 883 sc->vte_cdata.vte_rx_sparemap = NULL; 884 } 885 bus_dma_tag_destroy(sc->vte_cdata.vte_rx_tag); 886 sc->vte_cdata.vte_rx_tag = NULL; 887 } 888 /* TX descriptor ring. */ 889 if (sc->vte_cdata.vte_tx_ring_tag != NULL) { 890 if (sc->vte_cdata.vte_tx_ring_paddr != 0) 891 bus_dmamap_unload(sc->vte_cdata.vte_tx_ring_tag, 892 sc->vte_cdata.vte_tx_ring_map); 893 if (sc->vte_cdata.vte_tx_ring != NULL) 894 bus_dmamem_free(sc->vte_cdata.vte_tx_ring_tag, 895 sc->vte_cdata.vte_tx_ring, 896 sc->vte_cdata.vte_tx_ring_map); 897 sc->vte_cdata.vte_tx_ring = NULL; 898 sc->vte_cdata.vte_tx_ring_paddr = 0; 899 bus_dma_tag_destroy(sc->vte_cdata.vte_tx_ring_tag); 900 sc->vte_cdata.vte_tx_ring_tag = NULL; 901 } 902 /* RX ring. */ 903 if (sc->vte_cdata.vte_rx_ring_tag != NULL) { 904 if (sc->vte_cdata.vte_rx_ring_paddr != 0) 905 bus_dmamap_unload(sc->vte_cdata.vte_rx_ring_tag, 906 sc->vte_cdata.vte_rx_ring_map); 907 if (sc->vte_cdata.vte_rx_ring != NULL) 908 bus_dmamem_free(sc->vte_cdata.vte_rx_ring_tag, 909 sc->vte_cdata.vte_rx_ring, 910 sc->vte_cdata.vte_rx_ring_map); 911 sc->vte_cdata.vte_rx_ring = NULL; 912 sc->vte_cdata.vte_rx_ring_paddr = 0; 913 bus_dma_tag_destroy(sc->vte_cdata.vte_rx_ring_tag); 914 sc->vte_cdata.vte_rx_ring_tag = NULL; 915 } 916 if (sc->vte_cdata.vte_buffer_tag != NULL) { 917 bus_dma_tag_destroy(sc->vte_cdata.vte_buffer_tag); 918 sc->vte_cdata.vte_buffer_tag = NULL; 919 } 920 if (sc->vte_cdata.vte_parent_tag != NULL) { 921 bus_dma_tag_destroy(sc->vte_cdata.vte_parent_tag); 922 sc->vte_cdata.vte_parent_tag = NULL; 923 } 924 } 925 926 static int 927 vte_shutdown(device_t dev) 928 { 929 930 return (vte_suspend(dev)); 931 } 932 933 static int 934 vte_suspend(device_t dev) 935 { 936 struct vte_softc *sc; 937 if_t ifp; 938 939 sc = device_get_softc(dev); 940 941 VTE_LOCK(sc); 942 ifp = sc->vte_ifp; 943 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 944 vte_stop(sc); 945 VTE_UNLOCK(sc); 946 947 return (0); 948 } 949 950 static int 951 vte_resume(device_t dev) 952 { 953 struct vte_softc *sc; 954 if_t ifp; 955 956 sc = device_get_softc(dev); 957 958 VTE_LOCK(sc); 959 ifp = sc->vte_ifp; 960 if ((if_getflags(ifp) & IFF_UP) != 0) { 961 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 962 vte_init_locked(sc); 963 } 964 VTE_UNLOCK(sc); 965 966 return (0); 967 } 968 969 static struct vte_txdesc * 970 vte_encap(struct vte_softc *sc, struct mbuf **m_head) 971 { 972 struct vte_txdesc *txd; 973 struct mbuf *m, *n; 974 bus_dma_segment_t txsegs[1]; 975 int copy, error, nsegs, padlen; 976 977 VTE_LOCK_ASSERT(sc); 978 979 M_ASSERTPKTHDR((*m_head)); 980 981 txd = &sc->vte_cdata.vte_txdesc[sc->vte_cdata.vte_tx_prod]; 982 m = *m_head; 983 /* 984 * Controller doesn't auto-pad, so we have to make sure pad 985 * short frames out to the minimum frame length. 986 */ 987 if (m->m_pkthdr.len < VTE_MIN_FRAMELEN) 988 padlen = VTE_MIN_FRAMELEN - m->m_pkthdr.len; 989 else 990 padlen = 0; 991 992 /* 993 * Controller does not support multi-fragmented TX buffers. 994 * Controller spends most of its TX processing time in 995 * de-fragmenting TX buffers. Either faster CPU or more 996 * advanced controller DMA engine is required to speed up 997 * TX path processing. 998 * To mitigate the de-fragmenting issue, perform deep copy 999 * from fragmented mbuf chains to a pre-allocated mbuf 1000 * cluster with extra cost of kernel memory. For frames 1001 * that is composed of single TX buffer, the deep copy is 1002 * bypassed. 1003 */ 1004 if (tx_deep_copy != 0) { 1005 copy = 0; 1006 if (m->m_next != NULL) 1007 copy++; 1008 if (padlen > 0 && (M_WRITABLE(m) == 0 || 1009 padlen > M_TRAILINGSPACE(m))) 1010 copy++; 1011 if (copy != 0) { 1012 /* Avoid expensive m_defrag(9) and do deep copy. */ 1013 n = sc->vte_cdata.vte_txmbufs[sc->vte_cdata.vte_tx_prod]; 1014 m_copydata(m, 0, m->m_pkthdr.len, mtod(n, char *)); 1015 n->m_pkthdr.len = m->m_pkthdr.len; 1016 n->m_len = m->m_pkthdr.len; 1017 m = n; 1018 txd->tx_flags |= VTE_TXMBUF; 1019 } 1020 1021 if (padlen > 0) { 1022 /* Zero out the bytes in the pad area. */ 1023 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1024 m->m_pkthdr.len += padlen; 1025 m->m_len = m->m_pkthdr.len; 1026 } 1027 } else { 1028 if (M_WRITABLE(m) == 0) { 1029 if (m->m_next != NULL || padlen > 0) { 1030 /* Get a writable copy. */ 1031 m = m_dup(*m_head, M_NOWAIT); 1032 /* Release original mbuf chains. */ 1033 m_freem(*m_head); 1034 if (m == NULL) { 1035 *m_head = NULL; 1036 return (NULL); 1037 } 1038 *m_head = m; 1039 } 1040 } 1041 1042 if (m->m_next != NULL) { 1043 m = m_defrag(*m_head, M_NOWAIT); 1044 if (m == NULL) { 1045 m_freem(*m_head); 1046 *m_head = NULL; 1047 return (NULL); 1048 } 1049 *m_head = m; 1050 } 1051 1052 if (padlen > 0) { 1053 if (M_TRAILINGSPACE(m) < padlen) { 1054 m = m_defrag(*m_head, M_NOWAIT); 1055 if (m == NULL) { 1056 m_freem(*m_head); 1057 *m_head = NULL; 1058 return (NULL); 1059 } 1060 *m_head = m; 1061 } 1062 /* Zero out the bytes in the pad area. */ 1063 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1064 m->m_pkthdr.len += padlen; 1065 m->m_len = m->m_pkthdr.len; 1066 } 1067 } 1068 1069 error = bus_dmamap_load_mbuf_sg(sc->vte_cdata.vte_tx_tag, 1070 txd->tx_dmamap, m, txsegs, &nsegs, 0); 1071 if (error != 0) { 1072 txd->tx_flags &= ~VTE_TXMBUF; 1073 return (NULL); 1074 } 1075 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1076 bus_dmamap_sync(sc->vte_cdata.vte_tx_tag, txd->tx_dmamap, 1077 BUS_DMASYNC_PREWRITE); 1078 1079 txd->tx_desc->dtlen = htole16(VTE_TX_LEN(txsegs[0].ds_len)); 1080 txd->tx_desc->dtbp = htole32(txsegs[0].ds_addr); 1081 sc->vte_cdata.vte_tx_cnt++; 1082 /* Update producer index. */ 1083 VTE_DESC_INC(sc->vte_cdata.vte_tx_prod, VTE_TX_RING_CNT); 1084 1085 /* Finally hand over ownership to controller. */ 1086 txd->tx_desc->dtst = htole16(VTE_DTST_TX_OWN); 1087 txd->tx_m = m; 1088 1089 return (txd); 1090 } 1091 1092 static void 1093 vte_start(if_t ifp) 1094 { 1095 struct vte_softc *sc; 1096 1097 sc = if_getsoftc(ifp); 1098 VTE_LOCK(sc); 1099 vte_start_locked(sc); 1100 VTE_UNLOCK(sc); 1101 } 1102 1103 static void 1104 vte_start_locked(struct vte_softc *sc) 1105 { 1106 if_t ifp; 1107 struct vte_txdesc *txd; 1108 struct mbuf *m_head; 1109 int enq; 1110 1111 ifp = sc->vte_ifp; 1112 1113 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1114 IFF_DRV_RUNNING || (sc->vte_flags & VTE_FLAG_LINK) == 0) 1115 return; 1116 1117 for (enq = 0; !if_sendq_empty(ifp); ) { 1118 /* Reserve one free TX descriptor. */ 1119 if (sc->vte_cdata.vte_tx_cnt >= VTE_TX_RING_CNT - 1) { 1120 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1121 break; 1122 } 1123 m_head = if_dequeue(ifp); 1124 if (m_head == NULL) 1125 break; 1126 /* 1127 * Pack the data into the transmit ring. If we 1128 * don't have room, set the OACTIVE flag and wait 1129 * for the NIC to drain the ring. 1130 */ 1131 if ((txd = vte_encap(sc, &m_head)) == NULL) { 1132 if (m_head != NULL) 1133 if_sendq_prepend(ifp, m_head); 1134 break; 1135 } 1136 1137 enq++; 1138 /* 1139 * If there's a BPF listener, bounce a copy of this frame 1140 * to him. 1141 */ 1142 ETHER_BPF_MTAP(ifp, m_head); 1143 /* Free consumed TX frame. */ 1144 if ((txd->tx_flags & VTE_TXMBUF) != 0) 1145 m_freem(m_head); 1146 } 1147 1148 if (enq > 0) { 1149 bus_dmamap_sync(sc->vte_cdata.vte_tx_ring_tag, 1150 sc->vte_cdata.vte_tx_ring_map, BUS_DMASYNC_PREREAD | 1151 BUS_DMASYNC_PREWRITE); 1152 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START); 1153 sc->vte_watchdog_timer = VTE_TX_TIMEOUT; 1154 } 1155 } 1156 1157 static void 1158 vte_watchdog(struct vte_softc *sc) 1159 { 1160 if_t ifp; 1161 1162 VTE_LOCK_ASSERT(sc); 1163 1164 if (sc->vte_watchdog_timer == 0 || --sc->vte_watchdog_timer) 1165 return; 1166 1167 ifp = sc->vte_ifp; 1168 if_printf(sc->vte_ifp, "watchdog timeout -- resetting\n"); 1169 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1170 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1171 vte_init_locked(sc); 1172 if (!if_sendq_empty(ifp)) 1173 vte_start_locked(sc); 1174 } 1175 1176 static int 1177 vte_ioctl(if_t ifp, u_long cmd, caddr_t data) 1178 { 1179 struct vte_softc *sc; 1180 struct ifreq *ifr; 1181 struct mii_data *mii; 1182 int error; 1183 1184 sc = if_getsoftc(ifp); 1185 ifr = (struct ifreq *)data; 1186 error = 0; 1187 switch (cmd) { 1188 case SIOCSIFFLAGS: 1189 VTE_LOCK(sc); 1190 if ((if_getflags(ifp) & IFF_UP) != 0) { 1191 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 1192 ((if_getflags(ifp) ^ sc->vte_if_flags) & 1193 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1194 vte_rxfilter(sc); 1195 else 1196 vte_init_locked(sc); 1197 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1198 vte_stop(sc); 1199 sc->vte_if_flags = if_getflags(ifp); 1200 VTE_UNLOCK(sc); 1201 break; 1202 case SIOCADDMULTI: 1203 case SIOCDELMULTI: 1204 VTE_LOCK(sc); 1205 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1206 vte_rxfilter(sc); 1207 VTE_UNLOCK(sc); 1208 break; 1209 case SIOCSIFMEDIA: 1210 case SIOCGIFMEDIA: 1211 mii = device_get_softc(sc->vte_miibus); 1212 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1213 break; 1214 default: 1215 error = ether_ioctl(ifp, cmd, data); 1216 break; 1217 } 1218 1219 return (error); 1220 } 1221 1222 static void 1223 vte_mac_config(struct vte_softc *sc) 1224 { 1225 struct mii_data *mii; 1226 uint16_t mcr; 1227 1228 VTE_LOCK_ASSERT(sc); 1229 1230 mii = device_get_softc(sc->vte_miibus); 1231 mcr = CSR_READ_2(sc, VTE_MCR0); 1232 mcr &= ~(MCR0_FC_ENB | MCR0_FULL_DUPLEX); 1233 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1234 mcr |= MCR0_FULL_DUPLEX; 1235 #ifdef notyet 1236 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1237 mcr |= MCR0_FC_ENB; 1238 /* 1239 * The data sheet is not clear whether the controller 1240 * honors received pause frames or not. The is no 1241 * separate control bit for RX pause frame so just 1242 * enable MCR0_FC_ENB bit. 1243 */ 1244 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1245 mcr |= MCR0_FC_ENB; 1246 #endif 1247 } 1248 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1249 } 1250 1251 static void 1252 vte_stats_clear(struct vte_softc *sc) 1253 { 1254 1255 /* Reading counter registers clears its contents. */ 1256 CSR_READ_2(sc, VTE_CNT_RX_DONE); 1257 CSR_READ_2(sc, VTE_CNT_MECNT0); 1258 CSR_READ_2(sc, VTE_CNT_MECNT1); 1259 CSR_READ_2(sc, VTE_CNT_MECNT2); 1260 CSR_READ_2(sc, VTE_CNT_MECNT3); 1261 CSR_READ_2(sc, VTE_CNT_TX_DONE); 1262 CSR_READ_2(sc, VTE_CNT_MECNT4); 1263 CSR_READ_2(sc, VTE_CNT_PAUSE); 1264 } 1265 1266 static void 1267 vte_stats_update(struct vte_softc *sc) 1268 { 1269 struct vte_hw_stats *stat; 1270 uint16_t value; 1271 1272 VTE_LOCK_ASSERT(sc); 1273 1274 stat = &sc->vte_stats; 1275 1276 CSR_READ_2(sc, VTE_MECISR); 1277 /* RX stats. */ 1278 stat->rx_frames += CSR_READ_2(sc, VTE_CNT_RX_DONE); 1279 value = CSR_READ_2(sc, VTE_CNT_MECNT0); 1280 stat->rx_bcast_frames += (value >> 8); 1281 stat->rx_mcast_frames += (value & 0xFF); 1282 value = CSR_READ_2(sc, VTE_CNT_MECNT1); 1283 stat->rx_runts += (value >> 8); 1284 stat->rx_crcerrs += (value & 0xFF); 1285 value = CSR_READ_2(sc, VTE_CNT_MECNT2); 1286 stat->rx_long_frames += (value & 0xFF); 1287 value = CSR_READ_2(sc, VTE_CNT_MECNT3); 1288 stat->rx_fifo_full += (value >> 8); 1289 stat->rx_desc_unavail += (value & 0xFF); 1290 1291 /* TX stats. */ 1292 stat->tx_frames += CSR_READ_2(sc, VTE_CNT_TX_DONE); 1293 value = CSR_READ_2(sc, VTE_CNT_MECNT4); 1294 stat->tx_underruns += (value >> 8); 1295 stat->tx_late_colls += (value & 0xFF); 1296 1297 value = CSR_READ_2(sc, VTE_CNT_PAUSE); 1298 stat->tx_pause_frames += (value >> 8); 1299 stat->rx_pause_frames += (value & 0xFF); 1300 } 1301 1302 static uint64_t 1303 vte_get_counter(if_t ifp, ift_counter cnt) 1304 { 1305 struct vte_softc *sc; 1306 struct vte_hw_stats *stat; 1307 1308 sc = if_getsoftc(ifp); 1309 stat = &sc->vte_stats; 1310 1311 switch (cnt) { 1312 case IFCOUNTER_OPACKETS: 1313 return (stat->tx_frames); 1314 case IFCOUNTER_COLLISIONS: 1315 return (stat->tx_late_colls); 1316 case IFCOUNTER_OERRORS: 1317 return (stat->tx_late_colls + stat->tx_underruns); 1318 case IFCOUNTER_IPACKETS: 1319 return (stat->rx_frames); 1320 case IFCOUNTER_IERRORS: 1321 return (stat->rx_crcerrs + stat->rx_runts + 1322 stat->rx_long_frames + stat->rx_fifo_full); 1323 default: 1324 return (if_get_counter_default(ifp, cnt)); 1325 } 1326 } 1327 1328 static void 1329 vte_intr(void *arg) 1330 { 1331 struct vte_softc *sc; 1332 if_t ifp; 1333 uint16_t status; 1334 int n; 1335 1336 sc = (struct vte_softc *)arg; 1337 VTE_LOCK(sc); 1338 1339 ifp = sc->vte_ifp; 1340 /* Reading VTE_MISR acknowledges interrupts. */ 1341 status = CSR_READ_2(sc, VTE_MISR); 1342 if ((status & VTE_INTRS) == 0) { 1343 /* Not ours. */ 1344 VTE_UNLOCK(sc); 1345 return; 1346 } 1347 1348 /* Disable interrupts. */ 1349 CSR_WRITE_2(sc, VTE_MIER, 0); 1350 for (n = 8; (status & VTE_INTRS) != 0;) { 1351 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 1352 break; 1353 if ((status & (MISR_RX_DONE | MISR_RX_DESC_UNAVAIL | 1354 MISR_RX_FIFO_FULL)) != 0) 1355 vte_rxeof(sc); 1356 if ((status & MISR_TX_DONE) != 0) 1357 vte_txeof(sc); 1358 if ((status & MISR_EVENT_CNT_OFLOW) != 0) 1359 vte_stats_update(sc); 1360 if (!if_sendq_empty(ifp)) 1361 vte_start_locked(sc); 1362 if (--n > 0) 1363 status = CSR_READ_2(sc, VTE_MISR); 1364 else 1365 break; 1366 } 1367 1368 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1369 /* Re-enable interrupts. */ 1370 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); 1371 } 1372 VTE_UNLOCK(sc); 1373 } 1374 1375 static void 1376 vte_txeof(struct vte_softc *sc) 1377 { 1378 if_t ifp; 1379 struct vte_txdesc *txd; 1380 uint16_t status; 1381 int cons, prog; 1382 1383 VTE_LOCK_ASSERT(sc); 1384 1385 ifp = sc->vte_ifp; 1386 1387 if (sc->vte_cdata.vte_tx_cnt == 0) 1388 return; 1389 bus_dmamap_sync(sc->vte_cdata.vte_tx_ring_tag, 1390 sc->vte_cdata.vte_tx_ring_map, BUS_DMASYNC_POSTREAD | 1391 BUS_DMASYNC_POSTWRITE); 1392 cons = sc->vte_cdata.vte_tx_cons; 1393 /* 1394 * Go through our TX list and free mbufs for those 1395 * frames which have been transmitted. 1396 */ 1397 for (prog = 0; sc->vte_cdata.vte_tx_cnt > 0; prog++) { 1398 txd = &sc->vte_cdata.vte_txdesc[cons]; 1399 status = le16toh(txd->tx_desc->dtst); 1400 if ((status & VTE_DTST_TX_OWN) != 0) 1401 break; 1402 sc->vte_cdata.vte_tx_cnt--; 1403 /* Reclaim transmitted mbufs. */ 1404 bus_dmamap_sync(sc->vte_cdata.vte_tx_tag, txd->tx_dmamap, 1405 BUS_DMASYNC_POSTWRITE); 1406 bus_dmamap_unload(sc->vte_cdata.vte_tx_tag, txd->tx_dmamap); 1407 if ((txd->tx_flags & VTE_TXMBUF) == 0) 1408 m_freem(txd->tx_m); 1409 txd->tx_flags &= ~VTE_TXMBUF; 1410 txd->tx_m = NULL; 1411 prog++; 1412 VTE_DESC_INC(cons, VTE_TX_RING_CNT); 1413 } 1414 1415 if (prog > 0) { 1416 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1417 sc->vte_cdata.vte_tx_cons = cons; 1418 /* 1419 * Unarm watchdog timer only when there is no pending 1420 * frames in TX queue. 1421 */ 1422 if (sc->vte_cdata.vte_tx_cnt == 0) 1423 sc->vte_watchdog_timer = 0; 1424 } 1425 } 1426 1427 static int 1428 vte_newbuf(struct vte_softc *sc, struct vte_rxdesc *rxd) 1429 { 1430 struct mbuf *m; 1431 bus_dma_segment_t segs[1]; 1432 bus_dmamap_t map; 1433 int nsegs; 1434 1435 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1436 if (m == NULL) 1437 return (ENOBUFS); 1438 m->m_len = m->m_pkthdr.len = MCLBYTES; 1439 m_adj(m, sizeof(uint32_t)); 1440 1441 if (bus_dmamap_load_mbuf_sg(sc->vte_cdata.vte_rx_tag, 1442 sc->vte_cdata.vte_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1443 m_freem(m); 1444 return (ENOBUFS); 1445 } 1446 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1447 1448 if (rxd->rx_m != NULL) { 1449 bus_dmamap_sync(sc->vte_cdata.vte_rx_tag, rxd->rx_dmamap, 1450 BUS_DMASYNC_POSTREAD); 1451 bus_dmamap_unload(sc->vte_cdata.vte_rx_tag, rxd->rx_dmamap); 1452 } 1453 map = rxd->rx_dmamap; 1454 rxd->rx_dmamap = sc->vte_cdata.vte_rx_sparemap; 1455 sc->vte_cdata.vte_rx_sparemap = map; 1456 bus_dmamap_sync(sc->vte_cdata.vte_rx_tag, rxd->rx_dmamap, 1457 BUS_DMASYNC_PREREAD); 1458 rxd->rx_m = m; 1459 rxd->rx_desc->drbp = htole32(segs[0].ds_addr); 1460 rxd->rx_desc->drlen = htole16(VTE_RX_LEN(segs[0].ds_len)); 1461 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1462 1463 return (0); 1464 } 1465 1466 /* 1467 * It's not supposed to see this controller on strict-alignment 1468 * architectures but make it work for completeness. 1469 */ 1470 #ifndef __NO_STRICT_ALIGNMENT 1471 static struct mbuf * 1472 vte_fixup_rx(if_t ifp, struct mbuf *m) 1473 { 1474 uint16_t *src, *dst; 1475 int i; 1476 1477 src = mtod(m, uint16_t *); 1478 dst = src - 1; 1479 1480 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1481 *dst++ = *src++; 1482 m->m_data -= ETHER_ALIGN; 1483 return (m); 1484 } 1485 #endif 1486 1487 static void 1488 vte_rxeof(struct vte_softc *sc) 1489 { 1490 if_t ifp; 1491 struct vte_rxdesc *rxd; 1492 struct mbuf *m; 1493 uint16_t status, total_len; 1494 int cons, prog; 1495 1496 bus_dmamap_sync(sc->vte_cdata.vte_rx_ring_tag, 1497 sc->vte_cdata.vte_rx_ring_map, BUS_DMASYNC_POSTREAD | 1498 BUS_DMASYNC_POSTWRITE); 1499 cons = sc->vte_cdata.vte_rx_cons; 1500 ifp = sc->vte_ifp; 1501 for (prog = 0; (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0; prog++, 1502 VTE_DESC_INC(cons, VTE_RX_RING_CNT)) { 1503 rxd = &sc->vte_cdata.vte_rxdesc[cons]; 1504 status = le16toh(rxd->rx_desc->drst); 1505 if ((status & VTE_DRST_RX_OWN) != 0) 1506 break; 1507 total_len = VTE_RX_LEN(le16toh(rxd->rx_desc->drlen)); 1508 m = rxd->rx_m; 1509 if ((status & VTE_DRST_RX_OK) == 0) { 1510 /* Discard errored frame. */ 1511 rxd->rx_desc->drlen = 1512 htole16(MCLBYTES - sizeof(uint32_t)); 1513 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1514 continue; 1515 } 1516 if (vte_newbuf(sc, rxd) != 0) { 1517 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1518 rxd->rx_desc->drlen = 1519 htole16(MCLBYTES - sizeof(uint32_t)); 1520 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1521 continue; 1522 } 1523 1524 /* 1525 * It seems there is no way to strip FCS bytes. 1526 */ 1527 m->m_pkthdr.len = m->m_len = total_len - ETHER_CRC_LEN; 1528 m->m_pkthdr.rcvif = ifp; 1529 #ifndef __NO_STRICT_ALIGNMENT 1530 vte_fixup_rx(ifp, m); 1531 #endif 1532 VTE_UNLOCK(sc); 1533 if_input(ifp, m); 1534 VTE_LOCK(sc); 1535 } 1536 1537 if (prog > 0) { 1538 /* Update the consumer index. */ 1539 sc->vte_cdata.vte_rx_cons = cons; 1540 /* 1541 * Sync updated RX descriptors such that controller see 1542 * modified RX buffer addresses. 1543 */ 1544 bus_dmamap_sync(sc->vte_cdata.vte_rx_ring_tag, 1545 sc->vte_cdata.vte_rx_ring_map, 1546 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1547 #ifdef notyet 1548 /* 1549 * Update residue counter. Controller does not 1550 * keep track of number of available RX descriptors 1551 * such that driver should have to update VTE_MRDCR 1552 * to make controller know how many free RX 1553 * descriptors were added to controller. This is 1554 * a similar mechanism used in VIA velocity 1555 * controllers and it indicates controller just 1556 * polls OWN bit of current RX descriptor pointer. 1557 * A couple of severe issues were seen on sample 1558 * board where the controller continuously emits TX 1559 * pause frames once RX pause threshold crossed. 1560 * Once triggered it never recovered form that 1561 * state, I couldn't find a way to make it back to 1562 * work at least. This issue effectively 1563 * disconnected the system from network. Also, the 1564 * controller used 00:00:00:00:00:00 as source 1565 * station address of TX pause frame. Probably this 1566 * is one of reason why vendor recommends not to 1567 * enable flow control on R6040 controller. 1568 */ 1569 CSR_WRITE_2(sc, VTE_MRDCR, prog | 1570 (((VTE_RX_RING_CNT * 2) / 10) << 1571 VTE_MRDCR_RX_PAUSE_THRESH_SHIFT)); 1572 #endif 1573 } 1574 } 1575 1576 static void 1577 vte_tick(void *arg) 1578 { 1579 struct vte_softc *sc; 1580 struct mii_data *mii; 1581 1582 sc = (struct vte_softc *)arg; 1583 1584 VTE_LOCK_ASSERT(sc); 1585 1586 mii = device_get_softc(sc->vte_miibus); 1587 mii_tick(mii); 1588 vte_stats_update(sc); 1589 vte_txeof(sc); 1590 vte_watchdog(sc); 1591 callout_reset(&sc->vte_tick_ch, hz, vte_tick, sc); 1592 } 1593 1594 static void 1595 vte_reset(struct vte_softc *sc) 1596 { 1597 uint16_t mcr, mdcsc; 1598 int i; 1599 1600 mdcsc = CSR_READ_2(sc, VTE_MDCSC); 1601 mcr = CSR_READ_2(sc, VTE_MCR1); 1602 CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET); 1603 for (i = VTE_RESET_TIMEOUT; i > 0; i--) { 1604 DELAY(10); 1605 if ((CSR_READ_2(sc, VTE_MCR1) & MCR1_MAC_RESET) == 0) 1606 break; 1607 } 1608 if (i == 0) 1609 device_printf(sc->vte_dev, "reset timeout(0x%04x)!\n", mcr); 1610 /* 1611 * Follow the guide of vendor recommended way to reset MAC. 1612 * Vendor confirms relying on MCR1_MAC_RESET of VTE_MCR1 is 1613 * not reliable so manually reset internal state machine. 1614 */ 1615 CSR_WRITE_2(sc, VTE_MACSM, 0x0002); 1616 CSR_WRITE_2(sc, VTE_MACSM, 0); 1617 DELAY(5000); 1618 1619 /* 1620 * On some SoCs (like Vortex86DX3) MDC speed control register value 1621 * needs to be restored to original value instead of default one, 1622 * otherwise some PHY registers may fail to be read. 1623 */ 1624 if (mdcsc != MDCSC_DEFAULT) 1625 CSR_WRITE_2(sc, VTE_MDCSC, mdcsc); 1626 } 1627 1628 static void 1629 vte_init(void *xsc) 1630 { 1631 struct vte_softc *sc; 1632 1633 sc = (struct vte_softc *)xsc; 1634 VTE_LOCK(sc); 1635 vte_init_locked(sc); 1636 VTE_UNLOCK(sc); 1637 } 1638 1639 static void 1640 vte_init_locked(struct vte_softc *sc) 1641 { 1642 if_t ifp; 1643 bus_addr_t paddr; 1644 uint8_t *eaddr; 1645 1646 VTE_LOCK_ASSERT(sc); 1647 1648 ifp = sc->vte_ifp; 1649 1650 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1651 return; 1652 /* 1653 * Cancel any pending I/O. 1654 */ 1655 vte_stop(sc); 1656 /* 1657 * Reset the chip to a known state. 1658 */ 1659 vte_reset(sc); 1660 1661 /* Initialize RX descriptors. */ 1662 if (vte_init_rx_ring(sc) != 0) { 1663 device_printf(sc->vte_dev, "no memory for RX buffers.\n"); 1664 vte_stop(sc); 1665 return; 1666 } 1667 if (vte_init_tx_ring(sc) != 0) { 1668 device_printf(sc->vte_dev, "no memory for TX buffers.\n"); 1669 vte_stop(sc); 1670 return; 1671 } 1672 1673 /* 1674 * Reprogram the station address. Controller supports up 1675 * to 4 different station addresses so driver programs the 1676 * first station address as its own ethernet address and 1677 * configure the remaining three addresses as perfect 1678 * multicast addresses. 1679 */ 1680 eaddr = if_getlladdr(sc->vte_ifp); 1681 CSR_WRITE_2(sc, VTE_MID0L, eaddr[1] << 8 | eaddr[0]); 1682 CSR_WRITE_2(sc, VTE_MID0M, eaddr[3] << 8 | eaddr[2]); 1683 CSR_WRITE_2(sc, VTE_MID0H, eaddr[5] << 8 | eaddr[4]); 1684 1685 /* Set TX descriptor base addresses. */ 1686 paddr = sc->vte_cdata.vte_tx_ring_paddr; 1687 CSR_WRITE_2(sc, VTE_MTDSA1, paddr >> 16); 1688 CSR_WRITE_2(sc, VTE_MTDSA0, paddr & 0xFFFF); 1689 /* Set RX descriptor base addresses. */ 1690 paddr = sc->vte_cdata.vte_rx_ring_paddr; 1691 CSR_WRITE_2(sc, VTE_MRDSA1, paddr >> 16); 1692 CSR_WRITE_2(sc, VTE_MRDSA0, paddr & 0xFFFF); 1693 /* 1694 * Initialize RX descriptor residue counter and set RX 1695 * pause threshold to 20% of available RX descriptors. 1696 * See comments on vte_rxeof() for details on flow control 1697 * issues. 1698 */ 1699 CSR_WRITE_2(sc, VTE_MRDCR, (VTE_RX_RING_CNT & VTE_MRDCR_RESIDUE_MASK) | 1700 (((VTE_RX_RING_CNT * 2) / 10) << VTE_MRDCR_RX_PAUSE_THRESH_SHIFT)); 1701 1702 /* 1703 * Always use maximum frame size that controller can 1704 * support. Otherwise received frames that has longer 1705 * frame length than vte(4) MTU would be silently dropped 1706 * in controller. This would break path-MTU discovery as 1707 * sender wouldn't get any responses from receiver. The 1708 * RX buffer size should be multiple of 4. 1709 * Note, jumbo frames are silently ignored by controller 1710 * and even MAC counters do not detect them. 1711 */ 1712 CSR_WRITE_2(sc, VTE_MRBSR, VTE_RX_BUF_SIZE_MAX); 1713 1714 /* Configure FIFO. */ 1715 CSR_WRITE_2(sc, VTE_MBCR, MBCR_FIFO_XFER_LENGTH_16 | 1716 MBCR_TX_FIFO_THRESH_64 | MBCR_RX_FIFO_THRESH_16 | 1717 MBCR_SDRAM_BUS_REQ_TIMER_DEFAULT); 1718 1719 /* 1720 * Configure TX/RX MACs. Actual resolved duplex and flow 1721 * control configuration is done after detecting a valid 1722 * link. Note, we don't generate early interrupt here 1723 * as well since FreeBSD does not have interrupt latency 1724 * problems like Windows. 1725 */ 1726 CSR_WRITE_2(sc, VTE_MCR0, MCR0_ACCPT_LONG_PKT); 1727 /* 1728 * We manually keep track of PHY status changes to 1729 * configure resolved duplex and flow control since only 1730 * duplex configuration can be automatically reflected to 1731 * MCR0. 1732 */ 1733 CSR_WRITE_2(sc, VTE_MCR1, MCR1_PKT_LENGTH_1537 | 1734 MCR1_EXCESS_COL_RETRY_16); 1735 1736 /* Initialize RX filter. */ 1737 vte_rxfilter(sc); 1738 1739 /* Disable TX/RX interrupt moderation control. */ 1740 CSR_WRITE_2(sc, VTE_MRICR, 0); 1741 CSR_WRITE_2(sc, VTE_MTICR, 0); 1742 1743 /* Enable MAC event counter interrupts. */ 1744 CSR_WRITE_2(sc, VTE_MECIER, VTE_MECIER_INTRS); 1745 /* Clear MAC statistics. */ 1746 vte_stats_clear(sc); 1747 1748 /* Acknowledge all pending interrupts and clear it. */ 1749 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); 1750 CSR_WRITE_2(sc, VTE_MISR, 0); 1751 1752 sc->vte_flags &= ~VTE_FLAG_LINK; 1753 /* Switch to the current media. */ 1754 vte_mediachange_locked(ifp); 1755 1756 callout_reset(&sc->vte_tick_ch, hz, vte_tick, sc); 1757 1758 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 1759 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1760 } 1761 1762 static void 1763 vte_stop(struct vte_softc *sc) 1764 { 1765 if_t ifp; 1766 struct vte_txdesc *txd; 1767 struct vte_rxdesc *rxd; 1768 int i; 1769 1770 VTE_LOCK_ASSERT(sc); 1771 /* 1772 * Mark the interface down and cancel the watchdog timer. 1773 */ 1774 ifp = sc->vte_ifp; 1775 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 1776 sc->vte_flags &= ~VTE_FLAG_LINK; 1777 callout_stop(&sc->vte_tick_ch); 1778 sc->vte_watchdog_timer = 0; 1779 vte_stats_update(sc); 1780 /* Disable interrupts. */ 1781 CSR_WRITE_2(sc, VTE_MIER, 0); 1782 CSR_WRITE_2(sc, VTE_MECIER, 0); 1783 /* Stop RX/TX MACs. */ 1784 vte_stop_mac(sc); 1785 /* Clear interrupts. */ 1786 CSR_READ_2(sc, VTE_MISR); 1787 /* 1788 * Free TX/RX mbufs still in the queues. 1789 */ 1790 for (i = 0; i < VTE_RX_RING_CNT; i++) { 1791 rxd = &sc->vte_cdata.vte_rxdesc[i]; 1792 if (rxd->rx_m != NULL) { 1793 bus_dmamap_sync(sc->vte_cdata.vte_rx_tag, 1794 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 1795 bus_dmamap_unload(sc->vte_cdata.vte_rx_tag, 1796 rxd->rx_dmamap); 1797 m_freem(rxd->rx_m); 1798 rxd->rx_m = NULL; 1799 } 1800 } 1801 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1802 txd = &sc->vte_cdata.vte_txdesc[i]; 1803 if (txd->tx_m != NULL) { 1804 bus_dmamap_sync(sc->vte_cdata.vte_tx_tag, 1805 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1806 bus_dmamap_unload(sc->vte_cdata.vte_tx_tag, 1807 txd->tx_dmamap); 1808 if ((txd->tx_flags & VTE_TXMBUF) == 0) 1809 m_freem(txd->tx_m); 1810 txd->tx_m = NULL; 1811 txd->tx_flags &= ~VTE_TXMBUF; 1812 } 1813 } 1814 /* Free TX mbuf pools used for deep copy. */ 1815 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1816 if (sc->vte_cdata.vte_txmbufs[i] != NULL) { 1817 m_freem(sc->vte_cdata.vte_txmbufs[i]); 1818 sc->vte_cdata.vte_txmbufs[i] = NULL; 1819 } 1820 } 1821 } 1822 1823 static void 1824 vte_start_mac(struct vte_softc *sc) 1825 { 1826 uint16_t mcr; 1827 int i; 1828 1829 VTE_LOCK_ASSERT(sc); 1830 1831 /* Enable RX/TX MACs. */ 1832 mcr = CSR_READ_2(sc, VTE_MCR0); 1833 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 1834 (MCR0_RX_ENB | MCR0_TX_ENB)) { 1835 mcr |= MCR0_RX_ENB | MCR0_TX_ENB; 1836 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1837 for (i = VTE_TIMEOUT; i > 0; i--) { 1838 mcr = CSR_READ_2(sc, VTE_MCR0); 1839 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 1840 (MCR0_RX_ENB | MCR0_TX_ENB)) 1841 break; 1842 DELAY(10); 1843 } 1844 if (i == 0) 1845 device_printf(sc->vte_dev, 1846 "could not enable RX/TX MAC(0x%04x)!\n", mcr); 1847 } 1848 } 1849 1850 static void 1851 vte_stop_mac(struct vte_softc *sc) 1852 { 1853 uint16_t mcr; 1854 int i; 1855 1856 VTE_LOCK_ASSERT(sc); 1857 1858 /* Disable RX/TX MACs. */ 1859 mcr = CSR_READ_2(sc, VTE_MCR0); 1860 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 0) { 1861 mcr &= ~(MCR0_RX_ENB | MCR0_TX_ENB); 1862 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1863 for (i = VTE_TIMEOUT; i > 0; i--) { 1864 mcr = CSR_READ_2(sc, VTE_MCR0); 1865 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 0) 1866 break; 1867 DELAY(10); 1868 } 1869 if (i == 0) 1870 device_printf(sc->vte_dev, 1871 "could not disable RX/TX MAC(0x%04x)!\n", mcr); 1872 } 1873 } 1874 1875 static int 1876 vte_init_tx_ring(struct vte_softc *sc) 1877 { 1878 struct vte_tx_desc *desc; 1879 struct vte_txdesc *txd; 1880 bus_addr_t addr; 1881 int i; 1882 1883 VTE_LOCK_ASSERT(sc); 1884 1885 sc->vte_cdata.vte_tx_prod = 0; 1886 sc->vte_cdata.vte_tx_cons = 0; 1887 sc->vte_cdata.vte_tx_cnt = 0; 1888 1889 /* Pre-allocate TX mbufs for deep copy. */ 1890 if (tx_deep_copy != 0) { 1891 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1892 sc->vte_cdata.vte_txmbufs[i] = m_getcl(M_NOWAIT, 1893 MT_DATA, M_PKTHDR); 1894 if (sc->vte_cdata.vte_txmbufs[i] == NULL) 1895 return (ENOBUFS); 1896 sc->vte_cdata.vte_txmbufs[i]->m_pkthdr.len = MCLBYTES; 1897 sc->vte_cdata.vte_txmbufs[i]->m_len = MCLBYTES; 1898 } 1899 } 1900 desc = sc->vte_cdata.vte_tx_ring; 1901 bzero(desc, VTE_TX_RING_SZ); 1902 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1903 txd = &sc->vte_cdata.vte_txdesc[i]; 1904 txd->tx_m = NULL; 1905 if (i != VTE_TX_RING_CNT - 1) 1906 addr = sc->vte_cdata.vte_tx_ring_paddr + 1907 sizeof(struct vte_tx_desc) * (i + 1); 1908 else 1909 addr = sc->vte_cdata.vte_tx_ring_paddr + 1910 sizeof(struct vte_tx_desc) * 0; 1911 desc = &sc->vte_cdata.vte_tx_ring[i]; 1912 desc->dtnp = htole32(addr); 1913 txd->tx_desc = desc; 1914 } 1915 1916 bus_dmamap_sync(sc->vte_cdata.vte_tx_ring_tag, 1917 sc->vte_cdata.vte_tx_ring_map, BUS_DMASYNC_PREREAD | 1918 BUS_DMASYNC_PREWRITE); 1919 return (0); 1920 } 1921 1922 static int 1923 vte_init_rx_ring(struct vte_softc *sc) 1924 { 1925 struct vte_rx_desc *desc; 1926 struct vte_rxdesc *rxd; 1927 bus_addr_t addr; 1928 int i; 1929 1930 VTE_LOCK_ASSERT(sc); 1931 1932 sc->vte_cdata.vte_rx_cons = 0; 1933 desc = sc->vte_cdata.vte_rx_ring; 1934 bzero(desc, VTE_RX_RING_SZ); 1935 for (i = 0; i < VTE_RX_RING_CNT; i++) { 1936 rxd = &sc->vte_cdata.vte_rxdesc[i]; 1937 rxd->rx_m = NULL; 1938 if (i != VTE_RX_RING_CNT - 1) 1939 addr = sc->vte_cdata.vte_rx_ring_paddr + 1940 sizeof(struct vte_rx_desc) * (i + 1); 1941 else 1942 addr = sc->vte_cdata.vte_rx_ring_paddr + 1943 sizeof(struct vte_rx_desc) * 0; 1944 desc = &sc->vte_cdata.vte_rx_ring[i]; 1945 desc->drnp = htole32(addr); 1946 rxd->rx_desc = desc; 1947 if (vte_newbuf(sc, rxd) != 0) 1948 return (ENOBUFS); 1949 } 1950 1951 bus_dmamap_sync(sc->vte_cdata.vte_rx_ring_tag, 1952 sc->vte_cdata.vte_rx_ring_map, BUS_DMASYNC_PREREAD | 1953 BUS_DMASYNC_PREWRITE); 1954 1955 return (0); 1956 } 1957 1958 struct vte_maddr_ctx { 1959 uint16_t rxfilt_perf[VTE_RXFILT_PERFECT_CNT][3]; 1960 uint16_t mchash[4]; 1961 u_int nperf; 1962 }; 1963 1964 static u_int 1965 vte_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1966 { 1967 struct vte_maddr_ctx *ctx = arg; 1968 uint8_t *eaddr; 1969 uint32_t crc; 1970 1971 /* 1972 * Program the first 3 multicast groups into the perfect filter. 1973 * For all others, use the hash table. 1974 */ 1975 if (ctx->nperf < VTE_RXFILT_PERFECT_CNT) { 1976 eaddr = LLADDR(sdl); 1977 ctx->rxfilt_perf[ctx->nperf][0] = eaddr[1] << 8 | eaddr[0]; 1978 ctx->rxfilt_perf[ctx->nperf][1] = eaddr[3] << 8 | eaddr[2]; 1979 ctx->rxfilt_perf[ctx->nperf][2] = eaddr[5] << 8 | eaddr[4]; 1980 ctx->nperf++; 1981 1982 return (1); 1983 } 1984 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 1985 ctx->mchash[crc >> 30] |= 1 << ((crc >> 26) & 0x0F); 1986 1987 return (1); 1988 } 1989 1990 static void 1991 vte_rxfilter(struct vte_softc *sc) 1992 { 1993 if_t ifp; 1994 struct vte_maddr_ctx ctx; 1995 uint16_t mcr; 1996 int i; 1997 1998 VTE_LOCK_ASSERT(sc); 1999 2000 ifp = sc->vte_ifp; 2001 2002 bzero(ctx.mchash, sizeof(ctx.mchash)); 2003 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) { 2004 ctx.rxfilt_perf[i][0] = 0xFFFF; 2005 ctx.rxfilt_perf[i][1] = 0xFFFF; 2006 ctx.rxfilt_perf[i][2] = 0xFFFF; 2007 } 2008 ctx.nperf = 0; 2009 2010 mcr = CSR_READ_2(sc, VTE_MCR0); 2011 mcr &= ~(MCR0_PROMISC | MCR0_MULTICAST); 2012 mcr |= MCR0_BROADCAST_DIS; 2013 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 2014 mcr &= ~MCR0_BROADCAST_DIS; 2015 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2016 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 2017 mcr |= MCR0_PROMISC; 2018 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 2019 mcr |= MCR0_MULTICAST; 2020 ctx.mchash[0] = 0xFFFF; 2021 ctx.mchash[1] = 0xFFFF; 2022 ctx.mchash[2] = 0xFFFF; 2023 ctx.mchash[3] = 0xFFFF; 2024 goto chipit; 2025 } 2026 2027 if_foreach_llmaddr(ifp, vte_hash_maddr, &ctx); 2028 if (ctx.mchash[0] != 0 || ctx.mchash[1] != 0 || 2029 ctx.mchash[2] != 0 || ctx.mchash[3] != 0) 2030 mcr |= MCR0_MULTICAST; 2031 2032 chipit: 2033 /* Program multicast hash table. */ 2034 CSR_WRITE_2(sc, VTE_MAR0, ctx.mchash[0]); 2035 CSR_WRITE_2(sc, VTE_MAR1, ctx.mchash[1]); 2036 CSR_WRITE_2(sc, VTE_MAR2, ctx.mchash[2]); 2037 CSR_WRITE_2(sc, VTE_MAR3, ctx.mchash[3]); 2038 /* Program perfect filter table. */ 2039 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) { 2040 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 0, 2041 ctx.rxfilt_perf[i][0]); 2042 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 2, 2043 ctx.rxfilt_perf[i][1]); 2044 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 4, 2045 ctx.rxfilt_perf[i][2]); 2046 } 2047 CSR_WRITE_2(sc, VTE_MCR0, mcr); 2048 CSR_READ_2(sc, VTE_MCR0); 2049 } 2050 2051 static int 2052 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2053 { 2054 int error, value; 2055 2056 if (arg1 == NULL) 2057 return (EINVAL); 2058 value = *(int *)arg1; 2059 error = sysctl_handle_int(oidp, &value, 0, req); 2060 if (error || req->newptr == NULL) 2061 return (error); 2062 if (value < low || value > high) 2063 return (EINVAL); 2064 *(int *)arg1 = value; 2065 2066 return (0); 2067 } 2068 2069 static int 2070 sysctl_hw_vte_int_mod(SYSCTL_HANDLER_ARGS) 2071 { 2072 2073 return (sysctl_int_range(oidp, arg1, arg2, req, 2074 VTE_IM_BUNDLE_MIN, VTE_IM_BUNDLE_MAX)); 2075 } 2076