1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2006 Juniper Networks
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33 #include <sys/conf.h>
34 #include <sys/endian.h>
35 #include <machine/bus.h>
36
37 #include <dev/ic/quicc.h>
38
39 #include <dev/uart/uart.h>
40 #include <dev/uart/uart_cpu.h>
41 #include <dev/uart/uart_bus.h>
42
43 #include "uart_if.h"
44
45 #define DEFAULT_RCLK ((266000000 * 2) / 16)
46
47 #define quicc_read2(bas, reg) \
48 bus_space_read_2((bas)->bst, (bas)->bsh, reg)
49 #define quicc_read4(bas, reg) \
50 bus_space_read_4((bas)->bst, (bas)->bsh, reg)
51
52 #define quicc_write2(bas, reg, val) \
53 bus_space_write_2((bas)->bst, (bas)->bsh, reg, val)
54 #define quicc_write4(bas, reg, val) \
55 bus_space_write_4((bas)->bst, (bas)->bsh, reg, val)
56
57 static int
quicc_divisor(int rclk,int baudrate)58 quicc_divisor(int rclk, int baudrate)
59 {
60 int act_baud, divisor, error;
61
62 if (baudrate == 0)
63 return (-1);
64
65 divisor = rclk / baudrate / 16;
66 if (divisor > 4096)
67 divisor = ((divisor >> 3) - 2) | 1;
68 else if (divisor >= 0)
69 divisor = (divisor - 1) << 1;
70 if (divisor < 0 || divisor >= 8192)
71 return (-1);
72 act_baud = rclk / (((divisor >> 1) + 1) << ((divisor & 1) ? 8 : 4));
73
74 /* 10 times error in percent: */
75 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1;
76
77 /* 3.0% maximum error tolerance: */
78 if (error < -30 || error > 30)
79 return (-1);
80
81 return (divisor);
82 }
83
84 static int
quicc_param(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)85 quicc_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
86 int parity)
87 {
88 int divisor;
89 uint16_t psmr;
90
91 if (baudrate > 0) {
92 divisor = quicc_divisor(bas->rclk, baudrate);
93 if (divisor == -1)
94 return (EINVAL);
95 quicc_write4(bas, QUICC_REG_BRG(bas->chan - 1),
96 divisor | 0x10000);
97 }
98
99 psmr = 0;
100 switch (databits) {
101 case 5: psmr |= 0x0000; break;
102 case 6: psmr |= 0x1000; break;
103 case 7: psmr |= 0x2000; break;
104 case 8: psmr |= 0x3000; break;
105 default: return (EINVAL);
106 }
107 switch (stopbits) {
108 case 1: psmr |= 0x0000; break;
109 case 2: psmr |= 0x4000; break;
110 default: return (EINVAL);
111 }
112 switch (parity) {
113 case UART_PARITY_EVEN: psmr |= 0x1a; break;
114 case UART_PARITY_MARK: psmr |= 0x1f; break;
115 case UART_PARITY_NONE: psmr |= 0x00; break;
116 case UART_PARITY_ODD: psmr |= 0x10; break;
117 case UART_PARITY_SPACE: psmr |= 0x15; break;
118 default: return (EINVAL);
119 }
120 quicc_write2(bas, QUICC_REG_SCC_PSMR(bas->chan - 1), psmr);
121 return (0);
122 }
123
124 static void
quicc_setup(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)125 quicc_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits,
126 int parity)
127 {
128
129 if (bas->rclk == 0)
130 bas->rclk = DEFAULT_RCLK;
131
132 /*
133 * GSMR_L = 0x00028034
134 * GSMR_H = 0x00000020
135 */
136 quicc_param(bas, baudrate, databits, stopbits, parity);
137
138 quicc_write2(bas, QUICC_REG_SCC_SCCE(bas->chan - 1), ~0);
139 quicc_write2(bas, QUICC_REG_SCC_SCCM(bas->chan - 1), 0x0027);
140 }
141
142 /*
143 * Low-level UART interface.
144 */
145 static int quicc_probe(struct uart_bas *bas);
146 static void quicc_init(struct uart_bas *bas, int, int, int, int);
147 static void quicc_term(struct uart_bas *bas);
148 static void quicc_putc(struct uart_bas *bas, int);
149 static int quicc_rxready(struct uart_bas *bas);
150 static int quicc_getc(struct uart_bas *bas, struct mtx *);
151
152 static struct uart_ops uart_quicc_ops = {
153 .probe = quicc_probe,
154 .init = quicc_init,
155 .term = quicc_term,
156 .putc = quicc_putc,
157 .rxready = quicc_rxready,
158 .getc = quicc_getc,
159 };
160
161 static int
quicc_probe(struct uart_bas * bas)162 quicc_probe(struct uart_bas *bas)
163 {
164
165 return (0);
166 }
167
168 static void
quicc_init(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)169 quicc_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
170 int parity)
171 {
172
173 quicc_setup(bas, baudrate, databits, stopbits, parity);
174 }
175
176 static void
quicc_term(struct uart_bas * bas)177 quicc_term(struct uart_bas *bas)
178 {
179 }
180
181 static void
quicc_putc(struct uart_bas * bas,int c)182 quicc_putc(struct uart_bas *bas, int c)
183 {
184 int unit;
185 uint16_t toseq;
186
187 unit = bas->chan - 1;
188 while (quicc_read2(bas, QUICC_PRAM_SCC_UART_TOSEQ(unit)) & 0x2000)
189 DELAY(10);
190
191 toseq = 0x2000 | (c & 0xff);
192 quicc_write2(bas, QUICC_PRAM_SCC_UART_TOSEQ(unit), toseq);
193 }
194
195 static int
quicc_rxready(struct uart_bas * bas)196 quicc_rxready(struct uart_bas *bas)
197 {
198 uint16_t rb;
199
200 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
201 return ((quicc_read2(bas, rb) & 0x8000) ? 0 : 1);
202 }
203
204 static int
quicc_getc(struct uart_bas * bas,struct mtx * hwmtx)205 quicc_getc(struct uart_bas *bas, struct mtx *hwmtx)
206 {
207 volatile char *buf;
208 int c;
209 uint16_t rb, sc;
210
211 uart_lock(hwmtx);
212
213 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
214
215 while ((sc = quicc_read2(bas, rb)) & 0x8000) {
216 uart_unlock(hwmtx);
217 DELAY(4);
218 uart_lock(hwmtx);
219 }
220
221 buf = (void *)(uintptr_t)quicc_read4(bas, rb + 4);
222 c = *buf;
223 quicc_write2(bas, rb, sc | 0x8000);
224
225 uart_unlock(hwmtx);
226
227 return (c);
228 }
229
230 /*
231 * High-level UART interface.
232 */
233 struct quicc_softc {
234 struct uart_softc base;
235 };
236
237 static int quicc_bus_attach(struct uart_softc *);
238 static int quicc_bus_detach(struct uart_softc *);
239 static int quicc_bus_flush(struct uart_softc *, int);
240 static int quicc_bus_getsig(struct uart_softc *);
241 static int quicc_bus_ioctl(struct uart_softc *, int, intptr_t);
242 static int quicc_bus_ipend(struct uart_softc *);
243 static int quicc_bus_param(struct uart_softc *, int, int, int, int);
244 static int quicc_bus_probe(struct uart_softc *);
245 static int quicc_bus_receive(struct uart_softc *);
246 static int quicc_bus_setsig(struct uart_softc *, int);
247 static int quicc_bus_transmit(struct uart_softc *);
248 static void quicc_bus_grab(struct uart_softc *);
249 static void quicc_bus_ungrab(struct uart_softc *);
250
251 static kobj_method_t quicc_methods[] = {
252 KOBJMETHOD(uart_attach, quicc_bus_attach),
253 KOBJMETHOD(uart_detach, quicc_bus_detach),
254 KOBJMETHOD(uart_flush, quicc_bus_flush),
255 KOBJMETHOD(uart_getsig, quicc_bus_getsig),
256 KOBJMETHOD(uart_ioctl, quicc_bus_ioctl),
257 KOBJMETHOD(uart_ipend, quicc_bus_ipend),
258 KOBJMETHOD(uart_param, quicc_bus_param),
259 KOBJMETHOD(uart_probe, quicc_bus_probe),
260 KOBJMETHOD(uart_receive, quicc_bus_receive),
261 KOBJMETHOD(uart_setsig, quicc_bus_setsig),
262 KOBJMETHOD(uart_transmit, quicc_bus_transmit),
263 KOBJMETHOD(uart_grab, quicc_bus_grab),
264 KOBJMETHOD(uart_ungrab, quicc_bus_ungrab),
265 { 0, 0 }
266 };
267
268 struct uart_class uart_quicc_class = {
269 "quicc",
270 quicc_methods,
271 sizeof(struct quicc_softc),
272 .uc_ops = &uart_quicc_ops,
273 .uc_range = 2,
274 .uc_rclk = DEFAULT_RCLK,
275 .uc_rshift = 0
276 };
277
278 #define SIGCHG(c, i, s, d) \
279 if (c) { \
280 i |= (i & s) ? s : s | d; \
281 } else { \
282 i = (i & s) ? (i & ~s) | d : i; \
283 }
284
285 static int
quicc_bus_attach(struct uart_softc * sc)286 quicc_bus_attach(struct uart_softc *sc)
287 {
288 struct uart_bas *bas;
289 struct uart_devinfo *di;
290 uint16_t st, rb;
291
292 bas = &sc->sc_bas;
293 if (sc->sc_sysdev != NULL) {
294 di = sc->sc_sysdev;
295 quicc_param(bas, di->baudrate, di->databits, di->stopbits,
296 di->parity);
297 } else {
298 quicc_setup(bas, 9600, 8, 1, UART_PARITY_NONE);
299 }
300
301 /* Enable interrupts on the receive buffer. */
302 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
303 st = quicc_read2(bas, rb);
304 quicc_write2(bas, rb, st | 0x9000);
305
306 (void)quicc_bus_getsig(sc);
307
308 return (0);
309 }
310
311 static int
quicc_bus_detach(struct uart_softc * sc)312 quicc_bus_detach(struct uart_softc *sc)
313 {
314
315 return (0);
316 }
317
318 static int
quicc_bus_flush(struct uart_softc * sc,int what)319 quicc_bus_flush(struct uart_softc *sc, int what)
320 {
321
322 return (0);
323 }
324
325 static int
quicc_bus_getsig(struct uart_softc * sc)326 quicc_bus_getsig(struct uart_softc *sc)
327 {
328 uint32_t new, old, sig;
329 uint32_t dummy;
330
331 do {
332 old = sc->sc_hwsig;
333 sig = old;
334 uart_lock(sc->sc_hwmtx);
335 /* XXX SIGNALS */
336 dummy = 0;
337 uart_unlock(sc->sc_hwmtx);
338 SIGCHG(dummy, sig, SER_CTS, SER_DCTS);
339 SIGCHG(dummy, sig, SER_DCD, SER_DDCD);
340 SIGCHG(dummy, sig, SER_DSR, SER_DDSR);
341 new = sig & ~SER_MASK_DELTA;
342 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
343 return (sig);
344 }
345
346 static int
quicc_bus_ioctl(struct uart_softc * sc,int request,intptr_t data)347 quicc_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
348 {
349 struct uart_bas *bas;
350 uint32_t brg;
351 int baudrate, error;
352
353 bas = &sc->sc_bas;
354 error = 0;
355 uart_lock(sc->sc_hwmtx);
356 switch (request) {
357 case UART_IOCTL_BREAK:
358 break;
359 case UART_IOCTL_BAUD:
360 brg = quicc_read4(bas, QUICC_REG_BRG(bas->chan - 1)) & 0x1fff;
361 brg = (brg & 1) ? (brg + 1) << 3 : (brg + 2) >> 1;
362 baudrate = bas->rclk / (brg * 16);
363 *(int*)data = baudrate;
364 break;
365 default:
366 error = EINVAL;
367 break;
368 }
369 uart_unlock(sc->sc_hwmtx);
370 return (error);
371 }
372
373 static int
quicc_bus_ipend(struct uart_softc * sc)374 quicc_bus_ipend(struct uart_softc *sc)
375 {
376 struct uart_bas *bas;
377 int ipend;
378 uint16_t scce;
379
380 bas = &sc->sc_bas;
381 ipend = 0;
382
383 uart_lock(sc->sc_hwmtx);
384 scce = quicc_read2(bas, QUICC_REG_SCC_SCCE(bas->chan - 1));
385 quicc_write2(bas, QUICC_REG_SCC_SCCE(bas->chan - 1), ~0);
386 uart_unlock(sc->sc_hwmtx);
387 if (scce & 0x0001)
388 ipend |= SER_INT_RXREADY;
389 if (scce & 0x0002)
390 ipend |= SER_INT_TXIDLE;
391 if (scce & 0x0004)
392 ipend |= SER_INT_OVERRUN;
393 if (scce & 0x0020)
394 ipend |= SER_INT_BREAK;
395 /* XXX SIGNALS */
396 return (ipend);
397 }
398
399 static int
quicc_bus_param(struct uart_softc * sc,int baudrate,int databits,int stopbits,int parity)400 quicc_bus_param(struct uart_softc *sc, int baudrate, int databits,
401 int stopbits, int parity)
402 {
403 int error;
404
405 uart_lock(sc->sc_hwmtx);
406 error = quicc_param(&sc->sc_bas, baudrate, databits, stopbits,
407 parity);
408 uart_unlock(sc->sc_hwmtx);
409 return (error);
410 }
411
412 static int
quicc_bus_probe(struct uart_softc * sc)413 quicc_bus_probe(struct uart_softc *sc)
414 {
415 int error;
416
417 error = quicc_probe(&sc->sc_bas);
418 if (error)
419 return (error);
420
421 sc->sc_rxfifosz = 1;
422 sc->sc_txfifosz = 1;
423
424 device_set_descf(sc->sc_dev, "quicc, channel %d", sc->sc_bas.chan);
425 return (0);
426 }
427
428 static int
quicc_bus_receive(struct uart_softc * sc)429 quicc_bus_receive(struct uart_softc *sc)
430 {
431 struct uart_bas *bas;
432 volatile char *buf;
433 uint16_t st, rb;
434
435 bas = &sc->sc_bas;
436 uart_lock(sc->sc_hwmtx);
437 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
438 st = quicc_read2(bas, rb);
439 buf = (void *)(uintptr_t)quicc_read4(bas, rb + 4);
440 uart_rx_put(sc, *buf);
441 quicc_write2(bas, rb, st | 0x9000);
442 uart_unlock(sc->sc_hwmtx);
443 return (0);
444 }
445
446 static int
quicc_bus_setsig(struct uart_softc * sc,int sig)447 quicc_bus_setsig(struct uart_softc *sc, int sig)
448 {
449 uint32_t new, old;
450
451 do {
452 old = sc->sc_hwsig;
453 new = old;
454 if (sig & SER_DDTR) {
455 SIGCHG(sig & SER_DTR, new, SER_DTR,
456 SER_DDTR);
457 }
458 if (sig & SER_DRTS) {
459 SIGCHG(sig & SER_RTS, new, SER_RTS,
460 SER_DRTS);
461 }
462 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
463
464 uart_lock(sc->sc_hwmtx);
465 /* XXX SIGNALS */
466 uart_unlock(sc->sc_hwmtx);
467 return (0);
468 }
469
470 static int
quicc_bus_transmit(struct uart_softc * sc)471 quicc_bus_transmit(struct uart_softc *sc)
472 {
473 volatile char *buf;
474 struct uart_bas *bas;
475 uint16_t st, tb;
476
477 bas = &sc->sc_bas;
478 uart_lock(sc->sc_hwmtx);
479 tb = quicc_read2(bas, QUICC_PRAM_SCC_TBASE(bas->chan - 1));
480 st = quicc_read2(bas, tb);
481 buf = (void *)(uintptr_t)quicc_read4(bas, tb + 4);
482 *buf = sc->sc_txbuf[0];
483 quicc_write2(bas, tb + 2, 1);
484 quicc_write2(bas, tb, st | 0x9000);
485 sc->sc_txbusy = 1;
486 uart_unlock(sc->sc_hwmtx);
487 return (0);
488 }
489
490 static void
quicc_bus_grab(struct uart_softc * sc)491 quicc_bus_grab(struct uart_softc *sc)
492 {
493 struct uart_bas *bas;
494 uint16_t st, rb;
495
496 /* Disable interrupts on the receive buffer. */
497 bas = &sc->sc_bas;
498 uart_lock(sc->sc_hwmtx);
499 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
500 st = quicc_read2(bas, rb);
501 quicc_write2(bas, rb, st & ~0x9000);
502 uart_unlock(sc->sc_hwmtx);
503 }
504
505 static void
quicc_bus_ungrab(struct uart_softc * sc)506 quicc_bus_ungrab(struct uart_softc *sc)
507 {
508 struct uart_bas *bas;
509 uint16_t st, rb;
510
511 /* Enable interrupts on the receive buffer. */
512 bas = &sc->sc_bas;
513 uart_lock(sc->sc_hwmtx);
514 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
515 st = quicc_read2(bas, rb);
516 quicc_write2(bas, rb, st | 0x9000);
517 uart_unlock(sc->sc_hwmtx);
518 }
519