1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003 Marcel Moolenaar 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "opt_acpi.h" 30 #include "opt_platform.h" 31 #include "opt_uart.h" 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/conf.h> 40 #include <sys/kernel.h> 41 #include <sys/sysctl.h> 42 #include <machine/bus.h> 43 44 #ifdef FDT 45 #include <dev/fdt/fdt_common.h> 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 #endif 49 50 #include <dev/uart/uart.h> 51 #include <dev/uart/uart_cpu.h> 52 #ifdef FDT 53 #include <dev/uart/uart_cpu_fdt.h> 54 #endif 55 #include <dev/uart/uart_bus.h> 56 #include <dev/uart/uart_dev_ns8250.h> 57 #include <dev/uart/uart_ppstypes.h> 58 #ifdef DEV_ACPI 59 #include <dev/uart/uart_cpu_acpi.h> 60 #include <contrib/dev/acpica/include/acpi.h> 61 #endif 62 63 #include <dev/ic/ns16550.h> 64 65 #include "uart_if.h" 66 67 #define DEFAULT_RCLK 1843200 68 69 /* 70 * Set the default baudrate tolerance to 3.0%. 71 * 72 * Some embedded boards have odd reference clocks (eg 25MHz) 73 * and we need to handle higher variances in the target baud rate. 74 */ 75 #ifndef UART_DEV_TOLERANCE_PCT 76 #define UART_DEV_TOLERANCE_PCT 30 77 #endif /* UART_DEV_TOLERANCE_PCT */ 78 79 static int broken_txfifo = 0; 80 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 81 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 82 83 /* 84 * Clear pending interrupts. THRE is cleared by reading IIR. Data 85 * that may have been received gets lost here. 86 */ 87 static void 88 ns8250_clrint(struct uart_bas *bas) 89 { 90 uint8_t iir, lsr; 91 92 iir = uart_getreg(bas, REG_IIR); 93 while ((iir & IIR_NOPEND) == 0) { 94 iir &= IIR_IMASK; 95 if (iir == IIR_RLS) { 96 lsr = uart_getreg(bas, REG_LSR); 97 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 98 (void)uart_getreg(bas, REG_DATA); 99 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 100 (void)uart_getreg(bas, REG_DATA); 101 else if (iir == IIR_MLSC) 102 (void)uart_getreg(bas, REG_MSR); 103 uart_barrier(bas); 104 iir = uart_getreg(bas, REG_IIR); 105 } 106 } 107 108 static int 109 ns8250_delay(struct uart_bas *bas) 110 { 111 int divisor; 112 u_char lcr; 113 114 lcr = uart_getreg(bas, REG_LCR); 115 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 116 uart_barrier(bas); 117 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 118 uart_barrier(bas); 119 uart_setreg(bas, REG_LCR, lcr); 120 uart_barrier(bas); 121 122 /* 1/10th the time to transmit 1 character (estimate). */ 123 if (divisor <= 134) 124 return (16000000 * divisor / bas->rclk); 125 return (16000 * divisor / (bas->rclk / 1000)); 126 } 127 128 static int 129 ns8250_divisor(int rclk, int baudrate) 130 { 131 int actual_baud, divisor; 132 int error; 133 134 if (baudrate == 0) 135 return (0); 136 137 divisor = (rclk / (baudrate << 3) + 1) >> 1; 138 if (divisor == 0 || divisor >= 65536) 139 return (0); 140 actual_baud = rclk / (divisor << 4); 141 142 /* 10 times error in percent: */ 143 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) / 2; 144 145 /* enforce maximum error tolerance: */ 146 if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT) 147 return (0); 148 149 return (divisor); 150 } 151 152 static int 153 ns8250_drain(struct uart_bas *bas, int what) 154 { 155 int delay, limit; 156 157 delay = ns8250_delay(bas); 158 159 if (what & UART_DRAIN_TRANSMITTER) { 160 /* 161 * Pick an arbitrary high limit to avoid getting stuck in 162 * an infinite loop when the hardware is broken. Make the 163 * limit high enough to handle large FIFOs. 164 */ 165 limit = 10*1024; 166 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 167 DELAY(delay); 168 if (limit == 0) { 169 /* printf("ns8250: transmitter appears stuck... "); */ 170 return (EIO); 171 } 172 } 173 174 if (what & UART_DRAIN_RECEIVER) { 175 /* 176 * Pick an arbitrary high limit to avoid getting stuck in 177 * an infinite loop when the hardware is broken. Make the 178 * limit high enough to handle large FIFOs and integrated 179 * UARTs. The HP rx2600 for example has 3 UARTs on the 180 * management board that tend to get a lot of data send 181 * to it when the UART is first activated. Assume that we 182 * have finished draining if LSR_RXRDY is not asserted both 183 * prior to and after a DELAY; but as long as LSR_RXRDY is 184 * asserted, read (and discard) characters as quickly as 185 * possible. 186 */ 187 limit=10*4096; 188 while (limit && (uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 189 do { 190 (void)uart_getreg(bas, REG_DATA); 191 uart_barrier(bas); 192 } while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit); 193 uart_barrier(bas); 194 DELAY(delay << 2); 195 } 196 if (limit == 0) { 197 /* printf("ns8250: receiver appears broken... "); */ 198 return (EIO); 199 } 200 } 201 202 return (0); 203 } 204 205 /* 206 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 207 * drained. WARNING: this function clobbers the FIFO setting! 208 */ 209 static void 210 ns8250_flush(struct uart_bas *bas, int what) 211 { 212 uint8_t fcr; 213 214 fcr = FCR_ENABLE; 215 #ifdef CPU_XBURST 216 fcr |= FCR_UART_ON; 217 #endif 218 if (what & UART_FLUSH_TRANSMITTER) 219 fcr |= FCR_XMT_RST; 220 if (what & UART_FLUSH_RECEIVER) 221 fcr |= FCR_RCV_RST; 222 uart_setreg(bas, REG_FCR, fcr); 223 uart_barrier(bas); 224 } 225 226 static int 227 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 228 int parity) 229 { 230 int divisor; 231 uint8_t lcr; 232 233 lcr = 0; 234 if (databits >= 8) 235 lcr |= LCR_8BITS; 236 else if (databits == 7) 237 lcr |= LCR_7BITS; 238 else if (databits == 6) 239 lcr |= LCR_6BITS; 240 else 241 lcr |= LCR_5BITS; 242 if (stopbits > 1) 243 lcr |= LCR_STOPB; 244 lcr |= parity << 3; 245 246 /* Set baudrate. */ 247 if (baudrate > 0) { 248 divisor = ns8250_divisor(bas->rclk, baudrate); 249 if (divisor == 0) 250 return (EINVAL); 251 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 252 uart_barrier(bas); 253 uart_setreg(bas, REG_DLL, divisor & 0xff); 254 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 255 uart_barrier(bas); 256 } 257 258 /* Set LCR and clear DLAB. */ 259 uart_setreg(bas, REG_LCR, lcr); 260 uart_barrier(bas); 261 return (0); 262 } 263 264 /* 265 * Low-level UART interface. 266 */ 267 static int ns8250_probe(struct uart_bas *bas); 268 static void ns8250_init(struct uart_bas *bas, int, int, int, int); 269 static void ns8250_term(struct uart_bas *bas); 270 static void ns8250_putc(struct uart_bas *bas, int); 271 static int ns8250_rxready(struct uart_bas *bas); 272 static int ns8250_getc(struct uart_bas *bas, struct mtx *); 273 274 struct uart_ops uart_ns8250_ops = { 275 .probe = ns8250_probe, 276 .init = ns8250_init, 277 .term = ns8250_term, 278 .putc = ns8250_putc, 279 .rxready = ns8250_rxready, 280 .getc = ns8250_getc, 281 }; 282 283 static int 284 ns8250_probe(struct uart_bas *bas) 285 { 286 u_char val; 287 288 #ifdef CPU_XBURST 289 uart_setreg(bas, REG_FCR, FCR_UART_ON); 290 #endif 291 292 /* Check known 0 bits that don't depend on DLAB. */ 293 val = uart_getreg(bas, REG_IIR); 294 if (val & 0x30) 295 return (ENXIO); 296 /* 297 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 298 * chip, but otherwise doesn't seem to have a function. In 299 * other words, uart(4) works regardless. Ignore that bit so 300 * the probe succeeds. 301 */ 302 val = uart_getreg(bas, REG_MCR); 303 if (val & 0xa0) 304 return (ENXIO); 305 306 return (0); 307 } 308 309 static void 310 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 311 int parity) 312 { 313 u_char ier, val; 314 315 if (bas->rclk == 0) 316 bas->rclk = DEFAULT_RCLK; 317 ns8250_param(bas, baudrate, databits, stopbits, parity); 318 319 /* Disable all interrupt sources. */ 320 /* 321 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 322 * UARTs split the receive time-out interrupt bit out separately as 323 * 0x10. This gets handled by ier_mask and ier_rxbits below. 324 */ 325 ier = uart_getreg(bas, REG_IER) & 0xe0; 326 uart_setreg(bas, REG_IER, ier); 327 uart_barrier(bas); 328 329 /* Disable the FIFO (if present). */ 330 val = 0; 331 #ifdef CPU_XBURST 332 val |= FCR_UART_ON; 333 #endif 334 uart_setreg(bas, REG_FCR, val); 335 uart_barrier(bas); 336 337 /* Set RTS & DTR. */ 338 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 339 uart_barrier(bas); 340 341 ns8250_clrint(bas); 342 } 343 344 static void 345 ns8250_term(struct uart_bas *bas) 346 { 347 348 /* Clear RTS & DTR. */ 349 uart_setreg(bas, REG_MCR, MCR_IE); 350 uart_barrier(bas); 351 } 352 353 static void 354 ns8250_putc(struct uart_bas *bas, int c) 355 { 356 int limit; 357 358 limit = 250000; 359 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 360 DELAY(4); 361 uart_setreg(bas, REG_DATA, c); 362 uart_barrier(bas); 363 } 364 365 static int 366 ns8250_rxready(struct uart_bas *bas) 367 { 368 369 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 370 } 371 372 static int 373 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 374 { 375 int c; 376 377 uart_lock(hwmtx); 378 379 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 380 uart_unlock(hwmtx); 381 DELAY(4); 382 uart_lock(hwmtx); 383 } 384 385 c = uart_getreg(bas, REG_DATA); 386 387 uart_unlock(hwmtx); 388 389 return (c); 390 } 391 392 static kobj_method_t ns8250_methods[] = { 393 KOBJMETHOD(uart_attach, ns8250_bus_attach), 394 KOBJMETHOD(uart_detach, ns8250_bus_detach), 395 KOBJMETHOD(uart_flush, ns8250_bus_flush), 396 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 397 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 398 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 399 KOBJMETHOD(uart_param, ns8250_bus_param), 400 KOBJMETHOD(uart_probe, ns8250_bus_probe), 401 KOBJMETHOD(uart_receive, ns8250_bus_receive), 402 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 403 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 404 KOBJMETHOD(uart_grab, ns8250_bus_grab), 405 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 406 { 0, 0 } 407 }; 408 409 struct uart_class uart_ns8250_class = { 410 "ns8250", 411 ns8250_methods, 412 sizeof(struct ns8250_softc), 413 .uc_ops = &uart_ns8250_ops, 414 .uc_range = 8, 415 .uc_rclk = DEFAULT_RCLK, 416 .uc_rshift = 0 417 }; 418 419 /* 420 * XXX -- refactor out ACPI and FDT ifdefs 421 */ 422 #ifdef DEV_ACPI 423 static struct acpi_uart_compat_data acpi_compat_data[] = { 424 {"AMD0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 425 {"AMDI0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 426 {"MRVL0001", &uart_ns8250_class, ACPI_DBG2_16550_SUBSET, 2, 0, 200000000, UART_F_BUSY_DETECT, "Marvell / Synopsys Designware UART"}, 427 {"SCX0006", &uart_ns8250_class, 0, 2, 0, 62500000, UART_F_BUSY_DETECT, "SynQuacer / Synopsys Designware UART"}, 428 {"HISI0031", &uart_ns8250_class, 0, 2, 0, 200000000, UART_F_BUSY_DETECT, "HiSilicon / Synopsys Designware UART"}, 429 {"NXP0018", &uart_ns8250_class, 0, 0, 0, 350000000, UART_F_BUSY_DETECT, "NXP / Synopsys Designware UART"}, 430 {"PNP0500", &uart_ns8250_class, 0, 0, 0, 0, 0, "Standard PC COM port"}, 431 {"PNP0501", &uart_ns8250_class, 0, 0, 0, 0, 0, "16550A-compatible COM port"}, 432 {"PNP0502", &uart_ns8250_class, 0, 0, 0, 0, 0, "Multiport serial device (non-intelligent 16550)"}, 433 {"PNP0510", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 434 {"PNP0511", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 435 {"WACF004", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen"}, 436 {"WACF00E", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen 00e"}, 437 {"FUJ02E5", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet at FuS Lifebook T"}, 438 {NULL, NULL, 0, 0 , 0, 0, 0, NULL}, 439 }; 440 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data); 441 #endif 442 443 #ifdef FDT 444 static struct ofw_compat_data compat_data[] = { 445 {"ns16550", (uintptr_t)&uart_ns8250_class}, 446 {"ns16550a", (uintptr_t)&uart_ns8250_class}, 447 {NULL, (uintptr_t)NULL}, 448 }; 449 UART_FDT_CLASS_AND_DEVICE(compat_data); 450 #endif 451 452 /* Use token-pasting to form SER_ and MSR_ named constants. */ 453 #define SER(sig) SER_##sig 454 #define SERD(sig) SER_D##sig 455 #define MSR(sig) MSR_##sig 456 #define MSRD(sig) MSR_D##sig 457 458 /* 459 * Detect signal changes using software delta detection. The previous state of 460 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the 461 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the 462 * new state of both the signal and the delta bits. 463 */ 464 #define SIGCHGSW(var, msr, sig) \ 465 if ((msr) & MSR(sig)) { \ 466 if ((var & SER(sig)) == 0) \ 467 var |= SERD(sig) | SER(sig); \ 468 } else { \ 469 if ((var & SER(sig)) != 0) \ 470 var = SERD(sig) | (var & ~SER(sig)); \ 471 } 472 473 /* 474 * Detect signal changes using the hardware msr delta bits. This is currently 475 * used only when PPS timing information is being captured using the "narrow 476 * pulse" option. With a narrow PPS pulse the signal may not still be asserted 477 * by time the interrupt handler is invoked. The hardware will latch the fact 478 * that it changed in the delta bits. 479 */ 480 #define SIGCHGHW(var, msr, sig) \ 481 if ((msr) & MSRD(sig)) { \ 482 if (((msr) & MSR(sig)) != 0) \ 483 var |= SERD(sig) | SER(sig); \ 484 else \ 485 var = SERD(sig) | (var & ~SER(sig)); \ 486 } 487 488 int 489 ns8250_bus_attach(struct uart_softc *sc) 490 { 491 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 492 struct uart_bas *bas; 493 unsigned int ivar; 494 #ifdef FDT 495 phandle_t node; 496 pcell_t cell; 497 #endif 498 499 #ifdef FDT 500 /* Check whether uart has a broken txfifo. */ 501 node = ofw_bus_get_node(sc->sc_dev); 502 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 503 broken_txfifo = cell ? 1 : 0; 504 #endif 505 506 bas = &sc->sc_bas; 507 508 ns8250->busy_detect = bas->busy_detect; 509 ns8250->mcr = uart_getreg(bas, REG_MCR); 510 ns8250->fcr = FCR_ENABLE; 511 #ifdef CPU_XBURST 512 ns8250->fcr |= FCR_UART_ON; 513 #endif 514 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 515 &ivar)) { 516 if (UART_FLAGS_FCR_RX_LOW(ivar)) 517 ns8250->fcr |= FCR_RX_LOW; 518 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 519 ns8250->fcr |= FCR_RX_MEDL; 520 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 521 ns8250->fcr |= FCR_RX_HIGH; 522 else 523 ns8250->fcr |= FCR_RX_MEDH; 524 } else 525 ns8250->fcr |= FCR_RX_MEDH; 526 527 /* Get IER mask */ 528 ivar = 0xf0; 529 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 530 &ivar); 531 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 532 533 /* Get IER RX interrupt bits */ 534 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 535 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 536 &ivar); 537 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 538 539 uart_setreg(bas, REG_FCR, ns8250->fcr); 540 uart_barrier(bas); 541 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 542 543 if (ns8250->mcr & MCR_DTR) 544 sc->sc_hwsig |= SER_DTR; 545 if (ns8250->mcr & MCR_RTS) 546 sc->sc_hwsig |= SER_RTS; 547 ns8250_bus_getsig(sc); 548 549 ns8250_clrint(bas); 550 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 551 ns8250->ier |= ns8250->ier_rxbits; 552 uart_setreg(bas, REG_IER, ns8250->ier); 553 uart_barrier(bas); 554 555 /* 556 * Timing of the H/W access was changed with r253161 of uart_core.c 557 * It has been observed that an ITE IT8513E would signal a break 558 * condition with pretty much every character it received, unless 559 * it had enough time to settle between ns8250_bus_attach() and 560 * ns8250_bus_ipend() -- which it accidentally had before r253161. 561 * It's not understood why the UART chip behaves this way and it 562 * could very well be that the DELAY make the H/W work in the same 563 * accidental manner as before. More analysis is warranted, but 564 * at least now we fixed a known regression. 565 */ 566 DELAY(200); 567 return (0); 568 } 569 570 int 571 ns8250_bus_detach(struct uart_softc *sc) 572 { 573 struct ns8250_softc *ns8250; 574 struct uart_bas *bas; 575 u_char ier; 576 577 ns8250 = (struct ns8250_softc *)sc; 578 bas = &sc->sc_bas; 579 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 580 uart_setreg(bas, REG_IER, ier); 581 uart_barrier(bas); 582 ns8250_clrint(bas); 583 return (0); 584 } 585 586 int 587 ns8250_bus_flush(struct uart_softc *sc, int what) 588 { 589 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 590 struct uart_bas *bas; 591 int error; 592 593 bas = &sc->sc_bas; 594 uart_lock(sc->sc_hwmtx); 595 if (sc->sc_rxfifosz > 1) { 596 ns8250_flush(bas, what); 597 uart_setreg(bas, REG_FCR, ns8250->fcr); 598 uart_barrier(bas); 599 error = 0; 600 } else 601 error = ns8250_drain(bas, what); 602 uart_unlock(sc->sc_hwmtx); 603 return (error); 604 } 605 606 int 607 ns8250_bus_getsig(struct uart_softc *sc) 608 { 609 uint32_t old, sig; 610 uint8_t msr; 611 612 /* 613 * The delta bits are reputed to be broken on some hardware, so use 614 * software delta detection by default. Use the hardware delta bits 615 * when capturing PPS pulses which are too narrow for software detection 616 * to see the edges. Hardware delta for RI doesn't work like the 617 * others, so always use software for it. Other threads may be changing 618 * other (non-MSR) bits in sc_hwsig, so loop until it can successfully 619 * update without other changes happening. Note that the SIGCHGxx() 620 * macros carefully preserve the delta bits when we have to loop several 621 * times and a signal transitions between iterations. 622 */ 623 do { 624 old = sc->sc_hwsig; 625 sig = old; 626 uart_lock(sc->sc_hwmtx); 627 msr = uart_getreg(&sc->sc_bas, REG_MSR); 628 uart_unlock(sc->sc_hwmtx); 629 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) { 630 SIGCHGHW(sig, msr, DSR); 631 SIGCHGHW(sig, msr, CTS); 632 SIGCHGHW(sig, msr, DCD); 633 } else { 634 SIGCHGSW(sig, msr, DSR); 635 SIGCHGSW(sig, msr, CTS); 636 SIGCHGSW(sig, msr, DCD); 637 } 638 SIGCHGSW(sig, msr, RI); 639 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA)); 640 return (sig); 641 } 642 643 int 644 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 645 { 646 struct uart_bas *bas; 647 int baudrate, divisor, error; 648 uint8_t efr, lcr; 649 650 bas = &sc->sc_bas; 651 error = 0; 652 uart_lock(sc->sc_hwmtx); 653 switch (request) { 654 case UART_IOCTL_BREAK: 655 lcr = uart_getreg(bas, REG_LCR); 656 if (data) 657 lcr |= LCR_SBREAK; 658 else 659 lcr &= ~LCR_SBREAK; 660 uart_setreg(bas, REG_LCR, lcr); 661 uart_barrier(bas); 662 break; 663 case UART_IOCTL_IFLOW: 664 lcr = uart_getreg(bas, REG_LCR); 665 uart_barrier(bas); 666 uart_setreg(bas, REG_LCR, 0xbf); 667 uart_barrier(bas); 668 efr = uart_getreg(bas, REG_EFR); 669 if (data) 670 efr |= EFR_RTS; 671 else 672 efr &= ~EFR_RTS; 673 uart_setreg(bas, REG_EFR, efr); 674 uart_barrier(bas); 675 uart_setreg(bas, REG_LCR, lcr); 676 uart_barrier(bas); 677 break; 678 case UART_IOCTL_OFLOW: 679 lcr = uart_getreg(bas, REG_LCR); 680 uart_barrier(bas); 681 uart_setreg(bas, REG_LCR, 0xbf); 682 uart_barrier(bas); 683 efr = uart_getreg(bas, REG_EFR); 684 if (data) 685 efr |= EFR_CTS; 686 else 687 efr &= ~EFR_CTS; 688 uart_setreg(bas, REG_EFR, efr); 689 uart_barrier(bas); 690 uart_setreg(bas, REG_LCR, lcr); 691 uart_barrier(bas); 692 break; 693 case UART_IOCTL_BAUD: 694 lcr = uart_getreg(bas, REG_LCR); 695 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 696 uart_barrier(bas); 697 divisor = uart_getreg(bas, REG_DLL) | 698 (uart_getreg(bas, REG_DLH) << 8); 699 uart_barrier(bas); 700 uart_setreg(bas, REG_LCR, lcr); 701 uart_barrier(bas); 702 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 703 if (baudrate > 0) 704 *(int*)data = baudrate; 705 else 706 error = ENXIO; 707 break; 708 default: 709 error = EINVAL; 710 break; 711 } 712 uart_unlock(sc->sc_hwmtx); 713 return (error); 714 } 715 716 int 717 ns8250_bus_ipend(struct uart_softc *sc) 718 { 719 struct uart_bas *bas; 720 struct ns8250_softc *ns8250; 721 int ipend; 722 uint8_t iir, lsr; 723 724 ns8250 = (struct ns8250_softc *)sc; 725 bas = &sc->sc_bas; 726 uart_lock(sc->sc_hwmtx); 727 iir = uart_getreg(bas, REG_IIR); 728 729 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 730 (void)uart_getreg(bas, DW_REG_USR); 731 uart_unlock(sc->sc_hwmtx); 732 return (0); 733 } 734 if (iir & IIR_NOPEND) { 735 uart_unlock(sc->sc_hwmtx); 736 return (0); 737 } 738 ipend = 0; 739 if (iir & IIR_RXRDY) { 740 lsr = uart_getreg(bas, REG_LSR); 741 if (lsr & LSR_OE) 742 ipend |= SER_INT_OVERRUN; 743 if (lsr & LSR_BI) 744 ipend |= SER_INT_BREAK; 745 if (lsr & LSR_RXRDY) 746 ipend |= SER_INT_RXREADY; 747 } else { 748 if (iir & IIR_TXRDY) { 749 ipend |= SER_INT_TXIDLE; 750 ns8250->ier &= ~IER_ETXRDY; 751 uart_setreg(bas, REG_IER, ns8250->ier); 752 uart_barrier(bas); 753 } else 754 ipend |= SER_INT_SIGCHG; 755 } 756 if (ipend == 0) 757 ns8250_clrint(bas); 758 uart_unlock(sc->sc_hwmtx); 759 return (ipend); 760 } 761 762 int 763 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 764 int stopbits, int parity) 765 { 766 struct ns8250_softc *ns8250; 767 struct uart_bas *bas; 768 int error, limit; 769 770 ns8250 = (struct ns8250_softc*)sc; 771 bas = &sc->sc_bas; 772 uart_lock(sc->sc_hwmtx); 773 /* 774 * When using DW UART with BUSY detection it is necessary to wait 775 * until all serial transfers are finished before manipulating the 776 * line control. LCR will not be affected when UART is busy. 777 */ 778 if (ns8250->busy_detect != 0) { 779 /* 780 * Pick an arbitrary high limit to avoid getting stuck in 781 * an infinite loop in case when the hardware is broken. 782 */ 783 limit = 10 * 1024; 784 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 785 --limit) 786 DELAY(4); 787 788 if (limit <= 0) { 789 /* UART appears to be stuck */ 790 uart_unlock(sc->sc_hwmtx); 791 return (EIO); 792 } 793 } 794 795 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 796 uart_unlock(sc->sc_hwmtx); 797 return (error); 798 } 799 800 int 801 ns8250_bus_probe(struct uart_softc *sc) 802 { 803 struct uart_bas *bas; 804 int count, delay, error, limit; 805 uint8_t lsr, mcr, ier; 806 uint8_t val; 807 808 bas = &sc->sc_bas; 809 810 error = ns8250_probe(bas); 811 if (error) 812 return (error); 813 814 mcr = MCR_IE; 815 if (sc->sc_sysdev == NULL) { 816 /* By using ns8250_init() we also set DTR and RTS. */ 817 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 818 } else 819 mcr |= MCR_DTR | MCR_RTS; 820 821 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 822 if (error) 823 return (error); 824 825 /* 826 * Set loopback mode. This avoids having garbage on the wire and 827 * also allows us send and receive data. We set DTR and RTS to 828 * avoid the possibility that automatic flow-control prevents 829 * any data from being sent. 830 */ 831 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 832 uart_barrier(bas); 833 834 /* 835 * Enable FIFOs. And check that the UART has them. If not, we're 836 * done. Since this is the first time we enable the FIFOs, we reset 837 * them. 838 */ 839 val = FCR_ENABLE; 840 #ifdef CPU_XBURST 841 val |= FCR_UART_ON; 842 #endif 843 uart_setreg(bas, REG_FCR, val); 844 uart_barrier(bas); 845 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 846 /* 847 * NS16450 or INS8250. We don't bother to differentiate 848 * between them. They're too old to be interesting. 849 */ 850 uart_setreg(bas, REG_MCR, mcr); 851 uart_barrier(bas); 852 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 853 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 854 return (0); 855 } 856 857 val = FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST; 858 #ifdef CPU_XBURST 859 val |= FCR_UART_ON; 860 #endif 861 uart_setreg(bas, REG_FCR, val); 862 uart_barrier(bas); 863 864 count = 0; 865 delay = ns8250_delay(bas); 866 867 /* We have FIFOs. Drain the transmitter and receiver. */ 868 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 869 if (error) { 870 uart_setreg(bas, REG_MCR, mcr); 871 val = 0; 872 #ifdef CPU_XBURST 873 val |= FCR_UART_ON; 874 #endif 875 uart_setreg(bas, REG_FCR, val); 876 uart_barrier(bas); 877 goto describe; 878 } 879 880 /* 881 * We should have a sufficiently clean "pipe" to determine the 882 * size of the FIFOs. We send as much characters as is reasonable 883 * and wait for the overflow bit in the LSR register to be 884 * asserted, counting the characters as we send them. Based on 885 * that count we know the FIFO size. 886 */ 887 do { 888 uart_setreg(bas, REG_DATA, 0); 889 uart_barrier(bas); 890 count++; 891 892 limit = 30; 893 lsr = 0; 894 /* 895 * LSR bits are cleared upon read, so we must accumulate 896 * them to be able to test LSR_OE below. 897 */ 898 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 899 --limit) 900 DELAY(delay); 901 if (limit == 0) { 902 /* See the comment in ns8250_init(). */ 903 ier = uart_getreg(bas, REG_IER) & 0xe0; 904 uart_setreg(bas, REG_IER, ier); 905 uart_setreg(bas, REG_MCR, mcr); 906 val = 0; 907 #ifdef CPU_XBURST 908 val |= FCR_UART_ON; 909 #endif 910 uart_setreg(bas, REG_FCR, val); 911 uart_barrier(bas); 912 count = 0; 913 goto describe; 914 } 915 } while ((lsr & LSR_OE) == 0 && count < 260); 916 count--; 917 918 uart_setreg(bas, REG_MCR, mcr); 919 920 /* Reset FIFOs. */ 921 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 922 923 describe: 924 if (count >= 14 && count <= 16) { 925 sc->sc_rxfifosz = 16; 926 device_set_desc(sc->sc_dev, "16550 or compatible"); 927 } else if (count >= 28 && count <= 32) { 928 sc->sc_rxfifosz = 32; 929 device_set_desc(sc->sc_dev, "16650 or compatible"); 930 } else if (count >= 56 && count <= 64) { 931 sc->sc_rxfifosz = 64; 932 device_set_desc(sc->sc_dev, "16750 or compatible"); 933 } else if (count >= 112 && count <= 128) { 934 sc->sc_rxfifosz = 128; 935 device_set_desc(sc->sc_dev, "16950 or compatible"); 936 } else if (count >= 224 && count <= 256) { 937 sc->sc_rxfifosz = 256; 938 device_set_desc(sc->sc_dev, "16x50 with 256 byte FIFO"); 939 } else { 940 sc->sc_rxfifosz = 16; 941 device_set_desc(sc->sc_dev, 942 "Non-standard ns8250 class UART with FIFOs"); 943 } 944 945 /* 946 * Force the Tx FIFO size to 16 bytes for now. We don't program the 947 * Tx trigger. Also, we assume that all data has been sent when the 948 * interrupt happens. 949 */ 950 sc->sc_txfifosz = 16; 951 952 #if 0 953 /* 954 * XXX there are some issues related to hardware flow control and 955 * it's likely that uart(4) is the cause. This basically needs more 956 * investigation, but we avoid using for hardware flow control 957 * until then. 958 */ 959 /* 16650s or higher have automatic flow control. */ 960 if (sc->sc_rxfifosz > 16) { 961 sc->sc_hwiflow = 1; 962 sc->sc_hwoflow = 1; 963 } 964 #endif 965 966 return (0); 967 } 968 969 int 970 ns8250_bus_receive(struct uart_softc *sc) 971 { 972 struct uart_bas *bas; 973 int xc; 974 uint8_t lsr; 975 976 bas = &sc->sc_bas; 977 uart_lock(sc->sc_hwmtx); 978 lsr = uart_getreg(bas, REG_LSR); 979 while (lsr & LSR_RXRDY) { 980 if (uart_rx_full(sc)) { 981 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 982 break; 983 } 984 xc = uart_getreg(bas, REG_DATA); 985 if (lsr & LSR_FE) 986 xc |= UART_STAT_FRAMERR; 987 if (lsr & LSR_PE) 988 xc |= UART_STAT_PARERR; 989 uart_rx_put(sc, xc); 990 lsr = uart_getreg(bas, REG_LSR); 991 } 992 /* Discard everything left in the Rx FIFO. */ 993 while (lsr & LSR_RXRDY) { 994 (void)uart_getreg(bas, REG_DATA); 995 uart_barrier(bas); 996 lsr = uart_getreg(bas, REG_LSR); 997 } 998 uart_unlock(sc->sc_hwmtx); 999 return (0); 1000 } 1001 1002 int 1003 ns8250_bus_setsig(struct uart_softc *sc, int sig) 1004 { 1005 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1006 struct uart_bas *bas; 1007 uint32_t new, old; 1008 1009 bas = &sc->sc_bas; 1010 do { 1011 old = sc->sc_hwsig; 1012 new = old; 1013 if (sig & SER_DDTR) { 1014 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR)); 1015 } 1016 if (sig & SER_DRTS) { 1017 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS)); 1018 } 1019 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 1020 uart_lock(sc->sc_hwmtx); 1021 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 1022 if (new & SER_DTR) 1023 ns8250->mcr |= MCR_DTR; 1024 if (new & SER_RTS) 1025 ns8250->mcr |= MCR_RTS; 1026 uart_setreg(bas, REG_MCR, ns8250->mcr); 1027 uart_barrier(bas); 1028 uart_unlock(sc->sc_hwmtx); 1029 return (0); 1030 } 1031 1032 int 1033 ns8250_bus_transmit(struct uart_softc *sc) 1034 { 1035 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1036 struct uart_bas *bas; 1037 int i; 1038 1039 bas = &sc->sc_bas; 1040 uart_lock(sc->sc_hwmtx); 1041 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 1042 DELAY(4); 1043 for (i = 0; i < sc->sc_txdatasz; i++) { 1044 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 1045 uart_barrier(bas); 1046 } 1047 if (!broken_txfifo) 1048 ns8250->ier |= IER_ETXRDY; 1049 uart_setreg(bas, REG_IER, ns8250->ier); 1050 uart_barrier(bas); 1051 if (broken_txfifo) 1052 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 1053 else 1054 sc->sc_txbusy = 1; 1055 uart_unlock(sc->sc_hwmtx); 1056 if (broken_txfifo) 1057 uart_sched_softih(sc, SER_INT_TXIDLE); 1058 return (0); 1059 } 1060 1061 void 1062 ns8250_bus_grab(struct uart_softc *sc) 1063 { 1064 struct uart_bas *bas = &sc->sc_bas; 1065 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1066 u_char ier; 1067 1068 /* 1069 * turn off all interrupts to enter polling mode. Leave the 1070 * saved mask alone. We'll restore whatever it was in ungrab. 1071 * All pending interrupt signals are reset when IER is set to 0. 1072 */ 1073 uart_lock(sc->sc_hwmtx); 1074 ier = uart_getreg(bas, REG_IER); 1075 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 1076 uart_barrier(bas); 1077 uart_unlock(sc->sc_hwmtx); 1078 } 1079 1080 void 1081 ns8250_bus_ungrab(struct uart_softc *sc) 1082 { 1083 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1084 struct uart_bas *bas = &sc->sc_bas; 1085 1086 /* 1087 * Restore previous interrupt mask 1088 */ 1089 uart_lock(sc->sc_hwmtx); 1090 uart_setreg(bas, REG_IER, ns8250->ier); 1091 uart_barrier(bas); 1092 uart_unlock(sc->sc_hwmtx); 1093 } 1094