1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2003 Marcel Moolenaar 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "opt_acpi.h" 30 #include "opt_platform.h" 31 #include "opt_uart.h" 32 33 #include <sys/cdefs.h> 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/conf.h> 38 #include <sys/kernel.h> 39 #include <sys/sysctl.h> 40 #include <machine/bus.h> 41 42 #ifdef FDT 43 #include <dev/fdt/fdt_common.h> 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 #endif 47 48 #include <dev/uart/uart.h> 49 #include <dev/uart/uart_cpu.h> 50 #ifdef FDT 51 #include <dev/uart/uart_cpu_fdt.h> 52 #endif 53 #include <dev/uart/uart_bus.h> 54 #include <dev/uart/uart_dev_ns8250.h> 55 #include <dev/uart/uart_ppstypes.h> 56 #ifdef DEV_ACPI 57 #include <dev/uart/uart_cpu_acpi.h> 58 #include <contrib/dev/acpica/include/acpi.h> 59 #endif 60 61 #include <dev/ic/ns16550.h> 62 63 #include "uart_if.h" 64 65 #define DEFAULT_RCLK 1843200 66 67 /* 68 * Set the default baudrate tolerance to 3.0%. 69 * 70 * Some embedded boards have odd reference clocks (eg 25MHz) 71 * and we need to handle higher variances in the target baud rate. 72 */ 73 #ifndef UART_DEV_TOLERANCE_PCT 74 #define UART_DEV_TOLERANCE_PCT 30 75 #endif /* UART_DEV_TOLERANCE_PCT */ 76 77 static int broken_txfifo = 0; 78 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 79 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 80 81 /* 82 * Clear pending interrupts. THRE is cleared by reading IIR. Data 83 * that may have been received gets lost here. 84 */ 85 static void 86 ns8250_clrint(struct uart_bas *bas) 87 { 88 uint8_t iir, lsr; 89 90 iir = uart_getreg(bas, REG_IIR); 91 while ((iir & IIR_NOPEND) == 0) { 92 iir &= IIR_IMASK; 93 if (iir == IIR_RLS) { 94 lsr = uart_getreg(bas, REG_LSR); 95 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 96 (void)uart_getreg(bas, REG_DATA); 97 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 98 (void)uart_getreg(bas, REG_DATA); 99 else if (iir == IIR_MLSC) 100 (void)uart_getreg(bas, REG_MSR); 101 uart_barrier(bas); 102 iir = uart_getreg(bas, REG_IIR); 103 } 104 } 105 106 static int 107 ns8250_delay(struct uart_bas *bas) 108 { 109 int divisor; 110 u_char lcr; 111 112 lcr = uart_getreg(bas, REG_LCR); 113 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 114 uart_barrier(bas); 115 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 116 uart_barrier(bas); 117 uart_setreg(bas, REG_LCR, lcr); 118 uart_barrier(bas); 119 120 /* 1/10th the time to transmit 1 character (estimate). */ 121 if (divisor <= 134) 122 return (16000000 * divisor / bas->rclk); 123 return (16000 * divisor / (bas->rclk / 1000)); 124 } 125 126 static int 127 ns8250_divisor(int rclk, int baudrate) 128 { 129 int actual_baud, divisor; 130 int error; 131 132 if (baudrate == 0) 133 return (0); 134 135 divisor = (rclk / (baudrate << 3) + 1) >> 1; 136 if (divisor == 0 || divisor >= 65536) 137 return (0); 138 actual_baud = rclk / (divisor << 4); 139 140 /* 10 times error in percent: */ 141 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) / 2; 142 143 /* enforce maximum error tolerance: */ 144 if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT) 145 return (0); 146 147 return (divisor); 148 } 149 150 static int 151 ns8250_drain(struct uart_bas *bas, int what) 152 { 153 int delay, limit; 154 155 delay = ns8250_delay(bas); 156 157 if (what & UART_DRAIN_TRANSMITTER) { 158 /* 159 * Pick an arbitrary high limit to avoid getting stuck in 160 * an infinite loop when the hardware is broken. Make the 161 * limit high enough to handle large FIFOs. 162 */ 163 limit = 10*1024; 164 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 165 DELAY(delay); 166 if (limit == 0) { 167 /* printf("ns8250: transmitter appears stuck... "); */ 168 return (EIO); 169 } 170 } 171 172 if (what & UART_DRAIN_RECEIVER) { 173 /* 174 * Pick an arbitrary high limit to avoid getting stuck in 175 * an infinite loop when the hardware is broken. Make the 176 * limit high enough to handle large FIFOs and integrated 177 * UARTs. The HP rx2600 for example has 3 UARTs on the 178 * management board that tend to get a lot of data send 179 * to it when the UART is first activated. Assume that we 180 * have finished draining if LSR_RXRDY is not asserted both 181 * prior to and after a DELAY; but as long as LSR_RXRDY is 182 * asserted, read (and discard) characters as quickly as 183 * possible. 184 */ 185 limit=10*4096; 186 while (limit && (uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 187 do { 188 (void)uart_getreg(bas, REG_DATA); 189 uart_barrier(bas); 190 } while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit); 191 uart_barrier(bas); 192 DELAY(delay << 2); 193 } 194 if (limit == 0) { 195 /* printf("ns8250: receiver appears broken... "); */ 196 return (EIO); 197 } 198 } 199 200 return (0); 201 } 202 203 /* 204 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 205 * drained. WARNING: this function clobbers the FIFO setting! 206 */ 207 static void 208 ns8250_flush(struct uart_bas *bas, int what) 209 { 210 uint8_t fcr; 211 uint8_t lsr; 212 int drain = 0; 213 214 fcr = FCR_ENABLE; 215 #ifdef CPU_XBURST 216 fcr |= FCR_UART_ON; 217 #endif 218 if (what & UART_FLUSH_TRANSMITTER) 219 fcr |= FCR_XMT_RST; 220 if (what & UART_FLUSH_RECEIVER) 221 fcr |= FCR_RCV_RST; 222 uart_setreg(bas, REG_FCR, fcr); 223 uart_barrier(bas); 224 225 /* 226 * Detect and work around emulated UARTs which don't implement the 227 * FCR register; on these systems we need to drain the FIFO since 228 * the flush we request doesn't happen. One such system is the 229 * Firecracker VMM, aka. the rust-vmm/vm-superio emulation code: 230 * https://github.com/rust-vmm/vm-superio/issues/83 231 */ 232 lsr = uart_getreg(bas, REG_LSR); 233 if (((lsr & LSR_TEMT) == 0) && (what & UART_FLUSH_TRANSMITTER)) 234 drain |= UART_DRAIN_TRANSMITTER; 235 if ((lsr & LSR_RXRDY) && (what & UART_FLUSH_RECEIVER)) 236 drain |= UART_DRAIN_RECEIVER; 237 if (drain != 0) { 238 printf("ns8250: UART FCR is broken\n"); 239 ns8250_drain(bas, drain); 240 } 241 } 242 243 static int 244 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 245 int parity) 246 { 247 int divisor; 248 uint8_t lcr; 249 250 /* Don't change settings when running on Hyper-V */ 251 if (vm_guest == VM_GUEST_HV) 252 return (0); 253 254 lcr = 0; 255 if (databits >= 8) 256 lcr |= LCR_8BITS; 257 else if (databits == 7) 258 lcr |= LCR_7BITS; 259 else if (databits == 6) 260 lcr |= LCR_6BITS; 261 else 262 lcr |= LCR_5BITS; 263 if (stopbits > 1) 264 lcr |= LCR_STOPB; 265 lcr |= parity << 3; 266 267 /* Set baudrate. */ 268 if (baudrate > 0) { 269 divisor = ns8250_divisor(bas->rclk, baudrate); 270 if (divisor == 0) 271 return (EINVAL); 272 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 273 uart_barrier(bas); 274 uart_setreg(bas, REG_DLL, divisor & 0xff); 275 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 276 uart_barrier(bas); 277 } 278 279 /* Set LCR and clear DLAB. */ 280 uart_setreg(bas, REG_LCR, lcr); 281 uart_barrier(bas); 282 return (0); 283 } 284 285 /* 286 * Low-level UART interface. 287 */ 288 static int ns8250_probe(struct uart_bas *bas); 289 static void ns8250_init(struct uart_bas *bas, int, int, int, int); 290 static void ns8250_term(struct uart_bas *bas); 291 static void ns8250_putc(struct uart_bas *bas, int); 292 static int ns8250_rxready(struct uart_bas *bas); 293 static int ns8250_getc(struct uart_bas *bas, struct mtx *); 294 295 struct uart_ops uart_ns8250_ops = { 296 .probe = ns8250_probe, 297 .init = ns8250_init, 298 .term = ns8250_term, 299 .putc = ns8250_putc, 300 .rxready = ns8250_rxready, 301 .getc = ns8250_getc, 302 }; 303 304 static int 305 ns8250_probe(struct uart_bas *bas) 306 { 307 u_char val; 308 309 #ifdef CPU_XBURST 310 uart_setreg(bas, REG_FCR, FCR_UART_ON); 311 #endif 312 313 /* Check known 0 bits that don't depend on DLAB. */ 314 val = uart_getreg(bas, REG_IIR); 315 if (val & 0x30) 316 return (ENXIO); 317 /* 318 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 319 * chip, but otherwise doesn't seem to have a function. In 320 * other words, uart(4) works regardless. Ignore that bit so 321 * the probe succeeds. 322 */ 323 val = uart_getreg(bas, REG_MCR); 324 if (val & 0xa0) 325 return (ENXIO); 326 327 return (0); 328 } 329 330 static void 331 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 332 int parity) 333 { 334 u_char ier, val; 335 336 if (bas->rclk == 0) 337 bas->rclk = DEFAULT_RCLK; 338 ns8250_param(bas, baudrate, databits, stopbits, parity); 339 340 /* Disable all interrupt sources. */ 341 /* 342 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 343 * UARTs split the receive time-out interrupt bit out separately as 344 * 0x10. This gets handled by ier_mask and ier_rxbits below. 345 */ 346 ier = uart_getreg(bas, REG_IER) & 0xe0; 347 uart_setreg(bas, REG_IER, ier); 348 uart_barrier(bas); 349 350 /* Disable the FIFO (if present). */ 351 val = 0; 352 #ifdef CPU_XBURST 353 val |= FCR_UART_ON; 354 #endif 355 uart_setreg(bas, REG_FCR, val); 356 uart_barrier(bas); 357 358 /* Set RTS & DTR. */ 359 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 360 uart_barrier(bas); 361 362 ns8250_clrint(bas); 363 } 364 365 static void 366 ns8250_term(struct uart_bas *bas) 367 { 368 369 /* Clear RTS & DTR. */ 370 uart_setreg(bas, REG_MCR, MCR_IE); 371 uart_barrier(bas); 372 } 373 374 static void 375 ns8250_putc(struct uart_bas *bas, int c) 376 { 377 int limit; 378 379 if (vm_guest != VM_GUEST_HV) { 380 limit = 250000; 381 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 382 DELAY(4); 383 } 384 uart_setreg(bas, REG_DATA, c); 385 uart_barrier(bas); 386 } 387 388 static int 389 ns8250_rxready(struct uart_bas *bas) 390 { 391 392 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 393 } 394 395 static int 396 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 397 { 398 int c; 399 400 uart_lock(hwmtx); 401 402 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 403 uart_unlock(hwmtx); 404 DELAY(4); 405 uart_lock(hwmtx); 406 } 407 408 c = uart_getreg(bas, REG_DATA); 409 410 uart_unlock(hwmtx); 411 412 return (c); 413 } 414 415 static kobj_method_t ns8250_methods[] = { 416 KOBJMETHOD(uart_attach, ns8250_bus_attach), 417 KOBJMETHOD(uart_detach, ns8250_bus_detach), 418 KOBJMETHOD(uart_flush, ns8250_bus_flush), 419 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 420 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 421 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 422 KOBJMETHOD(uart_param, ns8250_bus_param), 423 KOBJMETHOD(uart_probe, ns8250_bus_probe), 424 KOBJMETHOD(uart_receive, ns8250_bus_receive), 425 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 426 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 427 KOBJMETHOD(uart_txbusy, ns8250_bus_txbusy), 428 KOBJMETHOD(uart_grab, ns8250_bus_grab), 429 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 430 KOBJMETHOD_END 431 }; 432 433 struct uart_class uart_ns8250_class = { 434 "ns8250", 435 ns8250_methods, 436 sizeof(struct ns8250_softc), 437 .uc_ops = &uart_ns8250_ops, 438 .uc_range = 8, 439 .uc_rclk = DEFAULT_RCLK, 440 .uc_rshift = 0 441 }; 442 443 /* 444 * XXX -- refactor out ACPI and FDT ifdefs 445 */ 446 #ifdef DEV_ACPI 447 static struct acpi_uart_compat_data acpi_compat_data[] = { 448 {"AMD0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 449 {"AMDI0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 450 {"MRVL0001", &uart_ns8250_class, ACPI_DBG2_16550_SUBSET, 2, 0, 200000000, UART_F_BUSY_DETECT, "Marvell / Synopsys Designware UART"}, 451 {"SCX0006", &uart_ns8250_class, 0, 2, 0, 62500000, UART_F_BUSY_DETECT, "SynQuacer / Synopsys Designware UART"}, 452 {"HISI0031", &uart_ns8250_class, 0, 2, 0, 200000000, UART_F_BUSY_DETECT, "HiSilicon / Synopsys Designware UART"}, 453 {"NXP0018", &uart_ns8250_class, 0, 0, 0, 350000000, UART_F_BUSY_DETECT, "NXP / Synopsys Designware UART"}, 454 {"PNP0500", &uart_ns8250_class, 0, 0, 0, 0, 0, "Standard PC COM port"}, 455 {"PNP0501", &uart_ns8250_class, 0, 0, 0, 0, 0, "16550A-compatible COM port"}, 456 {"PNP0502", &uart_ns8250_class, 0, 0, 0, 0, 0, "Multiport serial device (non-intelligent 16550)"}, 457 {"PNP0510", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 458 {"PNP0511", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 459 {"WACF004", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen"}, 460 {"WACF00E", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen 00e"}, 461 {"FUJ02E5", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet at FuS Lifebook T"}, 462 {NULL, NULL, 0, 0 , 0, 0, 0, NULL}, 463 }; 464 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data); 465 #endif 466 467 #ifdef FDT 468 static struct ofw_compat_data compat_data[] = { 469 {"ns16550", (uintptr_t)&uart_ns8250_class}, 470 {"ns16550a", (uintptr_t)&uart_ns8250_class}, 471 {NULL, (uintptr_t)NULL}, 472 }; 473 UART_FDT_CLASS_AND_DEVICE(compat_data); 474 #endif 475 476 /* Use token-pasting to form SER_ and MSR_ named constants. */ 477 #define SER(sig) SER_##sig 478 #define SERD(sig) SER_D##sig 479 #define MSR(sig) MSR_##sig 480 #define MSRD(sig) MSR_D##sig 481 482 /* 483 * Detect signal changes using software delta detection. The previous state of 484 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the 485 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the 486 * new state of both the signal and the delta bits. 487 */ 488 #define SIGCHGSW(var, msr, sig) \ 489 if ((msr) & MSR(sig)) { \ 490 if ((var & SER(sig)) == 0) \ 491 var |= SERD(sig) | SER(sig); \ 492 } else { \ 493 if ((var & SER(sig)) != 0) \ 494 var = SERD(sig) | (var & ~SER(sig)); \ 495 } 496 497 /* 498 * Detect signal changes using the hardware msr delta bits. This is currently 499 * used only when PPS timing information is being captured using the "narrow 500 * pulse" option. With a narrow PPS pulse the signal may not still be asserted 501 * by time the interrupt handler is invoked. The hardware will latch the fact 502 * that it changed in the delta bits. 503 */ 504 #define SIGCHGHW(var, msr, sig) \ 505 if ((msr) & MSRD(sig)) { \ 506 if (((msr) & MSR(sig)) != 0) \ 507 var |= SERD(sig) | SER(sig); \ 508 else \ 509 var = SERD(sig) | (var & ~SER(sig)); \ 510 } 511 512 int 513 ns8250_bus_attach(struct uart_softc *sc) 514 { 515 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 516 struct uart_bas *bas; 517 unsigned int ivar; 518 #ifdef FDT 519 phandle_t node; 520 pcell_t cell; 521 #endif 522 523 #ifdef FDT 524 /* Check whether uart has a broken txfifo. */ 525 node = ofw_bus_get_node(sc->sc_dev); 526 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 527 broken_txfifo = cell ? 1 : 0; 528 #endif 529 530 bas = &sc->sc_bas; 531 532 ns8250->busy_detect = bas->busy_detect; 533 ns8250->mcr = uart_getreg(bas, REG_MCR); 534 ns8250->fcr = FCR_ENABLE; 535 #ifdef CPU_XBURST 536 ns8250->fcr |= FCR_UART_ON; 537 #endif 538 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 539 &ivar)) { 540 if (UART_FLAGS_FCR_RX_LOW(ivar)) 541 ns8250->fcr |= FCR_RX_LOW; 542 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 543 ns8250->fcr |= FCR_RX_MEDL; 544 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 545 ns8250->fcr |= FCR_RX_HIGH; 546 else 547 ns8250->fcr |= FCR_RX_MEDH; 548 } else 549 ns8250->fcr |= FCR_RX_MEDH; 550 551 /* Get IER mask */ 552 ivar = 0xf0; 553 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 554 &ivar); 555 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 556 557 /* Get IER RX interrupt bits */ 558 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 559 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 560 &ivar); 561 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 562 563 uart_setreg(bas, REG_FCR, ns8250->fcr); 564 uart_barrier(bas); 565 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 566 567 if (ns8250->mcr & MCR_DTR) 568 sc->sc_hwsig |= SER_DTR; 569 if (ns8250->mcr & MCR_RTS) 570 sc->sc_hwsig |= SER_RTS; 571 ns8250_bus_getsig(sc); 572 573 ns8250_clrint(bas); 574 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 575 ns8250->ier |= ns8250->ier_rxbits; 576 uart_setreg(bas, REG_IER, ns8250->ier); 577 uart_barrier(bas); 578 579 /* 580 * Timing of the H/W access was changed with r253161 of uart_core.c 581 * It has been observed that an ITE IT8513E would signal a break 582 * condition with pretty much every character it received, unless 583 * it had enough time to settle between ns8250_bus_attach() and 584 * ns8250_bus_ipend() -- which it accidentally had before r253161. 585 * It's not understood why the UART chip behaves this way and it 586 * could very well be that the DELAY make the H/W work in the same 587 * accidental manner as before. More analysis is warranted, but 588 * at least now we fixed a known regression. 589 */ 590 DELAY(200); 591 return (0); 592 } 593 594 int 595 ns8250_bus_detach(struct uart_softc *sc) 596 { 597 struct ns8250_softc *ns8250; 598 struct uart_bas *bas; 599 u_char ier; 600 601 ns8250 = (struct ns8250_softc *)sc; 602 bas = &sc->sc_bas; 603 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 604 uart_setreg(bas, REG_IER, ier); 605 uart_barrier(bas); 606 ns8250_clrint(bas); 607 return (0); 608 } 609 610 int 611 ns8250_bus_flush(struct uart_softc *sc, int what) 612 { 613 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 614 struct uart_bas *bas; 615 int error; 616 617 bas = &sc->sc_bas; 618 uart_lock(sc->sc_hwmtx); 619 if (sc->sc_rxfifosz > 1) { 620 ns8250_flush(bas, what); 621 uart_setreg(bas, REG_FCR, ns8250->fcr); 622 uart_barrier(bas); 623 error = 0; 624 } else 625 error = ns8250_drain(bas, what); 626 uart_unlock(sc->sc_hwmtx); 627 return (error); 628 } 629 630 int 631 ns8250_bus_getsig(struct uart_softc *sc) 632 { 633 uint32_t old, sig; 634 uint8_t msr; 635 636 /* 637 * The delta bits are reputed to be broken on some hardware, so use 638 * software delta detection by default. Use the hardware delta bits 639 * when capturing PPS pulses which are too narrow for software detection 640 * to see the edges. Hardware delta for RI doesn't work like the 641 * others, so always use software for it. Other threads may be changing 642 * other (non-MSR) bits in sc_hwsig, so loop until it can successfully 643 * update without other changes happening. Note that the SIGCHGxx() 644 * macros carefully preserve the delta bits when we have to loop several 645 * times and a signal transitions between iterations. 646 */ 647 do { 648 old = sc->sc_hwsig; 649 sig = old; 650 uart_lock(sc->sc_hwmtx); 651 msr = uart_getreg(&sc->sc_bas, REG_MSR); 652 uart_unlock(sc->sc_hwmtx); 653 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) { 654 SIGCHGHW(sig, msr, DSR); 655 SIGCHGHW(sig, msr, CTS); 656 SIGCHGHW(sig, msr, DCD); 657 } else { 658 SIGCHGSW(sig, msr, DSR); 659 SIGCHGSW(sig, msr, CTS); 660 SIGCHGSW(sig, msr, DCD); 661 } 662 SIGCHGSW(sig, msr, RI); 663 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA)); 664 return (sig); 665 } 666 667 int 668 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 669 { 670 struct uart_bas *bas; 671 int baudrate, divisor, error; 672 uint8_t efr, lcr; 673 674 bas = &sc->sc_bas; 675 error = 0; 676 uart_lock(sc->sc_hwmtx); 677 switch (request) { 678 case UART_IOCTL_BREAK: 679 lcr = uart_getreg(bas, REG_LCR); 680 if (data) 681 lcr |= LCR_SBREAK; 682 else 683 lcr &= ~LCR_SBREAK; 684 uart_setreg(bas, REG_LCR, lcr); 685 uart_barrier(bas); 686 break; 687 case UART_IOCTL_IFLOW: 688 lcr = uart_getreg(bas, REG_LCR); 689 uart_barrier(bas); 690 uart_setreg(bas, REG_LCR, 0xbf); 691 uart_barrier(bas); 692 efr = uart_getreg(bas, REG_EFR); 693 if (data) 694 efr |= EFR_RTS; 695 else 696 efr &= ~EFR_RTS; 697 uart_setreg(bas, REG_EFR, efr); 698 uart_barrier(bas); 699 uart_setreg(bas, REG_LCR, lcr); 700 uart_barrier(bas); 701 break; 702 case UART_IOCTL_OFLOW: 703 lcr = uart_getreg(bas, REG_LCR); 704 uart_barrier(bas); 705 uart_setreg(bas, REG_LCR, 0xbf); 706 uart_barrier(bas); 707 efr = uart_getreg(bas, REG_EFR); 708 if (data) 709 efr |= EFR_CTS; 710 else 711 efr &= ~EFR_CTS; 712 uart_setreg(bas, REG_EFR, efr); 713 uart_barrier(bas); 714 uart_setreg(bas, REG_LCR, lcr); 715 uart_barrier(bas); 716 break; 717 case UART_IOCTL_BAUD: 718 lcr = uart_getreg(bas, REG_LCR); 719 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 720 uart_barrier(bas); 721 divisor = uart_getreg(bas, REG_DLL) | 722 (uart_getreg(bas, REG_DLH) << 8); 723 uart_barrier(bas); 724 uart_setreg(bas, REG_LCR, lcr); 725 uart_barrier(bas); 726 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 727 if (baudrate > 0) 728 *(int*)data = baudrate; 729 else 730 error = ENXIO; 731 break; 732 default: 733 error = EINVAL; 734 break; 735 } 736 uart_unlock(sc->sc_hwmtx); 737 return (error); 738 } 739 740 int 741 ns8250_bus_ipend(struct uart_softc *sc) 742 { 743 struct uart_bas *bas; 744 struct ns8250_softc *ns8250; 745 int ipend; 746 uint8_t iir, lsr; 747 748 ns8250 = (struct ns8250_softc *)sc; 749 bas = &sc->sc_bas; 750 uart_lock(sc->sc_hwmtx); 751 iir = uart_getreg(bas, REG_IIR); 752 753 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 754 (void)uart_getreg(bas, DW_REG_USR); 755 uart_unlock(sc->sc_hwmtx); 756 return (0); 757 } 758 if (iir & IIR_NOPEND) { 759 uart_unlock(sc->sc_hwmtx); 760 return (0); 761 } 762 ipend = 0; 763 if (iir & IIR_RXRDY) { 764 lsr = uart_getreg(bas, REG_LSR); 765 if (lsr & LSR_OE) 766 ipend |= SER_INT_OVERRUN; 767 if (lsr & LSR_BI) 768 ipend |= SER_INT_BREAK; 769 if (lsr & LSR_RXRDY) 770 ipend |= SER_INT_RXREADY; 771 } else { 772 if (iir & IIR_TXRDY) { 773 ipend |= SER_INT_TXIDLE; 774 ns8250->ier &= ~IER_ETXRDY; 775 uart_setreg(bas, REG_IER, ns8250->ier); 776 uart_barrier(bas); 777 } else 778 ipend |= SER_INT_SIGCHG; 779 } 780 if (ipend == 0) 781 ns8250_clrint(bas); 782 uart_unlock(sc->sc_hwmtx); 783 return (ipend); 784 } 785 786 int 787 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 788 int stopbits, int parity) 789 { 790 struct ns8250_softc *ns8250; 791 struct uart_bas *bas; 792 int error, limit; 793 794 ns8250 = (struct ns8250_softc*)sc; 795 bas = &sc->sc_bas; 796 uart_lock(sc->sc_hwmtx); 797 /* 798 * When using DW UART with BUSY detection it is necessary to wait 799 * until all serial transfers are finished before manipulating the 800 * line control. LCR will not be affected when UART is busy. 801 */ 802 if (ns8250->busy_detect != 0) { 803 /* 804 * Pick an arbitrary high limit to avoid getting stuck in 805 * an infinite loop in case when the hardware is broken. 806 */ 807 limit = 10 * 1024; 808 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 809 --limit) 810 DELAY(4); 811 812 if (limit <= 0) { 813 /* UART appears to be stuck */ 814 uart_unlock(sc->sc_hwmtx); 815 return (EIO); 816 } 817 } 818 819 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 820 uart_unlock(sc->sc_hwmtx); 821 return (error); 822 } 823 824 int 825 ns8250_bus_probe(struct uart_softc *sc) 826 { 827 struct uart_bas *bas; 828 int count, delay, error, limit; 829 uint8_t lsr, mcr, ier; 830 uint8_t val; 831 832 bas = &sc->sc_bas; 833 834 error = ns8250_probe(bas); 835 if (error) 836 return (error); 837 838 mcr = MCR_IE; 839 if (sc->sc_sysdev == NULL) { 840 /* By using ns8250_init() we also set DTR and RTS. */ 841 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 842 } else 843 mcr |= MCR_DTR | MCR_RTS; 844 845 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 846 if (error) 847 return (error); 848 849 /* 850 * Set loopback mode. This avoids having garbage on the wire and 851 * also allows us send and receive data. We set DTR and RTS to 852 * avoid the possibility that automatic flow-control prevents 853 * any data from being sent. 854 */ 855 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 856 uart_barrier(bas); 857 858 /* 859 * Enable FIFOs. And check that the UART has them. If not, we're 860 * done. Since this is the first time we enable the FIFOs, we reset 861 * them. 862 */ 863 val = FCR_ENABLE; 864 #ifdef CPU_XBURST 865 val |= FCR_UART_ON; 866 #endif 867 uart_setreg(bas, REG_FCR, val); 868 uart_barrier(bas); 869 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 870 /* 871 * NS16450 or INS8250. We don't bother to differentiate 872 * between them. They're too old to be interesting. 873 */ 874 uart_setreg(bas, REG_MCR, mcr); 875 uart_barrier(bas); 876 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 877 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 878 return (0); 879 } 880 881 val = FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST; 882 #ifdef CPU_XBURST 883 val |= FCR_UART_ON; 884 #endif 885 uart_setreg(bas, REG_FCR, val); 886 uart_barrier(bas); 887 888 count = 0; 889 delay = ns8250_delay(bas); 890 891 /* We have FIFOs. Drain the transmitter and receiver. */ 892 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 893 if (error) { 894 uart_setreg(bas, REG_MCR, mcr); 895 val = 0; 896 #ifdef CPU_XBURST 897 val |= FCR_UART_ON; 898 #endif 899 uart_setreg(bas, REG_FCR, val); 900 uart_barrier(bas); 901 goto describe; 902 } 903 904 /* 905 * We should have a sufficiently clean "pipe" to determine the 906 * size of the FIFOs. We send as much characters as is reasonable 907 * and wait for the overflow bit in the LSR register to be 908 * asserted, counting the characters as we send them. Based on 909 * that count we know the FIFO size. 910 */ 911 do { 912 uart_setreg(bas, REG_DATA, 0); 913 uart_barrier(bas); 914 count++; 915 916 limit = 30; 917 lsr = 0; 918 /* 919 * LSR bits are cleared upon read, so we must accumulate 920 * them to be able to test LSR_OE below. 921 */ 922 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 923 --limit) 924 DELAY(delay); 925 if (limit == 0) { 926 /* See the comment in ns8250_init(). */ 927 ier = uart_getreg(bas, REG_IER) & 0xe0; 928 uart_setreg(bas, REG_IER, ier); 929 uart_setreg(bas, REG_MCR, mcr); 930 val = 0; 931 #ifdef CPU_XBURST 932 val |= FCR_UART_ON; 933 #endif 934 uart_setreg(bas, REG_FCR, val); 935 uart_barrier(bas); 936 count = 0; 937 goto describe; 938 } 939 } while ((lsr & LSR_OE) == 0 && count < 260); 940 count--; 941 942 uart_setreg(bas, REG_MCR, mcr); 943 944 /* Reset FIFOs. */ 945 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 946 947 describe: 948 if (count >= 14 && count <= 16) { 949 sc->sc_rxfifosz = 16; 950 device_set_desc(sc->sc_dev, "16550 or compatible"); 951 } else if (count >= 28 && count <= 32) { 952 sc->sc_rxfifosz = 32; 953 device_set_desc(sc->sc_dev, "16650 or compatible"); 954 } else if (count >= 56 && count <= 64) { 955 sc->sc_rxfifosz = 64; 956 device_set_desc(sc->sc_dev, "16750 or compatible"); 957 } else if (count >= 112 && count <= 128) { 958 sc->sc_rxfifosz = 128; 959 device_set_desc(sc->sc_dev, "16950 or compatible"); 960 } else if (count >= 224 && count <= 256) { 961 sc->sc_rxfifosz = 256; 962 device_set_desc(sc->sc_dev, "16x50 with 256 byte FIFO"); 963 } else { 964 sc->sc_rxfifosz = 16; 965 device_set_desc(sc->sc_dev, 966 "Non-standard ns8250 class UART with FIFOs"); 967 } 968 969 /* 970 * Force the Tx FIFO size to 16 bytes for now. We don't program the 971 * Tx trigger. Also, we assume that all data has been sent when the 972 * interrupt happens. 973 */ 974 sc->sc_txfifosz = 16; 975 976 #if 0 977 /* 978 * XXX there are some issues related to hardware flow control and 979 * it's likely that uart(4) is the cause. This basically needs more 980 * investigation, but we avoid using for hardware flow control 981 * until then. 982 */ 983 /* 16650s or higher have automatic flow control. */ 984 if (sc->sc_rxfifosz > 16) { 985 sc->sc_hwiflow = 1; 986 sc->sc_hwoflow = 1; 987 } 988 #endif 989 990 return (0); 991 } 992 993 int 994 ns8250_bus_receive(struct uart_softc *sc) 995 { 996 struct uart_bas *bas; 997 int xc; 998 uint8_t lsr; 999 1000 bas = &sc->sc_bas; 1001 uart_lock(sc->sc_hwmtx); 1002 lsr = uart_getreg(bas, REG_LSR); 1003 while (lsr & LSR_RXRDY) { 1004 if (uart_rx_full(sc)) { 1005 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 1006 break; 1007 } 1008 xc = uart_getreg(bas, REG_DATA); 1009 if (lsr & LSR_FE) 1010 xc |= UART_STAT_FRAMERR; 1011 if (lsr & LSR_PE) 1012 xc |= UART_STAT_PARERR; 1013 uart_rx_put(sc, xc); 1014 lsr = uart_getreg(bas, REG_LSR); 1015 } 1016 /* Discard everything left in the Rx FIFO. */ 1017 while (lsr & LSR_RXRDY) { 1018 (void)uart_getreg(bas, REG_DATA); 1019 uart_barrier(bas); 1020 lsr = uart_getreg(bas, REG_LSR); 1021 } 1022 uart_unlock(sc->sc_hwmtx); 1023 return (0); 1024 } 1025 1026 int 1027 ns8250_bus_setsig(struct uart_softc *sc, int sig) 1028 { 1029 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1030 struct uart_bas *bas; 1031 uint32_t new, old; 1032 1033 bas = &sc->sc_bas; 1034 do { 1035 old = sc->sc_hwsig; 1036 new = old; 1037 if (sig & SER_DDTR) { 1038 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR)); 1039 } 1040 if (sig & SER_DRTS) { 1041 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS)); 1042 } 1043 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 1044 uart_lock(sc->sc_hwmtx); 1045 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 1046 if (new & SER_DTR) 1047 ns8250->mcr |= MCR_DTR; 1048 if (new & SER_RTS) 1049 ns8250->mcr |= MCR_RTS; 1050 uart_setreg(bas, REG_MCR, ns8250->mcr); 1051 uart_barrier(bas); 1052 uart_unlock(sc->sc_hwmtx); 1053 return (0); 1054 } 1055 1056 int 1057 ns8250_bus_transmit(struct uart_softc *sc) 1058 { 1059 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1060 struct uart_bas *bas; 1061 int i; 1062 1063 bas = &sc->sc_bas; 1064 uart_lock(sc->sc_hwmtx); 1065 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 1066 DELAY(4); 1067 for (i = 0; i < sc->sc_txdatasz; i++) { 1068 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 1069 uart_barrier(bas); 1070 } 1071 if (!broken_txfifo) 1072 ns8250->ier |= IER_ETXRDY; 1073 uart_setreg(bas, REG_IER, ns8250->ier); 1074 uart_barrier(bas); 1075 if (broken_txfifo) 1076 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 1077 else 1078 sc->sc_txbusy = 1; 1079 uart_unlock(sc->sc_hwmtx); 1080 if (broken_txfifo) 1081 uart_sched_softih(sc, SER_INT_TXIDLE); 1082 return (0); 1083 } 1084 1085 bool 1086 ns8250_bus_txbusy(struct uart_softc *sc) 1087 { 1088 struct uart_bas *bas = &sc->sc_bas; 1089 1090 if ((uart_getreg(bas, REG_LSR) & (LSR_TEMT | LSR_THRE)) != 1091 (LSR_TEMT | LSR_THRE)) 1092 return (true); 1093 return (false); 1094 } 1095 1096 void 1097 ns8250_bus_grab(struct uart_softc *sc) 1098 { 1099 struct uart_bas *bas = &sc->sc_bas; 1100 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1101 u_char ier; 1102 1103 /* 1104 * turn off all interrupts to enter polling mode. Leave the 1105 * saved mask alone. We'll restore whatever it was in ungrab. 1106 * All pending interrupt signals are reset when IER is set to 0. 1107 */ 1108 uart_lock(sc->sc_hwmtx); 1109 ier = uart_getreg(bas, REG_IER); 1110 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 1111 uart_barrier(bas); 1112 uart_unlock(sc->sc_hwmtx); 1113 } 1114 1115 void 1116 ns8250_bus_ungrab(struct uart_softc *sc) 1117 { 1118 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1119 struct uart_bas *bas = &sc->sc_bas; 1120 1121 /* 1122 * Restore previous interrupt mask 1123 */ 1124 uart_lock(sc->sc_hwmtx); 1125 uart_setreg(bas, REG_IER, ns8250->ier); 1126 uart_barrier(bas); 1127 uart_unlock(sc->sc_hwmtx); 1128 } 1129