1 /*-
2 * Copyright (c) 2018 Diane Bruce
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 /*
27 * Based on uart_dev_pl011.c
28 * Copyright (c) 2012 Semihalf.
29 * All rights reserved.
30 */
31 /*
32 * The mini Uart has the following features:
33 * - 7 or 8 bit operation.
34 * - 1 start and 1 stop bit.
35 * - No parities.
36 * - Break generation.
37 * - 8 symbols deep FIFOs for receive and transmit.
38 * - SW controlled RTS, SW readable CTS.
39 * - Auto flow control with programmable FIFO level.
40 * - 16550 like registers.
41 * - Baudrate derived from system clock.
42 * This is a mini UART and it does NOT have the following capabilities:
43 * - Break detection
44 * - Framing errors detection.
45 * - Parity bit
46 * - Receive Time-out interrupt
47 * - DCD, DSR, DTR or RI signals.
48 * The implemented UART is not a 16650 compatible UART However as far
49 * as possible the first 8 control and status registers are laid out
50 * like a 16550 UART. All 16550 register bits which are not supported can
51 * be written but will be ignored and read back as 0. All control bits
52 * for simple UART receive/transmit operations are available.
53 */
54
55 #include "opt_acpi.h"
56 #include "opt_platform.h"
57
58 #include <sys/cdefs.h>
59 #include <sys/param.h>
60 #include <sys/systm.h>
61 #include <sys/kernel.h>
62 #include <sys/bus.h>
63
64 #include <machine/bus.h>
65 #include <machine/machdep.h>
66 #include <machine/pcpu.h>
67
68 #include <dev/uart/uart.h>
69 #include <dev/uart/uart_cpu.h>
70 #ifdef FDT
71 #include <dev/uart/uart_cpu_fdt.h>
72 #include <dev/ofw/ofw_bus.h>
73 #endif
74 #include <dev/uart/uart_bus.h>
75 #include "uart_if.h"
76
77 /* BCM2835 Micro UART registers and masks*/
78 #define AUX_MU_IO_REG 0x00 /* I/O register */
79
80 /*
81 * According to errata bits 1 and 2 are swapped,
82 * Also bits 2 and 3 are required to enable interrupts.
83 */
84 #define AUX_MU_IER_REG 0x01
85 #define IER_RXENABLE (1)
86 #define IER_TXENABLE (1<<1)
87 #define IER_REQUIRED (3<<2)
88 #define IER_MASK_ALL (IER_TXENABLE|IER_RXENABLE)
89
90 #define AUX_MU_IIR_REG 0x02
91 #define IIR_READY (1)
92 #define IIR_TXREADY (1<<1)
93 #define IIR_RXREADY (1<<2)
94 #define IIR_CLEAR (3<<1)
95
96 #define AUX_MU_LCR_REG 0x03
97 #define LCR_WLEN7 (0)
98 #define LCR_WLEN8 (3)
99
100 #define AUX_MU_MCR_REG 0x04
101 #define AUX_MCR_RTS (1<<1)
102
103 #define AUX_MU_LSR_REG 0x05
104 #define LSR_RXREADY (1)
105 #define LSR_OVRRUN (1<<1)
106 #define LSR_TXEMPTY (1<<5)
107 #define LSR_TXIDLE (1<<6)
108
109 #define AUX_MU_MSR_REG 0x06
110 #define MSR_CTS (1<<5)
111
112 #define AUX_MU_SCRATCH_REG 0x07
113
114 #define AUX_MU_CNTL_REG 0x08
115 #define CNTL_RXENAB (1)
116 #define CNTL_TXENAB (1<<1)
117
118 #define AUX_MU_STAT_REG 0x09
119 #define STAT_TX_SA (1<<1)
120 #define STAT_RX_SA (1)
121
122 #define AUX_MU_BAUD_REG 0x0a
123
124 /*
125 * FIXME: actual register size is SoC-dependent, we need to handle it
126 */
127 #define __uart_getreg(bas, reg) \
128 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
129 #define __uart_setreg(bas, reg, value) \
130 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
131
132 /*
133 * Low-level UART interface.
134 */
135 static int uart_mu_probe(struct uart_bas *bas);
136 static void uart_mu_init(struct uart_bas *bas, int, int, int, int);
137 static void uart_mu_term(struct uart_bas *bas);
138 static void uart_mu_putc(struct uart_bas *bas, int);
139 static int uart_mu_rxready(struct uart_bas *bas);
140 static int uart_mu_getc(struct uart_bas *bas, struct mtx *);
141
142 static struct uart_ops uart_mu_ops = {
143 .probe = uart_mu_probe,
144 .init = uart_mu_init,
145 .term = uart_mu_term,
146 .putc = uart_mu_putc,
147 .rxready = uart_mu_rxready,
148 .getc = uart_mu_getc,
149 };
150
151 static int
uart_mu_probe(struct uart_bas * bas)152 uart_mu_probe(struct uart_bas *bas)
153 {
154
155 return (0);
156 }
157
158 /*
159 * According to the docs, the cpu clock is locked to 250Mhz when
160 * the micro-uart is used
161 */
162 #define CPU_CLOCK 250000000
163
164 static void
uart_mu_param(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)165 uart_mu_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
166 int parity)
167 {
168 uint32_t line;
169 uint32_t baud;
170
171 /*
172 * Zero all settings to make sure
173 * UART is disabled and not configured
174 */
175 line = 0x0;
176 __uart_setreg(bas, AUX_MU_CNTL_REG, line);
177
178 /* As I know UART is disabled I can setup the line */
179 switch (databits) {
180 case 7:
181 line |= LCR_WLEN7;
182 break;
183 case 6:
184 case 8:
185 default:
186 line |= LCR_WLEN8;
187 break;
188 }
189
190 __uart_setreg(bas, AUX_MU_LCR_REG, line);
191
192 /* See 2.2.1 BCM2835-ARM-Peripherals baudrate */
193 if (baudrate != 0) {
194 baud = CPU_CLOCK / (8 * baudrate);
195 /* XXX
196 * baud = cpu_clock() / (8 * baudrate);
197 */
198 __uart_setreg(bas, AUX_MU_BAUD_REG, ((uint32_t)(baud & 0xFFFF)));
199 }
200
201 /* re-enable UART */
202 __uart_setreg(bas, AUX_MU_CNTL_REG, CNTL_RXENAB|CNTL_TXENAB);
203 }
204
205 static void
uart_mu_init(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)206 uart_mu_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
207 int parity)
208 {
209
210 /* Mask all interrupts */
211 __uart_setreg(bas, AUX_MU_IER_REG, 0);
212 uart_mu_param(bas, baudrate, databits, stopbits, parity);
213 }
214
215 static void
uart_mu_term(struct uart_bas * bas)216 uart_mu_term(struct uart_bas *bas)
217 {
218 }
219
220 static void
uart_mu_putc(struct uart_bas * bas,int c)221 uart_mu_putc(struct uart_bas *bas, int c)
222 {
223
224 /* Wait when TX FIFO full. Push character otherwise. */
225 while ((__uart_getreg(bas, AUX_MU_LSR_REG) & LSR_TXEMPTY) == 0)
226 ;
227 __uart_setreg(bas, AUX_MU_IO_REG, c & 0xff);
228 }
229
230 static int
uart_mu_rxready(struct uart_bas * bas)231 uart_mu_rxready(struct uart_bas *bas)
232 {
233
234 return ((__uart_getreg(bas, AUX_MU_LSR_REG) & LSR_RXREADY) != 0);
235 }
236
237 static int
uart_mu_getc(struct uart_bas * bas,struct mtx * hwmtx)238 uart_mu_getc(struct uart_bas *bas, struct mtx *hwmtx)
239 {
240 int c;
241
242 while(!uart_mu_rxready(bas))
243 ;
244 c = __uart_getreg(bas, AUX_MU_IO_REG) & 0xff;
245 return (c);
246 }
247
248 /*
249 * High-level UART interface.
250 */
251 struct uart_mu_softc {
252 struct uart_softc bas;
253 uint16_t aux_ier; /* Interrupt mask */
254 };
255
256 static int uart_mu_bus_attach(struct uart_softc *);
257 static int uart_mu_bus_detach(struct uart_softc *);
258 static int uart_mu_bus_flush(struct uart_softc *, int);
259 static int uart_mu_bus_getsig(struct uart_softc *);
260 static int uart_mu_bus_ioctl(struct uart_softc *, int, intptr_t);
261 static int uart_mu_bus_ipend(struct uart_softc *);
262 static int uart_mu_bus_param(struct uart_softc *, int, int, int, int);
263 static int uart_mu_bus_probe(struct uart_softc *);
264 static int uart_mu_bus_receive(struct uart_softc *);
265 static int uart_mu_bus_setsig(struct uart_softc *, int);
266 static int uart_mu_bus_transmit(struct uart_softc *);
267 static void uart_mu_bus_grab(struct uart_softc *);
268 static void uart_mu_bus_ungrab(struct uart_softc *);
269
270 static kobj_method_t uart_mu_methods[] = {
271 KOBJMETHOD(uart_attach, uart_mu_bus_attach),
272 KOBJMETHOD(uart_detach, uart_mu_bus_detach),
273 KOBJMETHOD(uart_flush, uart_mu_bus_flush),
274 KOBJMETHOD(uart_getsig, uart_mu_bus_getsig),
275 KOBJMETHOD(uart_ioctl, uart_mu_bus_ioctl),
276 KOBJMETHOD(uart_ipend, uart_mu_bus_ipend),
277 KOBJMETHOD(uart_param, uart_mu_bus_param),
278 KOBJMETHOD(uart_probe, uart_mu_bus_probe),
279 KOBJMETHOD(uart_receive, uart_mu_bus_receive),
280 KOBJMETHOD(uart_setsig, uart_mu_bus_setsig),
281 KOBJMETHOD(uart_transmit, uart_mu_bus_transmit),
282 KOBJMETHOD(uart_grab, uart_mu_bus_grab),
283 KOBJMETHOD(uart_ungrab, uart_mu_bus_ungrab),
284 { 0, 0 }
285 };
286
287 static struct uart_class uart_mu_class = {
288 "aux-uart",
289 uart_mu_methods,
290 sizeof(struct uart_mu_softc),
291 .uc_ops = &uart_mu_ops,
292 .uc_range = 0x48,
293 .uc_rclk = 0,
294 .uc_rshift = 2
295 };
296
297 #ifdef FDT
298 static struct ofw_compat_data fdt_compat_data[] = {
299 {"brcm,bcm2835-aux-uart" , (uintptr_t)&uart_mu_class},
300 {NULL, (uintptr_t)NULL},
301 };
302 UART_FDT_CLASS_AND_DEVICE(fdt_compat_data);
303 #endif
304
305 static int
uart_mu_bus_attach(struct uart_softc * sc)306 uart_mu_bus_attach(struct uart_softc *sc)
307 {
308 struct uart_mu_softc *psc;
309 struct uart_bas *bas;
310
311 psc = (struct uart_mu_softc *)sc;
312 bas = &sc->sc_bas;
313 /* Clear interrupts */
314 __uart_setreg(bas, AUX_MU_IIR_REG, IIR_CLEAR);
315 /* Enable interrupts */
316 psc->aux_ier = (IER_RXENABLE|IER_TXENABLE|IER_REQUIRED);
317 __uart_setreg(bas, AUX_MU_IER_REG, psc->aux_ier);
318 sc->sc_txbusy = 0;
319
320 return (0);
321 }
322
323 static int
uart_mu_bus_detach(struct uart_softc * sc)324 uart_mu_bus_detach(struct uart_softc *sc)
325 {
326
327 return (0);
328 }
329
330 static int
uart_mu_bus_flush(struct uart_softc * sc,int what)331 uart_mu_bus_flush(struct uart_softc *sc, int what)
332 {
333
334 return (0);
335 }
336
337 static int
uart_mu_bus_getsig(struct uart_softc * sc)338 uart_mu_bus_getsig(struct uart_softc *sc)
339 {
340
341 return (0);
342 }
343
344 static int
uart_mu_bus_ioctl(struct uart_softc * sc,int request,intptr_t data)345 uart_mu_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
346 {
347 int error;
348
349 error = 0;
350 uart_lock(sc->sc_hwmtx);
351 switch (request) {
352 case UART_IOCTL_BREAK:
353 break;
354 case UART_IOCTL_BAUD:
355 *(int*)data = 115200;
356 break;
357 default:
358 error = EINVAL;
359 break;
360 }
361 uart_unlock(sc->sc_hwmtx);
362
363 return (error);
364 }
365
366 static int
uart_mu_bus_ipend(struct uart_softc * sc)367 uart_mu_bus_ipend(struct uart_softc *sc)
368 {
369 struct uart_mu_softc *psc;
370 struct uart_bas *bas;
371 uint32_t ints;
372 int ipend;
373
374 psc = (struct uart_mu_softc *)sc;
375 bas = &sc->sc_bas;
376
377 uart_lock(sc->sc_hwmtx);
378 ints = __uart_getreg(bas, AUX_MU_IIR_REG);
379 ipend = 0;
380
381 /*
382 * According to docs only one of IIR_RXREADY
383 * or IIR_TXREADY are valid eg. Only one or the other.
384 */
385 if (ints & IIR_RXREADY) {
386 ipend |= SER_INT_RXREADY;
387 } else if (ints & IIR_TXREADY) {
388 if (__uart_getreg(bas, AUX_MU_LSR_REG) & LSR_TXIDLE) {
389 if (sc->sc_txbusy)
390 ipend |= SER_INT_TXIDLE;
391
392 /* Disable TX interrupt */
393 __uart_setreg(bas, AUX_MU_IER_REG,
394 psc->aux_ier & ~IER_TXENABLE);
395 }
396 }
397
398 uart_unlock(sc->sc_hwmtx);
399
400 return (ipend);
401 }
402
403 static int
uart_mu_bus_param(struct uart_softc * sc,int baudrate,int databits,int stopbits,int parity)404 uart_mu_bus_param(struct uart_softc *sc, int baudrate, int databits,
405 int stopbits, int parity)
406 {
407
408 uart_lock(sc->sc_hwmtx);
409 uart_mu_param(&sc->sc_bas, baudrate, databits, stopbits, parity);
410 uart_unlock(sc->sc_hwmtx);
411
412 return (0);
413 }
414
415 static int
uart_mu_bus_probe(struct uart_softc * sc)416 uart_mu_bus_probe(struct uart_softc *sc)
417 {
418
419 /* MU always has 8 byte deep fifo */
420 sc->sc_rxfifosz = 8;
421 sc->sc_txfifosz = 8;
422 device_set_desc(sc->sc_dev, "BCM2835 Mini-UART");
423
424 return (0);
425 }
426
427 static int
uart_mu_bus_receive(struct uart_softc * sc)428 uart_mu_bus_receive(struct uart_softc *sc)
429 {
430 struct uart_bas *bas;
431 uint32_t lsr, xc;
432 int rx;
433
434 bas = &sc->sc_bas;
435 uart_lock(sc->sc_hwmtx);
436
437 lsr = __uart_getreg(bas, AUX_MU_LSR_REG);
438 while (lsr & LSR_RXREADY) {
439 xc = __uart_getreg(bas, AUX_MU_IO_REG);
440 rx = xc & 0xff;
441 if (uart_rx_full(sc)) {
442 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
443 break;
444 }
445 uart_rx_put(sc, rx);
446 lsr = __uart_getreg(bas, AUX_MU_LSR_REG);
447 }
448 uart_unlock(sc->sc_hwmtx);
449
450 return (0);
451 }
452
453 static int
uart_mu_bus_setsig(struct uart_softc * sc,int sig)454 uart_mu_bus_setsig(struct uart_softc *sc, int sig)
455 {
456
457 return (0);
458 }
459
460 static int
uart_mu_bus_transmit(struct uart_softc * sc)461 uart_mu_bus_transmit(struct uart_softc *sc)
462 {
463 struct uart_mu_softc *psc;
464 struct uart_bas *bas;
465 int i;
466
467 psc = (struct uart_mu_softc *)sc;
468 bas = &sc->sc_bas;
469 uart_lock(sc->sc_hwmtx);
470
471 for (i = 0; i < sc->sc_txdatasz; i++) {
472 __uart_setreg(bas, AUX_MU_IO_REG, sc->sc_txbuf[i] & 0xff);
473 uart_barrier(bas);
474 }
475
476 /* Mark busy and enable TX interrupt */
477 sc->sc_txbusy = 1;
478 __uart_setreg(bas, AUX_MU_IER_REG, psc->aux_ier);
479
480 uart_unlock(sc->sc_hwmtx);
481
482 return (0);
483 }
484
485 static void
uart_mu_bus_grab(struct uart_softc * sc)486 uart_mu_bus_grab(struct uart_softc *sc)
487 {
488 struct uart_mu_softc *psc;
489 struct uart_bas *bas;
490
491 psc = (struct uart_mu_softc *)sc;
492 bas = &sc->sc_bas;
493
494 /* Disable interrupts on switch to polling */
495 uart_lock(sc->sc_hwmtx);
496 __uart_setreg(bas, AUX_MU_IER_REG, psc->aux_ier &~IER_MASK_ALL);
497 uart_unlock(sc->sc_hwmtx);
498 }
499
500 static void
uart_mu_bus_ungrab(struct uart_softc * sc)501 uart_mu_bus_ungrab(struct uart_softc *sc)
502 {
503 struct uart_mu_softc *psc;
504 struct uart_bas *bas;
505
506 psc = (struct uart_mu_softc *)sc;
507 bas = &sc->sc_bas;
508
509 /* Switch to using interrupts while not grabbed */
510 uart_lock(sc->sc_hwmtx);
511 __uart_setreg(bas, AUX_MU_CNTL_REG, CNTL_RXENAB|CNTL_TXENAB);
512 __uart_setreg(bas, AUX_MU_IER_REG, psc->aux_ier);
513 uart_unlock(sc->sc_hwmtx);
514 }
515