1098ca2bdSWarner Losh /*-
24d846d26SWarner Losh * SPDX-License-Identifier: BSD-2-Clause
3718cf2ccSPedro F. Giffuni *
427d5dc18SMarcel Moolenaar * Copyright (c) 2003 Marcel Moolenaar
527d5dc18SMarcel Moolenaar * All rights reserved.
627d5dc18SMarcel Moolenaar *
727d5dc18SMarcel Moolenaar * Redistribution and use in source and binary forms, with or without
827d5dc18SMarcel Moolenaar * modification, are permitted provided that the following conditions
927d5dc18SMarcel Moolenaar * are met:
1027d5dc18SMarcel Moolenaar *
1127d5dc18SMarcel Moolenaar * 1. Redistributions of source code must retain the above copyright
1227d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer.
1327d5dc18SMarcel Moolenaar * 2. Redistributions in binary form must reproduce the above copyright
1427d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer in the
1527d5dc18SMarcel Moolenaar * documentation and/or other materials provided with the distribution.
1627d5dc18SMarcel Moolenaar *
1727d5dc18SMarcel Moolenaar * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
1827d5dc18SMarcel Moolenaar * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
1927d5dc18SMarcel Moolenaar * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
2027d5dc18SMarcel Moolenaar * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2127d5dc18SMarcel Moolenaar * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2227d5dc18SMarcel Moolenaar * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
2327d5dc18SMarcel Moolenaar * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
2427d5dc18SMarcel Moolenaar * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2527d5dc18SMarcel Moolenaar * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2627d5dc18SMarcel Moolenaar * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2727d5dc18SMarcel Moolenaar */
2827d5dc18SMarcel Moolenaar
2927d5dc18SMarcel Moolenaar #ifndef _DEV_UART_H_
3027d5dc18SMarcel Moolenaar #define _DEV_UART_H_
3127d5dc18SMarcel Moolenaar
3227d5dc18SMarcel Moolenaar /*
3327d5dc18SMarcel Moolenaar * Bus access structure. This structure holds the minimum information needed
3427d5dc18SMarcel Moolenaar * to access the UART. The rclk field, although not important to actually
3527d5dc18SMarcel Moolenaar * access the UART, is important for baudrate programming, delay loops and
3627d5dc18SMarcel Moolenaar * other timing related computations.
3727d5dc18SMarcel Moolenaar */
3827d5dc18SMarcel Moolenaar struct uart_bas {
3927d5dc18SMarcel Moolenaar bus_space_tag_t bst;
4027d5dc18SMarcel Moolenaar bus_space_handle_t bsh;
41875f70dbSMarcel Moolenaar u_int chan;
4227d5dc18SMarcel Moolenaar u_int rclk;
43875f70dbSMarcel Moolenaar u_int regshft;
44c214a270SRuslan Bukin u_int regiowidth;
45f30f0f2bSMatt Macy u_int busy_detect;
4627d5dc18SMarcel Moolenaar };
4727d5dc18SMarcel Moolenaar
4827d5dc18SMarcel Moolenaar #define uart_regofs(bas, reg) ((reg) << (bas)->regshft)
49c214a270SRuslan Bukin #define uart_regiowidth(bas) ((bas)->regiowidth)
5027d5dc18SMarcel Moolenaar
51c214a270SRuslan Bukin static inline uint32_t
uart_getreg(struct uart_bas * bas,int reg)52c214a270SRuslan Bukin uart_getreg(struct uart_bas *bas, int reg)
53c214a270SRuslan Bukin {
54c214a270SRuslan Bukin uint32_t ret;
55c214a270SRuslan Bukin
56c214a270SRuslan Bukin switch (uart_regiowidth(bas)) {
57*f8c7bbd1SAndrew Turner #if !defined(__i386__)
58*f8c7bbd1SAndrew Turner case 8:
59*f8c7bbd1SAndrew Turner ret = bus_space_read_8(bas->bst, bas->bsh, uart_regofs(bas, reg));
60*f8c7bbd1SAndrew Turner break;
61*f8c7bbd1SAndrew Turner #endif
62c214a270SRuslan Bukin case 4:
63c214a270SRuslan Bukin ret = bus_space_read_4(bas->bst, bas->bsh, uart_regofs(bas, reg));
64c214a270SRuslan Bukin break;
65c214a270SRuslan Bukin case 2:
66c214a270SRuslan Bukin ret = bus_space_read_2(bas->bst, bas->bsh, uart_regofs(bas, reg));
67c214a270SRuslan Bukin break;
68c214a270SRuslan Bukin default:
69c214a270SRuslan Bukin ret = bus_space_read_1(bas->bst, bas->bsh, uart_regofs(bas, reg));
70c214a270SRuslan Bukin break;
71c214a270SRuslan Bukin }
72c214a270SRuslan Bukin
73c214a270SRuslan Bukin return (ret);
74c214a270SRuslan Bukin }
75c214a270SRuslan Bukin
76c214a270SRuslan Bukin static inline void
uart_setreg(struct uart_bas * bas,int reg,uint32_t value)77*f8c7bbd1SAndrew Turner uart_setreg(struct uart_bas *bas, int reg, uint32_t value)
78c214a270SRuslan Bukin {
79c214a270SRuslan Bukin
80c214a270SRuslan Bukin switch (uart_regiowidth(bas)) {
81*f8c7bbd1SAndrew Turner #if !defined(__i386__)
82*f8c7bbd1SAndrew Turner case 8:
83*f8c7bbd1SAndrew Turner bus_space_write_8(bas->bst, bas->bsh, uart_regofs(bas, reg), value);
84*f8c7bbd1SAndrew Turner break;
85*f8c7bbd1SAndrew Turner #endif
86c214a270SRuslan Bukin case 4:
87c214a270SRuslan Bukin bus_space_write_4(bas->bst, bas->bsh, uart_regofs(bas, reg), value);
88c214a270SRuslan Bukin break;
89c214a270SRuslan Bukin case 2:
90c214a270SRuslan Bukin bus_space_write_2(bas->bst, bas->bsh, uart_regofs(bas, reg), value);
91c214a270SRuslan Bukin break;
92c214a270SRuslan Bukin default:
93c214a270SRuslan Bukin bus_space_write_1(bas->bst, bas->bsh, uart_regofs(bas, reg), value);
94c214a270SRuslan Bukin break;
95c214a270SRuslan Bukin }
96c214a270SRuslan Bukin }
9727d5dc18SMarcel Moolenaar
9827d5dc18SMarcel Moolenaar /*
9927d5dc18SMarcel Moolenaar * XXX we don't know the length of the bus space address range in use by
10027d5dc18SMarcel Moolenaar * the UART. Since barriers don't use the length field currently, we put
10127d5dc18SMarcel Moolenaar * a zero there for now.
10227d5dc18SMarcel Moolenaar */
10327d5dc18SMarcel Moolenaar #define uart_barrier(bas) \
10427d5dc18SMarcel Moolenaar bus_space_barrier((bas)->bst, (bas)->bsh, 0, 0, \
10527d5dc18SMarcel Moolenaar BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
10627d5dc18SMarcel Moolenaar
10727d5dc18SMarcel Moolenaar /*
108f8100ce2SMarcel Moolenaar * UART device classes.
109f8100ce2SMarcel Moolenaar */
110f8100ce2SMarcel Moolenaar struct uart_class;
111f8100ce2SMarcel Moolenaar
112f8100ce2SMarcel Moolenaar extern struct uart_class uart_ns8250_class __attribute__((weak));
1136b7ba544SRafal Jaworowski extern struct uart_class uart_quicc_class __attribute__((weak));
114f8100ce2SMarcel Moolenaar extern struct uart_class uart_z8530_class __attribute__((weak));
11564958185SIan Lepore
116f8100ce2SMarcel Moolenaar /*
11727d5dc18SMarcel Moolenaar * Device flags.
11827d5dc18SMarcel Moolenaar */
11927d5dc18SMarcel Moolenaar #define UART_FLAGS_CONSOLE(f) ((f) & 0x10)
12027d5dc18SMarcel Moolenaar #define UART_FLAGS_DBGPORT(f) ((f) & 0x80)
121823c77d7SSam Leffler #define UART_FLAGS_FCR_RX_LOW(f) ((f) & 0x100)
122823c77d7SSam Leffler #define UART_FLAGS_FCR_RX_MEDL(f) ((f) & 0x200)
123823c77d7SSam Leffler #define UART_FLAGS_FCR_RX_MEDH(f) ((f) & 0x400)
124823c77d7SSam Leffler #define UART_FLAGS_FCR_RX_HIGH(f) ((f) & 0x800)
12527d5dc18SMarcel Moolenaar
12627d5dc18SMarcel Moolenaar /*
12727d5dc18SMarcel Moolenaar * Data parity values (magical numbers related to ns8250).
12827d5dc18SMarcel Moolenaar */
12927d5dc18SMarcel Moolenaar #define UART_PARITY_NONE 0
13027d5dc18SMarcel Moolenaar #define UART_PARITY_ODD 1
13127d5dc18SMarcel Moolenaar #define UART_PARITY_EVEN 3
13227d5dc18SMarcel Moolenaar #define UART_PARITY_MARK 5
13327d5dc18SMarcel Moolenaar #define UART_PARITY_SPACE 7
13427d5dc18SMarcel Moolenaar
13527d5dc18SMarcel Moolenaar #endif /* _DEV_UART_H_ */
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