1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (C) 2012-2016 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #include "opt_cam.h" 31 #include "opt_nvme.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/buf.h> 36 #include <sys/bus.h> 37 #include <sys/conf.h> 38 #include <sys/ioccom.h> 39 #include <sys/proc.h> 40 #include <sys/smp.h> 41 #include <sys/uio.h> 42 #include <sys/sbuf.h> 43 #include <sys/endian.h> 44 #include <machine/stdarg.h> 45 #include <vm/vm.h> 46 47 #include "nvme_private.h" 48 49 #define B4_CHK_RDY_DELAY_MS 2300 /* work around controller bug */ 50 51 static void nvme_ctrlr_construct_and_submit_aer(struct nvme_controller *ctrlr, 52 struct nvme_async_event_request *aer); 53 54 static void 55 nvme_ctrlr_barrier(struct nvme_controller *ctrlr, int flags) 56 { 57 bus_barrier(ctrlr->resource, 0, rman_get_size(ctrlr->resource), flags); 58 } 59 60 static void 61 nvme_ctrlr_devctl_log(struct nvme_controller *ctrlr, const char *type, const char *msg, ...) 62 { 63 struct sbuf sb; 64 va_list ap; 65 int error; 66 67 if (sbuf_new(&sb, NULL, 0, SBUF_AUTOEXTEND | SBUF_NOWAIT) == NULL) 68 return; 69 sbuf_printf(&sb, "%s: ", device_get_nameunit(ctrlr->dev)); 70 va_start(ap, msg); 71 sbuf_vprintf(&sb, msg, ap); 72 va_end(ap); 73 error = sbuf_finish(&sb); 74 if (error == 0) 75 printf("%s\n", sbuf_data(&sb)); 76 77 sbuf_clear(&sb); 78 sbuf_printf(&sb, "name=\"%s\" reason=\"", device_get_nameunit(ctrlr->dev)); 79 va_start(ap, msg); 80 sbuf_vprintf(&sb, msg, ap); 81 va_end(ap); 82 sbuf_printf(&sb, "\""); 83 error = sbuf_finish(&sb); 84 if (error == 0) 85 devctl_notify("nvme", "controller", type, sbuf_data(&sb)); 86 sbuf_delete(&sb); 87 } 88 89 static int 90 nvme_ctrlr_construct_admin_qpair(struct nvme_controller *ctrlr) 91 { 92 struct nvme_qpair *qpair; 93 uint32_t num_entries; 94 int error; 95 96 qpair = &ctrlr->adminq; 97 qpair->id = 0; 98 qpair->cpu = CPU_FFS(&cpuset_domain[ctrlr->domain]) - 1; 99 qpair->domain = ctrlr->domain; 100 101 num_entries = NVME_ADMIN_ENTRIES; 102 TUNABLE_INT_FETCH("hw.nvme.admin_entries", &num_entries); 103 /* 104 * If admin_entries was overridden to an invalid value, revert it 105 * back to our default value. 106 */ 107 if (num_entries < NVME_MIN_ADMIN_ENTRIES || 108 num_entries > NVME_MAX_ADMIN_ENTRIES) { 109 nvme_printf(ctrlr, "invalid hw.nvme.admin_entries=%d " 110 "specified\n", num_entries); 111 num_entries = NVME_ADMIN_ENTRIES; 112 } 113 114 /* 115 * The admin queue's max xfer size is treated differently than the 116 * max I/O xfer size. 16KB is sufficient here - maybe even less? 117 */ 118 error = nvme_qpair_construct(qpair, num_entries, NVME_ADMIN_TRACKERS, 119 ctrlr); 120 return (error); 121 } 122 123 #define QP(ctrlr, c) ((c) * (ctrlr)->num_io_queues / mp_ncpus) 124 125 static int 126 nvme_ctrlr_construct_io_qpairs(struct nvme_controller *ctrlr) 127 { 128 struct nvme_qpair *qpair; 129 uint32_t cap_lo; 130 uint16_t mqes; 131 int c, error, i, n; 132 int num_entries, num_trackers, max_entries; 133 134 /* 135 * NVMe spec sets a hard limit of 64K max entries, but devices may 136 * specify a smaller limit, so we need to check the MQES field in the 137 * capabilities register. We have to cap the number of entries to the 138 * current stride allows for in BAR 0/1, otherwise the remainder entries 139 * are inaccessible. MQES should reflect this, and this is just a 140 * fail-safe. 141 */ 142 max_entries = 143 (rman_get_size(ctrlr->resource) - nvme_mmio_offsetof(doorbell[0])) / 144 (1 << (ctrlr->dstrd + 1)); 145 num_entries = NVME_IO_ENTRIES; 146 TUNABLE_INT_FETCH("hw.nvme.io_entries", &num_entries); 147 cap_lo = nvme_mmio_read_4(ctrlr, cap_lo); 148 mqes = NVME_CAP_LO_MQES(cap_lo); 149 num_entries = min(num_entries, mqes + 1); 150 num_entries = min(num_entries, max_entries); 151 152 num_trackers = NVME_IO_TRACKERS; 153 TUNABLE_INT_FETCH("hw.nvme.io_trackers", &num_trackers); 154 155 num_trackers = max(num_trackers, NVME_MIN_IO_TRACKERS); 156 num_trackers = min(num_trackers, NVME_MAX_IO_TRACKERS); 157 /* 158 * No need to have more trackers than entries in the submit queue. Note 159 * also that for a queue size of N, we can only have (N-1) commands 160 * outstanding, hence the "-1" here. 161 */ 162 num_trackers = min(num_trackers, (num_entries-1)); 163 164 /* 165 * Our best estimate for the maximum number of I/Os that we should 166 * normally have in flight at one time. This should be viewed as a hint, 167 * not a hard limit and will need to be revisited when the upper layers 168 * of the storage system grows multi-queue support. 169 */ 170 ctrlr->max_hw_pend_io = num_trackers * ctrlr->num_io_queues * 3 / 4; 171 172 ctrlr->ioq = malloc(ctrlr->num_io_queues * sizeof(struct nvme_qpair), 173 M_NVME, M_ZERO | M_WAITOK); 174 175 for (i = c = n = 0; i < ctrlr->num_io_queues; i++, c += n) { 176 qpair = &ctrlr->ioq[i]; 177 178 /* 179 * Admin queue has ID=0. IO queues start at ID=1 - 180 * hence the 'i+1' here. 181 */ 182 qpair->id = i + 1; 183 if (ctrlr->num_io_queues > 1) { 184 /* Find number of CPUs served by this queue. */ 185 for (n = 1; QP(ctrlr, c + n) == i; n++) 186 ; 187 /* Shuffle multiple NVMe devices between CPUs. */ 188 qpair->cpu = c + (device_get_unit(ctrlr->dev)+n/2) % n; 189 qpair->domain = pcpu_find(qpair->cpu)->pc_domain; 190 } else { 191 qpair->cpu = CPU_FFS(&cpuset_domain[ctrlr->domain]) - 1; 192 qpair->domain = ctrlr->domain; 193 } 194 195 /* 196 * For I/O queues, use the controller-wide max_xfer_size 197 * calculated in nvme_attach(). 198 */ 199 error = nvme_qpair_construct(qpair, num_entries, num_trackers, 200 ctrlr); 201 if (error) 202 return (error); 203 204 /* 205 * Do not bother binding interrupts if we only have one I/O 206 * interrupt thread for this controller. 207 */ 208 if (ctrlr->num_io_queues > 1) 209 bus_bind_intr(ctrlr->dev, qpair->res, qpair->cpu); 210 } 211 212 return (0); 213 } 214 215 static void 216 nvme_ctrlr_fail(struct nvme_controller *ctrlr) 217 { 218 int i; 219 220 /* 221 * No need to disable queues before failing them. Failing is a superet 222 * of disabling (though pedantically we'd abort the AERs silently with 223 * a different error, though when we fail, that hardly matters). 224 */ 225 ctrlr->is_failed = true; 226 nvme_qpair_fail(&ctrlr->adminq); 227 if (ctrlr->ioq != NULL) { 228 for (i = 0; i < ctrlr->num_io_queues; i++) { 229 nvme_qpair_fail(&ctrlr->ioq[i]); 230 } 231 } 232 nvme_notify_fail_consumers(ctrlr); 233 } 234 235 void 236 nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr, 237 struct nvme_request *req) 238 { 239 240 mtx_lock(&ctrlr->lock); 241 STAILQ_INSERT_TAIL(&ctrlr->fail_req, req, stailq); 242 mtx_unlock(&ctrlr->lock); 243 if (!ctrlr->is_dying) 244 taskqueue_enqueue(ctrlr->taskqueue, &ctrlr->fail_req_task); 245 } 246 247 static void 248 nvme_ctrlr_fail_req_task(void *arg, int pending) 249 { 250 struct nvme_controller *ctrlr = arg; 251 struct nvme_request *req; 252 253 mtx_lock(&ctrlr->lock); 254 while ((req = STAILQ_FIRST(&ctrlr->fail_req)) != NULL) { 255 STAILQ_REMOVE_HEAD(&ctrlr->fail_req, stailq); 256 mtx_unlock(&ctrlr->lock); 257 nvme_qpair_manual_complete_request(req->qpair, req, 258 NVME_SCT_GENERIC, NVME_SC_ABORTED_BY_REQUEST); 259 mtx_lock(&ctrlr->lock); 260 } 261 mtx_unlock(&ctrlr->lock); 262 } 263 264 /* 265 * Wait for RDY to change. 266 * 267 * Starts sleeping for 1us and geometrically increases it the longer we wait, 268 * capped at 1ms. 269 */ 270 static int 271 nvme_ctrlr_wait_for_ready(struct nvme_controller *ctrlr, int desired_val) 272 { 273 int timeout = ticks + MSEC_2_TICKS(ctrlr->ready_timeout_in_ms); 274 sbintime_t delta_t = SBT_1US; 275 uint32_t csts; 276 277 while (1) { 278 csts = nvme_mmio_read_4(ctrlr, csts); 279 if (csts == NVME_GONE) /* Hot unplug. */ 280 return (ENXIO); 281 if (NVMEV(NVME_CSTS_REG_RDY, csts) == desired_val) 282 break; 283 if (timeout - ticks < 0) { 284 nvme_printf(ctrlr, "controller ready did not become %d " 285 "within %d ms\n", desired_val, ctrlr->ready_timeout_in_ms); 286 return (ENXIO); 287 } 288 289 pause_sbt("nvmerdy", delta_t, 0, C_PREL(1)); 290 delta_t = min(SBT_1MS, delta_t * 3 / 2); 291 } 292 293 return (0); 294 } 295 296 static int 297 nvme_ctrlr_disable(struct nvme_controller *ctrlr) 298 { 299 uint32_t cc; 300 uint32_t csts; 301 uint8_t en, rdy; 302 int err; 303 304 cc = nvme_mmio_read_4(ctrlr, cc); 305 csts = nvme_mmio_read_4(ctrlr, csts); 306 307 en = NVMEV(NVME_CC_REG_EN, cc); 308 rdy = NVMEV(NVME_CSTS_REG_RDY, csts); 309 310 /* 311 * Per 3.1.5 in NVME 1.3 spec, transitioning CC.EN from 0 to 1 312 * when CSTS.RDY is 1 or transitioning CC.EN from 1 to 0 when 313 * CSTS.RDY is 0 "has undefined results" So make sure that CSTS.RDY 314 * isn't the desired value. Short circuit if we're already disabled. 315 */ 316 if (en == 0) { 317 /* Wait for RDY == 0 or timeout & fail */ 318 if (rdy == 0) 319 return (0); 320 return (nvme_ctrlr_wait_for_ready(ctrlr, 0)); 321 } 322 if (rdy == 0) { 323 /* EN == 1, wait for RDY == 1 or timeout & fail */ 324 err = nvme_ctrlr_wait_for_ready(ctrlr, 1); 325 if (err != 0) 326 return (err); 327 } 328 329 cc &= ~NVMEM(NVME_CC_REG_EN); 330 nvme_mmio_write_4(ctrlr, cc, cc); 331 332 /* 333 * A few drives have firmware bugs that freeze the drive if we access 334 * the mmio too soon after we disable. 335 */ 336 if (ctrlr->quirks & QUIRK_DELAY_B4_CHK_RDY) 337 pause("nvmeR", MSEC_2_TICKS(B4_CHK_RDY_DELAY_MS)); 338 return (nvme_ctrlr_wait_for_ready(ctrlr, 0)); 339 } 340 341 static int 342 nvme_ctrlr_enable(struct nvme_controller *ctrlr) 343 { 344 uint32_t cc; 345 uint32_t csts; 346 uint32_t aqa; 347 uint32_t qsize; 348 uint8_t en, rdy; 349 int err; 350 351 cc = nvme_mmio_read_4(ctrlr, cc); 352 csts = nvme_mmio_read_4(ctrlr, csts); 353 354 en = NVMEV(NVME_CC_REG_EN, cc); 355 rdy = NVMEV(NVME_CSTS_REG_RDY, csts); 356 357 /* 358 * See note in nvme_ctrlr_disable. Short circuit if we're already enabled. 359 */ 360 if (en == 1) { 361 if (rdy == 1) 362 return (0); 363 return (nvme_ctrlr_wait_for_ready(ctrlr, 1)); 364 } 365 366 /* EN == 0 already wait for RDY == 0 or timeout & fail */ 367 err = nvme_ctrlr_wait_for_ready(ctrlr, 0); 368 if (err != 0) 369 return (err); 370 371 nvme_mmio_write_8(ctrlr, asq, ctrlr->adminq.cmd_bus_addr); 372 nvme_mmio_write_8(ctrlr, acq, ctrlr->adminq.cpl_bus_addr); 373 374 /* acqs and asqs are 0-based. */ 375 qsize = ctrlr->adminq.num_entries - 1; 376 377 aqa = 0; 378 aqa |= NVMEF(NVME_AQA_REG_ACQS, qsize); 379 aqa |= NVMEF(NVME_AQA_REG_ASQS, qsize); 380 nvme_mmio_write_4(ctrlr, aqa, aqa); 381 382 /* Initialization values for CC */ 383 cc = 0; 384 cc |= NVMEF(NVME_CC_REG_EN, 1); 385 cc |= NVMEF(NVME_CC_REG_CSS, 0); 386 cc |= NVMEF(NVME_CC_REG_AMS, 0); 387 cc |= NVMEF(NVME_CC_REG_SHN, 0); 388 cc |= NVMEF(NVME_CC_REG_IOSQES, 6); /* SQ entry size == 64 == 2^6 */ 389 cc |= NVMEF(NVME_CC_REG_IOCQES, 4); /* CQ entry size == 16 == 2^4 */ 390 391 /* 392 * Use the Memory Page Size selected during device initialization. Note 393 * that value stored in mps is suitable to use here without adjusting by 394 * NVME_MPS_SHIFT. 395 */ 396 cc |= NVMEF(NVME_CC_REG_MPS, ctrlr->mps); 397 398 nvme_ctrlr_barrier(ctrlr, BUS_SPACE_BARRIER_WRITE); 399 nvme_mmio_write_4(ctrlr, cc, cc); 400 401 return (nvme_ctrlr_wait_for_ready(ctrlr, 1)); 402 } 403 404 static void 405 nvme_ctrlr_disable_qpairs(struct nvme_controller *ctrlr) 406 { 407 int i; 408 409 nvme_admin_qpair_disable(&ctrlr->adminq); 410 /* 411 * I/O queues are not allocated before the initial HW 412 * reset, so do not try to disable them. Use is_initialized 413 * to determine if this is the initial HW reset. 414 */ 415 if (ctrlr->is_initialized) { 416 for (i = 0; i < ctrlr->num_io_queues; i++) 417 nvme_io_qpair_disable(&ctrlr->ioq[i]); 418 } 419 } 420 421 static int 422 nvme_ctrlr_hw_reset(struct nvme_controller *ctrlr) 423 { 424 int err; 425 426 TSENTER(); 427 428 nvme_ctrlr_disable_qpairs(ctrlr); 429 430 err = nvme_ctrlr_disable(ctrlr); 431 if (err != 0) 432 goto out; 433 434 err = nvme_ctrlr_enable(ctrlr); 435 out: 436 437 TSEXIT(); 438 return (err); 439 } 440 441 void 442 nvme_ctrlr_reset(struct nvme_controller *ctrlr) 443 { 444 int cmpset; 445 446 cmpset = atomic_cmpset_32(&ctrlr->is_resetting, 0, 1); 447 448 if (cmpset == 0 || ctrlr->is_failed) 449 /* 450 * Controller is already resetting or has failed. Return 451 * immediately since there is no need to kick off another 452 * reset in these cases. 453 */ 454 return; 455 456 if (!ctrlr->is_dying) 457 taskqueue_enqueue(ctrlr->taskqueue, &ctrlr->reset_task); 458 } 459 460 static int 461 nvme_ctrlr_identify(struct nvme_controller *ctrlr) 462 { 463 struct nvme_completion_poll_status status; 464 465 status.done = 0; 466 nvme_ctrlr_cmd_identify_controller(ctrlr, &ctrlr->cdata, 467 nvme_completion_poll_cb, &status); 468 nvme_completion_poll(&status); 469 if (nvme_completion_is_error(&status.cpl)) { 470 nvme_printf(ctrlr, "nvme_identify_controller failed!\n"); 471 return (ENXIO); 472 } 473 474 /* Convert data to host endian */ 475 nvme_controller_data_swapbytes(&ctrlr->cdata); 476 477 /* 478 * Use MDTS to ensure our default max_xfer_size doesn't exceed what the 479 * controller supports. 480 */ 481 if (ctrlr->cdata.mdts > 0) 482 ctrlr->max_xfer_size = min(ctrlr->max_xfer_size, 483 1 << (ctrlr->cdata.mdts + NVME_MPS_SHIFT + 484 NVME_CAP_HI_MPSMIN(ctrlr->cap_hi))); 485 486 return (0); 487 } 488 489 static int 490 nvme_ctrlr_set_num_qpairs(struct nvme_controller *ctrlr) 491 { 492 struct nvme_completion_poll_status status; 493 int cq_allocated, sq_allocated; 494 495 status.done = 0; 496 nvme_ctrlr_cmd_set_num_queues(ctrlr, ctrlr->num_io_queues, 497 nvme_completion_poll_cb, &status); 498 nvme_completion_poll(&status); 499 if (nvme_completion_is_error(&status.cpl)) { 500 nvme_printf(ctrlr, "nvme_ctrlr_set_num_qpairs failed!\n"); 501 return (ENXIO); 502 } 503 504 /* 505 * Data in cdw0 is 0-based. 506 * Lower 16-bits indicate number of submission queues allocated. 507 * Upper 16-bits indicate number of completion queues allocated. 508 */ 509 sq_allocated = (status.cpl.cdw0 & 0xFFFF) + 1; 510 cq_allocated = (status.cpl.cdw0 >> 16) + 1; 511 512 /* 513 * Controller may allocate more queues than we requested, 514 * so use the minimum of the number requested and what was 515 * actually allocated. 516 */ 517 ctrlr->num_io_queues = min(ctrlr->num_io_queues, sq_allocated); 518 ctrlr->num_io_queues = min(ctrlr->num_io_queues, cq_allocated); 519 if (ctrlr->num_io_queues > vm_ndomains) 520 ctrlr->num_io_queues -= ctrlr->num_io_queues % vm_ndomains; 521 522 return (0); 523 } 524 525 static int 526 nvme_ctrlr_create_qpairs(struct nvme_controller *ctrlr) 527 { 528 struct nvme_completion_poll_status status; 529 struct nvme_qpair *qpair; 530 int i; 531 532 for (i = 0; i < ctrlr->num_io_queues; i++) { 533 qpair = &ctrlr->ioq[i]; 534 535 status.done = 0; 536 nvme_ctrlr_cmd_create_io_cq(ctrlr, qpair, 537 nvme_completion_poll_cb, &status); 538 nvme_completion_poll(&status); 539 if (nvme_completion_is_error(&status.cpl)) { 540 nvme_printf(ctrlr, "nvme_create_io_cq failed!\n"); 541 return (ENXIO); 542 } 543 544 status.done = 0; 545 nvme_ctrlr_cmd_create_io_sq(ctrlr, qpair, 546 nvme_completion_poll_cb, &status); 547 nvme_completion_poll(&status); 548 if (nvme_completion_is_error(&status.cpl)) { 549 nvme_printf(ctrlr, "nvme_create_io_sq failed!\n"); 550 return (ENXIO); 551 } 552 } 553 554 return (0); 555 } 556 557 static int 558 nvme_ctrlr_delete_qpairs(struct nvme_controller *ctrlr) 559 { 560 struct nvme_completion_poll_status status; 561 struct nvme_qpair *qpair; 562 563 for (int i = 0; i < ctrlr->num_io_queues; i++) { 564 qpair = &ctrlr->ioq[i]; 565 566 status.done = 0; 567 nvme_ctrlr_cmd_delete_io_sq(ctrlr, qpair, 568 nvme_completion_poll_cb, &status); 569 nvme_completion_poll(&status); 570 if (nvme_completion_is_error(&status.cpl)) { 571 nvme_printf(ctrlr, "nvme_destroy_io_sq failed!\n"); 572 return (ENXIO); 573 } 574 575 status.done = 0; 576 nvme_ctrlr_cmd_delete_io_cq(ctrlr, qpair, 577 nvme_completion_poll_cb, &status); 578 nvme_completion_poll(&status); 579 if (nvme_completion_is_error(&status.cpl)) { 580 nvme_printf(ctrlr, "nvme_destroy_io_cq failed!\n"); 581 return (ENXIO); 582 } 583 } 584 585 return (0); 586 } 587 588 static int 589 nvme_ctrlr_construct_namespaces(struct nvme_controller *ctrlr) 590 { 591 struct nvme_namespace *ns; 592 uint32_t i; 593 594 for (i = 0; i < min(ctrlr->cdata.nn, NVME_MAX_NAMESPACES); i++) { 595 ns = &ctrlr->ns[i]; 596 nvme_ns_construct(ns, i+1, ctrlr); 597 } 598 599 return (0); 600 } 601 602 static bool 603 is_log_page_id_valid(uint8_t page_id) 604 { 605 606 switch (page_id) { 607 case NVME_LOG_ERROR: 608 case NVME_LOG_HEALTH_INFORMATION: 609 case NVME_LOG_FIRMWARE_SLOT: 610 case NVME_LOG_CHANGED_NAMESPACE: 611 case NVME_LOG_COMMAND_EFFECT: 612 case NVME_LOG_RES_NOTIFICATION: 613 case NVME_LOG_SANITIZE_STATUS: 614 return (true); 615 } 616 617 return (false); 618 } 619 620 static uint32_t 621 nvme_ctrlr_get_log_page_size(struct nvme_controller *ctrlr, uint8_t page_id) 622 { 623 uint32_t log_page_size; 624 625 switch (page_id) { 626 case NVME_LOG_ERROR: 627 log_page_size = min( 628 sizeof(struct nvme_error_information_entry) * 629 (ctrlr->cdata.elpe + 1), NVME_MAX_AER_LOG_SIZE); 630 break; 631 case NVME_LOG_HEALTH_INFORMATION: 632 log_page_size = sizeof(struct nvme_health_information_page); 633 break; 634 case NVME_LOG_FIRMWARE_SLOT: 635 log_page_size = sizeof(struct nvme_firmware_page); 636 break; 637 case NVME_LOG_CHANGED_NAMESPACE: 638 log_page_size = sizeof(struct nvme_ns_list); 639 break; 640 case NVME_LOG_COMMAND_EFFECT: 641 log_page_size = sizeof(struct nvme_command_effects_page); 642 break; 643 case NVME_LOG_RES_NOTIFICATION: 644 log_page_size = sizeof(struct nvme_res_notification_page); 645 break; 646 case NVME_LOG_SANITIZE_STATUS: 647 log_page_size = sizeof(struct nvme_sanitize_status_page); 648 break; 649 default: 650 log_page_size = 0; 651 break; 652 } 653 654 return (log_page_size); 655 } 656 657 static void 658 nvme_ctrlr_log_critical_warnings(struct nvme_controller *ctrlr, 659 uint8_t state) 660 { 661 662 if (state & NVME_CRIT_WARN_ST_AVAILABLE_SPARE) 663 nvme_ctrlr_devctl_log(ctrlr, "critical", 664 "available spare space below threshold"); 665 666 if (state & NVME_CRIT_WARN_ST_TEMPERATURE) 667 nvme_ctrlr_devctl_log(ctrlr, "critical", 668 "temperature above threshold"); 669 670 if (state & NVME_CRIT_WARN_ST_DEVICE_RELIABILITY) 671 nvme_ctrlr_devctl_log(ctrlr, "critical", 672 "device reliability degraded"); 673 674 if (state & NVME_CRIT_WARN_ST_READ_ONLY) 675 nvme_ctrlr_devctl_log(ctrlr, "critical", 676 "media placed in read only mode"); 677 678 if (state & NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP) 679 nvme_ctrlr_devctl_log(ctrlr, "critical", 680 "volatile memory backup device failed"); 681 682 if (state & NVME_CRIT_WARN_ST_RESERVED_MASK) 683 nvme_ctrlr_devctl_log(ctrlr, "critical", 684 "unknown critical warning(s): state = 0x%02x", state); 685 } 686 687 static void 688 nvme_ctrlr_async_event_log_page_cb(void *arg, const struct nvme_completion *cpl) 689 { 690 struct nvme_async_event_request *aer = arg; 691 struct nvme_health_information_page *health_info; 692 struct nvme_ns_list *nsl; 693 struct nvme_error_information_entry *err; 694 int i; 695 696 /* 697 * If the log page fetch for some reason completed with an error, 698 * don't pass log page data to the consumers. In practice, this case 699 * should never happen. 700 */ 701 if (nvme_completion_is_error(cpl)) 702 nvme_notify_async_consumers(aer->ctrlr, &aer->cpl, 703 aer->log_page_id, NULL, 0); 704 else { 705 /* Convert data to host endian */ 706 switch (aer->log_page_id) { 707 case NVME_LOG_ERROR: 708 err = (struct nvme_error_information_entry *)aer->log_page_buffer; 709 for (i = 0; i < (aer->ctrlr->cdata.elpe + 1); i++) 710 nvme_error_information_entry_swapbytes(err++); 711 break; 712 case NVME_LOG_HEALTH_INFORMATION: 713 nvme_health_information_page_swapbytes( 714 (struct nvme_health_information_page *)aer->log_page_buffer); 715 break; 716 case NVME_LOG_CHANGED_NAMESPACE: 717 nvme_ns_list_swapbytes( 718 (struct nvme_ns_list *)aer->log_page_buffer); 719 break; 720 case NVME_LOG_COMMAND_EFFECT: 721 nvme_command_effects_page_swapbytes( 722 (struct nvme_command_effects_page *)aer->log_page_buffer); 723 break; 724 case NVME_LOG_RES_NOTIFICATION: 725 nvme_res_notification_page_swapbytes( 726 (struct nvme_res_notification_page *)aer->log_page_buffer); 727 break; 728 case NVME_LOG_SANITIZE_STATUS: 729 nvme_sanitize_status_page_swapbytes( 730 (struct nvme_sanitize_status_page *)aer->log_page_buffer); 731 break; 732 default: 733 break; 734 } 735 736 if (aer->log_page_id == NVME_LOG_HEALTH_INFORMATION) { 737 health_info = (struct nvme_health_information_page *) 738 aer->log_page_buffer; 739 nvme_ctrlr_log_critical_warnings(aer->ctrlr, 740 health_info->critical_warning); 741 /* 742 * Critical warnings reported through the 743 * SMART/health log page are persistent, so 744 * clear the associated bits in the async event 745 * config so that we do not receive repeated 746 * notifications for the same event. 747 */ 748 aer->ctrlr->async_event_config &= 749 ~health_info->critical_warning; 750 nvme_ctrlr_cmd_set_async_event_config(aer->ctrlr, 751 aer->ctrlr->async_event_config, NULL, NULL); 752 } else if (aer->log_page_id == NVME_LOG_CHANGED_NAMESPACE && 753 !nvme_use_nvd) { 754 nsl = (struct nvme_ns_list *)aer->log_page_buffer; 755 for (i = 0; i < nitems(nsl->ns) && nsl->ns[i] != 0; i++) { 756 if (nsl->ns[i] > NVME_MAX_NAMESPACES) 757 break; 758 nvme_notify_ns(aer->ctrlr, nsl->ns[i]); 759 } 760 } 761 762 /* 763 * Pass the cpl data from the original async event completion, 764 * not the log page fetch. 765 */ 766 nvme_notify_async_consumers(aer->ctrlr, &aer->cpl, 767 aer->log_page_id, aer->log_page_buffer, aer->log_page_size); 768 } 769 770 /* 771 * Repost another asynchronous event request to replace the one 772 * that just completed. 773 */ 774 nvme_ctrlr_construct_and_submit_aer(aer->ctrlr, aer); 775 } 776 777 static void 778 nvme_ctrlr_async_event_cb(void *arg, const struct nvme_completion *cpl) 779 { 780 struct nvme_async_event_request *aer = arg; 781 782 if (nvme_completion_is_error(cpl)) { 783 /* 784 * Do not retry failed async event requests. This avoids 785 * infinite loops where a new async event request is submitted 786 * to replace the one just failed, only to fail again and 787 * perpetuate the loop. 788 */ 789 return; 790 } 791 792 /* Associated log page is in bits 23:16 of completion entry dw0. */ 793 aer->log_page_id = NVMEV(NVME_ASYNC_EVENT_LOG_PAGE_ID, cpl->cdw0); 794 795 nvme_printf(aer->ctrlr, "async event occurred (type 0x%x, info 0x%02x," 796 " page 0x%02x)\n", NVMEV(NVME_ASYNC_EVENT_TYPE, cpl->cdw0), 797 NVMEV(NVME_ASYNC_EVENT_INFO, cpl->cdw0), 798 aer->log_page_id); 799 800 if (is_log_page_id_valid(aer->log_page_id)) { 801 aer->log_page_size = nvme_ctrlr_get_log_page_size(aer->ctrlr, 802 aer->log_page_id); 803 memcpy(&aer->cpl, cpl, sizeof(*cpl)); 804 nvme_ctrlr_cmd_get_log_page(aer->ctrlr, aer->log_page_id, 805 NVME_GLOBAL_NAMESPACE_TAG, aer->log_page_buffer, 806 aer->log_page_size, nvme_ctrlr_async_event_log_page_cb, 807 aer); 808 /* Wait to notify consumers until after log page is fetched. */ 809 } else { 810 nvme_notify_async_consumers(aer->ctrlr, cpl, aer->log_page_id, 811 NULL, 0); 812 813 /* 814 * Repost another asynchronous event request to replace the one 815 * that just completed. 816 */ 817 nvme_ctrlr_construct_and_submit_aer(aer->ctrlr, aer); 818 } 819 } 820 821 static void 822 nvme_ctrlr_construct_and_submit_aer(struct nvme_controller *ctrlr, 823 struct nvme_async_event_request *aer) 824 { 825 struct nvme_request *req; 826 827 aer->ctrlr = ctrlr; 828 req = nvme_allocate_request_null(nvme_ctrlr_async_event_cb, aer); 829 aer->req = req; 830 831 /* 832 * Disable timeout here, since asynchronous event requests should by 833 * nature never be timed out. 834 */ 835 req->timeout = false; 836 req->cmd.opc = NVME_OPC_ASYNC_EVENT_REQUEST; 837 nvme_ctrlr_submit_admin_request(ctrlr, req); 838 } 839 840 static void 841 nvme_ctrlr_configure_aer(struct nvme_controller *ctrlr) 842 { 843 struct nvme_completion_poll_status status; 844 struct nvme_async_event_request *aer; 845 uint32_t i; 846 847 ctrlr->async_event_config = NVME_CRIT_WARN_ST_AVAILABLE_SPARE | 848 NVME_CRIT_WARN_ST_DEVICE_RELIABILITY | 849 NVME_CRIT_WARN_ST_READ_ONLY | 850 NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP; 851 if (ctrlr->cdata.ver >= NVME_REV(1, 2)) 852 ctrlr->async_event_config |= NVME_ASYNC_EVENT_NS_ATTRIBUTE | 853 NVME_ASYNC_EVENT_FW_ACTIVATE; 854 855 status.done = 0; 856 nvme_ctrlr_cmd_get_feature(ctrlr, NVME_FEAT_TEMPERATURE_THRESHOLD, 857 0, NULL, 0, nvme_completion_poll_cb, &status); 858 nvme_completion_poll(&status); 859 if (nvme_completion_is_error(&status.cpl) || 860 (status.cpl.cdw0 & 0xFFFF) == 0xFFFF || 861 (status.cpl.cdw0 & 0xFFFF) == 0x0000) { 862 nvme_printf(ctrlr, "temperature threshold not supported\n"); 863 } else 864 ctrlr->async_event_config |= NVME_CRIT_WARN_ST_TEMPERATURE; 865 866 nvme_ctrlr_cmd_set_async_event_config(ctrlr, 867 ctrlr->async_event_config, NULL, NULL); 868 869 /* aerl is a zero-based value, so we need to add 1 here. */ 870 ctrlr->num_aers = min(NVME_MAX_ASYNC_EVENTS, (ctrlr->cdata.aerl+1)); 871 872 for (i = 0; i < ctrlr->num_aers; i++) { 873 aer = &ctrlr->aer[i]; 874 nvme_ctrlr_construct_and_submit_aer(ctrlr, aer); 875 } 876 } 877 878 static void 879 nvme_ctrlr_configure_int_coalescing(struct nvme_controller *ctrlr) 880 { 881 882 ctrlr->int_coal_time = 0; 883 TUNABLE_INT_FETCH("hw.nvme.int_coal_time", 884 &ctrlr->int_coal_time); 885 886 ctrlr->int_coal_threshold = 0; 887 TUNABLE_INT_FETCH("hw.nvme.int_coal_threshold", 888 &ctrlr->int_coal_threshold); 889 890 nvme_ctrlr_cmd_set_interrupt_coalescing(ctrlr, ctrlr->int_coal_time, 891 ctrlr->int_coal_threshold, NULL, NULL); 892 } 893 894 static void 895 nvme_ctrlr_hmb_free(struct nvme_controller *ctrlr) 896 { 897 struct nvme_hmb_chunk *hmbc; 898 int i; 899 900 if (ctrlr->hmb_desc_paddr) { 901 bus_dmamap_unload(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_map); 902 bus_dmamem_free(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_vaddr, 903 ctrlr->hmb_desc_map); 904 ctrlr->hmb_desc_paddr = 0; 905 } 906 if (ctrlr->hmb_desc_tag) { 907 bus_dma_tag_destroy(ctrlr->hmb_desc_tag); 908 ctrlr->hmb_desc_tag = NULL; 909 } 910 for (i = 0; i < ctrlr->hmb_nchunks; i++) { 911 hmbc = &ctrlr->hmb_chunks[i]; 912 bus_dmamap_unload(ctrlr->hmb_tag, hmbc->hmbc_map); 913 bus_dmamem_free(ctrlr->hmb_tag, hmbc->hmbc_vaddr, 914 hmbc->hmbc_map); 915 } 916 ctrlr->hmb_nchunks = 0; 917 if (ctrlr->hmb_tag) { 918 bus_dma_tag_destroy(ctrlr->hmb_tag); 919 ctrlr->hmb_tag = NULL; 920 } 921 if (ctrlr->hmb_chunks) { 922 free(ctrlr->hmb_chunks, M_NVME); 923 ctrlr->hmb_chunks = NULL; 924 } 925 } 926 927 static void 928 nvme_ctrlr_hmb_alloc(struct nvme_controller *ctrlr) 929 { 930 struct nvme_hmb_chunk *hmbc; 931 size_t pref, min, minc, size; 932 int err, i; 933 uint64_t max; 934 935 /* Limit HMB to 5% of RAM size per device by default. */ 936 max = (uint64_t)physmem * PAGE_SIZE / 20; 937 TUNABLE_UINT64_FETCH("hw.nvme.hmb_max", &max); 938 939 /* 940 * Units of Host Memory Buffer in the Identify info are always in terms 941 * of 4k units. 942 */ 943 min = (long long unsigned)ctrlr->cdata.hmmin * NVME_HMB_UNITS; 944 if (max == 0 || max < min) 945 return; 946 pref = MIN((long long unsigned)ctrlr->cdata.hmpre * NVME_HMB_UNITS, max); 947 minc = MAX(ctrlr->cdata.hmminds * NVME_HMB_UNITS, ctrlr->page_size); 948 if (min > 0 && ctrlr->cdata.hmmaxd > 0) 949 minc = MAX(minc, min / ctrlr->cdata.hmmaxd); 950 ctrlr->hmb_chunk = pref; 951 952 again: 953 /* 954 * However, the chunk sizes, number of chunks, and alignment of chunks 955 * are all based on the current MPS (ctrlr->page_size). 956 */ 957 ctrlr->hmb_chunk = roundup2(ctrlr->hmb_chunk, ctrlr->page_size); 958 ctrlr->hmb_nchunks = howmany(pref, ctrlr->hmb_chunk); 959 if (ctrlr->cdata.hmmaxd > 0 && ctrlr->hmb_nchunks > ctrlr->cdata.hmmaxd) 960 ctrlr->hmb_nchunks = ctrlr->cdata.hmmaxd; 961 ctrlr->hmb_chunks = malloc(sizeof(struct nvme_hmb_chunk) * 962 ctrlr->hmb_nchunks, M_NVME, M_WAITOK); 963 err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev), 964 ctrlr->page_size, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 965 ctrlr->hmb_chunk, 1, ctrlr->hmb_chunk, 0, NULL, NULL, &ctrlr->hmb_tag); 966 if (err != 0) { 967 nvme_printf(ctrlr, "HMB tag create failed %d\n", err); 968 nvme_ctrlr_hmb_free(ctrlr); 969 return; 970 } 971 972 for (i = 0; i < ctrlr->hmb_nchunks; i++) { 973 hmbc = &ctrlr->hmb_chunks[i]; 974 if (bus_dmamem_alloc(ctrlr->hmb_tag, 975 (void **)&hmbc->hmbc_vaddr, BUS_DMA_NOWAIT, 976 &hmbc->hmbc_map)) { 977 nvme_printf(ctrlr, "failed to alloc HMB\n"); 978 break; 979 } 980 if (bus_dmamap_load(ctrlr->hmb_tag, hmbc->hmbc_map, 981 hmbc->hmbc_vaddr, ctrlr->hmb_chunk, nvme_single_map, 982 &hmbc->hmbc_paddr, BUS_DMA_NOWAIT) != 0) { 983 bus_dmamem_free(ctrlr->hmb_tag, hmbc->hmbc_vaddr, 984 hmbc->hmbc_map); 985 nvme_printf(ctrlr, "failed to load HMB\n"); 986 break; 987 } 988 bus_dmamap_sync(ctrlr->hmb_tag, hmbc->hmbc_map, 989 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 990 } 991 992 if (i < ctrlr->hmb_nchunks && i * ctrlr->hmb_chunk < min && 993 ctrlr->hmb_chunk / 2 >= minc) { 994 ctrlr->hmb_nchunks = i; 995 nvme_ctrlr_hmb_free(ctrlr); 996 ctrlr->hmb_chunk /= 2; 997 goto again; 998 } 999 ctrlr->hmb_nchunks = i; 1000 if (ctrlr->hmb_nchunks * ctrlr->hmb_chunk < min) { 1001 nvme_ctrlr_hmb_free(ctrlr); 1002 return; 1003 } 1004 1005 size = sizeof(struct nvme_hmb_desc) * ctrlr->hmb_nchunks; 1006 err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev), 1007 16, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1008 size, 1, size, 0, NULL, NULL, &ctrlr->hmb_desc_tag); 1009 if (err != 0) { 1010 nvme_printf(ctrlr, "HMB desc tag create failed %d\n", err); 1011 nvme_ctrlr_hmb_free(ctrlr); 1012 return; 1013 } 1014 if (bus_dmamem_alloc(ctrlr->hmb_desc_tag, 1015 (void **)&ctrlr->hmb_desc_vaddr, BUS_DMA_WAITOK, 1016 &ctrlr->hmb_desc_map)) { 1017 nvme_printf(ctrlr, "failed to alloc HMB desc\n"); 1018 nvme_ctrlr_hmb_free(ctrlr); 1019 return; 1020 } 1021 if (bus_dmamap_load(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_map, 1022 ctrlr->hmb_desc_vaddr, size, nvme_single_map, 1023 &ctrlr->hmb_desc_paddr, BUS_DMA_NOWAIT) != 0) { 1024 bus_dmamem_free(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_vaddr, 1025 ctrlr->hmb_desc_map); 1026 nvme_printf(ctrlr, "failed to load HMB desc\n"); 1027 nvme_ctrlr_hmb_free(ctrlr); 1028 return; 1029 } 1030 1031 for (i = 0; i < ctrlr->hmb_nchunks; i++) { 1032 memset(&ctrlr->hmb_desc_vaddr[i], 0, 1033 sizeof(struct nvme_hmb_desc)); 1034 ctrlr->hmb_desc_vaddr[i].addr = 1035 htole64(ctrlr->hmb_chunks[i].hmbc_paddr); 1036 ctrlr->hmb_desc_vaddr[i].size = htole32(ctrlr->hmb_chunk / ctrlr->page_size); 1037 } 1038 bus_dmamap_sync(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_map, 1039 BUS_DMASYNC_PREWRITE); 1040 1041 nvme_printf(ctrlr, "Allocated %lluMB host memory buffer\n", 1042 (long long unsigned)ctrlr->hmb_nchunks * ctrlr->hmb_chunk 1043 / 1024 / 1024); 1044 } 1045 1046 static void 1047 nvme_ctrlr_hmb_enable(struct nvme_controller *ctrlr, bool enable, bool memret) 1048 { 1049 struct nvme_completion_poll_status status; 1050 uint32_t cdw11; 1051 1052 cdw11 = 0; 1053 if (enable) 1054 cdw11 |= 1; 1055 if (memret) 1056 cdw11 |= 2; 1057 status.done = 0; 1058 nvme_ctrlr_cmd_set_feature(ctrlr, NVME_FEAT_HOST_MEMORY_BUFFER, cdw11, 1059 ctrlr->hmb_nchunks * ctrlr->hmb_chunk / ctrlr->page_size, 1060 ctrlr->hmb_desc_paddr, ctrlr->hmb_desc_paddr >> 32, 1061 ctrlr->hmb_nchunks, NULL, 0, 1062 nvme_completion_poll_cb, &status); 1063 nvme_completion_poll(&status); 1064 if (nvme_completion_is_error(&status.cpl)) 1065 nvme_printf(ctrlr, "nvme_ctrlr_hmb_enable failed!\n"); 1066 } 1067 1068 static void 1069 nvme_ctrlr_start(void *ctrlr_arg, bool resetting) 1070 { 1071 struct nvme_controller *ctrlr = ctrlr_arg; 1072 uint32_t old_num_io_queues; 1073 int i; 1074 1075 TSENTER(); 1076 1077 /* 1078 * Only reset adminq here when we are restarting the 1079 * controller after a reset. During initialization, 1080 * we have already submitted admin commands to get 1081 * the number of I/O queues supported, so cannot reset 1082 * the adminq again here. 1083 */ 1084 if (resetting) { 1085 nvme_qpair_reset(&ctrlr->adminq); 1086 nvme_admin_qpair_enable(&ctrlr->adminq); 1087 } 1088 1089 if (ctrlr->ioq != NULL) { 1090 for (i = 0; i < ctrlr->num_io_queues; i++) 1091 nvme_qpair_reset(&ctrlr->ioq[i]); 1092 } 1093 1094 /* 1095 * If it was a reset on initialization command timeout, just 1096 * return here, letting initialization code fail gracefully. 1097 */ 1098 if (resetting && !ctrlr->is_initialized) 1099 return; 1100 1101 if (resetting && nvme_ctrlr_identify(ctrlr) != 0) { 1102 nvme_ctrlr_fail(ctrlr); 1103 return; 1104 } 1105 1106 /* 1107 * The number of qpairs are determined during controller initialization, 1108 * including using NVMe SET_FEATURES/NUMBER_OF_QUEUES to determine the 1109 * HW limit. We call SET_FEATURES again here so that it gets called 1110 * after any reset for controllers that depend on the driver to 1111 * explicit specify how many queues it will use. This value should 1112 * never change between resets, so panic if somehow that does happen. 1113 */ 1114 if (resetting) { 1115 old_num_io_queues = ctrlr->num_io_queues; 1116 if (nvme_ctrlr_set_num_qpairs(ctrlr) != 0) { 1117 nvme_ctrlr_fail(ctrlr); 1118 return; 1119 } 1120 1121 if (old_num_io_queues != ctrlr->num_io_queues) { 1122 panic("num_io_queues changed from %u to %u", 1123 old_num_io_queues, ctrlr->num_io_queues); 1124 } 1125 } 1126 1127 if (ctrlr->cdata.hmpre > 0 && ctrlr->hmb_nchunks == 0) { 1128 nvme_ctrlr_hmb_alloc(ctrlr); 1129 if (ctrlr->hmb_nchunks > 0) 1130 nvme_ctrlr_hmb_enable(ctrlr, true, false); 1131 } else if (ctrlr->hmb_nchunks > 0) 1132 nvme_ctrlr_hmb_enable(ctrlr, true, true); 1133 1134 if (nvme_ctrlr_create_qpairs(ctrlr) != 0) { 1135 nvme_ctrlr_fail(ctrlr); 1136 return; 1137 } 1138 1139 if (nvme_ctrlr_construct_namespaces(ctrlr) != 0) { 1140 nvme_ctrlr_fail(ctrlr); 1141 return; 1142 } 1143 1144 nvme_ctrlr_configure_aer(ctrlr); 1145 nvme_ctrlr_configure_int_coalescing(ctrlr); 1146 1147 for (i = 0; i < ctrlr->num_io_queues; i++) 1148 nvme_io_qpair_enable(&ctrlr->ioq[i]); 1149 TSEXIT(); 1150 } 1151 1152 void 1153 nvme_ctrlr_start_config_hook(void *arg) 1154 { 1155 struct nvme_controller *ctrlr = arg; 1156 1157 TSENTER(); 1158 1159 /* 1160 * Don't call pre/post reset here. We've not yet created the qpairs, 1161 * haven't setup the ISRs, so there's no need to 'drain' them or 1162 * 'exclude' them. 1163 */ 1164 if (nvme_ctrlr_hw_reset(ctrlr) != 0) { 1165 fail: 1166 nvme_ctrlr_fail(ctrlr); 1167 config_intrhook_disestablish(&ctrlr->config_hook); 1168 return; 1169 } 1170 1171 #ifdef NVME_2X_RESET 1172 /* 1173 * Reset controller twice to ensure we do a transition from cc.en==1 to 1174 * cc.en==0. This is because we don't really know what status the 1175 * controller was left in when boot handed off to OS. Linux doesn't do 1176 * this, however, and when the controller is in state cc.en == 0, no 1177 * I/O can happen. 1178 */ 1179 if (nvme_ctrlr_hw_reset(ctrlr) != 0) 1180 goto fail; 1181 #endif 1182 1183 nvme_qpair_reset(&ctrlr->adminq); 1184 nvme_admin_qpair_enable(&ctrlr->adminq); 1185 1186 if (nvme_ctrlr_identify(ctrlr) == 0 && 1187 nvme_ctrlr_set_num_qpairs(ctrlr) == 0 && 1188 nvme_ctrlr_construct_io_qpairs(ctrlr) == 0) 1189 nvme_ctrlr_start(ctrlr, false); 1190 else 1191 goto fail; 1192 1193 nvme_sysctl_initialize_ctrlr(ctrlr); 1194 config_intrhook_disestablish(&ctrlr->config_hook); 1195 1196 ctrlr->is_initialized = 1; 1197 nvme_notify_new_controller(ctrlr); 1198 TSEXIT(); 1199 } 1200 1201 static void 1202 nvme_ctrlr_reset_task(void *arg, int pending) 1203 { 1204 struct nvme_controller *ctrlr = arg; 1205 int status; 1206 1207 nvme_ctrlr_devctl_log(ctrlr, "RESET", "resetting controller"); 1208 status = nvme_ctrlr_hw_reset(ctrlr); 1209 if (status == 0) 1210 nvme_ctrlr_start(ctrlr, true); 1211 else 1212 nvme_ctrlr_fail(ctrlr); 1213 1214 atomic_cmpset_32(&ctrlr->is_resetting, 1, 0); 1215 } 1216 1217 /* 1218 * Poll all the queues enabled on the device for completion. 1219 */ 1220 void 1221 nvme_ctrlr_poll(struct nvme_controller *ctrlr) 1222 { 1223 int i; 1224 1225 nvme_qpair_process_completions(&ctrlr->adminq); 1226 1227 for (i = 0; i < ctrlr->num_io_queues; i++) 1228 if (ctrlr->ioq && ctrlr->ioq[i].cpl) 1229 nvme_qpair_process_completions(&ctrlr->ioq[i]); 1230 } 1231 1232 /* 1233 * Poll the single-vector interrupt case: num_io_queues will be 1 and 1234 * there's only a single vector. While we're polling, we mask further 1235 * interrupts in the controller. 1236 */ 1237 void 1238 nvme_ctrlr_shared_handler(void *arg) 1239 { 1240 struct nvme_controller *ctrlr = arg; 1241 1242 nvme_mmio_write_4(ctrlr, intms, 1); 1243 nvme_ctrlr_poll(ctrlr); 1244 nvme_mmio_write_4(ctrlr, intmc, 1); 1245 } 1246 1247 static void 1248 nvme_pt_done(void *arg, const struct nvme_completion *cpl) 1249 { 1250 struct nvme_pt_command *pt = arg; 1251 struct mtx *mtx = pt->driver_lock; 1252 uint16_t status; 1253 1254 bzero(&pt->cpl, sizeof(pt->cpl)); 1255 pt->cpl.cdw0 = cpl->cdw0; 1256 1257 status = cpl->status; 1258 status &= ~NVMEM(NVME_STATUS_P); 1259 pt->cpl.status = status; 1260 1261 mtx_lock(mtx); 1262 pt->driver_lock = NULL; 1263 wakeup(pt); 1264 mtx_unlock(mtx); 1265 } 1266 1267 int 1268 nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr, 1269 struct nvme_pt_command *pt, uint32_t nsid, int is_user_buffer, 1270 int is_admin_cmd) 1271 { 1272 struct nvme_request *req; 1273 struct mtx *mtx; 1274 struct buf *buf = NULL; 1275 int ret = 0; 1276 1277 if (pt->len > 0) { 1278 if (pt->len > ctrlr->max_xfer_size) { 1279 nvme_printf(ctrlr, "pt->len (%d) " 1280 "exceeds max_xfer_size (%d)\n", pt->len, 1281 ctrlr->max_xfer_size); 1282 return EIO; 1283 } 1284 if (is_user_buffer) { 1285 /* 1286 * Ensure the user buffer is wired for the duration of 1287 * this pass-through command. 1288 */ 1289 PHOLD(curproc); 1290 buf = uma_zalloc(pbuf_zone, M_WAITOK); 1291 buf->b_iocmd = pt->is_read ? BIO_READ : BIO_WRITE; 1292 if (vmapbuf(buf, pt->buf, pt->len, 1) < 0) { 1293 ret = EFAULT; 1294 goto err; 1295 } 1296 req = nvme_allocate_request_vaddr(buf->b_data, pt->len, 1297 nvme_pt_done, pt); 1298 } else 1299 req = nvme_allocate_request_vaddr(pt->buf, pt->len, 1300 nvme_pt_done, pt); 1301 } else 1302 req = nvme_allocate_request_null(nvme_pt_done, pt); 1303 1304 /* Assume user space already converted to little-endian */ 1305 req->cmd.opc = pt->cmd.opc; 1306 req->cmd.fuse = pt->cmd.fuse; 1307 req->cmd.rsvd2 = pt->cmd.rsvd2; 1308 req->cmd.rsvd3 = pt->cmd.rsvd3; 1309 req->cmd.cdw10 = pt->cmd.cdw10; 1310 req->cmd.cdw11 = pt->cmd.cdw11; 1311 req->cmd.cdw12 = pt->cmd.cdw12; 1312 req->cmd.cdw13 = pt->cmd.cdw13; 1313 req->cmd.cdw14 = pt->cmd.cdw14; 1314 req->cmd.cdw15 = pt->cmd.cdw15; 1315 1316 req->cmd.nsid = htole32(nsid); 1317 1318 mtx = mtx_pool_find(mtxpool_sleep, pt); 1319 pt->driver_lock = mtx; 1320 1321 if (is_admin_cmd) 1322 nvme_ctrlr_submit_admin_request(ctrlr, req); 1323 else 1324 nvme_ctrlr_submit_io_request(ctrlr, req); 1325 1326 mtx_lock(mtx); 1327 while (pt->driver_lock != NULL) 1328 mtx_sleep(pt, mtx, PRIBIO, "nvme_pt", 0); 1329 mtx_unlock(mtx); 1330 1331 if (buf != NULL) { 1332 vunmapbuf(buf); 1333 err: 1334 uma_zfree(pbuf_zone, buf); 1335 PRELE(curproc); 1336 } 1337 1338 return (ret); 1339 } 1340 1341 static int 1342 nvme_ctrlr_ioctl(struct cdev *cdev, u_long cmd, caddr_t arg, int flag, 1343 struct thread *td) 1344 { 1345 struct nvme_controller *ctrlr; 1346 struct nvme_pt_command *pt; 1347 1348 ctrlr = cdev->si_drv1; 1349 1350 switch (cmd) { 1351 case NVME_RESET_CONTROLLER: 1352 nvme_ctrlr_reset(ctrlr); 1353 break; 1354 case NVME_PASSTHROUGH_CMD: 1355 pt = (struct nvme_pt_command *)arg; 1356 return (nvme_ctrlr_passthrough_cmd(ctrlr, pt, le32toh(pt->cmd.nsid), 1357 1 /* is_user_buffer */, 1 /* is_admin_cmd */)); 1358 case NVME_GET_NSID: 1359 { 1360 struct nvme_get_nsid *gnsid = (struct nvme_get_nsid *)arg; 1361 strncpy(gnsid->cdev, device_get_nameunit(ctrlr->dev), 1362 sizeof(gnsid->cdev)); 1363 gnsid->cdev[sizeof(gnsid->cdev) - 1] = '\0'; 1364 gnsid->nsid = 0; 1365 break; 1366 } 1367 case NVME_GET_MAX_XFER_SIZE: 1368 *(uint64_t *)arg = ctrlr->max_xfer_size; 1369 break; 1370 default: 1371 return (ENOTTY); 1372 } 1373 1374 return (0); 1375 } 1376 1377 static struct cdevsw nvme_ctrlr_cdevsw = { 1378 .d_version = D_VERSION, 1379 .d_flags = 0, 1380 .d_ioctl = nvme_ctrlr_ioctl 1381 }; 1382 1383 int 1384 nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev) 1385 { 1386 struct make_dev_args md_args; 1387 uint32_t cap_lo; 1388 uint32_t cap_hi; 1389 uint32_t to, vs, pmrcap; 1390 int status, timeout_period; 1391 1392 ctrlr->dev = dev; 1393 1394 mtx_init(&ctrlr->lock, "nvme ctrlr lock", NULL, MTX_DEF); 1395 if (bus_get_domain(dev, &ctrlr->domain) != 0) 1396 ctrlr->domain = 0; 1397 1398 ctrlr->cap_lo = cap_lo = nvme_mmio_read_4(ctrlr, cap_lo); 1399 if (bootverbose) { 1400 device_printf(dev, "CapLo: 0x%08x: MQES %u%s%s%s%s, TO %u\n", 1401 cap_lo, NVME_CAP_LO_MQES(cap_lo), 1402 NVME_CAP_LO_CQR(cap_lo) ? ", CQR" : "", 1403 NVME_CAP_LO_AMS(cap_lo) ? ", AMS" : "", 1404 (NVME_CAP_LO_AMS(cap_lo) & 0x1) ? " WRRwUPC" : "", 1405 (NVME_CAP_LO_AMS(cap_lo) & 0x2) ? " VS" : "", 1406 NVME_CAP_LO_TO(cap_lo)); 1407 } 1408 ctrlr->cap_hi = cap_hi = nvme_mmio_read_4(ctrlr, cap_hi); 1409 if (bootverbose) { 1410 device_printf(dev, "CapHi: 0x%08x: DSTRD %u%s, CSS %x%s, " 1411 "CPS %x, MPSMIN %u, MPSMAX %u%s%s%s%s%s\n", cap_hi, 1412 NVME_CAP_HI_DSTRD(cap_hi), 1413 NVME_CAP_HI_NSSRS(cap_hi) ? ", NSSRS" : "", 1414 NVME_CAP_HI_CSS(cap_hi), 1415 NVME_CAP_HI_BPS(cap_hi) ? ", BPS" : "", 1416 NVME_CAP_HI_CPS(cap_hi), 1417 NVME_CAP_HI_MPSMIN(cap_hi), 1418 NVME_CAP_HI_MPSMAX(cap_hi), 1419 NVME_CAP_HI_PMRS(cap_hi) ? ", PMRS" : "", 1420 NVME_CAP_HI_CMBS(cap_hi) ? ", CMBS" : "", 1421 NVME_CAP_HI_NSSS(cap_hi) ? ", NSSS" : "", 1422 NVME_CAP_HI_CRWMS(cap_hi) ? ", CRWMS" : "", 1423 NVME_CAP_HI_CRIMS(cap_hi) ? ", CRIMS" : ""); 1424 } 1425 if (bootverbose) { 1426 vs = nvme_mmio_read_4(ctrlr, vs); 1427 device_printf(dev, "Version: 0x%08x: %d.%d\n", vs, 1428 NVME_MAJOR(vs), NVME_MINOR(vs)); 1429 } 1430 if (bootverbose && NVME_CAP_HI_PMRS(cap_hi)) { 1431 pmrcap = nvme_mmio_read_4(ctrlr, pmrcap); 1432 device_printf(dev, "PMRCap: 0x%08x: BIR %u%s%s, PMRTU %u, " 1433 "PMRWBM %x, PMRTO %u%s\n", pmrcap, 1434 NVME_PMRCAP_BIR(pmrcap), 1435 NVME_PMRCAP_RDS(pmrcap) ? ", RDS" : "", 1436 NVME_PMRCAP_WDS(pmrcap) ? ", WDS" : "", 1437 NVME_PMRCAP_PMRTU(pmrcap), 1438 NVME_PMRCAP_PMRWBM(pmrcap), 1439 NVME_PMRCAP_PMRTO(pmrcap), 1440 NVME_PMRCAP_CMSS(pmrcap) ? ", CMSS" : ""); 1441 } 1442 1443 ctrlr->dstrd = NVME_CAP_HI_DSTRD(cap_hi) + 2; 1444 1445 ctrlr->mps = NVME_CAP_HI_MPSMIN(cap_hi); 1446 ctrlr->page_size = 1 << (NVME_MPS_SHIFT + ctrlr->mps); 1447 1448 /* Get ready timeout value from controller, in units of 500ms. */ 1449 to = NVME_CAP_LO_TO(cap_lo) + 1; 1450 ctrlr->ready_timeout_in_ms = to * 500; 1451 1452 timeout_period = NVME_ADMIN_TIMEOUT_PERIOD; 1453 TUNABLE_INT_FETCH("hw.nvme.admin_timeout_period", &timeout_period); 1454 timeout_period = min(timeout_period, NVME_MAX_TIMEOUT_PERIOD); 1455 timeout_period = max(timeout_period, NVME_MIN_TIMEOUT_PERIOD); 1456 ctrlr->admin_timeout_period = timeout_period; 1457 1458 timeout_period = NVME_DEFAULT_TIMEOUT_PERIOD; 1459 TUNABLE_INT_FETCH("hw.nvme.timeout_period", &timeout_period); 1460 timeout_period = min(timeout_period, NVME_MAX_TIMEOUT_PERIOD); 1461 timeout_period = max(timeout_period, NVME_MIN_TIMEOUT_PERIOD); 1462 ctrlr->timeout_period = timeout_period; 1463 1464 nvme_retry_count = NVME_DEFAULT_RETRY_COUNT; 1465 TUNABLE_INT_FETCH("hw.nvme.retry_count", &nvme_retry_count); 1466 1467 ctrlr->enable_aborts = 0; 1468 TUNABLE_INT_FETCH("hw.nvme.enable_aborts", &ctrlr->enable_aborts); 1469 1470 /* Cap transfers by the maximum addressable by page-sized PRP (4KB pages -> 2MB). */ 1471 ctrlr->max_xfer_size = MIN(maxphys, (ctrlr->page_size / 8 * ctrlr->page_size)); 1472 if (nvme_ctrlr_construct_admin_qpair(ctrlr) != 0) 1473 return (ENXIO); 1474 1475 /* 1476 * Create 2 threads for the taskqueue. The reset thread will block when 1477 * it detects that the controller has failed until all I/O has been 1478 * failed up the stack. The fail_req task needs to be able to run in 1479 * this case to finish the request failure for some cases. 1480 * 1481 * We could partially solve this race by draining the failed requeust 1482 * queue before proceding to free the sim, though nothing would stop 1483 * new I/O from coming in after we do that drain, but before we reach 1484 * cam_sim_free, so this big hammer is used instead. 1485 */ 1486 ctrlr->taskqueue = taskqueue_create("nvme_taskq", M_WAITOK, 1487 taskqueue_thread_enqueue, &ctrlr->taskqueue); 1488 taskqueue_start_threads(&ctrlr->taskqueue, 2, PI_DISK, "nvme taskq"); 1489 1490 ctrlr->is_resetting = 0; 1491 ctrlr->is_initialized = 0; 1492 ctrlr->notification_sent = 0; 1493 TASK_INIT(&ctrlr->reset_task, 0, nvme_ctrlr_reset_task, ctrlr); 1494 TASK_INIT(&ctrlr->fail_req_task, 0, nvme_ctrlr_fail_req_task, ctrlr); 1495 STAILQ_INIT(&ctrlr->fail_req); 1496 ctrlr->is_failed = false; 1497 1498 make_dev_args_init(&md_args); 1499 md_args.mda_devsw = &nvme_ctrlr_cdevsw; 1500 md_args.mda_uid = UID_ROOT; 1501 md_args.mda_gid = GID_WHEEL; 1502 md_args.mda_mode = 0600; 1503 md_args.mda_unit = device_get_unit(dev); 1504 md_args.mda_si_drv1 = (void *)ctrlr; 1505 status = make_dev_s(&md_args, &ctrlr->cdev, "nvme%d", 1506 device_get_unit(dev)); 1507 if (status != 0) 1508 return (ENXIO); 1509 1510 return (0); 1511 } 1512 1513 void 1514 nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev) 1515 { 1516 int gone, i; 1517 1518 ctrlr->is_dying = true; 1519 1520 if (ctrlr->resource == NULL) 1521 goto nores; 1522 if (!mtx_initialized(&ctrlr->adminq.lock)) 1523 goto noadminq; 1524 1525 /* 1526 * Check whether it is a hot unplug or a clean driver detach. 1527 * If device is not there any more, skip any shutdown commands. 1528 */ 1529 gone = (nvme_mmio_read_4(ctrlr, csts) == NVME_GONE); 1530 if (gone) 1531 nvme_ctrlr_fail(ctrlr); 1532 else 1533 nvme_notify_fail_consumers(ctrlr); 1534 1535 for (i = 0; i < NVME_MAX_NAMESPACES; i++) 1536 nvme_ns_destruct(&ctrlr->ns[i]); 1537 1538 if (ctrlr->cdev) 1539 destroy_dev(ctrlr->cdev); 1540 1541 if (ctrlr->is_initialized) { 1542 if (!gone) { 1543 if (ctrlr->hmb_nchunks > 0) 1544 nvme_ctrlr_hmb_enable(ctrlr, false, false); 1545 nvme_ctrlr_delete_qpairs(ctrlr); 1546 } 1547 nvme_ctrlr_hmb_free(ctrlr); 1548 } 1549 if (ctrlr->ioq != NULL) { 1550 for (i = 0; i < ctrlr->num_io_queues; i++) 1551 nvme_io_qpair_destroy(&ctrlr->ioq[i]); 1552 free(ctrlr->ioq, M_NVME); 1553 } 1554 nvme_admin_qpair_destroy(&ctrlr->adminq); 1555 1556 /* 1557 * Notify the controller of a shutdown, even though this is due to 1558 * a driver unload, not a system shutdown (this path is not invoked 1559 * during shutdown). This ensures the controller receives a 1560 * shutdown notification in case the system is shutdown before 1561 * reloading the driver. 1562 */ 1563 if (!gone) 1564 nvme_ctrlr_shutdown(ctrlr); 1565 1566 if (!gone) 1567 nvme_ctrlr_disable(ctrlr); 1568 1569 noadminq: 1570 if (ctrlr->taskqueue) 1571 taskqueue_free(ctrlr->taskqueue); 1572 1573 if (ctrlr->tag) 1574 bus_teardown_intr(ctrlr->dev, ctrlr->res, ctrlr->tag); 1575 1576 if (ctrlr->res) 1577 bus_release_resource(ctrlr->dev, SYS_RES_IRQ, 1578 rman_get_rid(ctrlr->res), ctrlr->res); 1579 1580 if (ctrlr->bar4_resource != NULL) { 1581 bus_release_resource(dev, SYS_RES_MEMORY, 1582 ctrlr->bar4_resource_id, ctrlr->bar4_resource); 1583 } 1584 1585 bus_release_resource(dev, SYS_RES_MEMORY, 1586 ctrlr->resource_id, ctrlr->resource); 1587 1588 nores: 1589 mtx_destroy(&ctrlr->lock); 1590 } 1591 1592 void 1593 nvme_ctrlr_shutdown(struct nvme_controller *ctrlr) 1594 { 1595 uint32_t cc; 1596 uint32_t csts; 1597 int timeout; 1598 1599 cc = nvme_mmio_read_4(ctrlr, cc); 1600 cc &= ~NVMEM(NVME_CC_REG_SHN); 1601 cc |= NVMEF(NVME_CC_REG_SHN, NVME_SHN_NORMAL); 1602 nvme_mmio_write_4(ctrlr, cc, cc); 1603 1604 timeout = ticks + (ctrlr->cdata.rtd3e == 0 ? 5 * hz : 1605 ((uint64_t)ctrlr->cdata.rtd3e * hz + 999999) / 1000000); 1606 while (1) { 1607 csts = nvme_mmio_read_4(ctrlr, csts); 1608 if (csts == NVME_GONE) /* Hot unplug. */ 1609 break; 1610 if (NVME_CSTS_GET_SHST(csts) == NVME_SHST_COMPLETE) 1611 break; 1612 if (timeout - ticks < 0) { 1613 nvme_printf(ctrlr, "shutdown timeout\n"); 1614 break; 1615 } 1616 pause("nvmeshut", 1); 1617 } 1618 } 1619 1620 void 1621 nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 1622 struct nvme_request *req) 1623 { 1624 1625 nvme_qpair_submit_request(&ctrlr->adminq, req); 1626 } 1627 1628 void 1629 nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 1630 struct nvme_request *req) 1631 { 1632 struct nvme_qpair *qpair; 1633 1634 qpair = &ctrlr->ioq[QP(ctrlr, curcpu)]; 1635 nvme_qpair_submit_request(qpair, req); 1636 } 1637 1638 device_t 1639 nvme_ctrlr_get_device(struct nvme_controller *ctrlr) 1640 { 1641 1642 return (ctrlr->dev); 1643 } 1644 1645 const struct nvme_controller_data * 1646 nvme_ctrlr_get_data(struct nvme_controller *ctrlr) 1647 { 1648 1649 return (&ctrlr->cdata); 1650 } 1651 1652 int 1653 nvme_ctrlr_suspend(struct nvme_controller *ctrlr) 1654 { 1655 int to = hz; 1656 1657 /* 1658 * Can't touch failed controllers, so it's already suspended. 1659 */ 1660 if (ctrlr->is_failed) 1661 return (0); 1662 1663 /* 1664 * We don't want the reset taskqueue running, since it does similar 1665 * things, so prevent it from running after we start. Wait for any reset 1666 * that may have been started to complete. The reset process we follow 1667 * will ensure that any new I/O will queue and be given to the hardware 1668 * after we resume (though there should be none). 1669 */ 1670 while (atomic_cmpset_32(&ctrlr->is_resetting, 0, 1) == 0 && to-- > 0) 1671 pause("nvmesusp", 1); 1672 if (to <= 0) { 1673 nvme_printf(ctrlr, 1674 "Competing reset task didn't finish. Try again later.\n"); 1675 return (EWOULDBLOCK); 1676 } 1677 1678 if (ctrlr->hmb_nchunks > 0) 1679 nvme_ctrlr_hmb_enable(ctrlr, false, false); 1680 1681 /* 1682 * Per Section 7.6.2 of NVMe spec 1.4, to properly suspend, we need to 1683 * delete the hardware I/O queues, and then shutdown. This properly 1684 * flushes any metadata the drive may have stored so it can survive 1685 * having its power removed and prevents the unsafe shutdown count from 1686 * incriminating. Once we delete the qpairs, we have to disable them 1687 * before shutting down. 1688 */ 1689 nvme_ctrlr_delete_qpairs(ctrlr); 1690 nvme_ctrlr_disable_qpairs(ctrlr); 1691 nvme_ctrlr_shutdown(ctrlr); 1692 1693 return (0); 1694 } 1695 1696 int 1697 nvme_ctrlr_resume(struct nvme_controller *ctrlr) 1698 { 1699 1700 /* 1701 * Can't touch failed controllers, so nothing to do to resume. 1702 */ 1703 if (ctrlr->is_failed) 1704 return (0); 1705 1706 if (nvme_ctrlr_hw_reset(ctrlr) != 0) 1707 goto fail; 1708 1709 /* 1710 * Now that we've reset the hardware, we can restart the controller. Any 1711 * I/O that was pending is requeued. Any admin commands are aborted with 1712 * an error. Once we've restarted, take the controller out of reset. 1713 */ 1714 nvme_ctrlr_start(ctrlr, true); 1715 (void)atomic_cmpset_32(&ctrlr->is_resetting, 1, 0); 1716 1717 return (0); 1718 fail: 1719 /* 1720 * Since we can't bring the controller out of reset, announce and fail 1721 * the controller. However, we have to return success for the resume 1722 * itself, due to questionable APIs. 1723 */ 1724 nvme_printf(ctrlr, "Failed to reset on resume, failing.\n"); 1725 nvme_ctrlr_fail(ctrlr); 1726 (void)atomic_cmpset_32(&ctrlr->is_resetting, 1, 0); 1727 return (0); 1728 } 1729