1 /*
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2020-2023, Broadcom Inc. All rights reserved.
5 * Support: <[email protected]>
6 *
7 * Authors: Sumit Saxena <[email protected]>
8 * Chandrakanth Patil <[email protected]>
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are
12 * met:
13 *
14 * 1. Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright notice,
17 * this list of conditions and the following disclaimer in the documentation and/or other
18 * materials provided with the distribution.
19 * 3. Neither the name of the Broadcom Inc. nor the names of its contributors
20 * may be used to endorse or promote products derived from this software without
21 * specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 *
35 * The views and conclusions contained in the software and documentation are
36 * those of the authors and should not be interpreted as representing
37 * official policies,either expressed or implied, of the FreeBSD Project.
38 *
39 * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131
40 *
41 * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD
42 */
43
44 #ifndef _MPI3MRVAR_H
45 #define _MPI3MRVAR_H
46
47 #include <sys/cdefs.h>
48 #include <sys/types.h>
49 #include <sys/param.h>
50 #include <sys/systm.h>
51 #include <sys/kernel.h>
52 #include <sys/module.h>
53 #include <sys/bus.h>
54 #include <sys/conf.h>
55 #include <sys/malloc.h>
56 #include <sys/sysctl.h>
57 #include <sys/uio.h>
58 #include <sys/selinfo.h>
59 #include <sys/poll.h>
60
61 #include <sys/lock.h>
62 #include <sys/mutex.h>
63 #include <sys/endian.h>
64 #include <sys/sysent.h>
65 #include <sys/taskqueue.h>
66 #include <sys/smp.h>
67
68 #include <machine/bus.h>
69 #include <machine/resource.h>
70 #include <sys/rman.h>
71
72 #include <dev/pci/pcireg.h>
73 #include <dev/pci/pcivar.h>
74 #include <dev/pci/pci_private.h>
75
76 #include <cam/cam.h>
77 #include <cam/cam_ccb.h>
78 #include <cam/cam_debug.h>
79 #include <cam/cam_sim.h>
80 #include <cam/cam_xpt_sim.h>
81 #include <cam/cam_xpt_periph.h>
82 #include <cam/cam_periph.h>
83 #include <cam/scsi/scsi_all.h>
84 #include <cam/scsi/scsi_message.h>
85
86 #include <cam/scsi/smp_all.h>
87 #include <sys/queue.h>
88 #include <sys/kthread.h>
89 #include "mpi/mpi30_api.h"
90
91 #define MPI3MR_DRIVER_VERSION "8.6.0.2.0"
92 #define MPI3MR_DRIVER_RELDATE "17th May 2023"
93
94 #define MPI3MR_DRIVER_NAME "mpi3mr"
95
96 #define MPI3MR_NAME_LENGTH 32
97 #define IOCNAME "%s: "
98
99 #define SAS4116_CHIP_REV_A0 0
100 #define SAS4116_CHIP_REV_B0 1
101
102 #define MPI3MR_SG_DEPTH (MPI3MR_4K_PGSZ/sizeof(Mpi3SGESimple_t))
103 #define MPI3MR_MAX_SECTORS 2048
104 #define MPI3MR_MAX_CMDS_LUN 7
105 #define MPI3MR_MAX_CDB_LENGTH 16
106 #define MPI3MR_MAX_LUN 16895
107
108 #define MPI3MR_SATA_QDEPTH 32
109 #define MPI3MR_SAS_QDEPTH 64
110 #define MPI3MR_RAID_QDEPTH 128
111 #define MPI3MR_NVME_QDEPTH 128
112
113 #define MPI3MR_4K_PGSZ 4096
114 #define MPI3MR_AREQQ_SIZE (2 * MPI3MR_4K_PGSZ)
115 #define MPI3MR_AREPQ_SIZE (4 * MPI3MR_4K_PGSZ)
116 #define MPI3MR_AREQ_FRAME_SZ 128
117 #define MPI3MR_AREP_FRAME_SZ 16
118
119 #define MPI3MR_OPREQQ_SIZE (8 * MPI3MR_4K_PGSZ)
120 #define MPI3MR_OPREPQ_SIZE (4 * MPI3MR_4K_PGSZ)
121
122 /* Operational queue management definitions */
123 #define MPI3MR_OP_REQ_Q_QD 512
124 #define MPI3MR_OP_REP_Q_QD 1024
125 #define MPI3MR_OP_REP_Q_QD_A0 4096
126
127 #define MPI3MR_CHAINSGE_SIZE MPI3MR_4K_PGSZ
128
129 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \
130 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \
131 MPI3_SGE_FLAGS_END_OF_LIST)
132
133 #define MPI3MR_HOSTTAG_INVALID 0xFFFF
134 #define MPI3MR_HOSTTAG_INITCMDS 1
135 #define MPI3MR_HOSTTAG_IOCTLCMDS 2
136 #define MPI3MR_HOSTTAG_PELABORT 3
137 #define MPI3MR_HOSTTAG_PELWAIT 4
138 #define MPI3MR_HOSTTAG_TMS 5
139
140 #define MAX_MGMT_ADAPTERS 8
141 #define MPI3MR_WAIT_BEFORE_CTRL_RESET 5
142
143
144 struct mpi3mr_mgmt_info {
145 uint16_t count;
146 struct mpi3mr_softc *sc_ptr[MAX_MGMT_ADAPTERS];
147 int max_index;
148 };
149
150 extern char fmt_os_ver[16];
151
152 #define MPI3MR_OS_VERSION(raw_os_ver, fmt_os_ver) sprintf(raw_os_ver, "%d", __FreeBSD_version); \
153 sprintf(fmt_os_ver, "%c%c.%c%c.%c%c%c",\
154 raw_os_ver[0], raw_os_ver[1], raw_os_ver[2],\
155 raw_os_ver[3], raw_os_ver[4], raw_os_ver[5],\
156 raw_os_ver[6]);
157 #define MPI3MR_NUM_DEVRMCMD 1
158 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_TMS + 1)
159 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \
160 MPI3MR_NUM_DEVRMCMD - 1)
161 #define MPI3MR_INTERNALCMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX
162
163 #define MPI3MR_NUM_EVTACKCMD 4
164 #define MPI3MR_HOSTTAG_EVTACKCMD_MIN (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1)
165 #define MPI3MR_HOSTTAG_EVTACKCMD_MAX (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \
166 MPI3MR_NUM_EVTACKCMD - 1)
167
168 /* command/controller interaction timeout definitions in seconds */
169 #define MPI3MR_INTADMCMD_TIMEOUT 60
170 #define MPI3MR_PORTENABLE_TIMEOUT 300
171 #define MPI3MR_ABORTTM_TIMEOUT 60
172 #define MPI3MR_RESETTM_TIMEOUT 60
173 #define MPI3MR_TSUPDATE_INTERVAL 900
174 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120
175 #define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180
176 #define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5
177 #define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180
178 #define MPI3MR_RESET_ACK_TIMEOUT 30
179 #define MPI3MR_MUR_TIMEOUT 120
180
181 #define MPI3MR_CMD_NOTUSED 0x8000
182 #define MPI3MR_CMD_COMPLETE 0x0001
183 #define MPI3MR_CMD_PENDING 0x0002
184 #define MPI3MR_CMD_REPLYVALID 0x0004
185 #define MPI3MR_CMD_RESET 0x0008
186
187 #define MPI3MR_NUM_EVTREPLIES 64
188 #define MPI3MR_SENSEBUF_SZ 256
189 #define MPI3MR_SENSEBUF_FACTOR 3
190 #define MPI3MR_CHAINBUF_FACTOR 3
191
192 #define MPT3SAS_HOSTPGSZ_4KEXP 12
193
194 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF
195
196 /* Controller Reset related definitions */
197 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5
198 #define MPI3MR_MAX_SHUTDOWN_RETRY_COUNT 2
199
200 /* ResponseCode values */
201 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF)
202 #define MPI3MR_RSP_TM_COMPLETE 0x00
203 #define MPI3MR_RSP_INVALID_FRAME 0x02
204 #define MPI3MR_RSP_TM_NOT_SUPPORTED 0x04
205 #define MPI3MR_RSP_TM_FAILED 0x05
206 #define MPI3MR_RSP_TM_SUCCEEDED 0x08
207 #define MPI3MR_RSP_TM_INVALID_LUN 0x09
208 #define MPI3MR_RSP_TM_OVERLAPPED_TAG 0x0A
209 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \
210 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC
211
212 /* Definitions for the controller security status*/
213 #define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C
214 #define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02
215
216 #define MPI3MR_INVALID_DEVICE 0x00
217 #define MPI3MR_CONFIG_SECURE_DEVICE 0x04
218 #define MPI3MR_HARD_SECURE_DEVICE 0x08
219 #define MPI3MR_TAMPERED_DEVICE 0x0C
220
221 #define MPI3MR_DEFAULT_MDTS (128 * 1024)
222 #define MPI3MR_DEFAULT_PGSZEXP (12)
223 #define MPI3MR_MAX_IOCTL_TRANSFER_SIZE (1024 * 1024)
224
225 #define MPI3MR_DEVRMHS_RETRYCOUNT 3
226 #define MPI3MR_PELCMDS_RETRYCOUNT 3
227
228 #define MPI3MR_PERIODIC_DELAY 1 /* 1 second heartbeat/watchdog check */
229
230 struct completion {
231 unsigned int done;
232 struct mtx lock;
233 };
234
235 typedef union {
236 volatile unsigned int val;
237 unsigned int val_rdonly;
238 } mpi3mr_atomic_t;
239
240 #define mpi3mr_atomic_read(v) atomic_load_acq_int(&(v)->val)
241 #define mpi3mr_atomic_set(v,i) atomic_store_rel_int(&(v)->val, i)
242 #define mpi3mr_atomic_dec(v) atomic_subtract_int(&(v)->val, 1)
243 #define mpi3mr_atomic_inc(v) atomic_add_int(&(v)->val, 1)
244 #define mpi3mr_atomic_add(v, u) atomic_add_int(&(v)->val, u)
245 #define mpi3mr_atomic_sub(v, u) atomic_subtract_int(&(v)->val, u)
246
247 /* IOCTL data transfer sge*/
248 #define MPI3MR_NUM_IOCTL_SGE 256
249 #define MPI3MR_IOCTL_SGE_SIZE (8 * 1024)
250
251 struct dma_memory_desc {
252 U32 size;
253 void *addr;
254 bus_dma_tag_t tag;
255 bus_dmamap_t dmamap;
256 bus_addr_t dma_addr;
257 };
258
259 enum mpi3mr_iocstate {
260 MRIOC_STATE_READY = 1,
261 MRIOC_STATE_RESET,
262 MRIOC_STATE_FAULT,
263 MRIOC_STATE_BECOMING_READY,
264 MRIOC_STATE_RESET_REQUESTED,
265 MRIOC_STATE_UNRECOVERABLE,
266 MRIOC_STATE_COUNT,
267 };
268
269 /* Init type definitions */
270 enum mpi3mr_init_type {
271 MPI3MR_INIT_TYPE_INIT = 0,
272 MPI3MR_INIT_TYPE_RESET,
273 MPI3MR_INIT_TYPE_RESUME,
274 };
275
276 /* Reset reason code definitions*/
277 enum mpi3mr_reset_reason {
278 MPI3MR_RESET_FROM_BRINGUP = 1,
279 MPI3MR_RESET_FROM_FAULT_WATCH = 2,
280 MPI3MR_RESET_FROM_IOCTL = 3,
281 MPI3MR_RESET_FROM_EH_HOS = 4,
282 MPI3MR_RESET_FROM_TM_TIMEOUT = 5,
283 MPI3MR_RESET_FROM_IOCTL_TIMEOUT = 6,
284 MPI3MR_RESET_FROM_MUR_FAILURE = 7,
285 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8,
286 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9,
287 MPI3MR_RESET_FROM_PE_TIMEOUT = 10,
288 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11,
289 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12,
290 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13,
291 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14,
292 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15,
293 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16,
294 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17,
295 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18,
296 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19,
297 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20,
298 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21,
299 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22,
300 MPI3MR_RESET_FROM_SYSFS = 23,
301 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24,
302 MPI3MR_RESET_FROM_DIAG_BUFFER_POST_TIMEOUT = 25,
303 MPI3MR_RESET_FROM_SCSIIO_TIMEOUT = 26,
304 MPI3MR_RESET_FROM_FIRMWARE = 27,
305 MPI3MR_DEFAULT_RESET_REASON = 28,
306 MPI3MR_RESET_REASON_COUNT,
307 };
308
309 struct mpi3mr_compimg_ver
310 {
311 U16 build_num;
312 U16 cust_id;
313 U8 ph_minor;
314 U8 ph_major;
315 U8 gen_minor;
316 U8 gen_major;
317 };
318
319 struct mpi3mr_ioc_facts
320 {
321 U32 ioc_capabilities;
322 struct mpi3mr_compimg_ver fw_ver;
323 U32 mpi_version;
324 U16 max_reqs;
325 U16 product_id;
326 U16 op_req_sz;
327 U16 reply_sz;
328 U16 exceptions;
329 U16 max_perids;
330 U16 max_pds;
331 U16 max_sasexpanders;
332 U16 max_sasinitiators;
333 U16 max_enclosures;
334 U16 max_pcieswitches;
335 U16 max_nvme;
336 U16 max_vds;
337 U16 max_hpds;
338 U16 max_advhpds;
339 U16 max_raidpds;
340 U16 min_devhandle;
341 U16 max_devhandle;
342 U16 max_op_req_q;
343 U16 max_op_reply_q;
344 U16 shutdown_timeout;
345 U8 ioc_num;
346 U8 who_init;
347 U16 max_msix_vectors;
348 U8 personality;
349 U8 dma_mask;
350 U8 protocol_flags;
351 U8 sge_mod_mask;
352 U8 sge_mod_value;
353 U8 sge_mod_shift;
354 U8 max_dev_per_tg;
355 U16 max_io_throttle_group;
356 U16 io_throttle_data_length;
357 U16 io_throttle_low;
358 U16 io_throttle_high;
359 };
360
361 struct mpi3mr_op_req_queue {
362 U16 ci;
363 U16 pi;
364 U16 num_reqs;
365 U8 qid;
366 U8 reply_qid;
367 U32 qsz;
368 void *q_base;
369 bus_dma_tag_t q_base_tag;
370 bus_dmamap_t q_base_dmamap;
371 bus_addr_t q_base_phys;
372 struct mtx q_lock;
373 };
374
375 struct mpi3mr_op_reply_queue {
376 U16 ci;
377 U8 ephase;
378 U8 qid;
379 U16 num_replies;
380 U32 qsz;
381 bus_dma_tag_t q_base_tag;
382 bus_dmamap_t q_base_dmamap;
383 void *q_base;
384 bus_addr_t q_base_phys;
385 mpi3mr_atomic_t pend_ios;
386 bool in_use;
387 struct mtx q_lock;
388 };
389
390 struct irq_info {
391 MPI3_REPLY_DESCRIPTORS_UNION *post_queue;
392 bus_dma_tag_t buffer_dmat;
393 struct resource *irq;
394 void *intrhand;
395 int irq_rid;
396 };
397
398 struct mpi3mr_irq_context {
399 struct mpi3mr_softc *sc;
400 U16 msix_index;
401 struct mpi3mr_op_reply_queue *op_reply_q;
402 char name[MPI3MR_NAME_LENGTH];
403 struct irq_info irq_info;
404 };
405
406 MALLOC_DECLARE(M_MPI3MR);
407 SYSCTL_DECL(_hw_mpi3mr);
408
409 typedef struct mpi3mr_drvr_cmd DRVR_CMD;
410 typedef void (*DRVR_CMD_CALLBACK)(struct mpi3mr_softc *mrioc, DRVR_CMD *drvrcmd);
411 struct mpi3mr_drvr_cmd {
412 struct mtx lock;
413 struct completion completion;
414 void *reply;
415 U8 *sensebuf;
416 U8 iou_rc;
417 U16 state;
418 U16 dev_handle;
419 U16 ioc_status;
420 U32 ioc_loginfo;
421 U8 is_waiting;
422 U8 is_senseprst;
423 U8 retry_count;
424 U16 host_tag;
425 DRVR_CMD_CALLBACK callback;
426 };
427
428 struct mpi3mr_cmd;
429 typedef void mpi3mr_evt_callback_t(struct mpi3mr_softc *, uintptr_t,
430 Mpi3EventNotificationReply_t *reply);
431 typedef void mpi3mr_cmd_callback_t(struct mpi3mr_softc *,
432 struct mpi3mr_cmd *cmd);
433
434 #define MPI3MR_IOVEC_COUNT 2
435
436 enum mpi3mr_data_xfer_direction {
437 MPI3MR_READ = 1,
438 MPI3MR_WRITE,
439 };
440
441 enum mpi3mr_cmd_state {
442 MPI3MR_CMD_STATE_FREE = 1,
443 MPI3MR_CMD_STATE_BUSY,
444 MPI3MR_CMD_STATE_IN_QUEUE,
445 MPI3MR_CMD_STATE_IN_TM,
446 };
447
448 enum mpi3mr_target_state {
449 MPI3MR_DEV_CREATED = 1,
450 MPI3MR_DEV_REMOVE_HS_STARTED = 2,
451 MPI3MR_DEV_DELETED = 3,
452 };
453
454 struct mpi3mr_cmd {
455 TAILQ_ENTRY(mpi3mr_cmd) next;
456 struct mpi3mr_softc *sc;
457 union ccb *ccb;
458 void *data;
459 u_int length;
460 struct mpi3mr_target *targ;
461 u_int data_dir;
462 u_int state;
463 bus_dmamap_t dmamap;
464 struct scsi_sense_data *sense;
465 struct callout callout;
466 bool callout_owner;
467 U16 hosttag;
468 U8 req_qidx;
469 Mpi3SCSIIORequest_t io_request;
470 };
471
472 struct mpi3mr_chain {
473 bus_dmamap_t buf_dmamap;
474 void *buf;
475 bus_addr_t buf_phys;
476 };
477
478 struct mpi3mr_event_handle {
479 TAILQ_ENTRY(mpi3mr_event_handle) eh_list;
480 mpi3mr_evt_callback_t *callback;
481 void *data;
482 uint8_t mask[16];
483 };
484
485 struct mpi3mr_fw_event_work {
486 U16 event;
487 void *event_data;
488 TAILQ_ENTRY(mpi3mr_fw_event_work) ev_link;
489 U8 send_ack;
490 U8 process_event;
491 U32 event_context;
492 U16 event_data_size;
493 };
494
495 /**
496 * struct delayed_dev_rmhs_node - Delayed device removal node
497 *
498 * @list: list head
499 * @handle: Device handle
500 * @iou_rc: IO Unit Control Reason Code
501 */
502 struct delayed_dev_rmhs_node {
503 TAILQ_ENTRY(delayed_dev_rmhs_node) list;
504 U16 handle;
505 U8 iou_rc;
506 };
507
508 /**
509 * struct delayed_evtack_node - Delayed event ack node
510 *
511 * @list: list head
512 * @event: MPI3 event ID
513 * @event_ctx: Event context
514 */
515 struct delayed_evtack_node {
516 TAILQ_ENTRY(delayed_evtack_node) list;
517 U8 event;
518 U32 event_ctx;
519 };
520
521 /* Reset types */
522 enum reset_type {
523 MPI3MR_NO_RESET,
524 MPI3MR_TRIGGER_SOFT_RESET,
525 };
526
527 struct mpi3mr_reset {
528 u_int type;
529 U32 reason;
530 int status;
531 bool ioctl_reset_snapdump;
532 };
533
534 struct mpi3mr_softc {
535 device_t mpi3mr_dev;
536 struct cdev *mpi3mr_cdev;
537 u_int mpi3mr_flags;
538 #define MPI3MR_FLAGS_SHUTDOWN (1 << 0)
539 #define MPI3MR_FLAGS_DIAGRESET (1 << 1)
540 #define MPI3MR_FLAGS_ATTACH_DONE (1 << 2)
541 #define MPI3MR_FLAGS_PORT_ENABLE_DONE (1 << 3)
542 U8 id;
543 int cpu_count;
544 char name[MPI3MR_NAME_LENGTH];
545 char driver_name[MPI3MR_NAME_LENGTH];
546 int bars;
547 bus_addr_t dma_loaddr;
548 u_int mpi3mr_debug;
549 struct mpi3mr_reset reset;
550 int max_msix_vectors;
551 int msix_count;
552 bool msix_enable;
553 int io_cmds_highwater;
554 int max_chains;
555 uint32_t chain_frame_size;
556 struct sysctl_ctx_list sysctl_ctx;
557 struct sysctl_oid *sysctl_tree;
558 char fw_version[32];
559 struct mpi3mr_chain *chains;
560 struct callout periodic;
561 struct callout device_check_callout;
562
563 struct mpi3mr_cam_softc *cam_sc;
564 struct mpi3mr_cmd **cmd_list;
565 TAILQ_HEAD(, mpi3mr_cmd) cmd_list_head;
566 struct mtx cmd_pool_lock;
567
568 struct resource *mpi3mr_regs_resource;
569 bus_space_handle_t mpi3mr_bhandle;
570 bus_space_tag_t mpi3mr_btag;
571 int mpi3mr_regs_rid;
572
573 bus_dma_tag_t mpi3mr_parent_dmat;
574 bus_dma_tag_t buffer_dmat;
575
576 int num_reqs;
577 int num_replies;
578 int num_chains;
579
580 TAILQ_HEAD(, mpi3mr_event_handle) event_list;
581 struct mpi3mr_event_handle *mpi3mr_log_eh;
582 struct intr_config_hook mpi3mr_ich;
583
584 struct mtx mpi3mr_mtx;
585 struct mtx io_lock;
586 U8 intr_enabled;
587 TAILQ_HEAD(, delayed_dev_rmhs_node) delayed_rmhs_list;
588 TAILQ_HEAD(, delayed_evtack_node) delayed_evtack_cmds_list;
589
590 U16 num_admin_reqs;
591 U32 admin_req_q_sz;
592 U16 admin_req_pi;
593 U16 admin_req_ci;
594 bus_dma_tag_t admin_req_tag;
595 bus_dmamap_t admin_req_dmamap;
596 bus_addr_t admin_req_phys;
597 U8 *admin_req;
598 struct mtx admin_req_lock;
599
600 U16 num_admin_replies;
601 U32 admin_reply_q_sz;
602 U16 admin_reply_ci;
603 U8 admin_reply_ephase;
604 bus_dma_tag_t admin_reply_tag;
605 bus_dmamap_t admin_reply_dmamap;
606 bus_addr_t admin_reply_phys;
607 U8 *admin_reply;
608 struct mtx admin_reply_lock;
609 bool admin_in_use;
610
611 U32 num_reply_bufs;
612 bus_dma_tag_t reply_buf_tag;
613 bus_dmamap_t reply_buf_dmamap;
614 bus_addr_t reply_buf_phys;
615 U8 *reply_buf;
616 bus_addr_t reply_buf_dma_max_address;
617 bus_addr_t reply_buf_dma_min_address;
618
619 U16 reply_free_q_sz;
620 bus_dma_tag_t reply_free_q_tag;
621 bus_dmamap_t reply_free_q_dmamap;
622 bus_addr_t reply_free_q_phys;
623 U64 *reply_free_q;
624 struct mtx reply_free_q_lock;
625 U32 reply_free_q_host_index;
626
627 U32 num_sense_bufs;
628 bus_dma_tag_t sense_buf_tag;
629 bus_dmamap_t sense_buf_dmamap;
630 bus_addr_t sense_buf_phys;
631 U8 *sense_buf;
632
633 U16 sense_buf_q_sz;
634 bus_dma_tag_t sense_buf_q_tag;
635 bus_dmamap_t sense_buf_q_dmamap;
636 bus_addr_t sense_buf_q_phys;
637 U64 *sense_buf_q;
638 struct mtx sense_buf_q_lock;
639 U32 sense_buf_q_host_index;
640
641 void *nvme_encap_prp_list;
642 bus_addr_t nvme_encap_prp_list_dma;
643 bus_dma_tag_t nvme_encap_prp_list_dmatag;
644 bus_dmamap_t nvme_encap_prp_list_dma_dmamap;
645 U32 nvme_encap_prp_sz;
646
647 U32 ready_timeout;
648
649 struct mpi3mr_irq_context *irq_ctx;
650
651 U16 num_queues; /* Number of request/reply queues */
652 struct mpi3mr_op_req_queue *op_req_q;
653 struct mpi3mr_op_reply_queue *op_reply_q;
654 U16 num_hosttag_op_req_q;
655
656 struct mpi3mr_drvr_cmd init_cmds;
657 struct mpi3mr_ioc_facts facts;
658 U16 reply_sz;
659 U16 op_reply_sz;
660
661 U32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS];
662
663 char fwevt_worker_name[MPI3MR_NAME_LENGTH];
664 struct workqueue_struct *fwevt_worker_thread;
665 struct mtx fwevt_lock;
666 struct mtx target_lock;
667
668 U16 max_host_ios;
669 bus_dma_tag_t chain_sgl_list_tag;
670 struct mpi3mr_chain *chain_sgl_list;
671 U16 chain_bitmap_sz;
672 void *chain_bitmap;
673 struct mtx chain_buf_lock;
674 U16 chain_buf_count;
675
676 struct mpi3mr_drvr_cmd ioctl_cmds;
677 struct mpi3mr_drvr_cmd host_tm_cmds;
678 struct mpi3mr_drvr_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD];
679 struct mpi3mr_drvr_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD];
680
681 U16 devrem_bitmap_sz;
682 void *devrem_bitmap;
683
684 U16 dev_handle_bitmap_sz;
685 void *removepend_bitmap;
686
687 U16 evtack_cmds_bitmap_sz;
688 void *evtack_cmds_bitmap;
689
690 U32 ts_update_counter;
691 U8 reset_in_progress;
692 U8 unrecoverable;
693 U8 block_ioctls;
694 U8 in_prep_ciactv_rst;
695 U16 prep_ciactv_rst_counter;
696 struct mtx reset_mutex;
697
698 U8 prepare_for_reset;
699 U16 prepare_for_reset_timeout_counter;
700
701 U16 diagsave_timeout;
702 int logging_level;
703 U16 flush_io_count;
704
705 Mpi3DriverInfoLayout_t driver_info;
706
707 U16 change_count;
708
709 U8 *log_data_buffer;
710 U16 log_data_buffer_index;
711 U16 log_data_entry_size;
712
713 U8 pel_wait_pend;
714 U8 pel_abort_requested;
715 U8 pel_class;
716 U16 pel_locale;
717
718 struct mpi3mr_drvr_cmd pel_cmds;
719 struct mpi3mr_drvr_cmd pel_abort_cmd;
720 U32 newest_seqnum;
721 void *pel_seq_number;
722 bus_addr_t pel_seq_number_dma;
723 bus_dma_tag_t pel_seq_num_dmatag;
724 bus_dmamap_t pel_seq_num_dmamap;
725 U32 pel_seq_number_sz;
726
727 struct selinfo mpi3mr_select;
728 U32 mpi3mr_poll_waiting;
729 U32 mpi3mr_aen_triggered;
730
731 U16 wait_for_port_enable;
732 U16 track_mapping_events;
733 U16 pending_map_events;
734 mpi3mr_atomic_t fw_outstanding;
735 mpi3mr_atomic_t pend_ioctls;
736 struct proc *watchdog_thread;
737 void *watchdog_chan;
738 void *tm_chan;
739 u_int8_t remove_in_progress;
740 u_int8_t watchdog_thread_active;
741 u_int8_t do_timedout_reset;
742 bool allow_ios;
743 bool secure_ctrl;
744 mpi3mr_atomic_t pend_large_data_sz;
745
746 u_int32_t io_throttle_data_length;
747 u_int32_t io_throttle_high;
748 u_int32_t io_throttle_low;
749 u_int16_t num_io_throttle_group;
750 u_int iot_enable;
751 struct mpi3mr_throttle_group_info *throttle_groups;
752
753 struct dma_memory_desc ioctl_sge[MPI3MR_NUM_IOCTL_SGE];
754 struct dma_memory_desc ioctl_chain_sge;
755 struct dma_memory_desc ioctl_resp_sge;
756 bool ioctl_sges_allocated;
757 };
758
759 static __inline uint64_t
mpi3mr_regread64(struct mpi3mr_softc * sc,uint32_t offset)760 mpi3mr_regread64(struct mpi3mr_softc *sc, uint32_t offset)
761 {
762 return bus_space_read_8(sc->mpi3mr_btag, sc->mpi3mr_bhandle, offset);
763 }
764
765 static __inline void
mpi3mr_regwrite64(struct mpi3mr_softc * sc,uint32_t offset,uint64_t val)766 mpi3mr_regwrite64(struct mpi3mr_softc *sc, uint32_t offset, uint64_t val)
767 {
768 bus_space_write_8(sc->mpi3mr_btag, sc->mpi3mr_bhandle, offset, val);
769 }
770
771 static __inline uint32_t
mpi3mr_regread(struct mpi3mr_softc * sc,uint32_t offset)772 mpi3mr_regread(struct mpi3mr_softc *sc, uint32_t offset)
773 {
774 return bus_space_read_4(sc->mpi3mr_btag, sc->mpi3mr_bhandle, offset);
775 }
776
777 static __inline void
mpi3mr_regwrite(struct mpi3mr_softc * sc,uint32_t offset,uint32_t val)778 mpi3mr_regwrite(struct mpi3mr_softc *sc, uint32_t offset, uint32_t val)
779 {
780 bus_space_write_4(sc->mpi3mr_btag, sc->mpi3mr_bhandle, offset, val);
781 }
782
783 #define MPI3MR_INFO (1 << 0) /* Basic info */
784 #define MPI3MR_FAULT (1 << 1) /* Hardware faults */
785 #define MPI3MR_EVENT (1 << 2) /* Event data from the controller */
786 #define MPI3MR_LOG (1 << 3) /* Log data from the controller */
787 #define MPI3MR_RECOVERY (1 << 4) /* Command error recovery tracing */
788 #define MPI3MR_ERROR (1 << 5) /* Fatal driver/OS APIs failure */
789 #define MPI3MR_XINFO (1 << 6) /* Additional info logs*/
790 #define MPI3MR_TRACE (1 << 7) /* Trace functions */
791 #define MPI3MR_IOT (1 << 8) /* IO throttling related debugs */
792 #define MPI3MR_DEBUG_TM (1 << 9) /* Task management related debugs */
793 #define MPI3MR_DEBUG_IOCTL (1 << 10) /* IOCTL related debugs */
794
795 #define mpi3mr_printf(sc, args...) \
796 device_printf((sc)->mpi3mr_dev, ##args)
797
798 #define mpi3mr_print_field(sc, msg, args...) \
799 printf("\t" msg, ##args)
800
801 #define mpi3mr_vprintf(sc, args...) \
802 do { \
803 if (bootverbose) \
804 mpi3mr_printf(sc, ##args); \
805 } while (0)
806
807 #define mpi3mr_dprint(sc, level, msg, args...) \
808 do { \
809 if ((sc)->mpi3mr_debug & (level)) \
810 device_printf((sc)->mpi3mr_dev, msg, ##args); \
811 } while (0)
812
813 #define MPI3MR_PRINTFIELD_START(sc, tag...) \
814 mpi3mr_printf((sc), ##tag); \
815 mpi3mr_print_field((sc), ":\n")
816 #define MPI3MR_PRINTFIELD_END(sc, tag) \
817 mpi3mr_printf((sc), tag "\n")
818 #define MPI3MR_PRINTFIELD(sc, facts, attr, fmt) \
819 mpi3mr_print_field((sc), #attr ": " #fmt "\n", (facts)->attr)
820
821 #define mpi3mr_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \
822 kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg)
823 #define mpi3mr_kproc_exit(arg) kproc_exit(arg)
824
825 #if defined(CAM_PRIORITY_XPT)
826 #define MPI3MR_PRIORITY_XPT CAM_PRIORITY_XPT
827 #else
828 #define MPI3MR_PRIORITY_XPT 5
829 #endif
830
831 static __inline void
mpi3mr_clear_bit(int b,volatile void * p)832 mpi3mr_clear_bit(int b, volatile void *p)
833 {
834 atomic_clear_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f));
835 }
836
837 static __inline void
mpi3mr_set_bit(int b,volatile void * p)838 mpi3mr_set_bit(int b, volatile void *p)
839 {
840 atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f));
841 }
842
843 static __inline int
mpi3mr_test_bit(int b,volatile void * p)844 mpi3mr_test_bit(int b, volatile void *p)
845 {
846 return ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f));
847 }
848
849 static __inline int
mpi3mr_test_and_set_bit(int b,volatile void * p)850 mpi3mr_test_and_set_bit(int b, volatile void *p)
851 {
852 int ret = ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f));
853
854 atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f));
855 return ret;
856 }
857
858 static __inline int
mpi3mr_find_first_zero_bit(void * p,int bit_count)859 mpi3mr_find_first_zero_bit(void *p, int bit_count)
860 {
861 int i, sz, j=0;
862 U8 *loc;
863
864 sz = bit_count % 8 ? (bit_count / 8 + 1) : (bit_count / 8);
865 loc = malloc(sz, M_MPI3MR, M_NOWAIT | M_ZERO);
866
867 memcpy(loc, p, sz);
868
869 for (i = 0; i < sz; i++) {
870 j = 0;
871 while (j < 8) {
872 if (!((loc[i] >> j) & 0x1))
873 goto out;
874 j++;
875 }
876 }
877 out:
878 free(loc, M_MPI3MR);
879 return (i + j);
880 }
881
882 #define MPI3MR_DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
883
884 void
885 init_completion(struct completion *completion);
886
887 void
888 complete(struct completion *completion);
889
890 void wait_for_completion_timeout(struct completion *completion,
891 U32 timeout);
892 void wait_for_completion_timeout_tm(struct completion *completion,
893 U32 timeout, struct mpi3mr_softc *sc);
894 void mpi3mr_add_sg_single(void *paddr, U8 flags, U32 length,
895 bus_addr_t dma_addr);
896 void mpi3mr_enable_interrupts(struct mpi3mr_softc *sc);
897 void mpi3mr_disable_interrupts(struct mpi3mr_softc *sc);
898 void mpi3mr_memaddr_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error);
899 int mpi3mr_submit_admin_cmd(struct mpi3mr_softc *mrioc, void *admin_req,
900 U16 admin_req_sz);
901 int mpi3mr_submit_io(struct mpi3mr_softc *mrioc,
902 struct mpi3mr_op_req_queue *op_req_q, U8 *req);
903 int
904 mpi3mr_alloc_interrupts(struct mpi3mr_softc *sc, U16 setup_one);
905
906 void mpi3mr_cleanup_ioc(struct mpi3mr_softc *sc);
907 int mpi3mr_initialize_ioc(struct mpi3mr_softc *sc, U8 reason);
908 void mpi3mr_build_zero_len_sge(void *paddr);
909 int mpi3mr_issue_event_notification(struct mpi3mr_softc *sc);
910 int
911 mpi3mr_register_events(struct mpi3mr_softc *sc);
912 void mpi3mr_process_op_reply_desc(struct mpi3mr_softc *sc,
913 Mpi3DefaultReplyDescriptor_t *reply_desc, U64 *reply_dma);
914 struct mpi3mr_cmd *
915 mpi3mr_get_command(struct mpi3mr_softc *sc);
916 void
917 mpi3mr_release_command(struct mpi3mr_cmd *cmd);
918 int
919 mpi3mr_complete_io_cmd(struct mpi3mr_softc *sc,
920 struct mpi3mr_irq_context *irq_context);
921 int
922 mpi3mr_cam_detach(struct mpi3mr_softc *sc);
923 int
924 mpi3mr_cam_attach(struct mpi3mr_softc *sc);
925 struct mpi3mr_target *
926 mpi3mr_find_target_by_per_id(struct mpi3mr_cam_softc *cam_sc,
927 uint16_t per_id);
928 struct mpi3mr_target *
929 mpi3mr_find_target_by_dev_handle(struct mpi3mr_cam_softc *cam_sc,
930 uint16_t dev_handle);
931 int mpi3mr_create_device(struct mpi3mr_softc *sc,
932 Mpi3DevicePage0_t *dev_pg0);
933 void
934 mpi3mr_unmap_request(struct mpi3mr_softc *sc, struct mpi3mr_cmd *cmd);
935 void
936 init_completion(struct completion *completion);
937 void
938 complete(struct completion *completion);
939 void wait_for_completion_timeout(struct completion *completion,
940 U32 timeout);
941 void
942 poll_for_command_completion(struct mpi3mr_softc *sc,
943 struct mpi3mr_drvr_cmd *cmd, U16 wait);
944 int
945 mpi3mr_alloc_requests(struct mpi3mr_softc *sc);
946 void
947 mpi3mr_watchdog(void *arg);
948 int mpi3mr_issue_port_enable(struct mpi3mr_softc *mrioc, U8 async);
949 void
950 mpi3mr_isr(void *privdata);
951 int
952 mpi3mr_alloc_msix_queues(struct mpi3mr_softc *sc);
953 void
954 mpi3mr_destory_mtx(struct mpi3mr_softc *sc);
955 void
956 mpi3mr_free_mem(struct mpi3mr_softc *sc);
957 void
958 mpi3mr_cleanup_interrupts(struct mpi3mr_softc *sc);
959 int mpi3mr_setup_irqs(struct mpi3mr_softc *sc);
960 void mpi3mr_cleanup_event_taskq(struct mpi3mr_softc *sc);
961 void
962 mpi3mr_hexdump(void *buf, int sz, int format);
963 int mpi3mr_soft_reset_handler(struct mpi3mr_softc *sc,
964 U32 reset_reason, bool snapdump);
965 void
966 mpi3mrsas_release_simq_reinit(struct mpi3mr_cam_softc *cam_sc);
967 void
968 mpi3mr_watchdog_thread(void *arg);
969 void mpi3mr_add_device(struct mpi3mr_softc *sc, U16 per_id);
970 int mpi3mr_remove_device(struct mpi3mr_softc *sc, U16 handle);
971 int
972 mpi3mrsas_register_events(struct mpi3mr_softc *sc);
973 int mpi3mr_process_event_ack(struct mpi3mr_softc *sc, U8 event,
974 U32 event_ctx);
975 int mpi3mr_remove_device_from_os(struct mpi3mr_softc *sc, U16 handle);
976 void mpi3mr_remove_device_from_list(struct mpi3mr_softc *sc, struct mpi3mr_target *target,
977 bool must_delete);
978 void mpi3mr_update_device(struct mpi3mr_softc *mrioc,
979 struct mpi3mr_target *tgtdev, Mpi3DevicePage0_t *dev_pg0, bool is_added);
980 void mpi3mr_app_save_logdata(struct mpi3mr_softc *sc, char *event_data, U16 event_data_size);
981 void mpi3mr_set_io_divert_for_all_vd_in_tg(struct mpi3mr_softc *sc,
982 struct mpi3mr_throttle_group_info *tg, U8 divert_value);
983 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_softc *sc);
984 void mpi3mr_poll_pend_io_completions(struct mpi3mr_softc *sc);
985 void int_to_lun(unsigned int lun, U8 *req_lun);
986 void trigger_reset_from_watchdog(struct mpi3mr_softc *sc, U8 reset_type, U32 reset_reason);
987 void mpi3mr_alloc_ioctl_dma_memory(struct mpi3mr_softc *sc);
988 #endif /*MPI3MR_H_INCLUDED*/
989