1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright (c) 2024, Intel Corporation
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the Intel Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /**
33 * @file ice_lib.h
34 * @brief header for generic device and sysctl functions
35 *
36 * Contains definitions and function declarations for the ice_lib.c file. It
37 * does not depend on the iflib networking stack.
38 */
39
40 #ifndef _ICE_LIB_H_
41 #define _ICE_LIB_H_
42
43 #include <sys/types.h>
44 #include <sys/bus.h>
45 #include <sys/rman.h>
46 #include <sys/socket.h>
47 #include <sys/sbuf.h>
48 #include <sys/sysctl.h>
49 #include <sys/syslog.h>
50 #include <sys/module.h>
51 #include <sys/proc.h>
52
53 #include <net/if.h>
54 #include <net/if_var.h>
55 #include <net/if_media.h>
56 #include <net/ethernet.h>
57 #include <net/if_types.h>
58
59 #include <sys/bitstring.h>
60
61 #include "ice_dcb.h"
62 #include "ice_type.h"
63 #include "ice_common.h"
64 #include "ice_flow.h"
65 #include "ice_sched.h"
66 #include "ice_resmgr.h"
67
68 #include "ice_rdma_internal.h"
69
70 #include "ice_rss.h"
71
72 /* Hide debug sysctls unless INVARIANTS is enabled */
73 #ifdef INVARIANTS
74 #define ICE_CTLFLAG_DEBUG 0
75 #else
76 #define ICE_CTLFLAG_DEBUG CTLFLAG_SKIP
77 #endif
78
79 /**
80 * for_each_set_bit - For loop over each set bit in a bit string
81 * @bit: storage for the bit index
82 * @data: address of data block to loop over
83 * @nbits: maximum number of bits to loop over
84 *
85 * macro to create a for loop over a bit string, which runs the body once for
86 * each bit that is set in the string. The bit variable will be set to the
87 * index of each set bit in the string, with zero representing the first bit.
88 */
89 #define for_each_set_bit(bit, data, nbits) \
90 for (bit_ffs((bitstr_t *)(data), (nbits), &(bit)); \
91 (bit) != -1; \
92 bit_ffs_at((bitstr_t *)(data), (bit) + 1, (nbits), &(bit)))
93
94 /**
95 * @var broadcastaddr
96 * @brief broadcast MAC address
97 *
98 * constant defining the broadcast MAC address, used for programming the
99 * broadcast address as a MAC filter for the PF VSI.
100 */
101 static const u8 broadcastaddr[ETHER_ADDR_LEN] = {
102 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
103 };
104
105 MALLOC_DECLARE(M_ICE);
106
107 extern const char ice_driver_version[];
108 extern const uint8_t ice_major_version;
109 extern const uint8_t ice_minor_version;
110 extern const uint8_t ice_patch_version;
111 extern const uint8_t ice_rc_version;
112
113 /* global sysctl indicating whether the Tx FC filter should be enabled */
114 extern bool ice_enable_tx_fc_filter;
115
116 /* global sysctl indicating whether the Tx LLDP filter should be enabled */
117 extern bool ice_enable_tx_lldp_filter;
118
119 /* global sysctl indicating whether FW health status events should be enabled */
120 extern bool ice_enable_health_events;
121
122 /* global sysctl indicating whether to enable 5-layer scheduler topology */
123 extern bool ice_tx_balance_en;
124
125 /**
126 * @struct ice_bar_info
127 * @brief PCI BAR mapping information
128 *
129 * Contains data about a PCI BAR that the driver has mapped for use.
130 */
131 struct ice_bar_info {
132 struct resource *res;
133 bus_space_tag_t tag;
134 bus_space_handle_t handle;
135 bus_size_t size;
136 int rid;
137 };
138
139 /* Alignment for queues */
140 #define DBA_ALIGN 128
141
142 /* Maximum TSO size is (256K)-1 */
143 #define ICE_TSO_SIZE ((256*1024) - 1)
144
145 /* Minimum size for TSO MSS */
146 #define ICE_MIN_TSO_MSS 64
147
148 #define ICE_MAX_TX_SEGS 8
149 #define ICE_MAX_TSO_SEGS 128
150
151 #define ICE_MAX_DMA_SEG_SIZE ((16*1024) - 1)
152
153 #define ICE_MAX_RX_SEGS 5
154
155 #define ICE_MAX_TSO_HDR_SEGS 3
156
157 #define ICE_MSIX_BAR 3
158 #define ICE_MAX_MSIX_VECTORS (GLINT_DYN_CTL_MAX_INDEX + 1)
159
160 #define ICE_DEFAULT_DESC_COUNT 1024
161 #define ICE_MAX_DESC_COUNT 8160
162 #define ICE_MIN_DESC_COUNT 64
163 #define ICE_DESC_COUNT_INCR 32
164
165 /* List of hardware offloads we support */
166 #define ICE_CSUM_OFFLOAD (CSUM_IP | CSUM_IP_TCP | CSUM_IP_UDP | CSUM_IP_SCTP | \
167 CSUM_IP6_TCP| CSUM_IP6_UDP | CSUM_IP6_SCTP | \
168 CSUM_IP_TSO | CSUM_IP6_TSO)
169
170 /* Macros to decide what kind of hardware offload to enable */
171 #define ICE_CSUM_TCP (CSUM_IP_TCP|CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP6_TCP)
172 #define ICE_CSUM_UDP (CSUM_IP_UDP|CSUM_IP6_UDP)
173 #define ICE_CSUM_SCTP (CSUM_IP_SCTP|CSUM_IP6_SCTP)
174 #define ICE_CSUM_IP (CSUM_IP|CSUM_IP_TSO)
175
176 /* List of known RX CSUM offload flags */
177 #define ICE_RX_CSUM_FLAGS (CSUM_L3_CALC | CSUM_L3_VALID | CSUM_L4_CALC | \
178 CSUM_L4_VALID | CSUM_L5_CALC | CSUM_L5_VALID | \
179 CSUM_COALESCED)
180
181 /* List of interface capabilities supported by ice hardware */
182 #define ICE_FULL_CAPS \
183 (IFCAP_TSO4 | IFCAP_TSO6 | \
184 IFCAP_TXCSUM | IFCAP_TXCSUM_IPV6 | \
185 IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6 | \
186 IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO | \
187 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO | \
188 IFCAP_VLAN_MTU | IFCAP_JUMBO_MTU | IFCAP_LRO)
189
190 /* Safe mode disables support for hardware checksums and TSO */
191 #define ICE_SAFE_CAPS \
192 (ICE_FULL_CAPS & ~(IFCAP_HWCSUM | IFCAP_TSO | \
193 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM))
194
195 #define ICE_CAPS(sc) \
196 (ice_is_bit_set(sc->feat_en, ICE_FEATURE_SAFE_MODE) ? ICE_SAFE_CAPS : ICE_FULL_CAPS)
197
198 /**
199 * ICE_NVM_ACCESS
200 * @brief Private ioctl command number for NVM access ioctls
201 *
202 * The ioctl command number used by NVM update for accessing the driver for
203 * NVM access commands.
204 */
205 #define ICE_NVM_ACCESS \
206 (((((((('E' << 4) + '1') << 4) + 'K') << 4) + 'G') << 4) | 5)
207
208 /**
209 * ICE_DEBUG_DUMP
210 * @brief Private ioctl command number for retrieving debug dump data
211 *
212 * The ioctl command number used by a userspace tool for accessing the driver for
213 * getting debug dump data from the firmware.
214 */
215 #define ICE_DEBUG_DUMP \
216 (((((((('E' << 4) + '1') << 4) + 'K') << 4) + 'G') << 4) | 6)
217
218 #define ICE_AQ_LEN 1023
219 #define ICE_MBXQ_LEN 512
220 #define ICE_SBQ_LEN 512
221
222 #define ICE_CTRLQ_WORK_LIMIT 256
223
224 #define ICE_DFLT_TRAFFIC_CLASS BIT(0)
225
226 /* wait up to 50 microseconds for queue state change */
227 #define ICE_Q_WAIT_RETRY_LIMIT 5
228
229 #define ICE_UP_TABLE_TRANSLATE(val, i) \
230 (((val) << ICE_AQ_VSI_UP_TABLE_UP##i##_S) & \
231 ICE_AQ_VSI_UP_TABLE_UP##i##_M)
232
233 /*
234 * For now, set this to the hardware maximum. Each function gets a smaller
235 * number assigned to it in hw->func_caps.guar_num_vsi, though there
236 * appears to be no guarantee that is the maximum number that a function
237 * can use.
238 */
239 #define ICE_MAX_VSI_AVAILABLE 768
240
241 /* Maximum size of a single frame (for Tx and Rx) */
242 #define ICE_MAX_FRAME_SIZE ICE_AQ_SET_MAC_FRAME_SIZE_MAX
243
244 /* Maximum MTU size */
245 #define ICE_MAX_MTU (ICE_MAX_FRAME_SIZE - \
246 ETHER_HDR_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN)
247
248 /*
249 * Hardware requires that TSO packets have an segment size of at least 64
250 * bytes. To avoid sending bad frames to the hardware, the driver forces the
251 * MSS for all TSO packets to have a segment size of at least 64 bytes.
252 *
253 * However, if the MTU is reduced below a certain size, then the resulting
254 * larger MSS can result in transmitting segmented frames with a packet size
255 * larger than the MTU.
256 *
257 * Avoid this by preventing the MTU from being lowered below this limit.
258 * Alternative solutions require changing the TCP stack to disable offloading
259 * the segmentation when the requested segment size goes below 64 bytes.
260 */
261 #define ICE_MIN_MTU 112
262
263 /*
264 * The default number of queues reserved for a VF is 4, according to the
265 * AVF Base Mode specification.
266 */
267 #define ICE_DEFAULT_VF_QUEUES 4
268
269 /*
270 * An invalid VSI number to indicate that mirroring should be disabled.
271 */
272 #define ICE_INVALID_MIRROR_VSI ((u16)-1)
273 /*
274 * The maximum number of RX queues allowed per TC in a VSI.
275 */
276 #define ICE_MAX_RXQS_PER_TC 256
277
278 /*
279 * There are three settings that can be updated independently or
280 * altogether: Link speed, FEC, and Flow Control. These macros allow
281 * the caller to specify which setting(s) to update.
282 */
283 #define ICE_APPLY_LS BIT(0)
284 #define ICE_APPLY_FEC BIT(1)
285 #define ICE_APPLY_FC BIT(2)
286 #define ICE_APPLY_LS_FEC (ICE_APPLY_LS | ICE_APPLY_FEC)
287 #define ICE_APPLY_LS_FC (ICE_APPLY_LS | ICE_APPLY_FC)
288 #define ICE_APPLY_FEC_FC (ICE_APPLY_FEC | ICE_APPLY_FC)
289 #define ICE_APPLY_LS_FEC_FC (ICE_APPLY_LS_FEC | ICE_APPLY_FC)
290
291 /*
292 * Mask of valid flags that can be used as an input for the
293 * advertise_speed sysctl.
294 */
295 #define ICE_SYSCTL_SPEEDS_VALID_RANGE 0xFFF
296
297 /**
298 * @enum ice_dyn_idx_t
299 * @brief Dynamic Control ITR indexes
300 *
301 * This enum matches hardware bits and is meant to be used by DYN_CTLN
302 * registers and QINT registers or more generally anywhere in the manual
303 * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any
304 * register but instead is a special value meaning "don't update" ITR0/1/2.
305 */
306 enum ice_dyn_idx_t {
307 ICE_IDX_ITR0 = 0,
308 ICE_IDX_ITR1 = 1,
309 ICE_IDX_ITR2 = 2,
310 ICE_ITR_NONE = 3 /* ITR_NONE must not be used as an index */
311 };
312
313 /* By convenction ITR0 is used for RX, and ITR1 is used for TX */
314 #define ICE_RX_ITR ICE_IDX_ITR0
315 #define ICE_TX_ITR ICE_IDX_ITR1
316
317 #define ICE_ITR_MAX 8160
318
319 /* Define the default Tx and Rx ITR as 50us (translates to ~20k int/sec max) */
320 #define ICE_DFLT_TX_ITR 50
321 #define ICE_DFLT_RX_ITR 50
322
323 /* RS FEC register values */
324 #define ICE_RS_FEC_REG_SHIFT 2
325 #define ICE_RS_FEC_RECV_ID_SHIFT 4
326 #define ICE_RS_FEC_CORR_LOW_REG_PORT0 (0x02 << ICE_RS_FEC_REG_SHIFT)
327 #define ICE_RS_FEC_CORR_HIGH_REG_PORT0 (0x03 << ICE_RS_FEC_REG_SHIFT)
328 #define ICE_RS_FEC_UNCORR_LOW_REG_PORT0 (0x04 << ICE_RS_FEC_REG_SHIFT)
329 #define ICE_RS_FEC_UNCORR_HIGH_REG_PORT0 (0x05 << ICE_RS_FEC_REG_SHIFT)
330 #define ICE_RS_FEC_CORR_LOW_REG_PORT1 (0x42 << ICE_RS_FEC_REG_SHIFT)
331 #define ICE_RS_FEC_CORR_HIGH_REG_PORT1 (0x43 << ICE_RS_FEC_REG_SHIFT)
332 #define ICE_RS_FEC_UNCORR_LOW_REG_PORT1 (0x44 << ICE_RS_FEC_REG_SHIFT)
333 #define ICE_RS_FEC_UNCORR_HIGH_REG_PORT1 (0x45 << ICE_RS_FEC_REG_SHIFT)
334 #define ICE_RS_FEC_CORR_LOW_REG_PORT2 (0x4A << ICE_RS_FEC_REG_SHIFT)
335 #define ICE_RS_FEC_CORR_HIGH_REG_PORT2 (0x4B << ICE_RS_FEC_REG_SHIFT)
336 #define ICE_RS_FEC_UNCORR_LOW_REG_PORT2 (0x4C << ICE_RS_FEC_REG_SHIFT)
337 #define ICE_RS_FEC_UNCORR_HIGH_REG_PORT2 (0x4D << ICE_RS_FEC_REG_SHIFT)
338 #define ICE_RS_FEC_CORR_LOW_REG_PORT3 (0x52 << ICE_RS_FEC_REG_SHIFT)
339 #define ICE_RS_FEC_CORR_HIGH_REG_PORT3 (0x53 << ICE_RS_FEC_REG_SHIFT)
340 #define ICE_RS_FEC_UNCORR_LOW_REG_PORT3 (0x54 << ICE_RS_FEC_REG_SHIFT)
341 #define ICE_RS_FEC_UNCORR_HIGH_REG_PORT3 (0x55 << ICE_RS_FEC_REG_SHIFT)
342 #define ICE_RS_FEC_RECEIVER_ID_PCS0 (0x33 << ICE_RS_FEC_RECV_ID_SHIFT)
343 #define ICE_RS_FEC_RECEIVER_ID_PCS1 (0x34 << ICE_RS_FEC_RECV_ID_SHIFT)
344
345 /**
346 * ice_itr_to_reg - Convert an ITR setting into its register equivalent
347 * @hw: The device HW structure
348 * @itr_setting: the ITR setting to convert
349 *
350 * Based on the hardware ITR granularity, convert an ITR setting into the
351 * correct value to prepare programming to the HW.
352 */
ice_itr_to_reg(struct ice_hw * hw,u16 itr_setting)353 static inline u16 ice_itr_to_reg(struct ice_hw *hw, u16 itr_setting)
354 {
355 return itr_setting / hw->itr_gran;
356 }
357
358 /**
359 * @enum ice_rx_dtype
360 * @brief DTYPE header split options
361 *
362 * This enum matches the Rx context bits to define whether header split is
363 * enabled or not.
364 */
365 enum ice_rx_dtype {
366 ICE_RX_DTYPE_NO_SPLIT = 0,
367 ICE_RX_DTYPE_HEADER_SPLIT = 1,
368 ICE_RX_DTYPE_SPLIT_ALWAYS = 2,
369 };
370
371 /* Strings used for displaying FEC mode
372 *
373 * Use ice_fec_str() to get these unless these need to be embedded in a
374 * string constant.
375 */
376 #define ICE_FEC_STRING_AUTO "Auto"
377 #define ICE_FEC_STRING_RS "RS-FEC"
378 #define ICE_FEC_STRING_BASER "FC-FEC/BASE-R"
379 #define ICE_FEC_STRING_NONE "None"
380 #define ICE_FEC_STRING_DIS_AUTO "Auto (w/ No-FEC)"
381
382 /* Strings used for displaying Flow Control mode
383 *
384 * Use ice_fc_str() to get these unless these need to be embedded in a
385 * string constant.
386 */
387 #define ICE_FC_STRING_FULL "Full"
388 #define ICE_FC_STRING_TX "Tx"
389 #define ICE_FC_STRING_RX "Rx"
390 #define ICE_FC_STRING_NONE "None"
391
392 /*
393 * The number of times the ice_handle_i2c_req function will retry reading
394 * I2C data via the Admin Queue before returning EBUSY.
395 */
396 #define ICE_I2C_MAX_RETRIES 10
397
398 /*
399 * The Get Link Status AQ command and other link commands can return
400 * EAGAIN, indicating that the FW Link Management engine is busy.
401 * Define the number of times that the driver should retry sending these
402 * commands and the amount of time it should wait between those retries
403 * (in milliseconds) here.
404 */
405 #define ICE_LINK_AQ_MAX_RETRIES 10
406 #define ICE_LINK_RETRY_DELAY 17
407
408 /*
409 * The Start LLDP Agent AQ command will fail if it's sent too soon after
410 * the LLDP agent is stopped. The period between the stop and start
411 * commands must currently be at least 2 seconds.
412 */
413 #define ICE_START_LLDP_RETRY_WAIT (2 * hz)
414
415 /*
416 * Only certain clusters are valid for certain devices for the FW debug dump
417 * functionality, so define masks of those here.
418 */
419 #define ICE_FW_DEBUG_DUMP_VALID_CLUSTER_MASK_E810 0x4001AF
420 #define ICE_FW_DEBUG_DUMP_VALID_CLUSTER_MASK_E830 0x1AF
421
422 struct ice_softc;
423
424 /**
425 * @enum ice_rx_cso_stat
426 * @brief software checksum offload statistics
427 *
428 * Enumeration of possible checksum offload statistics captured by software
429 * during the Rx path.
430 */
431 enum ice_rx_cso_stat {
432 ICE_CSO_STAT_RX_IP4_ERR,
433 ICE_CSO_STAT_RX_IP6_ERR,
434 ICE_CSO_STAT_RX_L3_ERR,
435 ICE_CSO_STAT_RX_TCP_ERR,
436 ICE_CSO_STAT_RX_UDP_ERR,
437 ICE_CSO_STAT_RX_SCTP_ERR,
438 ICE_CSO_STAT_RX_L4_ERR,
439 ICE_CSO_STAT_RX_COUNT
440 };
441
442 /**
443 * @enum ice_tx_cso_stat
444 * @brief software checksum offload statistics
445 *
446 * Enumeration of possible checksum offload statistics captured by software
447 * during the Tx path.
448 */
449 enum ice_tx_cso_stat {
450 ICE_CSO_STAT_TX_TCP,
451 ICE_CSO_STAT_TX_UDP,
452 ICE_CSO_STAT_TX_SCTP,
453 ICE_CSO_STAT_TX_IP4,
454 ICE_CSO_STAT_TX_IP6,
455 ICE_CSO_STAT_TX_L3_ERR,
456 ICE_CSO_STAT_TX_L4_ERR,
457 ICE_CSO_STAT_TX_COUNT
458 };
459
460 /**
461 * @struct tx_stats
462 * @brief software Tx statistics
463 *
464 * Contains software counted Tx statistics for a single queue
465 */
466 struct tx_stats {
467 /* Soft Stats */
468 u64 tx_bytes;
469 u64 tx_packets;
470 u64 mss_too_small;
471 u64 tso;
472 u64 cso[ICE_CSO_STAT_TX_COUNT];
473 };
474
475 /**
476 * @struct rx_stats
477 * @brief software Rx statistics
478 *
479 * Contains software counted Rx statistics for a single queue
480 */
481 struct rx_stats {
482 /* Soft Stats */
483 u64 rx_packets;
484 u64 rx_bytes;
485 u64 desc_errs;
486 u64 cso[ICE_CSO_STAT_RX_COUNT];
487 };
488
489 /**
490 * @struct ice_vsi_hw_stats
491 * @brief hardware statistics for a VSI
492 *
493 * Stores statistics that are generated by hardware for a VSI.
494 */
495 struct ice_vsi_hw_stats {
496 struct ice_eth_stats prev;
497 struct ice_eth_stats cur;
498 bool offsets_loaded;
499 };
500
501 /**
502 * @struct ice_pf_hw_stats
503 * @brief hardware statistics for a PF
504 *
505 * Stores statistics that are generated by hardware for each PF.
506 */
507 struct ice_pf_hw_stats {
508 struct ice_hw_port_stats prev;
509 struct ice_hw_port_stats cur;
510 bool offsets_loaded;
511 };
512
513 /**
514 * @struct ice_pf_sw_stats
515 * @brief software statistics for a PF
516 *
517 * Contains software generated statistics relevant to a PF.
518 */
519 struct ice_pf_sw_stats {
520 /* # of reset events handled, by type */
521 u32 corer_count;
522 u32 globr_count;
523 u32 empr_count;
524 u32 pfr_count;
525
526 /* # of detected MDD events for Tx and Rx */
527 u32 tx_mdd_count;
528 u32 rx_mdd_count;
529
530 u64 rx_roc_error; /* port oversize packet stats, error_cnt \
531 from GLV_REPC VSI register + RxOversize */
532 };
533
534 /**
535 * @struct ice_tc_info
536 * @brief Traffic class information for a VSI
537 *
538 * Stores traffic class information used in configuring
539 * a VSI.
540 */
541 struct ice_tc_info {
542 u16 qoffset; /* Offset in VSI queue space */
543 u16 qcount_tx; /* TX queues for this Traffic Class */
544 u16 qcount_rx; /* RX queues */
545 };
546
547 /**
548 * @struct ice_vsi
549 * @brief VSI structure
550 *
551 * Contains data relevant to a single VSI
552 */
553 struct ice_vsi {
554 /* back pointer to the softc */
555 struct ice_softc *sc;
556
557 bool dynamic; /* if true, dynamically allocated */
558
559 enum ice_vsi_type type; /* type of this VSI */
560 u16 idx; /* software index to sc->all_vsi[] */
561
562 u16 *tx_qmap; /* Tx VSI to PF queue mapping */
563 u16 *rx_qmap; /* Rx VSI to PF queue mapping */
564
565 enum ice_resmgr_alloc_type qmap_type;
566
567 struct ice_tx_queue *tx_queues; /* Tx queue array */
568 struct ice_rx_queue *rx_queues; /* Rx queue array */
569
570 int num_tx_queues;
571 int num_rx_queues;
572 int num_vectors;
573
574 int16_t rx_itr;
575 int16_t tx_itr;
576
577 /* RSS configuration */
578 u16 rss_table_size; /* HW RSS table size */
579 u8 rss_lut_type; /* Used to configure Get/Set RSS LUT AQ call */
580
581 int max_frame_size;
582 u16 mbuf_sz;
583
584 struct ice_aqc_vsi_props info;
585
586 /* DCB configuration */
587 u8 num_tcs; /* Total number of enabled TCs */
588 u16 tc_map; /* bitmap of enabled Traffic Classes */
589 /* Information for each traffic class */
590 struct ice_tc_info tc_info[ICE_MAX_TRAFFIC_CLASS];
591
592 /* context for per-VSI sysctls */
593 struct sysctl_ctx_list ctx;
594 struct sysctl_oid *vsi_node;
595
596 /* context for per-txq sysctls */
597 struct sysctl_ctx_list txqs_ctx;
598 struct sysctl_oid *txqs_node;
599
600 /* context for per-rxq sysctls */
601 struct sysctl_ctx_list rxqs_ctx;
602 struct sysctl_oid *rxqs_node;
603
604 /* VSI-level stats */
605 struct ice_vsi_hw_stats hw_stats;
606
607 /* VSI mirroring details */
608 u16 mirror_src_vsi;
609 u16 rule_mir_ingress;
610 u16 rule_mir_egress;
611 };
612
613 /**
614 * @struct ice_debug_dump_cmd
615 * @brief arguments/return value for debug dump ioctl
616 */
617 struct ice_debug_dump_cmd {
618 u32 offset; /* offset to read/write from table, in bytes */
619 u16 cluster_id; /* also used to get next cluster id */
620 u16 table_id;
621 u16 data_size; /* size of data field, in bytes */
622 u16 reserved1;
623 u32 reserved2;
624 u8 data[];
625 };
626
627 /**
628 * @struct ice_serdes_equalization
629 * @brief serdes equalization info
630 */
631 struct ice_serdes_equalization {
632 int rx_equalization_pre1;
633 int rx_equalization_pre2;
634 int rx_equalization_post1;
635 int rx_equalization_bflf;
636 int rx_equalization_bfhf;
637 int rx_equalization_drate;
638 int tx_equalization_pre1;
639 int tx_equalization_pre2;
640 int tx_equalization_pre3;
641 int tx_equalization_atten;
642 int tx_equalization_post1;
643 };
644
645 /**
646 * @struct ice_fec_stats_to_sysctl
647 * @brief FEC stats register value of port
648 */
649 struct ice_fec_stats_to_sysctl {
650 u16 fec_corr_cnt_low;
651 u16 fec_corr_cnt_high;
652 u16 fec_uncorr_cnt_low;
653 u16 fec_uncorr_cnt_high;
654 };
655
656 #define ICE_MAX_SERDES_LANE_COUNT 4
657
658 /**
659 * @struct ice_regdump_to_sysctl
660 * @brief PHY stats of port
661 */
662 struct ice_regdump_to_sysctl {
663 /* A multilane port can have max 4 serdes */
664 struct ice_serdes_equalization equalization[ICE_MAX_SERDES_LANE_COUNT];
665 struct ice_fec_stats_to_sysctl stats;
666 };
667
668 /**
669 * @struct ice_port_topology
670 * @brief Port topology from lport i.e. serdes mapping, pcsquad, macport, cage
671 */
672 struct ice_port_topology {
673 u16 pcs_port;
674 u16 primary_serdes_lane;
675 u16 serdes_lane_count;
676 u16 pcs_quad_select;
677 };
678
679 /**
680 * @enum ice_state
681 * @brief Driver state flags
682 *
683 * Used to indicate the status of various driver events. Intended to be
684 * modified only using atomic operations, so that we can use it even in places
685 * which aren't locked.
686 */
687 enum ice_state {
688 ICE_STATE_CONTROLQ_EVENT_PENDING,
689 ICE_STATE_VFLR_PENDING,
690 ICE_STATE_MDD_PENDING,
691 ICE_STATE_RESET_OICR_RECV,
692 ICE_STATE_RESET_PFR_REQ,
693 ICE_STATE_PREPARED_FOR_RESET,
694 ICE_STATE_SUBIF_NEEDS_REINIT,
695 ICE_STATE_RESET_FAILED,
696 ICE_STATE_DRIVER_INITIALIZED,
697 ICE_STATE_NO_MEDIA,
698 ICE_STATE_RECOVERY_MODE,
699 ICE_STATE_ROLLBACK_MODE,
700 ICE_STATE_LINK_STATUS_REPORTED,
701 ICE_STATE_ATTACHING,
702 ICE_STATE_DETACHING,
703 ICE_STATE_LINK_DEFAULT_OVERRIDE_PENDING,
704 ICE_STATE_LLDP_RX_FLTR_FROM_DRIVER,
705 ICE_STATE_MULTIPLE_TCS,
706 ICE_STATE_DO_FW_DEBUG_DUMP,
707 ICE_STATE_LINK_ACTIVE_ON_DOWN,
708 ICE_STATE_FIRST_INIT_LINK,
709 ICE_STATE_DO_CREATE_MIRR_INTFC,
710 ICE_STATE_DO_DESTROY_MIRR_INTFC,
711 ICE_STATE_PHY_FW_INIT_PENDING,
712 /* This entry must be last */
713 ICE_STATE_LAST,
714 };
715
716 /* Functions for setting and checking driver state. Note the functions take
717 * bit positions, not bitmasks. The atomic_testandset_32 and
718 * atomic_testandclear_32 operations require bit positions, while the
719 * atomic_set_32 and atomic_clear_32 require bitmasks. This can easily lead to
720 * programming error, so we provide wrapper functions to avoid this.
721 */
722
723 /**
724 * ice_set_state - Set the specified state
725 * @s: the state bitmap
726 * @bit: the state to set
727 *
728 * Atomically update the state bitmap with the specified bit set.
729 */
730 static inline void
ice_set_state(volatile u32 * s,enum ice_state bit)731 ice_set_state(volatile u32 *s, enum ice_state bit)
732 {
733 /* atomic_set_32 expects a bitmask */
734 atomic_set_32(s, BIT(bit));
735 }
736
737 /**
738 * ice_clear_state - Clear the specified state
739 * @s: the state bitmap
740 * @bit: the state to clear
741 *
742 * Atomically update the state bitmap with the specified bit cleared.
743 */
744 static inline void
ice_clear_state(volatile u32 * s,enum ice_state bit)745 ice_clear_state(volatile u32 *s, enum ice_state bit)
746 {
747 /* atomic_clear_32 expects a bitmask */
748 atomic_clear_32(s, BIT(bit));
749 }
750
751 /**
752 * ice_testandset_state - Test and set the specified state
753 * @s: the state bitmap
754 * @bit: the bit to test
755 *
756 * Atomically update the state bitmap, setting the specified bit. Returns the
757 * previous value of the bit.
758 */
759 static inline u32
ice_testandset_state(volatile u32 * s,enum ice_state bit)760 ice_testandset_state(volatile u32 *s, enum ice_state bit)
761 {
762 /* atomic_testandset_32 expects a bit position */
763 return atomic_testandset_32(s, bit);
764 }
765
766 /**
767 * ice_testandclear_state - Test and clear the specified state
768 * @s: the state bitmap
769 * @bit: the bit to test
770 *
771 * Atomically update the state bitmap, clearing the specified bit. Returns the
772 * previous value of the bit.
773 */
774 static inline u32
ice_testandclear_state(volatile u32 * s,enum ice_state bit)775 ice_testandclear_state(volatile u32 *s, enum ice_state bit)
776 {
777 /* atomic_testandclear_32 expects a bit position */
778 return atomic_testandclear_32(s, bit);
779 }
780
781 /**
782 * ice_test_state - Test the specified state
783 * @s: the state bitmap
784 * @bit: the bit to test
785 *
786 * Return true if the state is set, false otherwise. Use this only if the flow
787 * does not need to update the state. If you must update the state as well,
788 * prefer ice_testandset_state or ice_testandclear_state.
789 */
790 static inline u32
ice_test_state(volatile u32 * s,enum ice_state bit)791 ice_test_state(volatile u32 *s, enum ice_state bit)
792 {
793 return (*s & BIT(bit)) ? true : false;
794 }
795
796 /**
797 * @struct ice_str_buf
798 * @brief static length buffer for string returning
799 *
800 * Structure containing a fixed size string buffer, used to implement
801 * numeric->string conversion functions that may want to return non-constant
802 * strings.
803 *
804 * This allows returning a fixed size string that is generated by a conversion
805 * function, and then copied to the used location without needing to use an
806 * explicit local variable passed by reference.
807 */
808 struct ice_str_buf {
809 char str[ICE_STR_BUF_LEN];
810 };
811
812 struct ice_str_buf _ice_aq_str(enum ice_aq_err aq_err);
813 struct ice_str_buf _ice_status_str(int status);
814 struct ice_str_buf _ice_err_str(int err);
815 struct ice_str_buf _ice_fltr_flag_str(u16 flag);
816 struct ice_str_buf _ice_log_sev_str(u8 log_level);
817 struct ice_str_buf _ice_mdd_tx_tclan_str(u8 event);
818 struct ice_str_buf _ice_mdd_tx_pqm_str(u8 event);
819 struct ice_str_buf _ice_mdd_rx_str(u8 event);
820 struct ice_str_buf _ice_fw_lldp_status(u32 lldp_status);
821
822 #define ice_aq_str(err) _ice_aq_str(err).str
823 #define ice_status_str(err) _ice_status_str(err).str
824 #define ice_err_str(err) _ice_err_str(err).str
825 #define ice_fltr_flag_str(flag) _ice_fltr_flag_str(flag).str
826
827 #define ice_mdd_tx_tclan_str(event) _ice_mdd_tx_tclan_str(event).str
828 #define ice_mdd_tx_pqm_str(event) _ice_mdd_tx_pqm_str(event).str
829 #define ice_mdd_rx_str(event) _ice_mdd_rx_str(event).str
830
831 #define ice_log_sev_str(log_level) _ice_log_sev_str(log_level).str
832 #define ice_fw_lldp_status(lldp_status) _ice_fw_lldp_status(lldp_status).str
833
834 /**
835 * ice_enable_intr - Enable interrupts for given vector
836 * @hw: the device private HW structure
837 * @vector: the interrupt index in PF space
838 *
839 * In MSI or Legacy interrupt mode, interrupt 0 is the only valid index.
840 */
841 static inline void
ice_enable_intr(struct ice_hw * hw,int vector)842 ice_enable_intr(struct ice_hw *hw, int vector)
843 {
844 u32 dyn_ctl;
845
846 /* Use ITR_NONE so that ITR configuration is not changed. */
847 dyn_ctl = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
848 (ICE_ITR_NONE << GLINT_DYN_CTL_ITR_INDX_S);
849 wr32(hw, GLINT_DYN_CTL(vector), dyn_ctl);
850 }
851
852 /**
853 * ice_disable_intr - Disable interrupts for given vector
854 * @hw: the device private HW structure
855 * @vector: the interrupt index in PF space
856 *
857 * In MSI or Legacy interrupt mode, interrupt 0 is the only valid index.
858 */
859 static inline void
ice_disable_intr(struct ice_hw * hw,int vector)860 ice_disable_intr(struct ice_hw *hw, int vector)
861 {
862 u32 dyn_ctl;
863
864 /* Use ITR_NONE so that ITR configuration is not changed. */
865 dyn_ctl = ICE_ITR_NONE << GLINT_DYN_CTL_ITR_INDX_S;
866 wr32(hw, GLINT_DYN_CTL(vector), dyn_ctl);
867 }
868
869 /**
870 * ice_is_tx_desc_done - determine if a Tx descriptor is done
871 * @txd: the Tx descriptor to check
872 *
873 * Returns true if hardware is done with a Tx descriptor and software is
874 * capable of re-using it.
875 */
876 static inline bool
ice_is_tx_desc_done(struct ice_tx_desc * txd)877 ice_is_tx_desc_done(struct ice_tx_desc *txd)
878 {
879 return (((txd->cmd_type_offset_bsz & ICE_TXD_QW1_DTYPE_M)
880 >> ICE_TXD_QW1_DTYPE_S) == ICE_TX_DESC_DTYPE_DESC_DONE);
881 }
882
883 /**
884 * ice_get_pf_id - Get the PF id from the hardware registers
885 * @hw: the ice hardware structure
886 *
887 * Reads the PF_FUNC_RID register and extracts the function number from it.
888 * Intended to be used in cases where hw->pf_id hasn't yet been assigned by
889 * ice_init_hw.
890 *
891 * @pre this function should be called only after PCI register access has been
892 * setup, and prior to ice_init_hw. After hardware has been initialized, the
893 * cached hw->pf_id value can be used.
894 */
895 static inline u8
ice_get_pf_id(struct ice_hw * hw)896 ice_get_pf_id(struct ice_hw *hw)
897 {
898 return (u8)((rd32(hw, PF_FUNC_RID) & PF_FUNC_RID_FUNCTION_NUMBER_M) >>
899 PF_FUNC_RID_FUNCTION_NUMBER_S);
900 }
901
902 /* Details of how to re-initialize depend on the networking stack */
903 void ice_request_stack_reinit(struct ice_softc *sc);
904
905 /* Details of how to check if the network stack is detaching us */
906 bool ice_driver_is_detaching(struct ice_softc *sc);
907
908 /* Details of how to setup/teardown a mirror interface */
909 /**
910 * @brief Create an interface for mirroring
911 */
912 int ice_create_mirror_interface(struct ice_softc *sc);
913 /**
914 * @brief Destroy created mirroring interface
915 */
916 void ice_destroy_mirror_interface(struct ice_softc *sc);
917
918 const char * ice_fw_module_str(enum ice_aqc_fw_logging_mod module);
919 void ice_add_fw_logging_tunables(struct ice_softc *sc,
920 struct sysctl_oid *parent);
921 void ice_handle_fw_log_event(struct ice_softc *sc, struct ice_aq_desc *desc,
922 void *buf);
923
924 int ice_process_ctrlq(struct ice_softc *sc, enum ice_ctl_q q_type, u16 *pending);
925 int ice_map_bar(device_t dev, struct ice_bar_info *bar, int bar_num);
926 void ice_free_bar(device_t dev, struct ice_bar_info *bar);
927 void ice_set_ctrlq_len(struct ice_hw *hw);
928 void ice_release_vsi(struct ice_vsi *vsi);
929 struct ice_vsi *ice_alloc_vsi(struct ice_softc *sc, enum ice_vsi_type type);
930 void ice_alloc_vsi_qmap(struct ice_vsi *vsi, const int max_tx_queues,
931 const int max_rx_queues);
932 void ice_free_vsi_qmaps(struct ice_vsi *vsi);
933 int ice_initialize_vsi(struct ice_vsi *vsi);
934 void ice_deinit_vsi(struct ice_vsi *vsi);
935 uint64_t ice_aq_speed_to_rate(struct ice_port_info *pi);
936 int ice_get_phy_type_low(uint64_t phy_type_low);
937 int ice_get_phy_type_high(uint64_t phy_type_high);
938 int ice_add_media_types(struct ice_softc *sc, struct ifmedia *media);
939 void ice_configure_rxq_interrupt(struct ice_hw *hw, u16 rxqid, u16 vector, u8 itr_idx);
940 void ice_configure_all_rxq_interrupts(struct ice_vsi *vsi);
941 void ice_configure_txq_interrupt(struct ice_hw *hw, u16 txqid, u16 vector, u8 itr_idx);
942 void ice_configure_all_txq_interrupts(struct ice_vsi *vsi);
943 void ice_flush_rxq_interrupts(struct ice_vsi *vsi);
944 void ice_flush_txq_interrupts(struct ice_vsi *vsi);
945 int ice_cfg_vsi_for_tx(struct ice_vsi *vsi);
946 int ice_cfg_vsi_for_rx(struct ice_vsi *vsi);
947 int ice_control_rx_queue(struct ice_vsi *vsi, u16 qidx, bool enable);
948 int ice_control_all_rx_queues(struct ice_vsi *vsi, bool enable);
949 int ice_cfg_pf_default_mac_filters(struct ice_softc *sc);
950 int ice_rm_pf_default_mac_filters(struct ice_softc *sc);
951 void ice_print_nvm_version(struct ice_softc *sc);
952 void ice_update_vsi_hw_stats(struct ice_vsi *vsi);
953 void ice_reset_vsi_stats(struct ice_vsi *vsi);
954 void ice_update_pf_stats(struct ice_softc *sc);
955 void ice_reset_pf_stats(struct ice_softc *sc);
956 void ice_add_device_sysctls(struct ice_softc *sc);
957 void ice_log_hmc_error(struct ice_hw *hw, device_t dev);
958 void ice_add_sysctls_eth_stats(struct sysctl_ctx_list *ctx,
959 struct sysctl_oid *parent,
960 struct ice_eth_stats *stats);
961 void ice_add_vsi_sysctls(struct ice_vsi *vsi);
962 void ice_add_sysctls_mac_stats(struct sysctl_ctx_list *ctx,
963 struct sysctl_oid *parent,
964 struct ice_softc *sc);
965 void ice_configure_misc_interrupts(struct ice_softc *sc);
966 int ice_sync_multicast_filters(struct ice_softc *sc);
967 int ice_add_vlan_hw_filters(struct ice_vsi *vsi, u16 *vid,
968 u16 length);
969 int ice_add_vlan_hw_filter(struct ice_vsi *vsi, u16 vid);
970 int ice_remove_vlan_hw_filters(struct ice_vsi *vsi, u16 *vid,
971 u16 length);
972 int ice_remove_vlan_hw_filter(struct ice_vsi *vsi, u16 vid);
973 void ice_add_vsi_tunables(struct ice_vsi *vsi, struct sysctl_oid *parent);
974 void ice_del_vsi_sysctl_ctx(struct ice_vsi *vsi);
975 void ice_add_device_tunables(struct ice_softc *sc);
976 int ice_add_vsi_mac_filter(struct ice_vsi *vsi, const u8 *addr);
977 int ice_remove_vsi_mac_filter(struct ice_vsi *vsi, const u8 *addr);
978 int ice_vsi_disable_tx(struct ice_vsi *vsi);
979 void ice_vsi_add_txqs_ctx(struct ice_vsi *vsi);
980 void ice_vsi_add_rxqs_ctx(struct ice_vsi *vsi);
981 void ice_vsi_del_txqs_ctx(struct ice_vsi *vsi);
982 void ice_vsi_del_rxqs_ctx(struct ice_vsi *vsi);
983 void ice_add_txq_sysctls(struct ice_tx_queue *txq);
984 void ice_add_rxq_sysctls(struct ice_rx_queue *rxq);
985 int ice_config_rss(struct ice_vsi *vsi);
986 void ice_clean_all_vsi_rss_cfg(struct ice_softc *sc);
987 int ice_load_pkg_file(struct ice_softc *sc);
988 void ice_log_pkg_init(struct ice_softc *sc, enum ice_ddp_state pkg_status);
989 uint64_t ice_get_ifnet_counter(struct ice_vsi *vsi, ift_counter counter);
990 void ice_save_pci_info(struct ice_hw *hw, device_t dev);
991 int ice_replay_all_vsi_cfg(struct ice_softc *sc);
992 void ice_link_up_msg(struct ice_softc *sc);
993 int ice_update_laa_mac(struct ice_softc *sc);
994 void ice_get_and_print_bus_info(struct ice_softc *sc);
995 const char *ice_fec_str(enum ice_fec_mode mode);
996 const char *ice_fc_str(enum ice_fc_mode mode);
997 const char *ice_fwd_act_str(enum ice_sw_fwd_act_type action);
998 const char *ice_state_to_str(enum ice_state state);
999 int ice_init_link_events(struct ice_softc *sc);
1000 void ice_configure_rx_itr(struct ice_vsi *vsi);
1001 void ice_configure_tx_itr(struct ice_vsi *vsi);
1002 void ice_setup_pf_vsi(struct ice_softc *sc);
1003 void ice_handle_mdd_event(struct ice_softc *sc);
1004 void ice_init_dcb_setup(struct ice_softc *sc);
1005 int ice_send_version(struct ice_softc *sc);
1006 int ice_cfg_pf_ethertype_filters(struct ice_softc *sc);
1007 void ice_init_link_configuration(struct ice_softc *sc);
1008 void ice_init_saved_phy_cfg(struct ice_softc *sc);
1009 int ice_apply_saved_phy_cfg(struct ice_softc *sc, u8 settings);
1010 void ice_set_link_management_mode(struct ice_softc *sc);
1011 int ice_module_event_handler(module_t mod, int what, void *arg);
1012 int ice_handle_nvm_access_ioctl(struct ice_softc *sc, struct ifdrv *ifd);
1013 int ice_handle_i2c_req(struct ice_softc *sc, struct ifi2creq *req);
1014 int ice_read_sff_eeprom(struct ice_softc *sc, u16 dev_addr, u16 offset, u8* data, u16 length);
1015 int ice_alloc_intr_tracking(struct ice_softc *sc);
1016 void ice_free_intr_tracking(struct ice_softc *sc);
1017 void ice_set_default_local_lldp_mib(struct ice_softc *sc);
1018 void ice_set_link(struct ice_softc *sc, bool enabled);
1019 void ice_add_rx_lldp_filter(struct ice_softc *sc);
1020 void ice_init_health_events(struct ice_softc *sc);
1021 void ice_cfg_pba_num(struct ice_softc *sc);
1022 int ice_handle_debug_dump_ioctl(struct ice_softc *sc, struct ifdrv *ifd);
1023 u8 ice_dcb_get_tc_map(const struct ice_dcbx_cfg *dcbcfg);
1024 void ice_do_dcb_reconfig(struct ice_softc *sc, bool pending_mib);
1025 int ice_setup_vsi_mirroring(struct ice_vsi *vsi);
1026
1027 #endif /* _ICE_LIB_H_ */
1028