1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2003 Stuart Walsh<[email protected]>
5 * and Duncan Barclay<[email protected]>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33 #include <sys/endian.h>
34 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/mbuf.h>
37 #include <sys/module.h>
38 #include <sys/rman.h>
39 #include <sys/socket.h>
40 #include <sys/sockio.h>
41 #include <sys/sysctl.h>
42
43 #include <net/bpf.h>
44 #include <net/if.h>
45 #include <net/if_var.h>
46 #include <net/ethernet.h>
47 #include <net/if_dl.h>
48 #include <net/if_media.h>
49 #include <net/if_types.h>
50 #include <net/if_vlan_var.h>
51
52 #include <dev/mii/mii.h>
53 #include <dev/mii/miivar.h>
54
55 #include <dev/pci/pcireg.h>
56 #include <dev/pci/pcivar.h>
57
58 #include <machine/bus.h>
59
60 #include <dev/bfe/if_bfereg.h>
61
62 MODULE_DEPEND(bfe, pci, 1, 1, 1);
63 MODULE_DEPEND(bfe, ether, 1, 1, 1);
64 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
65
66 /* "device miibus" required. See GENERIC if you get errors here. */
67 #include "miibus_if.h"
68
69 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */
70
71 static struct bfe_type bfe_devs[] = {
72 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401,
73 "Broadcom BCM4401 Fast Ethernet" },
74 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0,
75 "Broadcom BCM4401-B0 Fast Ethernet" },
76 { 0, 0, NULL }
77 };
78
79 static int bfe_probe (device_t);
80 static int bfe_attach (device_t);
81 static int bfe_detach (device_t);
82 static int bfe_suspend (device_t);
83 static int bfe_resume (device_t);
84 static void bfe_release_resources (struct bfe_softc *);
85 static void bfe_intr (void *);
86 static int bfe_encap (struct bfe_softc *, struct mbuf **);
87 static void bfe_start (if_t);
88 static void bfe_start_locked (if_t);
89 static int bfe_ioctl (if_t, u_long, caddr_t);
90 static void bfe_init (void *);
91 static void bfe_init_locked (void *);
92 static void bfe_stop (struct bfe_softc *);
93 static void bfe_watchdog (struct bfe_softc *);
94 static int bfe_shutdown (device_t);
95 static void bfe_tick (void *);
96 static void bfe_txeof (struct bfe_softc *);
97 static void bfe_rxeof (struct bfe_softc *);
98 static void bfe_set_rx_mode (struct bfe_softc *);
99 static int bfe_list_rx_init (struct bfe_softc *);
100 static void bfe_list_tx_init (struct bfe_softc *);
101 static void bfe_discard_buf (struct bfe_softc *, int);
102 static int bfe_list_newbuf (struct bfe_softc *, int);
103 static void bfe_rx_ring_free (struct bfe_softc *);
104
105 static void bfe_pci_setup (struct bfe_softc *, u_int32_t);
106 static int bfe_ifmedia_upd (if_t);
107 static void bfe_ifmedia_sts (if_t, struct ifmediareq *);
108 static int bfe_miibus_readreg (device_t, int, int);
109 static int bfe_miibus_writereg (device_t, int, int, int);
110 static void bfe_miibus_statchg (device_t);
111 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t,
112 u_long, const int);
113 static void bfe_get_config (struct bfe_softc *sc);
114 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *);
115 static void bfe_stats_update (struct bfe_softc *);
116 static void bfe_clear_stats (struct bfe_softc *);
117 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*);
118 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t);
119 static int bfe_resetphy (struct bfe_softc *);
120 static int bfe_setupphy (struct bfe_softc *);
121 static void bfe_chip_reset (struct bfe_softc *);
122 static void bfe_chip_halt (struct bfe_softc *);
123 static void bfe_core_reset (struct bfe_softc *);
124 static void bfe_core_disable (struct bfe_softc *);
125 static int bfe_dma_alloc (struct bfe_softc *);
126 static void bfe_dma_free (struct bfe_softc *sc);
127 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int);
128 static void bfe_cam_write (struct bfe_softc *, u_char *, int);
129 static int sysctl_bfe_stats (SYSCTL_HANDLER_ARGS);
130
131 static device_method_t bfe_methods[] = {
132 /* Device interface */
133 DEVMETHOD(device_probe, bfe_probe),
134 DEVMETHOD(device_attach, bfe_attach),
135 DEVMETHOD(device_detach, bfe_detach),
136 DEVMETHOD(device_shutdown, bfe_shutdown),
137 DEVMETHOD(device_suspend, bfe_suspend),
138 DEVMETHOD(device_resume, bfe_resume),
139
140 /* MII interface */
141 DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
142 DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
143 DEVMETHOD(miibus_statchg, bfe_miibus_statchg),
144
145 DEVMETHOD_END
146 };
147
148 static driver_t bfe_driver = {
149 "bfe",
150 bfe_methods,
151 sizeof(struct bfe_softc)
152 };
153
154 DRIVER_MODULE(bfe, pci, bfe_driver, 0, 0);
155 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, bfe, bfe_devs,
156 nitems(bfe_devs) - 1);
157 DRIVER_MODULE(miibus, bfe, miibus_driver, 0, 0);
158
159 /*
160 * Probe for a Broadcom 4401 chip.
161 */
162 static int
bfe_probe(device_t dev)163 bfe_probe(device_t dev)
164 {
165 struct bfe_type *t;
166
167 t = bfe_devs;
168
169 while (t->bfe_name != NULL) {
170 if (pci_get_vendor(dev) == t->bfe_vid &&
171 pci_get_device(dev) == t->bfe_did) {
172 device_set_desc(dev, t->bfe_name);
173 return (BUS_PROBE_DEFAULT);
174 }
175 t++;
176 }
177
178 return (ENXIO);
179 }
180
181 struct bfe_dmamap_arg {
182 bus_addr_t bfe_busaddr;
183 };
184
185 static int
bfe_dma_alloc(struct bfe_softc * sc)186 bfe_dma_alloc(struct bfe_softc *sc)
187 {
188 struct bfe_dmamap_arg ctx;
189 struct bfe_rx_data *rd;
190 struct bfe_tx_data *td;
191 int error, i;
192
193 /*
194 * parent tag. Apparently the chip cannot handle any DMA address
195 * greater than 1GB.
196 */
197 error = bus_dma_tag_create(bus_get_dma_tag(sc->bfe_dev), /* parent */
198 1, 0, /* alignment, boundary */
199 BFE_DMA_MAXADDR, /* lowaddr */
200 BUS_SPACE_MAXADDR, /* highaddr */
201 NULL, NULL, /* filter, filterarg */
202 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
203 0, /* nsegments */
204 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
205 0, /* flags */
206 NULL, NULL, /* lockfunc, lockarg */
207 &sc->bfe_parent_tag);
208 if (error != 0) {
209 device_printf(sc->bfe_dev, "cannot create parent DMA tag.\n");
210 goto fail;
211 }
212
213 /* Create tag for Tx ring. */
214 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
215 BFE_TX_RING_ALIGN, 0, /* alignment, boundary */
216 BUS_SPACE_MAXADDR, /* lowaddr */
217 BUS_SPACE_MAXADDR, /* highaddr */
218 NULL, NULL, /* filter, filterarg */
219 BFE_TX_LIST_SIZE, /* maxsize */
220 1, /* nsegments */
221 BFE_TX_LIST_SIZE, /* maxsegsize */
222 0, /* flags */
223 NULL, NULL, /* lockfunc, lockarg */
224 &sc->bfe_tx_tag);
225 if (error != 0) {
226 device_printf(sc->bfe_dev, "cannot create Tx ring DMA tag.\n");
227 goto fail;
228 }
229
230 /* Create tag for Rx ring. */
231 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
232 BFE_RX_RING_ALIGN, 0, /* alignment, boundary */
233 BUS_SPACE_MAXADDR, /* lowaddr */
234 BUS_SPACE_MAXADDR, /* highaddr */
235 NULL, NULL, /* filter, filterarg */
236 BFE_RX_LIST_SIZE, /* maxsize */
237 1, /* nsegments */
238 BFE_RX_LIST_SIZE, /* maxsegsize */
239 0, /* flags */
240 NULL, NULL, /* lockfunc, lockarg */
241 &sc->bfe_rx_tag);
242 if (error != 0) {
243 device_printf(sc->bfe_dev, "cannot create Rx ring DMA tag.\n");
244 goto fail;
245 }
246
247 /* Create tag for Tx buffers. */
248 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
249 1, 0, /* alignment, boundary */
250 BUS_SPACE_MAXADDR, /* lowaddr */
251 BUS_SPACE_MAXADDR, /* highaddr */
252 NULL, NULL, /* filter, filterarg */
253 MCLBYTES * BFE_MAXTXSEGS, /* maxsize */
254 BFE_MAXTXSEGS, /* nsegments */
255 MCLBYTES, /* maxsegsize */
256 0, /* flags */
257 NULL, NULL, /* lockfunc, lockarg */
258 &sc->bfe_txmbuf_tag);
259 if (error != 0) {
260 device_printf(sc->bfe_dev,
261 "cannot create Tx buffer DMA tag.\n");
262 goto fail;
263 }
264
265 /* Create tag for Rx buffers. */
266 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
267 1, 0, /* alignment, boundary */
268 BUS_SPACE_MAXADDR, /* lowaddr */
269 BUS_SPACE_MAXADDR, /* highaddr */
270 NULL, NULL, /* filter, filterarg */
271 MCLBYTES, /* maxsize */
272 1, /* nsegments */
273 MCLBYTES, /* maxsegsize */
274 0, /* flags */
275 NULL, NULL, /* lockfunc, lockarg */
276 &sc->bfe_rxmbuf_tag);
277 if (error != 0) {
278 device_printf(sc->bfe_dev,
279 "cannot create Rx buffer DMA tag.\n");
280 goto fail;
281 }
282
283 /* Allocate DMA'able memory and load DMA map. */
284 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
285 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_tx_map);
286 if (error != 0) {
287 device_printf(sc->bfe_dev,
288 "cannot allocate DMA'able memory for Tx ring.\n");
289 goto fail;
290 }
291 ctx.bfe_busaddr = 0;
292 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
293 sc->bfe_tx_list, BFE_TX_LIST_SIZE, bfe_dma_map, &ctx,
294 BUS_DMA_NOWAIT);
295 if (error != 0 || ctx.bfe_busaddr == 0) {
296 device_printf(sc->bfe_dev,
297 "cannot load DMA'able memory for Tx ring.\n");
298 goto fail;
299 }
300 sc->bfe_tx_dma = BFE_ADDR_LO(ctx.bfe_busaddr);
301
302 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
303 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_rx_map);
304 if (error != 0) {
305 device_printf(sc->bfe_dev,
306 "cannot allocate DMA'able memory for Rx ring.\n");
307 goto fail;
308 }
309 ctx.bfe_busaddr = 0;
310 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
311 sc->bfe_rx_list, BFE_RX_LIST_SIZE, bfe_dma_map, &ctx,
312 BUS_DMA_NOWAIT);
313 if (error != 0 || ctx.bfe_busaddr == 0) {
314 device_printf(sc->bfe_dev,
315 "cannot load DMA'able memory for Rx ring.\n");
316 goto fail;
317 }
318 sc->bfe_rx_dma = BFE_ADDR_LO(ctx.bfe_busaddr);
319
320 /* Create DMA maps for Tx buffers. */
321 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
322 td = &sc->bfe_tx_ring[i];
323 td->bfe_mbuf = NULL;
324 td->bfe_map = NULL;
325 error = bus_dmamap_create(sc->bfe_txmbuf_tag, 0, &td->bfe_map);
326 if (error != 0) {
327 device_printf(sc->bfe_dev,
328 "cannot create DMA map for Tx.\n");
329 goto fail;
330 }
331 }
332
333 /* Create spare DMA map for Rx buffers. */
334 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &sc->bfe_rx_sparemap);
335 if (error != 0) {
336 device_printf(sc->bfe_dev, "cannot create spare DMA map for Rx.\n");
337 goto fail;
338 }
339 /* Create DMA maps for Rx buffers. */
340 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
341 rd = &sc->bfe_rx_ring[i];
342 rd->bfe_mbuf = NULL;
343 rd->bfe_map = NULL;
344 rd->bfe_ctrl = 0;
345 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &rd->bfe_map);
346 if (error != 0) {
347 device_printf(sc->bfe_dev,
348 "cannot create DMA map for Rx.\n");
349 goto fail;
350 }
351 }
352
353 fail:
354 return (error);
355 }
356
357 static void
bfe_dma_free(struct bfe_softc * sc)358 bfe_dma_free(struct bfe_softc *sc)
359 {
360 struct bfe_tx_data *td;
361 struct bfe_rx_data *rd;
362 int i;
363
364 /* Tx ring. */
365 if (sc->bfe_tx_tag != NULL) {
366 if (sc->bfe_tx_dma != 0)
367 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
368 if (sc->bfe_tx_list != NULL)
369 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list,
370 sc->bfe_tx_map);
371 sc->bfe_tx_dma = 0;
372 sc->bfe_tx_list = NULL;
373 bus_dma_tag_destroy(sc->bfe_tx_tag);
374 sc->bfe_tx_tag = NULL;
375 }
376
377 /* Rx ring. */
378 if (sc->bfe_rx_tag != NULL) {
379 if (sc->bfe_rx_dma != 0)
380 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
381 if (sc->bfe_rx_list != NULL)
382 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list,
383 sc->bfe_rx_map);
384 sc->bfe_rx_dma = 0;
385 sc->bfe_rx_list = NULL;
386 bus_dma_tag_destroy(sc->bfe_rx_tag);
387 sc->bfe_rx_tag = NULL;
388 }
389
390 /* Tx buffers. */
391 if (sc->bfe_txmbuf_tag != NULL) {
392 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
393 td = &sc->bfe_tx_ring[i];
394 if (td->bfe_map != NULL) {
395 bus_dmamap_destroy(sc->bfe_txmbuf_tag,
396 td->bfe_map);
397 td->bfe_map = NULL;
398 }
399 }
400 bus_dma_tag_destroy(sc->bfe_txmbuf_tag);
401 sc->bfe_txmbuf_tag = NULL;
402 }
403
404 /* Rx buffers. */
405 if (sc->bfe_rxmbuf_tag != NULL) {
406 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
407 rd = &sc->bfe_rx_ring[i];
408 if (rd->bfe_map != NULL) {
409 bus_dmamap_destroy(sc->bfe_rxmbuf_tag,
410 rd->bfe_map);
411 rd->bfe_map = NULL;
412 }
413 }
414 if (sc->bfe_rx_sparemap != NULL) {
415 bus_dmamap_destroy(sc->bfe_rxmbuf_tag,
416 sc->bfe_rx_sparemap);
417 sc->bfe_rx_sparemap = NULL;
418 }
419 bus_dma_tag_destroy(sc->bfe_rxmbuf_tag);
420 sc->bfe_rxmbuf_tag = NULL;
421 }
422
423 if (sc->bfe_parent_tag != NULL) {
424 bus_dma_tag_destroy(sc->bfe_parent_tag);
425 sc->bfe_parent_tag = NULL;
426 }
427 }
428
429 static int
bfe_attach(device_t dev)430 bfe_attach(device_t dev)
431 {
432 if_t ifp = NULL;
433 struct bfe_softc *sc;
434 int error = 0, rid;
435
436 sc = device_get_softc(dev);
437 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
438 MTX_DEF);
439 callout_init_mtx(&sc->bfe_stat_co, &sc->bfe_mtx, 0);
440
441 sc->bfe_dev = dev;
442
443 /*
444 * Map control/status registers.
445 */
446 pci_enable_busmaster(dev);
447
448 rid = PCIR_BAR(0);
449 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
450 RF_ACTIVE);
451 if (sc->bfe_res == NULL) {
452 device_printf(dev, "couldn't map memory\n");
453 error = ENXIO;
454 goto fail;
455 }
456
457 /* Allocate interrupt */
458 rid = 0;
459
460 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
461 RF_SHAREABLE | RF_ACTIVE);
462 if (sc->bfe_irq == NULL) {
463 device_printf(dev, "couldn't map interrupt\n");
464 error = ENXIO;
465 goto fail;
466 }
467
468 if (bfe_dma_alloc(sc) != 0) {
469 device_printf(dev, "failed to allocate DMA resources\n");
470 error = ENXIO;
471 goto fail;
472 }
473
474 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
475 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
476 "stats", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
477 sysctl_bfe_stats, "I", "Statistics");
478
479 /* Set up ifnet structure */
480 ifp = sc->bfe_ifp = if_alloc(IFT_ETHER);
481 if_setsoftc(ifp, sc);
482 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
483 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
484 if_setioctlfn(ifp, bfe_ioctl);
485 if_setstartfn(ifp, bfe_start);
486 if_setinitfn(ifp, bfe_init);
487 if_setsendqlen(ifp, BFE_TX_QLEN);
488 if_setsendqready(ifp);
489
490 bfe_get_config(sc);
491
492 /* Reset the chip and turn on the PHY */
493 BFE_LOCK(sc);
494 bfe_chip_reset(sc);
495 BFE_UNLOCK(sc);
496
497 error = mii_attach(dev, &sc->bfe_miibus, ifp, bfe_ifmedia_upd,
498 bfe_ifmedia_sts, BMSR_DEFCAPMASK, sc->bfe_phyaddr, MII_OFFSET_ANY,
499 0);
500 if (error != 0) {
501 device_printf(dev, "attaching PHYs failed\n");
502 goto fail;
503 }
504
505 ether_ifattach(ifp, sc->bfe_enaddr);
506
507 /*
508 * Tell the upper layer(s) we support long frames.
509 */
510 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
511 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
512 if_setcapenablebit(ifp, IFCAP_VLAN_MTU, 0);
513
514 /*
515 * Hook interrupt last to avoid having to lock softc
516 */
517 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE,
518 NULL, bfe_intr, sc, &sc->bfe_intrhand);
519
520 if (error) {
521 device_printf(dev, "couldn't set up irq\n");
522 goto fail;
523 }
524 fail:
525 if (error != 0)
526 bfe_detach(dev);
527 return (error);
528 }
529
530 static int
bfe_detach(device_t dev)531 bfe_detach(device_t dev)
532 {
533 struct bfe_softc *sc;
534 if_t ifp;
535
536 sc = device_get_softc(dev);
537
538 ifp = sc->bfe_ifp;
539
540 if (device_is_attached(dev)) {
541 BFE_LOCK(sc);
542 sc->bfe_flags |= BFE_FLAG_DETACH;
543 bfe_stop(sc);
544 BFE_UNLOCK(sc);
545 callout_drain(&sc->bfe_stat_co);
546 if (ifp != NULL)
547 ether_ifdetach(ifp);
548 }
549
550 BFE_LOCK(sc);
551 bfe_chip_reset(sc);
552 BFE_UNLOCK(sc);
553
554 bus_generic_detach(dev);
555 if (sc->bfe_miibus != NULL)
556 device_delete_child(dev, sc->bfe_miibus);
557
558 bfe_release_resources(sc);
559 bfe_dma_free(sc);
560 mtx_destroy(&sc->bfe_mtx);
561
562 return (0);
563 }
564
565 /*
566 * Stop all chip I/O so that the kernel's probe routines don't
567 * get confused by errant DMAs when rebooting.
568 */
569 static int
bfe_shutdown(device_t dev)570 bfe_shutdown(device_t dev)
571 {
572 struct bfe_softc *sc;
573
574 sc = device_get_softc(dev);
575 BFE_LOCK(sc);
576 bfe_stop(sc);
577
578 BFE_UNLOCK(sc);
579
580 return (0);
581 }
582
583 static int
bfe_suspend(device_t dev)584 bfe_suspend(device_t dev)
585 {
586 struct bfe_softc *sc;
587
588 sc = device_get_softc(dev);
589 BFE_LOCK(sc);
590 bfe_stop(sc);
591 BFE_UNLOCK(sc);
592
593 return (0);
594 }
595
596 static int
bfe_resume(device_t dev)597 bfe_resume(device_t dev)
598 {
599 struct bfe_softc *sc;
600 if_t ifp;
601
602 sc = device_get_softc(dev);
603 ifp = sc->bfe_ifp;
604 BFE_LOCK(sc);
605 bfe_chip_reset(sc);
606 if (if_getflags(ifp) & IFF_UP) {
607 bfe_init_locked(sc);
608 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
609 !if_sendq_empty(ifp))
610 bfe_start_locked(ifp);
611 }
612 BFE_UNLOCK(sc);
613
614 return (0);
615 }
616
617 static int
bfe_miibus_readreg(device_t dev,int phy,int reg)618 bfe_miibus_readreg(device_t dev, int phy, int reg)
619 {
620 struct bfe_softc *sc;
621 u_int32_t ret;
622
623 sc = device_get_softc(dev);
624 bfe_readphy(sc, reg, &ret);
625
626 return (ret);
627 }
628
629 static int
bfe_miibus_writereg(device_t dev,int phy,int reg,int val)630 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
631 {
632 struct bfe_softc *sc;
633
634 sc = device_get_softc(dev);
635 bfe_writephy(sc, reg, val);
636
637 return (0);
638 }
639
640 static void
bfe_miibus_statchg(device_t dev)641 bfe_miibus_statchg(device_t dev)
642 {
643 struct bfe_softc *sc;
644 struct mii_data *mii;
645 u_int32_t val;
646 #ifdef notyet
647 u_int32_t flow;
648 #endif
649
650 sc = device_get_softc(dev);
651 mii = device_get_softc(sc->bfe_miibus);
652
653 sc->bfe_flags &= ~BFE_FLAG_LINK;
654 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
655 (IFM_ACTIVE | IFM_AVALID)) {
656 switch (IFM_SUBTYPE(mii->mii_media_active)) {
657 case IFM_10_T:
658 case IFM_100_TX:
659 sc->bfe_flags |= BFE_FLAG_LINK;
660 break;
661 default:
662 break;
663 }
664 }
665
666 /* XXX Should stop Rx/Tx engine prior to touching MAC. */
667 val = CSR_READ_4(sc, BFE_TX_CTRL);
668 val &= ~BFE_TX_DUPLEX;
669 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
670 val |= BFE_TX_DUPLEX;
671 #ifdef notyet
672 flow = CSR_READ_4(sc, BFE_RXCONF);
673 flow &= ~BFE_RXCONF_FLOW;
674 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
675 IFM_ETH_RXPAUSE) != 0)
676 flow |= BFE_RXCONF_FLOW;
677 CSR_WRITE_4(sc, BFE_RXCONF, flow);
678 /*
679 * It seems that the hardware has Tx pause issues
680 * so enable only Rx pause.
681 */
682 flow = CSR_READ_4(sc, BFE_MAC_FLOW);
683 flow &= ~BFE_FLOW_PAUSE_ENAB;
684 CSR_WRITE_4(sc, BFE_MAC_FLOW, flow);
685 #endif
686 }
687 CSR_WRITE_4(sc, BFE_TX_CTRL, val);
688 }
689
690 static void
bfe_tx_ring_free(struct bfe_softc * sc)691 bfe_tx_ring_free(struct bfe_softc *sc)
692 {
693 int i;
694
695 for(i = 0; i < BFE_TX_LIST_CNT; i++) {
696 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
697 bus_dmamap_sync(sc->bfe_txmbuf_tag,
698 sc->bfe_tx_ring[i].bfe_map, BUS_DMASYNC_POSTWRITE);
699 bus_dmamap_unload(sc->bfe_txmbuf_tag,
700 sc->bfe_tx_ring[i].bfe_map);
701 m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
702 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
703 }
704 }
705 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
706 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
707 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
708 }
709
710 static void
bfe_rx_ring_free(struct bfe_softc * sc)711 bfe_rx_ring_free(struct bfe_softc *sc)
712 {
713 int i;
714
715 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
716 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
717 bus_dmamap_sync(sc->bfe_rxmbuf_tag,
718 sc->bfe_rx_ring[i].bfe_map, BUS_DMASYNC_POSTREAD);
719 bus_dmamap_unload(sc->bfe_rxmbuf_tag,
720 sc->bfe_rx_ring[i].bfe_map);
721 m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
722 sc->bfe_rx_ring[i].bfe_mbuf = NULL;
723 }
724 }
725 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
726 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
727 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
728 }
729
730 static int
bfe_list_rx_init(struct bfe_softc * sc)731 bfe_list_rx_init(struct bfe_softc *sc)
732 {
733 struct bfe_rx_data *rd;
734 int i;
735
736 sc->bfe_rx_prod = sc->bfe_rx_cons = 0;
737 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
738 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
739 rd = &sc->bfe_rx_ring[i];
740 rd->bfe_mbuf = NULL;
741 rd->bfe_ctrl = 0;
742 if (bfe_list_newbuf(sc, i) != 0)
743 return (ENOBUFS);
744 }
745
746 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
747 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
748 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
749
750 return (0);
751 }
752
753 static void
bfe_list_tx_init(struct bfe_softc * sc)754 bfe_list_tx_init(struct bfe_softc *sc)
755 {
756 int i;
757
758 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
759 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
760 for (i = 0; i < BFE_TX_LIST_CNT; i++)
761 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
762
763 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
764 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
765 }
766
767 static void
bfe_discard_buf(struct bfe_softc * sc,int c)768 bfe_discard_buf(struct bfe_softc *sc, int c)
769 {
770 struct bfe_rx_data *r;
771 struct bfe_desc *d;
772
773 r = &sc->bfe_rx_ring[c];
774 d = &sc->bfe_rx_list[c];
775 d->bfe_ctrl = htole32(r->bfe_ctrl);
776 }
777
778 static int
bfe_list_newbuf(struct bfe_softc * sc,int c)779 bfe_list_newbuf(struct bfe_softc *sc, int c)
780 {
781 struct bfe_rxheader *rx_header;
782 struct bfe_desc *d;
783 struct bfe_rx_data *r;
784 struct mbuf *m;
785 bus_dma_segment_t segs[1];
786 bus_dmamap_t map;
787 u_int32_t ctrl;
788 int nsegs;
789
790 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
791 if (m == NULL)
792 return (ENOBUFS);
793 m->m_len = m->m_pkthdr.len = MCLBYTES;
794
795 if (bus_dmamap_load_mbuf_sg(sc->bfe_rxmbuf_tag, sc->bfe_rx_sparemap,
796 m, segs, &nsegs, 0) != 0) {
797 m_freem(m);
798 return (ENOBUFS);
799 }
800
801 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
802 r = &sc->bfe_rx_ring[c];
803 if (r->bfe_mbuf != NULL) {
804 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map,
805 BUS_DMASYNC_POSTREAD);
806 bus_dmamap_unload(sc->bfe_rxmbuf_tag, r->bfe_map);
807 }
808 map = r->bfe_map;
809 r->bfe_map = sc->bfe_rx_sparemap;
810 sc->bfe_rx_sparemap = map;
811 r->bfe_mbuf = m;
812
813 rx_header = mtod(m, struct bfe_rxheader *);
814 rx_header->len = 0;
815 rx_header->flags = 0;
816 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, BUS_DMASYNC_PREREAD);
817
818 ctrl = segs[0].ds_len & BFE_DESC_LEN;
819 KASSERT(ctrl > ETHER_MAX_LEN + 32, ("%s: buffer size too small(%d)!",
820 __func__, ctrl));
821 if (c == BFE_RX_LIST_CNT - 1)
822 ctrl |= BFE_DESC_EOT;
823 r->bfe_ctrl = ctrl;
824
825 d = &sc->bfe_rx_list[c];
826 d->bfe_ctrl = htole32(ctrl);
827 /* The chip needs all addresses to be added to BFE_PCI_DMA. */
828 d->bfe_addr = htole32(BFE_ADDR_LO(segs[0].ds_addr) + BFE_PCI_DMA);
829
830 return (0);
831 }
832
833 static void
bfe_get_config(struct bfe_softc * sc)834 bfe_get_config(struct bfe_softc *sc)
835 {
836 u_int8_t eeprom[128];
837
838 bfe_read_eeprom(sc, eeprom);
839
840 sc->bfe_enaddr[0] = eeprom[79];
841 sc->bfe_enaddr[1] = eeprom[78];
842 sc->bfe_enaddr[2] = eeprom[81];
843 sc->bfe_enaddr[3] = eeprom[80];
844 sc->bfe_enaddr[4] = eeprom[83];
845 sc->bfe_enaddr[5] = eeprom[82];
846
847 sc->bfe_phyaddr = eeprom[90] & 0x1f;
848 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
849
850 sc->bfe_core_unit = 0;
851 sc->bfe_dma_offset = BFE_PCI_DMA;
852 }
853
854 static void
bfe_pci_setup(struct bfe_softc * sc,u_int32_t cores)855 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores)
856 {
857 u_int32_t bar_orig, val;
858
859 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
860 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
861
862 val = CSR_READ_4(sc, BFE_SBINTVEC);
863 val |= cores;
864 CSR_WRITE_4(sc, BFE_SBINTVEC, val);
865
866 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
867 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
868 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
869
870 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
871 }
872
873 static void
bfe_clear_stats(struct bfe_softc * sc)874 bfe_clear_stats(struct bfe_softc *sc)
875 {
876 uint32_t reg;
877
878 BFE_LOCK_ASSERT(sc);
879
880 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
881 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
882 CSR_READ_4(sc, reg);
883 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
884 CSR_READ_4(sc, reg);
885 }
886
887 static int
bfe_resetphy(struct bfe_softc * sc)888 bfe_resetphy(struct bfe_softc *sc)
889 {
890 u_int32_t val;
891
892 bfe_writephy(sc, 0, BMCR_RESET);
893 DELAY(100);
894 bfe_readphy(sc, 0, &val);
895 if (val & BMCR_RESET) {
896 device_printf(sc->bfe_dev, "PHY Reset would not complete.\n");
897 return (ENXIO);
898 }
899 return (0);
900 }
901
902 static void
bfe_chip_halt(struct bfe_softc * sc)903 bfe_chip_halt(struct bfe_softc *sc)
904 {
905 BFE_LOCK_ASSERT(sc);
906 /* disable interrupts - not that it actually does..*/
907 CSR_WRITE_4(sc, BFE_IMASK, 0);
908 CSR_READ_4(sc, BFE_IMASK);
909
910 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
911 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
912
913 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
914 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
915 DELAY(10);
916 }
917
918 static void
bfe_chip_reset(struct bfe_softc * sc)919 bfe_chip_reset(struct bfe_softc *sc)
920 {
921 u_int32_t val;
922
923 BFE_LOCK_ASSERT(sc);
924
925 /* Set the interrupt vector for the enet core */
926 bfe_pci_setup(sc, BFE_INTVEC_ENET0);
927
928 /* is core up? */
929 val = CSR_READ_4(sc, BFE_SBTMSLOW) &
930 (BFE_RESET | BFE_REJECT | BFE_CLOCK);
931 if (val == BFE_CLOCK) {
932 /* It is, so shut it down */
933 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
934 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
935 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
936 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
937 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
938 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE,
939 100, 0);
940 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
941 }
942
943 bfe_core_reset(sc);
944 bfe_clear_stats(sc);
945
946 /*
947 * We want the phy registers to be accessible even when
948 * the driver is "downed" so initialize MDC preamble, frequency,
949 * and whether internal or external phy here.
950 */
951
952 /* 4402 has 62.5Mhz SB clock and internal phy */
953 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
954
955 /* Internal or external PHY? */
956 val = CSR_READ_4(sc, BFE_DEVCTRL);
957 if (!(val & BFE_IPP))
958 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
959 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
960 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
961 DELAY(100);
962 }
963
964 /* Enable CRC32 generation and set proper LED modes */
965 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
966
967 /* Reset or clear powerdown control bit */
968 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
969
970 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
971 BFE_LAZY_FC_MASK));
972
973 /*
974 * We don't want lazy interrupts, so just send them at
975 * the end of a frame, please
976 */
977 BFE_OR(sc, BFE_RCV_LAZY, 0);
978
979 /* Set max lengths, accounting for VLAN tags */
980 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
981 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
982
983 /* Set watermark XXX - magic */
984 CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
985
986 /*
987 * Initialise DMA channels
988 * - not forgetting dma addresses need to be added to BFE_PCI_DMA
989 */
990 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
991 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
992
993 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
994 BFE_RX_CTRL_ENABLE);
995 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
996
997 bfe_resetphy(sc);
998 bfe_setupphy(sc);
999 }
1000
1001 static void
bfe_core_disable(struct bfe_softc * sc)1002 bfe_core_disable(struct bfe_softc *sc)
1003 {
1004 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
1005 return;
1006
1007 /*
1008 * Set reject, wait for it set, then wait for the core to stop
1009 * being busy, then set reset and reject and enable the clocks.
1010 */
1011 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
1012 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
1013 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
1014 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
1015 BFE_RESET));
1016 CSR_READ_4(sc, BFE_SBTMSLOW);
1017 DELAY(10);
1018 /* Leave reset and reject set */
1019 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
1020 DELAY(10);
1021 }
1022
1023 static void
bfe_core_reset(struct bfe_softc * sc)1024 bfe_core_reset(struct bfe_softc *sc)
1025 {
1026 u_int32_t val;
1027
1028 /* Disable the core */
1029 bfe_core_disable(sc);
1030
1031 /* and bring it back up */
1032 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
1033 CSR_READ_4(sc, BFE_SBTMSLOW);
1034 DELAY(10);
1035
1036 /* Chip bug, clear SERR, IB and TO if they are set. */
1037 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
1038 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
1039 val = CSR_READ_4(sc, BFE_SBIMSTATE);
1040 if (val & (BFE_IBE | BFE_TO))
1041 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
1042
1043 /* Clear reset and allow it to move through the core */
1044 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
1045 CSR_READ_4(sc, BFE_SBTMSLOW);
1046 DELAY(10);
1047
1048 /* Leave the clock set */
1049 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
1050 CSR_READ_4(sc, BFE_SBTMSLOW);
1051 DELAY(10);
1052 }
1053
1054 static void
bfe_cam_write(struct bfe_softc * sc,u_char * data,int index)1055 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
1056 {
1057 u_int32_t val;
1058
1059 val = ((u_int32_t) data[2]) << 24;
1060 val |= ((u_int32_t) data[3]) << 16;
1061 val |= ((u_int32_t) data[4]) << 8;
1062 val |= ((u_int32_t) data[5]);
1063 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
1064 val = (BFE_CAM_HI_VALID |
1065 (((u_int32_t) data[0]) << 8) |
1066 (((u_int32_t) data[1])));
1067 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
1068 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
1069 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT)));
1070 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
1071 }
1072
1073 static u_int
bfe_write_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)1074 bfe_write_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1075 {
1076 struct bfe_softc *sc = arg;
1077
1078 bfe_cam_write(sc, LLADDR(sdl), cnt + 1);
1079
1080 return (1);
1081 }
1082
1083 static void
bfe_set_rx_mode(struct bfe_softc * sc)1084 bfe_set_rx_mode(struct bfe_softc *sc)
1085 {
1086 if_t ifp = sc->bfe_ifp;
1087 u_int32_t val;
1088
1089 BFE_LOCK_ASSERT(sc);
1090
1091 val = CSR_READ_4(sc, BFE_RXCONF);
1092
1093 if (if_getflags(ifp) & IFF_PROMISC)
1094 val |= BFE_RXCONF_PROMISC;
1095 else
1096 val &= ~BFE_RXCONF_PROMISC;
1097
1098 if (if_getflags(ifp) & IFF_BROADCAST)
1099 val &= ~BFE_RXCONF_DBCAST;
1100 else
1101 val |= BFE_RXCONF_DBCAST;
1102
1103 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
1104 bfe_cam_write(sc, if_getlladdr(sc->bfe_ifp), 0);
1105
1106 if (if_getflags(ifp) & IFF_ALLMULTI)
1107 val |= BFE_RXCONF_ALLMULTI;
1108 else {
1109 val &= ~BFE_RXCONF_ALLMULTI;
1110 if_foreach_llmaddr(ifp, bfe_write_maddr, sc);
1111 }
1112
1113 CSR_WRITE_4(sc, BFE_RXCONF, val);
1114 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
1115 }
1116
1117 static void
bfe_dma_map(void * arg,bus_dma_segment_t * segs,int nseg,int error)1118 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1119 {
1120 struct bfe_dmamap_arg *ctx;
1121
1122 if (error != 0)
1123 return;
1124
1125 KASSERT(nseg == 1, ("%s : %d segments returned!", __func__, nseg));
1126
1127 ctx = (struct bfe_dmamap_arg *)arg;
1128 ctx->bfe_busaddr = segs[0].ds_addr;
1129 }
1130
1131 static void
bfe_release_resources(struct bfe_softc * sc)1132 bfe_release_resources(struct bfe_softc *sc)
1133 {
1134
1135 if (sc->bfe_intrhand != NULL)
1136 bus_teardown_intr(sc->bfe_dev, sc->bfe_irq, sc->bfe_intrhand);
1137
1138 if (sc->bfe_irq != NULL)
1139 bus_release_resource(sc->bfe_dev, SYS_RES_IRQ, 0, sc->bfe_irq);
1140
1141 if (sc->bfe_res != NULL)
1142 bus_release_resource(sc->bfe_dev, SYS_RES_MEMORY, PCIR_BAR(0),
1143 sc->bfe_res);
1144
1145 if (sc->bfe_ifp != NULL)
1146 if_free(sc->bfe_ifp);
1147 }
1148
1149 static void
bfe_read_eeprom(struct bfe_softc * sc,u_int8_t * data)1150 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data)
1151 {
1152 long i;
1153 u_int16_t *ptr = (u_int16_t *)data;
1154
1155 for(i = 0; i < 128; i += 2)
1156 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
1157 }
1158
1159 static int
bfe_wait_bit(struct bfe_softc * sc,u_int32_t reg,u_int32_t bit,u_long timeout,const int clear)1160 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit,
1161 u_long timeout, const int clear)
1162 {
1163 u_long i;
1164
1165 for (i = 0; i < timeout; i++) {
1166 u_int32_t val = CSR_READ_4(sc, reg);
1167
1168 if (clear && !(val & bit))
1169 break;
1170 if (!clear && (val & bit))
1171 break;
1172 DELAY(10);
1173 }
1174 if (i == timeout) {
1175 device_printf(sc->bfe_dev,
1176 "BUG! Timeout waiting for bit %08x of register "
1177 "%x to %s.\n", bit, reg, (clear ? "clear" : "set"));
1178 return (-1);
1179 }
1180 return (0);
1181 }
1182
1183 static int
bfe_readphy(struct bfe_softc * sc,u_int32_t reg,u_int32_t * val)1184 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val)
1185 {
1186 int err;
1187
1188 /* Clear MII ISR */
1189 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1190 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1191 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
1192 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1193 (reg << BFE_MDIO_RA_SHIFT) |
1194 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
1195 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1196 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
1197
1198 return (err);
1199 }
1200
1201 static int
bfe_writephy(struct bfe_softc * sc,u_int32_t reg,u_int32_t val)1202 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val)
1203 {
1204 int status;
1205
1206 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1207 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1208 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
1209 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1210 (reg << BFE_MDIO_RA_SHIFT) |
1211 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
1212 (val & BFE_MDIO_DATA_DATA)));
1213 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1214
1215 return (status);
1216 }
1217
1218 /*
1219 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1220 * twice
1221 */
1222 static int
bfe_setupphy(struct bfe_softc * sc)1223 bfe_setupphy(struct bfe_softc *sc)
1224 {
1225 u_int32_t val;
1226
1227 /* Enable activity LED */
1228 bfe_readphy(sc, 26, &val);
1229 bfe_writephy(sc, 26, val & 0x7fff);
1230 bfe_readphy(sc, 26, &val);
1231
1232 /* Enable traffic meter LED mode */
1233 bfe_readphy(sc, 27, &val);
1234 bfe_writephy(sc, 27, val | (1 << 6));
1235
1236 return (0);
1237 }
1238
1239 static void
bfe_stats_update(struct bfe_softc * sc)1240 bfe_stats_update(struct bfe_softc *sc)
1241 {
1242 struct bfe_hw_stats *stats;
1243 if_t ifp;
1244 uint32_t mib[BFE_MIB_CNT];
1245 uint32_t reg, *val;
1246
1247 BFE_LOCK_ASSERT(sc);
1248
1249 val = mib;
1250 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
1251 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
1252 *val++ = CSR_READ_4(sc, reg);
1253 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
1254 *val++ = CSR_READ_4(sc, reg);
1255
1256 ifp = sc->bfe_ifp;
1257 stats = &sc->bfe_stats;
1258 /* Tx stat. */
1259 stats->tx_good_octets += mib[MIB_TX_GOOD_O];
1260 stats->tx_good_frames += mib[MIB_TX_GOOD_P];
1261 stats->tx_octets += mib[MIB_TX_O];
1262 stats->tx_frames += mib[MIB_TX_P];
1263 stats->tx_bcast_frames += mib[MIB_TX_BCAST];
1264 stats->tx_mcast_frames += mib[MIB_TX_MCAST];
1265 stats->tx_pkts_64 += mib[MIB_TX_64];
1266 stats->tx_pkts_65_127 += mib[MIB_TX_65_127];
1267 stats->tx_pkts_128_255 += mib[MIB_TX_128_255];
1268 stats->tx_pkts_256_511 += mib[MIB_TX_256_511];
1269 stats->tx_pkts_512_1023 += mib[MIB_TX_512_1023];
1270 stats->tx_pkts_1024_max += mib[MIB_TX_1024_MAX];
1271 stats->tx_jabbers += mib[MIB_TX_JABBER];
1272 stats->tx_oversize_frames += mib[MIB_TX_OSIZE];
1273 stats->tx_frag_frames += mib[MIB_TX_FRAG];
1274 stats->tx_underruns += mib[MIB_TX_URUNS];
1275 stats->tx_colls += mib[MIB_TX_TCOLS];
1276 stats->tx_single_colls += mib[MIB_TX_SCOLS];
1277 stats->tx_multi_colls += mib[MIB_TX_MCOLS];
1278 stats->tx_excess_colls += mib[MIB_TX_ECOLS];
1279 stats->tx_late_colls += mib[MIB_TX_LCOLS];
1280 stats->tx_deferrals += mib[MIB_TX_DEFERED];
1281 stats->tx_carrier_losts += mib[MIB_TX_CLOST];
1282 stats->tx_pause_frames += mib[MIB_TX_PAUSE];
1283 /* Rx stat. */
1284 stats->rx_good_octets += mib[MIB_RX_GOOD_O];
1285 stats->rx_good_frames += mib[MIB_RX_GOOD_P];
1286 stats->rx_octets += mib[MIB_RX_O];
1287 stats->rx_frames += mib[MIB_RX_P];
1288 stats->rx_bcast_frames += mib[MIB_RX_BCAST];
1289 stats->rx_mcast_frames += mib[MIB_RX_MCAST];
1290 stats->rx_pkts_64 += mib[MIB_RX_64];
1291 stats->rx_pkts_65_127 += mib[MIB_RX_65_127];
1292 stats->rx_pkts_128_255 += mib[MIB_RX_128_255];
1293 stats->rx_pkts_256_511 += mib[MIB_RX_256_511];
1294 stats->rx_pkts_512_1023 += mib[MIB_RX_512_1023];
1295 stats->rx_pkts_1024_max += mib[MIB_RX_1024_MAX];
1296 stats->rx_jabbers += mib[MIB_RX_JABBER];
1297 stats->rx_oversize_frames += mib[MIB_RX_OSIZE];
1298 stats->rx_frag_frames += mib[MIB_RX_FRAG];
1299 stats->rx_missed_frames += mib[MIB_RX_MISS];
1300 stats->rx_crc_align_errs += mib[MIB_RX_CRCA];
1301 stats->rx_runts += mib[MIB_RX_USIZE];
1302 stats->rx_crc_errs += mib[MIB_RX_CRC];
1303 stats->rx_align_errs += mib[MIB_RX_ALIGN];
1304 stats->rx_symbol_errs += mib[MIB_RX_SYM];
1305 stats->rx_pause_frames += mib[MIB_RX_PAUSE];
1306 stats->rx_control_frames += mib[MIB_RX_NPAUSE];
1307
1308 /* Update counters in ifnet. */
1309 if_inc_counter(ifp, IFCOUNTER_OPACKETS, (u_long)mib[MIB_TX_GOOD_P]);
1310 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (u_long)mib[MIB_TX_TCOLS]);
1311 if_inc_counter(ifp, IFCOUNTER_OERRORS, (u_long)mib[MIB_TX_URUNS] +
1312 (u_long)mib[MIB_TX_ECOLS] +
1313 (u_long)mib[MIB_TX_DEFERED] +
1314 (u_long)mib[MIB_TX_CLOST]);
1315
1316 if_inc_counter(ifp, IFCOUNTER_IPACKETS, (u_long)mib[MIB_RX_GOOD_P]);
1317
1318 if_inc_counter(ifp, IFCOUNTER_IERRORS, mib[MIB_RX_JABBER] +
1319 mib[MIB_RX_MISS] +
1320 mib[MIB_RX_CRCA] +
1321 mib[MIB_RX_USIZE] +
1322 mib[MIB_RX_CRC] +
1323 mib[MIB_RX_ALIGN] +
1324 mib[MIB_RX_SYM]);
1325 }
1326
1327 static void
bfe_txeof(struct bfe_softc * sc)1328 bfe_txeof(struct bfe_softc *sc)
1329 {
1330 struct bfe_tx_data *r;
1331 if_t ifp;
1332 int i, chipidx;
1333
1334 BFE_LOCK_ASSERT(sc);
1335
1336 ifp = sc->bfe_ifp;
1337
1338 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1339 chipidx /= sizeof(struct bfe_desc);
1340
1341 i = sc->bfe_tx_cons;
1342 if (i == chipidx)
1343 return;
1344 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
1345 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1346 /* Go through the mbufs and free those that have been transmitted */
1347 for (; i != chipidx; BFE_INC(i, BFE_TX_LIST_CNT)) {
1348 r = &sc->bfe_tx_ring[i];
1349 sc->bfe_tx_cnt--;
1350 if (r->bfe_mbuf == NULL)
1351 continue;
1352 bus_dmamap_sync(sc->bfe_txmbuf_tag, r->bfe_map,
1353 BUS_DMASYNC_POSTWRITE);
1354 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map);
1355
1356 m_freem(r->bfe_mbuf);
1357 r->bfe_mbuf = NULL;
1358 }
1359
1360 if (i != sc->bfe_tx_cons) {
1361 /* we freed up some mbufs */
1362 sc->bfe_tx_cons = i;
1363 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1364 }
1365
1366 if (sc->bfe_tx_cnt == 0)
1367 sc->bfe_watchdog_timer = 0;
1368 }
1369
1370 /* Pass a received packet up the stack */
1371 static void
bfe_rxeof(struct bfe_softc * sc)1372 bfe_rxeof(struct bfe_softc *sc)
1373 {
1374 struct mbuf *m;
1375 if_t ifp;
1376 struct bfe_rxheader *rxheader;
1377 struct bfe_rx_data *r;
1378 int cons, prog;
1379 u_int32_t status, current, len, flags;
1380
1381 BFE_LOCK_ASSERT(sc);
1382 cons = sc->bfe_rx_cons;
1383 status = CSR_READ_4(sc, BFE_DMARX_STAT);
1384 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1385
1386 ifp = sc->bfe_ifp;
1387
1388 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
1389 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1390
1391 for (prog = 0; current != cons; prog++,
1392 BFE_INC(cons, BFE_RX_LIST_CNT)) {
1393 r = &sc->bfe_rx_ring[cons];
1394 m = r->bfe_mbuf;
1395 /*
1396 * Rx status should be read from mbuf such that we can't
1397 * delay bus_dmamap_sync(9). This hardware limiation
1398 * results in inefficient mbuf usage as bfe(4) couldn't
1399 * reuse mapped buffer from errored frame.
1400 */
1401 if (bfe_list_newbuf(sc, cons) != 0) {
1402 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1403 bfe_discard_buf(sc, cons);
1404 continue;
1405 }
1406 rxheader = mtod(m, struct bfe_rxheader*);
1407 len = le16toh(rxheader->len);
1408 flags = le16toh(rxheader->flags);
1409
1410 /* Remove CRC bytes. */
1411 len -= ETHER_CRC_LEN;
1412
1413 /* flag an error and try again */
1414 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) {
1415 m_freem(m);
1416 continue;
1417 }
1418
1419 /* Make sure to skip header bytes written by hardware. */
1420 m_adj(m, BFE_RX_OFFSET);
1421 m->m_len = m->m_pkthdr.len = len;
1422
1423 m->m_pkthdr.rcvif = ifp;
1424 BFE_UNLOCK(sc);
1425 if_input(ifp, m);
1426 BFE_LOCK(sc);
1427 }
1428
1429 if (prog > 0) {
1430 sc->bfe_rx_cons = cons;
1431 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
1432 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1433 }
1434 }
1435
1436 static void
bfe_intr(void * xsc)1437 bfe_intr(void *xsc)
1438 {
1439 struct bfe_softc *sc = xsc;
1440 if_t ifp;
1441 u_int32_t istat;
1442
1443 ifp = sc->bfe_ifp;
1444
1445 BFE_LOCK(sc);
1446
1447 istat = CSR_READ_4(sc, BFE_ISTAT);
1448
1449 /*
1450 * Defer unsolicited interrupts - This is necessary because setting the
1451 * chips interrupt mask register to 0 doesn't actually stop the
1452 * interrupts
1453 */
1454 istat &= BFE_IMASK_DEF;
1455 CSR_WRITE_4(sc, BFE_ISTAT, istat);
1456 CSR_READ_4(sc, BFE_ISTAT);
1457
1458 /* not expecting this interrupt, disregard it */
1459 if (istat == 0 || (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
1460 BFE_UNLOCK(sc);
1461 return;
1462 }
1463
1464 /* A packet was received */
1465 if (istat & BFE_ISTAT_RX)
1466 bfe_rxeof(sc);
1467
1468 /* A packet was sent */
1469 if (istat & BFE_ISTAT_TX)
1470 bfe_txeof(sc);
1471
1472 if (istat & BFE_ISTAT_ERRORS) {
1473 if (istat & BFE_ISTAT_DSCE) {
1474 device_printf(sc->bfe_dev, "Descriptor Error\n");
1475 bfe_stop(sc);
1476 BFE_UNLOCK(sc);
1477 return;
1478 }
1479
1480 if (istat & BFE_ISTAT_DPE) {
1481 device_printf(sc->bfe_dev,
1482 "Descriptor Protocol Error\n");
1483 bfe_stop(sc);
1484 BFE_UNLOCK(sc);
1485 return;
1486 }
1487 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1488 bfe_init_locked(sc);
1489 }
1490
1491 /* We have packets pending, fire them out */
1492 if (!if_sendq_empty(ifp))
1493 bfe_start_locked(ifp);
1494
1495 BFE_UNLOCK(sc);
1496 }
1497
1498 static int
bfe_encap(struct bfe_softc * sc,struct mbuf ** m_head)1499 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head)
1500 {
1501 struct bfe_desc *d;
1502 struct bfe_tx_data *r, *r1;
1503 struct mbuf *m;
1504 bus_dmamap_t map;
1505 bus_dma_segment_t txsegs[BFE_MAXTXSEGS];
1506 uint32_t cur, si;
1507 int error, i, nsegs;
1508
1509 BFE_LOCK_ASSERT(sc);
1510
1511 M_ASSERTPKTHDR((*m_head));
1512
1513 si = cur = sc->bfe_tx_prod;
1514 r = &sc->bfe_tx_ring[cur];
1515 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, *m_head,
1516 txsegs, &nsegs, 0);
1517 if (error == EFBIG) {
1518 m = m_collapse(*m_head, M_NOWAIT, BFE_MAXTXSEGS);
1519 if (m == NULL) {
1520 m_freem(*m_head);
1521 *m_head = NULL;
1522 return (ENOMEM);
1523 }
1524 *m_head = m;
1525 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map,
1526 *m_head, txsegs, &nsegs, 0);
1527 if (error != 0) {
1528 m_freem(*m_head);
1529 *m_head = NULL;
1530 return (error);
1531 }
1532 } else if (error != 0)
1533 return (error);
1534 if (nsegs == 0) {
1535 m_freem(*m_head);
1536 *m_head = NULL;
1537 return (EIO);
1538 }
1539
1540 if (sc->bfe_tx_cnt + nsegs > BFE_TX_LIST_CNT - 1) {
1541 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map);
1542 return (ENOBUFS);
1543 }
1544
1545 for (i = 0; i < nsegs; i++) {
1546 d = &sc->bfe_tx_list[cur];
1547 d->bfe_ctrl = htole32(txsegs[i].ds_len & BFE_DESC_LEN);
1548 d->bfe_ctrl |= htole32(BFE_DESC_IOC);
1549 if (cur == BFE_TX_LIST_CNT - 1)
1550 /*
1551 * Tell the chip to wrap to the start of
1552 * the descriptor list.
1553 */
1554 d->bfe_ctrl |= htole32(BFE_DESC_EOT);
1555 /* The chip needs all addresses to be added to BFE_PCI_DMA. */
1556 d->bfe_addr = htole32(BFE_ADDR_LO(txsegs[i].ds_addr) +
1557 BFE_PCI_DMA);
1558 BFE_INC(cur, BFE_TX_LIST_CNT);
1559 }
1560
1561 /* Update producer index. */
1562 sc->bfe_tx_prod = cur;
1563
1564 /* Set EOF on the last descriptor. */
1565 cur = (cur + BFE_TX_LIST_CNT - 1) % BFE_TX_LIST_CNT;
1566 d = &sc->bfe_tx_list[cur];
1567 d->bfe_ctrl |= htole32(BFE_DESC_EOF);
1568
1569 /* Lastly set SOF on the first descriptor to avoid races. */
1570 d = &sc->bfe_tx_list[si];
1571 d->bfe_ctrl |= htole32(BFE_DESC_SOF);
1572
1573 r1 = &sc->bfe_tx_ring[cur];
1574 map = r->bfe_map;
1575 r->bfe_map = r1->bfe_map;
1576 r1->bfe_map = map;
1577 r1->bfe_mbuf = *m_head;
1578 sc->bfe_tx_cnt += nsegs;
1579
1580 bus_dmamap_sync(sc->bfe_txmbuf_tag, map, BUS_DMASYNC_PREWRITE);
1581
1582 return (0);
1583 }
1584
1585 /*
1586 * Set up to transmit a packet.
1587 */
1588 static void
bfe_start(if_t ifp)1589 bfe_start(if_t ifp)
1590 {
1591 BFE_LOCK((struct bfe_softc *)if_getsoftc(ifp));
1592 bfe_start_locked(ifp);
1593 BFE_UNLOCK((struct bfe_softc *)if_getsoftc(ifp));
1594 }
1595
1596 /*
1597 * Set up to transmit a packet. The softc is already locked.
1598 */
1599 static void
bfe_start_locked(if_t ifp)1600 bfe_start_locked(if_t ifp)
1601 {
1602 struct bfe_softc *sc;
1603 struct mbuf *m_head;
1604 int queued;
1605
1606 sc = if_getsoftc(ifp);
1607
1608 BFE_LOCK_ASSERT(sc);
1609
1610 /*
1611 * Not much point trying to send if the link is down
1612 * or we have nothing to send.
1613 */
1614 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1615 IFF_DRV_RUNNING || (sc->bfe_flags & BFE_FLAG_LINK) == 0)
1616 return;
1617
1618 for (queued = 0; !if_sendq_empty(ifp) &&
1619 sc->bfe_tx_cnt < BFE_TX_LIST_CNT - 1;) {
1620 m_head = if_dequeue(ifp);
1621 if (m_head == NULL)
1622 break;
1623
1624 /*
1625 * Pack the data into the tx ring. If we dont have
1626 * enough room, let the chip drain the ring.
1627 */
1628 if (bfe_encap(sc, &m_head)) {
1629 if (m_head == NULL)
1630 break;
1631 if_sendq_prepend(ifp, m_head);
1632 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1633 break;
1634 }
1635
1636 queued++;
1637
1638 /*
1639 * If there's a BPF listener, bounce a copy of this frame
1640 * to him.
1641 */
1642 BPF_MTAP(ifp, m_head);
1643 }
1644
1645 if (queued) {
1646 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
1647 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1648 /* Transmit - twice due to apparent hardware bug */
1649 CSR_WRITE_4(sc, BFE_DMATX_PTR,
1650 sc->bfe_tx_prod * sizeof(struct bfe_desc));
1651 /*
1652 * XXX It seems the following write is not necessary
1653 * to kick Tx command. What might be required would be
1654 * a way flushing PCI posted write. Reading the register
1655 * back ensures the flush operation. In addition,
1656 * hardware will execute PCI posted write in the long
1657 * run and watchdog timer for the kick command was set
1658 * to 5 seconds. Therefore I think the second write
1659 * access is not necessary or could be replaced with
1660 * read operation.
1661 */
1662 CSR_WRITE_4(sc, BFE_DMATX_PTR,
1663 sc->bfe_tx_prod * sizeof(struct bfe_desc));
1664
1665 /*
1666 * Set a timeout in case the chip goes out to lunch.
1667 */
1668 sc->bfe_watchdog_timer = 5;
1669 }
1670 }
1671
1672 static void
bfe_init(void * xsc)1673 bfe_init(void *xsc)
1674 {
1675 BFE_LOCK((struct bfe_softc *)xsc);
1676 bfe_init_locked(xsc);
1677 BFE_UNLOCK((struct bfe_softc *)xsc);
1678 }
1679
1680 static void
bfe_init_locked(void * xsc)1681 bfe_init_locked(void *xsc)
1682 {
1683 struct bfe_softc *sc = (struct bfe_softc*)xsc;
1684 if_t ifp = sc->bfe_ifp;
1685 struct mii_data *mii;
1686
1687 BFE_LOCK_ASSERT(sc);
1688
1689 mii = device_get_softc(sc->bfe_miibus);
1690
1691 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1692 return;
1693
1694 bfe_stop(sc);
1695 bfe_chip_reset(sc);
1696
1697 if (bfe_list_rx_init(sc) == ENOBUFS) {
1698 device_printf(sc->bfe_dev,
1699 "%s: Not enough memory for list buffers\n", __func__);
1700 bfe_stop(sc);
1701 return;
1702 }
1703 bfe_list_tx_init(sc);
1704
1705 bfe_set_rx_mode(sc);
1706
1707 /* Enable the chip and core */
1708 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1709 /* Enable interrupts */
1710 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1711
1712 /* Clear link state and change media. */
1713 sc->bfe_flags &= ~BFE_FLAG_LINK;
1714 mii_mediachg(mii);
1715
1716 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
1717 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1718
1719 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc);
1720 }
1721
1722 /*
1723 * Set media options.
1724 */
1725 static int
bfe_ifmedia_upd(if_t ifp)1726 bfe_ifmedia_upd(if_t ifp)
1727 {
1728 struct bfe_softc *sc;
1729 struct mii_data *mii;
1730 struct mii_softc *miisc;
1731 int error;
1732
1733 sc = if_getsoftc(ifp);
1734 BFE_LOCK(sc);
1735
1736 mii = device_get_softc(sc->bfe_miibus);
1737 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1738 PHY_RESET(miisc);
1739 error = mii_mediachg(mii);
1740 BFE_UNLOCK(sc);
1741
1742 return (error);
1743 }
1744
1745 /*
1746 * Report current media status.
1747 */
1748 static void
bfe_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)1749 bfe_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
1750 {
1751 struct bfe_softc *sc = if_getsoftc(ifp);
1752 struct mii_data *mii;
1753
1754 BFE_LOCK(sc);
1755 mii = device_get_softc(sc->bfe_miibus);
1756 mii_pollstat(mii);
1757 ifmr->ifm_active = mii->mii_media_active;
1758 ifmr->ifm_status = mii->mii_media_status;
1759 BFE_UNLOCK(sc);
1760 }
1761
1762 static int
bfe_ioctl(if_t ifp,u_long command,caddr_t data)1763 bfe_ioctl(if_t ifp, u_long command, caddr_t data)
1764 {
1765 struct bfe_softc *sc = if_getsoftc(ifp);
1766 struct ifreq *ifr = (struct ifreq *) data;
1767 struct mii_data *mii;
1768 int error = 0;
1769
1770 switch (command) {
1771 case SIOCSIFFLAGS:
1772 BFE_LOCK(sc);
1773 if (if_getflags(ifp) & IFF_UP) {
1774 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1775 bfe_set_rx_mode(sc);
1776 else if ((sc->bfe_flags & BFE_FLAG_DETACH) == 0)
1777 bfe_init_locked(sc);
1778 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1779 bfe_stop(sc);
1780 BFE_UNLOCK(sc);
1781 break;
1782 case SIOCADDMULTI:
1783 case SIOCDELMULTI:
1784 BFE_LOCK(sc);
1785 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1786 bfe_set_rx_mode(sc);
1787 BFE_UNLOCK(sc);
1788 break;
1789 case SIOCGIFMEDIA:
1790 case SIOCSIFMEDIA:
1791 mii = device_get_softc(sc->bfe_miibus);
1792 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1793 break;
1794 default:
1795 error = ether_ioctl(ifp, command, data);
1796 break;
1797 }
1798
1799 return (error);
1800 }
1801
1802 static void
bfe_watchdog(struct bfe_softc * sc)1803 bfe_watchdog(struct bfe_softc *sc)
1804 {
1805 if_t ifp;
1806
1807 BFE_LOCK_ASSERT(sc);
1808
1809 if (sc->bfe_watchdog_timer == 0 || --sc->bfe_watchdog_timer)
1810 return;
1811
1812 ifp = sc->bfe_ifp;
1813
1814 device_printf(sc->bfe_dev, "watchdog timeout -- resetting\n");
1815
1816 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1817 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1818 bfe_init_locked(sc);
1819
1820 if (!if_sendq_empty(ifp))
1821 bfe_start_locked(ifp);
1822 }
1823
1824 static void
bfe_tick(void * xsc)1825 bfe_tick(void *xsc)
1826 {
1827 struct bfe_softc *sc = xsc;
1828 struct mii_data *mii;
1829
1830 BFE_LOCK_ASSERT(sc);
1831
1832 mii = device_get_softc(sc->bfe_miibus);
1833 mii_tick(mii);
1834 bfe_stats_update(sc);
1835 bfe_watchdog(sc);
1836 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc);
1837 }
1838
1839 /*
1840 * Stop the adapter and free any mbufs allocated to the
1841 * RX and TX lists.
1842 */
1843 static void
bfe_stop(struct bfe_softc * sc)1844 bfe_stop(struct bfe_softc *sc)
1845 {
1846 if_t ifp;
1847
1848 BFE_LOCK_ASSERT(sc);
1849
1850 ifp = sc->bfe_ifp;
1851 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
1852 sc->bfe_flags &= ~BFE_FLAG_LINK;
1853 callout_stop(&sc->bfe_stat_co);
1854 sc->bfe_watchdog_timer = 0;
1855
1856 bfe_chip_halt(sc);
1857 bfe_tx_ring_free(sc);
1858 bfe_rx_ring_free(sc);
1859 }
1860
1861 static int
sysctl_bfe_stats(SYSCTL_HANDLER_ARGS)1862 sysctl_bfe_stats(SYSCTL_HANDLER_ARGS)
1863 {
1864 struct bfe_softc *sc;
1865 struct bfe_hw_stats *stats;
1866 int error, result;
1867
1868 result = -1;
1869 error = sysctl_handle_int(oidp, &result, 0, req);
1870
1871 if (error != 0 || req->newptr == NULL)
1872 return (error);
1873
1874 if (result != 1)
1875 return (error);
1876
1877 sc = (struct bfe_softc *)arg1;
1878 stats = &sc->bfe_stats;
1879
1880 printf("%s statistics:\n", device_get_nameunit(sc->bfe_dev));
1881 printf("Transmit good octets : %ju\n",
1882 (uintmax_t)stats->tx_good_octets);
1883 printf("Transmit good frames : %ju\n",
1884 (uintmax_t)stats->tx_good_frames);
1885 printf("Transmit octets : %ju\n",
1886 (uintmax_t)stats->tx_octets);
1887 printf("Transmit frames : %ju\n",
1888 (uintmax_t)stats->tx_frames);
1889 printf("Transmit broadcast frames : %ju\n",
1890 (uintmax_t)stats->tx_bcast_frames);
1891 printf("Transmit multicast frames : %ju\n",
1892 (uintmax_t)stats->tx_mcast_frames);
1893 printf("Transmit frames 64 bytes : %ju\n",
1894 (uint64_t)stats->tx_pkts_64);
1895 printf("Transmit frames 65 to 127 bytes : %ju\n",
1896 (uint64_t)stats->tx_pkts_65_127);
1897 printf("Transmit frames 128 to 255 bytes : %ju\n",
1898 (uint64_t)stats->tx_pkts_128_255);
1899 printf("Transmit frames 256 to 511 bytes : %ju\n",
1900 (uint64_t)stats->tx_pkts_256_511);
1901 printf("Transmit frames 512 to 1023 bytes : %ju\n",
1902 (uint64_t)stats->tx_pkts_512_1023);
1903 printf("Transmit frames 1024 to max bytes : %ju\n",
1904 (uint64_t)stats->tx_pkts_1024_max);
1905 printf("Transmit jabber errors : %u\n", stats->tx_jabbers);
1906 printf("Transmit oversized frames : %ju\n",
1907 (uint64_t)stats->tx_oversize_frames);
1908 printf("Transmit fragmented frames : %ju\n",
1909 (uint64_t)stats->tx_frag_frames);
1910 printf("Transmit underruns : %u\n", stats->tx_colls);
1911 printf("Transmit total collisions : %u\n", stats->tx_single_colls);
1912 printf("Transmit single collisions : %u\n", stats->tx_single_colls);
1913 printf("Transmit multiple collisions : %u\n", stats->tx_multi_colls);
1914 printf("Transmit excess collisions : %u\n", stats->tx_excess_colls);
1915 printf("Transmit late collisions : %u\n", stats->tx_late_colls);
1916 printf("Transmit deferrals : %u\n", stats->tx_deferrals);
1917 printf("Transmit carrier losts : %u\n", stats->tx_carrier_losts);
1918 printf("Transmit pause frames : %u\n", stats->tx_pause_frames);
1919
1920 printf("Receive good octets : %ju\n",
1921 (uintmax_t)stats->rx_good_octets);
1922 printf("Receive good frames : %ju\n",
1923 (uintmax_t)stats->rx_good_frames);
1924 printf("Receive octets : %ju\n",
1925 (uintmax_t)stats->rx_octets);
1926 printf("Receive frames : %ju\n",
1927 (uintmax_t)stats->rx_frames);
1928 printf("Receive broadcast frames : %ju\n",
1929 (uintmax_t)stats->rx_bcast_frames);
1930 printf("Receive multicast frames : %ju\n",
1931 (uintmax_t)stats->rx_mcast_frames);
1932 printf("Receive frames 64 bytes : %ju\n",
1933 (uint64_t)stats->rx_pkts_64);
1934 printf("Receive frames 65 to 127 bytes : %ju\n",
1935 (uint64_t)stats->rx_pkts_65_127);
1936 printf("Receive frames 128 to 255 bytes : %ju\n",
1937 (uint64_t)stats->rx_pkts_128_255);
1938 printf("Receive frames 256 to 511 bytes : %ju\n",
1939 (uint64_t)stats->rx_pkts_256_511);
1940 printf("Receive frames 512 to 1023 bytes : %ju\n",
1941 (uint64_t)stats->rx_pkts_512_1023);
1942 printf("Receive frames 1024 to max bytes : %ju\n",
1943 (uint64_t)stats->rx_pkts_1024_max);
1944 printf("Receive jabber errors : %u\n", stats->rx_jabbers);
1945 printf("Receive oversized frames : %ju\n",
1946 (uint64_t)stats->rx_oversize_frames);
1947 printf("Receive fragmented frames : %ju\n",
1948 (uint64_t)stats->rx_frag_frames);
1949 printf("Receive missed frames : %u\n", stats->rx_missed_frames);
1950 printf("Receive CRC align errors : %u\n", stats->rx_crc_align_errs);
1951 printf("Receive undersized frames : %u\n", stats->rx_runts);
1952 printf("Receive CRC errors : %u\n", stats->rx_crc_errs);
1953 printf("Receive align errors : %u\n", stats->rx_align_errs);
1954 printf("Receive symbol errors : %u\n", stats->rx_symbol_errs);
1955 printf("Receive pause frames : %u\n", stats->rx_pause_frames);
1956 printf("Receive control frames : %u\n", stats->rx_control_frames);
1957
1958 return (error);
1959 }
1960