1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 1998 - 2008 Søren Schmidt <[email protected]>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification, immediately at the beginning of the file.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 #include <sys/param.h>
31 #include <sys/module.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/ata.h>
35 #include <sys/bus.h>
36 #include <sys/endian.h>
37 #include <sys/malloc.h>
38 #include <sys/lock.h>
39 #include <sys/mutex.h>
40 #include <sys/sema.h>
41 #include <sys/taskqueue.h>
42 #include <vm/uma.h>
43 #include <machine/stdarg.h>
44 #include <machine/resource.h>
45 #include <machine/bus.h>
46 #include <sys/rman.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
49 #include <dev/ata/ata-all.h>
50 #include <dev/ata/ata-pci.h>
51 #include <ata_if.h>
52
53 /* local prototypes */
54 static int ata_serverworks_chipinit(device_t dev);
55 static int ata_serverworks_ch_attach(device_t dev);
56 static int ata_serverworks_ch_detach(device_t dev);
57 static void ata_serverworks_tf_read(struct ata_request *request);
58 static void ata_serverworks_tf_write(struct ata_request *request);
59 static int ata_serverworks_setmode(device_t dev, int target, int mode);
60 static void ata_serverworks_sata_reset(device_t dev);
61 static int ata_serverworks_status(device_t dev);
62
63 /* misc defines */
64 #define SWKS_33 0
65 #define SWKS_66 1
66 #define SWKS_100 2
67 #define SWKS_MIO 3
68
69 /*
70 * ServerWorks chipset support functions
71 */
72 static int
ata_serverworks_probe(device_t dev)73 ata_serverworks_probe(device_t dev)
74 {
75 struct ata_pci_controller *ctlr = device_get_softc(dev);
76 static const struct ata_chip_id ids[] =
77 {{ ATA_ROSB4, 0x00, SWKS_33, 0, ATA_WDMA2, "ROSB4" },
78 { ATA_CSB5, 0x92, SWKS_100, 0, ATA_UDMA5, "CSB5" },
79 { ATA_CSB5, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB5" },
80 { ATA_CSB6, 0x00, SWKS_100, 0, ATA_UDMA5, "CSB6" },
81 { ATA_CSB6_1, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB6" },
82 { ATA_HT1000, 0x00, SWKS_100, 0, ATA_UDMA5, "HT1000" },
83 { ATA_HT1000_S1, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" },
84 { ATA_HT1000_S2, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" },
85 { ATA_K2, 0x00, SWKS_MIO, 4, ATA_SA150, "K2" },
86 { ATA_FRODO4, 0x00, SWKS_MIO, 4, ATA_SA150, "Frodo4" },
87 { ATA_FRODO8, 0x00, SWKS_MIO, 8, ATA_SA150, "Frodo8" },
88 { 0, 0, 0, 0, 0, 0}};
89
90 if (pci_get_vendor(dev) != ATA_SERVERWORKS_ID)
91 return ENXIO;
92
93 if (!(ctlr->chip = ata_match_chip(dev, ids)))
94 return ENXIO;
95
96 ata_set_desc(dev);
97 ctlr->chipinit = ata_serverworks_chipinit;
98 return (BUS_PROBE_LOW_PRIORITY);
99 }
100
101 static int
ata_serverworks_status(device_t dev)102 ata_serverworks_status(device_t dev)
103 {
104 struct ata_channel *ch = device_get_softc(dev);
105 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
106
107 /*
108 * Check if this interrupt belongs to our channel.
109 */
110 if (!(ATA_INL(ctlr->r_res2, 0x1f80) & (1 << ch->unit)))
111 return (0);
112
113 /*
114 * We need to do a 4-byte read on the status reg before the values
115 * will report correctly
116 */
117
118 ATA_IDX_INL(ch,ATA_STATUS);
119
120 return ata_pci_status(dev);
121 }
122
123 static int
ata_serverworks_chipinit(device_t dev)124 ata_serverworks_chipinit(device_t dev)
125 {
126 struct ata_pci_controller *ctlr = device_get_softc(dev);
127
128 if (ata_setup_interrupt(dev, ata_generic_intr))
129 return ENXIO;
130
131 if (ctlr->chip->cfg1 == SWKS_MIO) {
132 ctlr->r_type2 = SYS_RES_MEMORY;
133 ctlr->r_rid2 = PCIR_BAR(5);
134 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
135 &ctlr->r_rid2, RF_ACTIVE)))
136 return ENXIO;
137
138 ctlr->channels = ctlr->chip->cfg2;
139 ctlr->ch_attach = ata_serverworks_ch_attach;
140 ctlr->ch_detach = ata_serverworks_ch_detach;
141 ctlr->setmode = ata_sata_setmode;
142 ctlr->getrev = ata_sata_getrev;
143 ctlr->reset = ata_serverworks_sata_reset;
144 return 0;
145 }
146 else if (ctlr->chip->cfg1 == SWKS_33) {
147 device_t *children;
148 int nchildren, i;
149
150 /* locate the ISA part in the southbridge and enable UDMA33 */
151 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
152 for (i = 0; i < nchildren; i++) {
153 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) {
154 pci_write_config(children[i], 0x64,
155 (pci_read_config(children[i], 0x64, 4) &
156 ~0x00002000) | 0x00004000, 4);
157 break;
158 }
159 }
160 free(children, M_TEMP);
161 }
162 }
163 else {
164 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x40) |
165 ((ctlr->chip->cfg1 == SWKS_100) ? 0x03 : 0x02), 1);
166 }
167 ctlr->setmode = ata_serverworks_setmode;
168 return 0;
169 }
170
171 static int
ata_serverworks_ch_attach(device_t dev)172 ata_serverworks_ch_attach(device_t dev)
173 {
174 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
175 struct ata_channel *ch = device_get_softc(dev);
176 int ch_offset;
177 int i;
178
179 ch_offset = ch->unit * 0x100;
180
181 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
182 ch->r_io[i].res = ctlr->r_res2;
183
184 /* setup ATA registers */
185 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
186 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04;
187 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
188 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
189 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
190 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
191 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
192 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c;
193 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20;
194 ata_default_registers(dev);
195
196 /* setup DMA registers */
197 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30;
198 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32;
199 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34;
200
201 /* setup SATA registers */
202 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40;
203 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44;
204 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48;
205
206 ch->flags |= ATA_NO_SLAVE | ATA_SATA | ATA_KNOWN_PRESENCE;
207 ata_pci_hw(dev);
208 ch->hw.tf_read = ata_serverworks_tf_read;
209 ch->hw.tf_write = ata_serverworks_tf_write;
210
211 if (ctlr->chip->chipid == ATA_K2) {
212 /*
213 * Set SICR registers to turn off waiting for a status message
214 * before sending FIS. Values obtained from the Darwin driver.
215 */
216
217 ATA_OUTL(ctlr->r_res2, ch_offset + 0x80,
218 ATA_INL(ctlr->r_res2, ch_offset + 0x80) & ~0x00040000);
219 ATA_OUTL(ctlr->r_res2, ch_offset + 0x88, 0);
220
221 /*
222 * Some controllers have a bug where they will send the command
223 * to the drive before seeing a DMA start, and then can begin
224 * receiving data before the DMA start arrives. The controller
225 * will then become confused and either corrupt the data or crash.
226 * Remedy this by starting DMA before sending the drive command.
227 */
228
229 ch->flags |= ATA_DMA_BEFORE_CMD;
230
231 /*
232 * The status register must be read as a long to fill the other
233 * registers.
234 */
235
236 ch->hw.status = ata_serverworks_status;
237 ch->flags |= ATA_STATUS_IS_LONG;
238 }
239
240 /* chip does not reliably do 64K DMA transfers */
241 ch->dma.max_iosize = 64 * DEV_BSIZE;
242
243 ata_pci_dmainit(dev);
244
245 return 0;
246 }
247
248 static int
ata_serverworks_ch_detach(device_t dev)249 ata_serverworks_ch_detach(device_t dev)
250 {
251
252 ata_pci_dmafini(dev);
253 return (0);
254 }
255
256 static void
ata_serverworks_tf_read(struct ata_request * request)257 ata_serverworks_tf_read(struct ata_request *request)
258 {
259 struct ata_channel *ch = device_get_softc(request->parent);
260
261 if (request->flags & ATA_R_48BIT) {
262 u_int16_t temp;
263
264 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT);
265 temp = ATA_IDX_INW(ch, ATA_SECTOR);
266 request->u.ata.lba = (u_int64_t)(temp & 0x00ff) |
267 ((u_int64_t)(temp & 0xff00) << 24);
268 temp = ATA_IDX_INW(ch, ATA_CYL_LSB);
269 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 8) |
270 ((u_int64_t)(temp & 0xff00) << 32);
271 temp = ATA_IDX_INW(ch, ATA_CYL_MSB);
272 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 16) |
273 ((u_int64_t)(temp & 0xff00) << 40);
274 }
275 else {
276 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT) & 0x00ff;
277 request->u.ata.lba = (ATA_IDX_INW(ch, ATA_SECTOR) & 0x00ff) |
278 ((ATA_IDX_INW(ch, ATA_CYL_LSB) & 0x00ff) << 8) |
279 ((ATA_IDX_INW(ch, ATA_CYL_MSB) & 0x00ff) << 16) |
280 ((ATA_IDX_INW(ch, ATA_DRIVE) & 0xf) << 24);
281 }
282 }
283
284 static void
ata_serverworks_tf_write(struct ata_request * request)285 ata_serverworks_tf_write(struct ata_request *request)
286 {
287 struct ata_channel *ch = device_get_softc(request->parent);
288
289 if (request->flags & ATA_R_48BIT) {
290 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
291 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
292 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) |
293 (request->u.ata.lba & 0x00ff));
294 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) |
295 ((request->u.ata.lba >> 8) & 0x00ff));
296 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) |
297 ((request->u.ata.lba >> 16) & 0x00ff));
298 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit));
299 }
300 else {
301 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
302 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
303 ATA_IDX_OUTW(ch, ATA_SECTOR, request->u.ata.lba);
304 ATA_IDX_OUTW(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
305 ATA_IDX_OUTW(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
306 ATA_IDX_OUTW(ch, ATA_DRIVE,
307 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) |
308 ((request->u.ata.lba >> 24) & 0x0f));
309 }
310 }
311
312 static int
ata_serverworks_setmode(device_t dev,int target,int mode)313 ata_serverworks_setmode(device_t dev, int target, int mode)
314 {
315 device_t parent = device_get_parent(dev);
316 struct ata_pci_controller *ctlr = device_get_softc(parent);
317 struct ata_channel *ch = device_get_softc(dev);
318 int devno = (ch->unit << 1) + target;
319 int offset = (devno ^ 0x01) << 3;
320 int piomode;
321 static const uint8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
322 static const uint8_t dmatimings[] = { 0x77, 0x21, 0x20 };
323
324 mode = min(mode, ctlr->chip->max_dma);
325 if (mode >= ATA_UDMA0) {
326 /* Set UDMA mode, enable UDMA, set WDMA2/PIO4 */
327 pci_write_config(parent, 0x56,
328 (pci_read_config(parent, 0x56, 2) &
329 ~(0xf << (devno << 2))) |
330 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
331 pci_write_config(parent, 0x54,
332 pci_read_config(parent, 0x54, 1) |
333 (0x01 << devno), 1);
334 pci_write_config(parent, 0x44,
335 (pci_read_config(parent, 0x44, 4) &
336 ~(0xff << offset)) |
337 (dmatimings[2] << offset), 4);
338 piomode = ATA_PIO4;
339 } else if (mode >= ATA_WDMA0) {
340 /* Disable UDMA, set WDMA mode and timings, calculate PIO. */
341 pci_write_config(parent, 0x54,
342 pci_read_config(parent, 0x54, 1) &
343 ~(0x01 << devno), 1);
344 pci_write_config(parent, 0x44,
345 (pci_read_config(parent, 0x44, 4) &
346 ~(0xff << offset)) |
347 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
348 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 :
349 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4;
350 } else {
351 /* Disable UDMA, set requested PIO. */
352 pci_write_config(parent, 0x54,
353 pci_read_config(parent, 0x54, 1) &
354 ~(0x01 << devno), 1);
355 piomode = mode;
356 }
357 /* Set PIO mode and timings, calculated above. */
358 if (ctlr->chip->cfg1 != SWKS_33) {
359 pci_write_config(parent, 0x4a,
360 (pci_read_config(parent, 0x4a, 2) &
361 ~(0xf << (devno << 2))) |
362 ((piomode - ATA_PIO0) << (devno<<2)),2);
363 }
364 pci_write_config(parent, 0x40,
365 (pci_read_config(parent, 0x40, 4) &
366 ~(0xff << offset)) |
367 (piotimings[ata_mode2idx(piomode)] << offset), 4);
368 return (mode);
369 }
370
371 static void
ata_serverworks_sata_reset(device_t dev)372 ata_serverworks_sata_reset(device_t dev)
373 {
374 struct ata_channel *ch = device_get_softc(dev);
375
376 if (ata_sata_phy_reset(dev, -1, 0))
377 ata_generic_reset(dev);
378 else
379 ch->devices = 0;
380 }
381
382 ATA_DECLARE_DRIVER(ata_serverworks);
383