1 /*-
2 * Copyright (c) 2000 Matthew C. Forman
3 *
4 * Based (heavily) on alpm.c which is:
5 *
6 * Copyright (c) 1998, 1999 Nicolas Souchu
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 /*
32 * Power management function/SMBus function support for the AMD 756 chip.
33 */
34
35 #include <sys/cdefs.h>
36 #include <sys/param.h>
37 #include <sys/bus.h>
38 #include <sys/kernel.h>
39 #include <sys/lock.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
42 #include <sys/systm.h>
43
44 #include <machine/bus.h>
45 #include <machine/resource.h>
46 #include <sys/rman.h>
47
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcireg.h>
50
51 #include <dev/smbus/smbconf.h>
52 #include "smbus_if.h"
53
54 #define AMDPM_DEBUG(x) if (amdpm_debug) (x)
55
56 #ifdef DEBUG
57 static int amdpm_debug = 1;
58 #else
59 static int amdpm_debug = 0;
60 #endif
61
62 #define AMDPM_VENDORID_AMD 0x1022
63 #define AMDPM_DEVICEID_AMD756PM 0x740b
64 #define AMDPM_DEVICEID_AMD766PM 0x7413
65 #define AMDPM_DEVICEID_AMD768PM 0x7443
66 #define AMDPM_DEVICEID_AMD8111PM 0x746B
67
68 #define AMDPM_VENDORID_HYGON 0x1d94
69
70 /* nVidia nForce chipset */
71 #define AMDPM_VENDORID_NVIDIA 0x10de
72 #define AMDPM_DEVICEID_NF_SMB 0x01b4
73
74 /* PCI Configuration space registers */
75 #define AMDPCI_PMBASE 0x58
76 #define NFPCI_PMBASE 0x14
77
78 #define AMDPCI_GEN_CONFIG_PM 0x41
79 #define AMDPCI_PMIOEN (1<<7)
80
81 #define AMDPCI_SCIINT_CONFIG_PM 0x42
82 #define AMDPCI_SCISEL_IRQ11 11
83
84 #define AMDPCI_REVID 0x08
85
86 /*
87 * I/O registers.
88 * Base address programmed via AMDPCI_PMBASE.
89 */
90
91 #define AMDSMB_GLOBAL_STATUS (0x00)
92 #define AMDSMB_GS_TO_STS (1<<5)
93 #define AMDSMB_GS_HCYC_STS (1<<4)
94 #define AMDSMB_GS_HST_STS (1<<3)
95 #define AMDSMB_GS_PRERR_STS (1<<2)
96 #define AMDSMB_GS_COL_STS (1<<1)
97 #define AMDSMB_GS_ABRT_STS (1<<0)
98 #define AMDSMB_GS_CLEAR_STS (AMDSMB_GS_TO_STS|AMDSMB_GS_HCYC_STS|AMDSMB_GS_PRERR_STS|AMDSMB_GS_COL_STS|AMDSMB_GS_ABRT_STS)
99
100 #define AMDSMB_GLOBAL_ENABLE (0x02)
101 #define AMDSMB_GE_ABORT (1<<5)
102 #define AMDSMB_GE_HCYC_EN (1<<4)
103 #define AMDSMB_GE_HOST_STC (1<<3)
104 #define AMDSMB_GE_CYC_QUICK 0
105 #define AMDSMB_GE_CYC_BYTE 1
106 #define AMDSMB_GE_CYC_BDATA 2
107 #define AMDSMB_GE_CYC_WDATA 3
108 #define AMDSMB_GE_CYC_PROCCALL 4
109 #define AMDSMB_GE_CYC_BLOCK 5
110
111 #define LSB 0x1 /* XXX: Better name: Read/Write? */
112
113 #define AMDSMB_HSTADDR (0x04)
114 #define AMDSMB_HSTDATA (0x06)
115 #define AMDSMB_HSTCMD (0x08)
116 #define AMDSMB_HSTDFIFO (0x09)
117 #define AMDSMB_HSLVDATA (0x0A)
118 #define AMDSMB_HSLVDA (0x0C)
119 #define AMDSMB_HSLVDDR (0x0E)
120 #define AMDSMB_SNPADDR (0x0F)
121
122 struct amdpm_softc {
123 int base;
124 int rid;
125 struct resource *res;
126 device_t smbus;
127 struct mtx lock;
128 };
129
130 #define AMDPM_LOCK(amdpm) mtx_lock(&(amdpm)->lock)
131 #define AMDPM_UNLOCK(amdpm) mtx_unlock(&(amdpm)->lock)
132 #define AMDPM_LOCK_ASSERT(amdpm) mtx_assert(&(amdpm)->lock, MA_OWNED)
133
134 #define AMDPM_SMBINB(amdpm,register) \
135 (bus_read_1(amdpm->res, register))
136 #define AMDPM_SMBOUTB(amdpm,register,value) \
137 (bus_write_1(amdpm->res, register, value))
138 #define AMDPM_SMBINW(amdpm,register) \
139 (bus_read_2(amdpm->res, register))
140 #define AMDPM_SMBOUTW(amdpm,register,value) \
141 (bus_write_2(amdpm->res, register, value))
142
143 static int amdpm_detach(device_t dev);
144
145 static int
amdpm_probe(device_t dev)146 amdpm_probe(device_t dev)
147 {
148 u_long base;
149 u_int16_t vid;
150 u_int16_t did;
151
152 vid = pci_get_vendor(dev);
153 did = pci_get_device(dev);
154 if ((vid == AMDPM_VENDORID_AMD) &&
155 ((did == AMDPM_DEVICEID_AMD756PM) ||
156 (did == AMDPM_DEVICEID_AMD766PM) ||
157 (did == AMDPM_DEVICEID_AMD768PM) ||
158 (did == AMDPM_DEVICEID_AMD8111PM))) {
159 device_set_desc(dev, "AMD 756/766/768/8111 Power Management Controller");
160
161 /*
162 * We have to do this, since the BIOS won't give us the
163 * resource info (not mine, anyway).
164 */
165 base = pci_read_config(dev, AMDPCI_PMBASE, 4);
166 base &= 0xff00;
167 bus_set_resource(dev, SYS_RES_IOPORT, AMDPCI_PMBASE,
168 base+0xe0, 32);
169 return (BUS_PROBE_DEFAULT);
170 }
171
172 if ((vid == AMDPM_VENDORID_NVIDIA) &&
173 (did == AMDPM_DEVICEID_NF_SMB)) {
174 device_set_desc(dev, "nForce SMBus Controller");
175
176 /*
177 * We have to do this, since the BIOS won't give us the
178 * resource info (not mine, anyway).
179 */
180 base = pci_read_config(dev, NFPCI_PMBASE, 4);
181 base &= 0xff00;
182 bus_set_resource(dev, SYS_RES_IOPORT, NFPCI_PMBASE,
183 base, 32);
184
185 return (BUS_PROBE_DEFAULT);
186 }
187
188 return ENXIO;
189 }
190
191 static int
amdpm_attach(device_t dev)192 amdpm_attach(device_t dev)
193 {
194 struct amdpm_softc *amdpm_sc = device_get_softc(dev);
195 u_char val_b;
196
197 /* Enable I/O block access */
198 val_b = pci_read_config(dev, AMDPCI_GEN_CONFIG_PM, 1);
199 pci_write_config(dev, AMDPCI_GEN_CONFIG_PM, val_b | AMDPCI_PMIOEN, 1);
200
201 /* Allocate I/O space */
202 if (pci_get_vendor(dev) == AMDPM_VENDORID_AMD ||
203 pci_get_vendor(dev) == AMDPM_VENDORID_HYGON)
204 amdpm_sc->rid = AMDPCI_PMBASE;
205 else
206 amdpm_sc->rid = NFPCI_PMBASE;
207 amdpm_sc->res = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
208 &amdpm_sc->rid, RF_ACTIVE);
209
210 if (amdpm_sc->res == NULL) {
211 device_printf(dev, "could not map i/o space\n");
212 return (ENXIO);
213 }
214
215 mtx_init(&amdpm_sc->lock, device_get_nameunit(dev), "amdpm", MTX_DEF);
216
217 /* Allocate a new smbus device */
218 amdpm_sc->smbus = device_add_child(dev, "smbus", -1);
219 if (!amdpm_sc->smbus) {
220 amdpm_detach(dev);
221 return (EINVAL);
222 }
223
224 bus_generic_attach(dev);
225
226 return (0);
227 }
228
229 static int
amdpm_detach(device_t dev)230 amdpm_detach(device_t dev)
231 {
232 struct amdpm_softc *amdpm_sc = device_get_softc(dev);
233
234 if (amdpm_sc->smbus) {
235 device_delete_child(dev, amdpm_sc->smbus);
236 amdpm_sc->smbus = NULL;
237 }
238
239 mtx_destroy(&amdpm_sc->lock);
240 if (amdpm_sc->res)
241 bus_release_resource(dev, SYS_RES_IOPORT, amdpm_sc->rid,
242 amdpm_sc->res);
243
244 return (0);
245 }
246
247 static int
amdpm_callback(device_t dev,int index,void * data)248 amdpm_callback(device_t dev, int index, void *data)
249 {
250 int error = 0;
251
252 switch (index) {
253 case SMB_REQUEST_BUS:
254 case SMB_RELEASE_BUS:
255 break;
256 default:
257 error = EINVAL;
258 }
259
260 return (error);
261 }
262
263 static int
amdpm_clear(struct amdpm_softc * sc)264 amdpm_clear(struct amdpm_softc *sc)
265 {
266
267 AMDPM_LOCK_ASSERT(sc);
268 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_STATUS, AMDSMB_GS_CLEAR_STS);
269 DELAY(10);
270
271 return (0);
272 }
273
274 #if 0
275 static int
276 amdpm_abort(struct amdpm_softc *sc)
277 {
278 u_short l;
279
280 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
281 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, l | AMDSMB_GE_ABORT);
282
283 return (0);
284 }
285 #endif
286
287 static int
amdpm_idle(struct amdpm_softc * sc)288 amdpm_idle(struct amdpm_softc *sc)
289 {
290 u_short sts;
291
292 AMDPM_LOCK_ASSERT(sc);
293 sts = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_STATUS);
294
295 AMDPM_DEBUG(printf("amdpm: busy? STS=0x%x\n", sts));
296
297 return (~(sts & AMDSMB_GS_HST_STS));
298 }
299
300 /*
301 * Poll the SMBus controller
302 */
303 static int
amdpm_wait(struct amdpm_softc * sc)304 amdpm_wait(struct amdpm_softc *sc)
305 {
306 int count = 10000;
307 u_short sts = 0;
308 int error;
309
310 AMDPM_LOCK_ASSERT(sc);
311 /* Wait for command to complete (SMBus controller is idle) */
312 while(count--) {
313 DELAY(10);
314 sts = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_STATUS);
315 if (!(sts & AMDSMB_GS_HST_STS))
316 break;
317 }
318
319 AMDPM_DEBUG(printf("amdpm: STS=0x%x (count=%d)\n", sts, count));
320
321 error = SMB_ENOERR;
322
323 if (!count)
324 error |= SMB_ETIMEOUT;
325
326 if (sts & AMDSMB_GS_ABRT_STS)
327 error |= SMB_EABORT;
328
329 if (sts & AMDSMB_GS_COL_STS)
330 error |= SMB_ENOACK;
331
332 if (sts & AMDSMB_GS_PRERR_STS)
333 error |= SMB_EBUSERR;
334
335 if (error != SMB_ENOERR)
336 amdpm_clear(sc);
337
338 return (error);
339 }
340
341 static int
amdpm_quick(device_t dev,u_char slave,int how)342 amdpm_quick(device_t dev, u_char slave, int how)
343 {
344 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
345 int error;
346 u_short l;
347
348 AMDPM_LOCK(sc);
349 amdpm_clear(sc);
350 if (!amdpm_idle(sc)) {
351 AMDPM_UNLOCK(sc);
352 return (EBUSY);
353 }
354
355 switch (how) {
356 case SMB_QWRITE:
357 AMDPM_DEBUG(printf("amdpm: QWRITE to 0x%x", slave));
358 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
359 break;
360 case SMB_QREAD:
361 AMDPM_DEBUG(printf("amdpm: QREAD to 0x%x", slave));
362 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
363 break;
364 default:
365 panic("%s: unknown QUICK command (%x)!", __func__, how);
366 }
367 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
368 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_QUICK | AMDSMB_GE_HOST_STC);
369
370 error = amdpm_wait(sc);
371
372 AMDPM_DEBUG(printf(", error=0x%x\n", error));
373 AMDPM_UNLOCK(sc);
374
375 return (error);
376 }
377
378 static int
amdpm_sendb(device_t dev,u_char slave,char byte)379 amdpm_sendb(device_t dev, u_char slave, char byte)
380 {
381 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
382 int error;
383 u_short l;
384
385 AMDPM_LOCK(sc);
386 amdpm_clear(sc);
387 if (!amdpm_idle(sc)) {
388 AMDPM_UNLOCK(sc);
389 return (SMB_EBUSY);
390 }
391
392 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
393 AMDPM_SMBOUTW(sc, AMDSMB_HSTDATA, byte);
394 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
395 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BYTE | AMDSMB_GE_HOST_STC);
396
397 error = amdpm_wait(sc);
398
399 AMDPM_DEBUG(printf("amdpm: SENDB to 0x%x, byte=0x%x, error=0x%x\n", slave, byte, error));
400 AMDPM_UNLOCK(sc);
401
402 return (error);
403 }
404
405 static int
amdpm_recvb(device_t dev,u_char slave,char * byte)406 amdpm_recvb(device_t dev, u_char slave, char *byte)
407 {
408 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
409 int error;
410 u_short l;
411
412 AMDPM_LOCK(sc);
413 amdpm_clear(sc);
414 if (!amdpm_idle(sc)) {
415 AMDPM_UNLOCK(sc);
416 return (SMB_EBUSY);
417 }
418
419 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
420 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
421 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BYTE | AMDSMB_GE_HOST_STC);
422
423 if ((error = amdpm_wait(sc)) == SMB_ENOERR)
424 *byte = AMDPM_SMBINW(sc, AMDSMB_HSTDATA);
425
426 AMDPM_DEBUG(printf("amdpm: RECVB from 0x%x, byte=0x%x, error=0x%x\n", slave, *byte, error));
427 AMDPM_UNLOCK(sc);
428
429 return (error);
430 }
431
432 static int
amdpm_writeb(device_t dev,u_char slave,char cmd,char byte)433 amdpm_writeb(device_t dev, u_char slave, char cmd, char byte)
434 {
435 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
436 int error;
437 u_short l;
438
439 AMDPM_LOCK(sc);
440 amdpm_clear(sc);
441 if (!amdpm_idle(sc)) {
442 AMDPM_UNLOCK(sc);
443 return (SMB_EBUSY);
444 }
445
446 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
447 AMDPM_SMBOUTW(sc, AMDSMB_HSTDATA, byte);
448 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
449 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
450 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BDATA | AMDSMB_GE_HOST_STC);
451
452 error = amdpm_wait(sc);
453
454 AMDPM_DEBUG(printf("amdpm: WRITEB to 0x%x, cmd=0x%x, byte=0x%x, error=0x%x\n", slave, cmd, byte, error));
455 AMDPM_UNLOCK(sc);
456
457 return (error);
458 }
459
460 static int
amdpm_readb(device_t dev,u_char slave,char cmd,char * byte)461 amdpm_readb(device_t dev, u_char slave, char cmd, char *byte)
462 {
463 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
464 int error;
465 u_short l;
466
467 AMDPM_LOCK(sc);
468 amdpm_clear(sc);
469 if (!amdpm_idle(sc)) {
470 AMDPM_UNLOCK(sc);
471 return (SMB_EBUSY);
472 }
473
474 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
475 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
476 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
477 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BDATA | AMDSMB_GE_HOST_STC);
478
479 if ((error = amdpm_wait(sc)) == SMB_ENOERR)
480 *byte = AMDPM_SMBINW(sc, AMDSMB_HSTDATA);
481
482 AMDPM_DEBUG(printf("amdpm: READB from 0x%x, cmd=0x%x, byte=0x%x, error=0x%x\n", slave, cmd, *byte, error));
483 AMDPM_UNLOCK(sc);
484
485 return (error);
486 }
487
488 static int
amdpm_writew(device_t dev,u_char slave,char cmd,short word)489 amdpm_writew(device_t dev, u_char slave, char cmd, short word)
490 {
491 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
492 int error;
493 u_short l;
494
495 AMDPM_LOCK(sc);
496 amdpm_clear(sc);
497 if (!amdpm_idle(sc)) {
498 AMDPM_UNLOCK(sc);
499 return (SMB_EBUSY);
500 }
501
502 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
503 AMDPM_SMBOUTW(sc, AMDSMB_HSTDATA, word);
504 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
505 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
506 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_WDATA | AMDSMB_GE_HOST_STC);
507
508 error = amdpm_wait(sc);
509
510 AMDPM_DEBUG(printf("amdpm: WRITEW to 0x%x, cmd=0x%x, word=0x%x, error=0x%x\n", slave, cmd, word, error));
511 AMDPM_UNLOCK(sc);
512
513 return (error);
514 }
515
516 static int
amdpm_readw(device_t dev,u_char slave,char cmd,short * word)517 amdpm_readw(device_t dev, u_char slave, char cmd, short *word)
518 {
519 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
520 int error;
521 u_short l;
522
523 AMDPM_LOCK(sc);
524 amdpm_clear(sc);
525 if (!amdpm_idle(sc)) {
526 AMDPM_UNLOCK(sc);
527 return (SMB_EBUSY);
528 }
529
530 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
531 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
532 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
533 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_WDATA | AMDSMB_GE_HOST_STC);
534
535 if ((error = amdpm_wait(sc)) == SMB_ENOERR)
536 *word = AMDPM_SMBINW(sc, AMDSMB_HSTDATA);
537
538 AMDPM_DEBUG(printf("amdpm: READW from 0x%x, cmd=0x%x, word=0x%x, error=0x%x\n", slave, cmd, *word, error));
539 AMDPM_UNLOCK(sc);
540
541 return (error);
542 }
543
544 static int
amdpm_bwrite(device_t dev,u_char slave,char cmd,u_char count,char * buf)545 amdpm_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf)
546 {
547 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
548 u_char i;
549 int error;
550 u_short l;
551
552 if (count < 1 || count > 32)
553 return (SMB_EINVAL);
554
555 AMDPM_LOCK(sc);
556 amdpm_clear(sc);
557 if (!amdpm_idle(sc)) {
558 AMDPM_UNLOCK(sc);
559 return (SMB_EBUSY);
560 }
561
562 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
563
564 /*
565 * Do we have to reset the internal 32-byte buffer?
566 * Can't see how to do this from the data sheet.
567 */
568 AMDPM_SMBOUTW(sc, AMDSMB_HSTDATA, count);
569
570 /* Fill the 32-byte internal buffer */
571 for (i = 0; i < count; i++) {
572 AMDPM_SMBOUTB(sc, AMDSMB_HSTDFIFO, buf[i]);
573 DELAY(2);
574 }
575 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
576 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
577 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE,
578 (l & 0xfff8) | AMDSMB_GE_CYC_BLOCK | AMDSMB_GE_HOST_STC);
579
580 error = amdpm_wait(sc);
581
582 AMDPM_DEBUG(printf("amdpm: WRITEBLK to 0x%x, count=0x%x, cmd=0x%x, error=0x%x", slave, count, cmd, error));
583 AMDPM_UNLOCK(sc);
584
585 return (error);
586 }
587
588 static int
amdpm_bread(device_t dev,u_char slave,char cmd,u_char * count,char * buf)589 amdpm_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf)
590 {
591 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
592 u_char data, len, i;
593 int error;
594 u_short l;
595
596 if (*count < 1 || *count > 32)
597 return (SMB_EINVAL);
598
599 AMDPM_LOCK(sc);
600 amdpm_clear(sc);
601 if (!amdpm_idle(sc)) {
602 AMDPM_UNLOCK(sc);
603 return (SMB_EBUSY);
604 }
605
606 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
607
608 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
609
610 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
611 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE,
612 (l & 0xfff8) | AMDSMB_GE_CYC_BLOCK | AMDSMB_GE_HOST_STC);
613
614 if ((error = amdpm_wait(sc)) != SMB_ENOERR)
615 goto error;
616
617 len = AMDPM_SMBINW(sc, AMDSMB_HSTDATA);
618
619 /* Read the 32-byte internal buffer */
620 for (i = 0; i < len; i++) {
621 data = AMDPM_SMBINB(sc, AMDSMB_HSTDFIFO);
622 if (i < *count)
623 buf[i] = data;
624 DELAY(2);
625 }
626 *count = len;
627
628 error:
629 AMDPM_DEBUG(printf("amdpm: READBLK to 0x%x, count=0x%x, cmd=0x%x, error=0x%x", slave, *count, cmd, error));
630 AMDPM_UNLOCK(sc);
631
632 return (error);
633 }
634
635 static device_method_t amdpm_methods[] = {
636 /* Device interface */
637 DEVMETHOD(device_probe, amdpm_probe),
638 DEVMETHOD(device_attach, amdpm_attach),
639 DEVMETHOD(device_detach, amdpm_detach),
640
641 /* SMBus interface */
642 DEVMETHOD(smbus_callback, amdpm_callback),
643 DEVMETHOD(smbus_quick, amdpm_quick),
644 DEVMETHOD(smbus_sendb, amdpm_sendb),
645 DEVMETHOD(smbus_recvb, amdpm_recvb),
646 DEVMETHOD(smbus_writeb, amdpm_writeb),
647 DEVMETHOD(smbus_readb, amdpm_readb),
648 DEVMETHOD(smbus_writew, amdpm_writew),
649 DEVMETHOD(smbus_readw, amdpm_readw),
650 DEVMETHOD(smbus_bwrite, amdpm_bwrite),
651 DEVMETHOD(smbus_bread, amdpm_bread),
652 { 0, 0 }
653 };
654
655 static driver_t amdpm_driver = {
656 "amdpm",
657 amdpm_methods,
658 sizeof(struct amdpm_softc),
659 };
660
661 DRIVER_MODULE(amdpm, pci, amdpm_driver, 0, 0);
662 DRIVER_MODULE(smbus, amdpm, smbus_driver, 0, 0);
663
664 MODULE_DEPEND(amdpm, pci, 1, 1, 1);
665 MODULE_DEPEND(amdpm, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER);
666 MODULE_VERSION(amdpm, 1);
667