1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008, Pyun YongHyeon <[email protected]> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 31 32 #include <sys/cdefs.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/malloc.h> 39 #include <sys/mbuf.h> 40 #include <sys/rman.h> 41 #include <sys/module.h> 42 #include <sys/queue.h> 43 #include <sys/socket.h> 44 #include <sys/sockio.h> 45 #include <sys/sysctl.h> 46 #include <sys/taskqueue.h> 47 48 #include <net/bpf.h> 49 #include <net/if.h> 50 #include <net/if_var.h> 51 #include <net/if_arp.h> 52 #include <net/ethernet.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 #include <net/if_vlan_var.h> 57 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/ip.h> 61 #include <netinet/tcp.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 69 #include <machine/bus.h> 70 #include <machine/in_cksum.h> 71 72 #include <dev/age/if_agereg.h> 73 #include <dev/age/if_agevar.h> 74 75 /* "device miibus" required. See GENERIC if you get errors here. */ 76 #include "miibus_if.h" 77 78 #define AGE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 79 80 MODULE_DEPEND(age, pci, 1, 1, 1); 81 MODULE_DEPEND(age, ether, 1, 1, 1); 82 MODULE_DEPEND(age, miibus, 1, 1, 1); 83 84 /* Tunables. */ 85 static int msi_disable = 0; 86 static int msix_disable = 0; 87 TUNABLE_INT("hw.age.msi_disable", &msi_disable); 88 TUNABLE_INT("hw.age.msix_disable", &msix_disable); 89 90 /* 91 * Devices supported by this driver. 92 */ 93 static struct age_dev { 94 uint16_t age_vendorid; 95 uint16_t age_deviceid; 96 const char *age_name; 97 } age_devs[] = { 98 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1, 99 "Attansic Technology Corp, L1 Gigabit Ethernet" }, 100 }; 101 102 static int age_miibus_readreg(device_t, int, int); 103 static int age_miibus_writereg(device_t, int, int, int); 104 static void age_miibus_statchg(device_t); 105 static void age_mediastatus(if_t, struct ifmediareq *); 106 static int age_mediachange(if_t); 107 static int age_probe(device_t); 108 static void age_get_macaddr(struct age_softc *); 109 static void age_phy_reset(struct age_softc *); 110 static int age_attach(device_t); 111 static int age_detach(device_t); 112 static void age_sysctl_node(struct age_softc *); 113 static void age_dmamap_cb(void *, bus_dma_segment_t *, int, int); 114 static int age_check_boundary(struct age_softc *); 115 static int age_dma_alloc(struct age_softc *); 116 static void age_dma_free(struct age_softc *); 117 static int age_shutdown(device_t); 118 static void age_setwol(struct age_softc *); 119 static int age_suspend(device_t); 120 static int age_resume(device_t); 121 static int age_encap(struct age_softc *, struct mbuf **); 122 static void age_start(if_t); 123 static void age_start_locked(if_t); 124 static void age_watchdog(struct age_softc *); 125 static int age_ioctl(if_t, u_long, caddr_t); 126 static void age_mac_config(struct age_softc *); 127 static void age_link_task(void *, int); 128 static void age_stats_update(struct age_softc *); 129 static int age_intr(void *); 130 static void age_int_task(void *, int); 131 static void age_txintr(struct age_softc *, int); 132 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 133 static int age_rxintr(struct age_softc *, int, int); 134 static void age_tick(void *); 135 static void age_reset(struct age_softc *); 136 static void age_init(void *); 137 static void age_init_locked(struct age_softc *); 138 static void age_stop(struct age_softc *); 139 static void age_stop_txmac(struct age_softc *); 140 static void age_stop_rxmac(struct age_softc *); 141 static void age_init_tx_ring(struct age_softc *); 142 static int age_init_rx_ring(struct age_softc *); 143 static void age_init_rr_ring(struct age_softc *); 144 static void age_init_cmb_block(struct age_softc *); 145 static void age_init_smb_block(struct age_softc *); 146 #ifndef __NO_STRICT_ALIGNMENT 147 static struct mbuf *age_fixup_rx(if_t, struct mbuf *); 148 #endif 149 static int age_newbuf(struct age_softc *, struct age_rxdesc *); 150 static void age_rxvlan(struct age_softc *); 151 static void age_rxfilter(struct age_softc *); 152 static int sysctl_age_stats(SYSCTL_HANDLER_ARGS); 153 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 154 static int sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS); 155 static int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS); 156 157 static device_method_t age_methods[] = { 158 /* Device interface. */ 159 DEVMETHOD(device_probe, age_probe), 160 DEVMETHOD(device_attach, age_attach), 161 DEVMETHOD(device_detach, age_detach), 162 DEVMETHOD(device_shutdown, age_shutdown), 163 DEVMETHOD(device_suspend, age_suspend), 164 DEVMETHOD(device_resume, age_resume), 165 166 /* MII interface. */ 167 DEVMETHOD(miibus_readreg, age_miibus_readreg), 168 DEVMETHOD(miibus_writereg, age_miibus_writereg), 169 DEVMETHOD(miibus_statchg, age_miibus_statchg), 170 { NULL, NULL } 171 }; 172 173 static driver_t age_driver = { 174 "age", 175 age_methods, 176 sizeof(struct age_softc) 177 }; 178 179 DRIVER_MODULE(age, pci, age_driver, 0, 0); 180 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, age, age_devs, 181 nitems(age_devs)); 182 DRIVER_MODULE(miibus, age, miibus_driver, 0, 0); 183 184 static struct resource_spec age_res_spec_mem[] = { 185 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 186 { -1, 0, 0 } 187 }; 188 189 static struct resource_spec age_irq_spec_legacy[] = { 190 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 191 { -1, 0, 0 } 192 }; 193 194 static struct resource_spec age_irq_spec_msi[] = { 195 { SYS_RES_IRQ, 1, RF_ACTIVE }, 196 { -1, 0, 0 } 197 }; 198 199 static struct resource_spec age_irq_spec_msix[] = { 200 { SYS_RES_IRQ, 1, RF_ACTIVE }, 201 { -1, 0, 0 } 202 }; 203 204 /* 205 * Read a PHY register on the MII of the L1. 206 */ 207 static int 208 age_miibus_readreg(device_t dev, int phy, int reg) 209 { 210 struct age_softc *sc; 211 uint32_t v; 212 int i; 213 214 sc = device_get_softc(dev); 215 216 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 217 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 218 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 219 DELAY(1); 220 v = CSR_READ_4(sc, AGE_MDIO); 221 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 222 break; 223 } 224 225 if (i == 0) { 226 device_printf(sc->age_dev, "phy read timeout : %d\n", reg); 227 return (0); 228 } 229 230 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 231 } 232 233 /* 234 * Write a PHY register on the MII of the L1. 235 */ 236 static int 237 age_miibus_writereg(device_t dev, int phy, int reg, int val) 238 { 239 struct age_softc *sc; 240 uint32_t v; 241 int i; 242 243 sc = device_get_softc(dev); 244 245 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 246 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 247 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 248 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 249 DELAY(1); 250 v = CSR_READ_4(sc, AGE_MDIO); 251 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 252 break; 253 } 254 255 if (i == 0) 256 device_printf(sc->age_dev, "phy write timeout : %d\n", reg); 257 258 return (0); 259 } 260 261 /* 262 * Callback from MII layer when media changes. 263 */ 264 static void 265 age_miibus_statchg(device_t dev) 266 { 267 struct age_softc *sc; 268 269 sc = device_get_softc(dev); 270 taskqueue_enqueue(taskqueue_swi, &sc->age_link_task); 271 } 272 273 /* 274 * Get the current interface media status. 275 */ 276 static void 277 age_mediastatus(if_t ifp, struct ifmediareq *ifmr) 278 { 279 struct age_softc *sc; 280 struct mii_data *mii; 281 282 sc = if_getsoftc(ifp); 283 AGE_LOCK(sc); 284 mii = device_get_softc(sc->age_miibus); 285 286 mii_pollstat(mii); 287 ifmr->ifm_status = mii->mii_media_status; 288 ifmr->ifm_active = mii->mii_media_active; 289 AGE_UNLOCK(sc); 290 } 291 292 /* 293 * Set hardware to newly-selected media. 294 */ 295 static int 296 age_mediachange(if_t ifp) 297 { 298 struct age_softc *sc; 299 struct mii_data *mii; 300 struct mii_softc *miisc; 301 int error; 302 303 sc = if_getsoftc(ifp); 304 AGE_LOCK(sc); 305 mii = device_get_softc(sc->age_miibus); 306 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 307 PHY_RESET(miisc); 308 error = mii_mediachg(mii); 309 AGE_UNLOCK(sc); 310 311 return (error); 312 } 313 314 static int 315 age_probe(device_t dev) 316 { 317 struct age_dev *sp; 318 int i; 319 uint16_t vendor, devid; 320 321 vendor = pci_get_vendor(dev); 322 devid = pci_get_device(dev); 323 sp = age_devs; 324 for (i = 0; i < nitems(age_devs); i++, sp++) { 325 if (vendor == sp->age_vendorid && 326 devid == sp->age_deviceid) { 327 device_set_desc(dev, sp->age_name); 328 return (BUS_PROBE_DEFAULT); 329 } 330 } 331 332 return (ENXIO); 333 } 334 335 static void 336 age_get_macaddr(struct age_softc *sc) 337 { 338 uint32_t ea[2], reg; 339 int i, vpdc; 340 341 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 342 if ((reg & SPI_VPD_ENB) != 0) { 343 /* Get VPD stored in TWSI EEPROM. */ 344 reg &= ~SPI_VPD_ENB; 345 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 346 } 347 348 if (pci_find_cap(sc->age_dev, PCIY_VPD, &vpdc) == 0) { 349 /* 350 * PCI VPD capability found, let TWSI reload EEPROM. 351 * This will set ethernet address of controller. 352 */ 353 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | 354 TWSI_CTRL_SW_LD_START); 355 for (i = 100; i > 0; i--) { 356 DELAY(1000); 357 reg = CSR_READ_4(sc, AGE_TWSI_CTRL); 358 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 359 break; 360 } 361 if (i == 0) 362 device_printf(sc->age_dev, 363 "reloading EEPROM timeout!\n"); 364 } else { 365 if (bootverbose) 366 device_printf(sc->age_dev, 367 "PCI VPD capability not found!\n"); 368 } 369 370 ea[0] = CSR_READ_4(sc, AGE_PAR0); 371 ea[1] = CSR_READ_4(sc, AGE_PAR1); 372 sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF; 373 sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF; 374 sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF; 375 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; 376 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; 377 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; 378 } 379 380 static void 381 age_phy_reset(struct age_softc *sc) 382 { 383 uint16_t reg, pn; 384 int i, linkup; 385 386 /* Reset PHY. */ 387 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 388 DELAY(2000); 389 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 390 DELAY(2000); 391 392 #define ATPHY_DBG_ADDR 0x1D 393 #define ATPHY_DBG_DATA 0x1E 394 #define ATPHY_CDTC 0x16 395 #define PHY_CDTC_ENB 0x0001 396 #define PHY_CDTC_POFF 8 397 #define ATPHY_CDTS 0x1C 398 #define PHY_CDTS_STAT_OK 0x0000 399 #define PHY_CDTS_STAT_SHORT 0x0100 400 #define PHY_CDTS_STAT_OPEN 0x0200 401 #define PHY_CDTS_STAT_INVAL 0x0300 402 #define PHY_CDTS_STAT_MASK 0x0300 403 404 /* Check power saving mode. Magic from Linux. */ 405 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET); 406 for (linkup = 0, pn = 0; pn < 4; pn++) { 407 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTC, 408 (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB); 409 for (i = 200; i > 0; i--) { 410 DELAY(1000); 411 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 412 ATPHY_CDTC); 413 if ((reg & PHY_CDTC_ENB) == 0) 414 break; 415 } 416 DELAY(1000); 417 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 418 ATPHY_CDTS); 419 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) { 420 linkup++; 421 break; 422 } 423 } 424 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, 425 BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 426 if (linkup == 0) { 427 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 428 ATPHY_DBG_ADDR, 0); 429 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 430 ATPHY_DBG_DATA, 0x124E); 431 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 432 ATPHY_DBG_ADDR, 1); 433 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 434 ATPHY_DBG_DATA); 435 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 436 ATPHY_DBG_DATA, reg | 0x03); 437 /* XXX */ 438 DELAY(1500 * 1000); 439 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 440 ATPHY_DBG_ADDR, 0); 441 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 442 ATPHY_DBG_DATA, 0x024E); 443 } 444 445 #undef ATPHY_DBG_ADDR 446 #undef ATPHY_DBG_DATA 447 #undef ATPHY_CDTC 448 #undef PHY_CDTC_ENB 449 #undef PHY_CDTC_POFF 450 #undef ATPHY_CDTS 451 #undef PHY_CDTS_STAT_OK 452 #undef PHY_CDTS_STAT_SHORT 453 #undef PHY_CDTS_STAT_OPEN 454 #undef PHY_CDTS_STAT_INVAL 455 #undef PHY_CDTS_STAT_MASK 456 } 457 458 static int 459 age_attach(device_t dev) 460 { 461 struct age_softc *sc; 462 if_t ifp; 463 uint16_t burst; 464 int error, i, msic, msixc, pmc; 465 466 error = 0; 467 sc = device_get_softc(dev); 468 sc->age_dev = dev; 469 470 mtx_init(&sc->age_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 471 MTX_DEF); 472 callout_init_mtx(&sc->age_tick_ch, &sc->age_mtx, 0); 473 TASK_INIT(&sc->age_int_task, 0, age_int_task, sc); 474 TASK_INIT(&sc->age_link_task, 0, age_link_task, sc); 475 476 /* Map the device. */ 477 pci_enable_busmaster(dev); 478 sc->age_res_spec = age_res_spec_mem; 479 sc->age_irq_spec = age_irq_spec_legacy; 480 error = bus_alloc_resources(dev, sc->age_res_spec, sc->age_res); 481 if (error != 0) { 482 device_printf(dev, "cannot allocate memory resources.\n"); 483 goto fail; 484 } 485 486 /* Set PHY address. */ 487 sc->age_phyaddr = AGE_PHY_ADDR; 488 489 /* Reset PHY. */ 490 age_phy_reset(sc); 491 492 /* Reset the ethernet controller. */ 493 age_reset(sc); 494 495 /* Get PCI and chip id/revision. */ 496 sc->age_rev = pci_get_revid(dev); 497 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 498 MASTER_CHIP_REV_SHIFT; 499 if (bootverbose) { 500 device_printf(dev, "PCI device revision : 0x%04x\n", 501 sc->age_rev); 502 device_printf(dev, "Chip id/revision : 0x%04x\n", 503 sc->age_chip_rev); 504 } 505 506 /* 507 * XXX 508 * Unintialized hardware returns an invalid chip id/revision 509 * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that 510 * unplugged cable results in putting hardware into automatic 511 * power down mode which in turn returns invalld chip revision. 512 */ 513 if (sc->age_chip_rev == 0xFFFF) { 514 device_printf(dev,"invalid chip revision : 0x%04x -- " 515 "not initialized?\n", sc->age_chip_rev); 516 error = ENXIO; 517 goto fail; 518 } 519 520 device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n", 521 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 522 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 523 524 /* Allocate IRQ resources. */ 525 msixc = pci_msix_count(dev); 526 msic = pci_msi_count(dev); 527 if (bootverbose) { 528 device_printf(dev, "MSIX count : %d\n", msixc); 529 device_printf(dev, "MSI count : %d\n", msic); 530 } 531 532 /* Prefer MSIX over MSI. */ 533 if (msix_disable == 0 || msi_disable == 0) { 534 if (msix_disable == 0 && msixc == AGE_MSIX_MESSAGES && 535 pci_alloc_msix(dev, &msixc) == 0) { 536 if (msic == AGE_MSIX_MESSAGES) { 537 device_printf(dev, "Using %d MSIX messages.\n", 538 msixc); 539 sc->age_flags |= AGE_FLAG_MSIX; 540 sc->age_irq_spec = age_irq_spec_msix; 541 } else 542 pci_release_msi(dev); 543 } 544 if (msi_disable == 0 && (sc->age_flags & AGE_FLAG_MSIX) == 0 && 545 msic == AGE_MSI_MESSAGES && 546 pci_alloc_msi(dev, &msic) == 0) { 547 if (msic == AGE_MSI_MESSAGES) { 548 device_printf(dev, "Using %d MSI messages.\n", 549 msic); 550 sc->age_flags |= AGE_FLAG_MSI; 551 sc->age_irq_spec = age_irq_spec_msi; 552 } else 553 pci_release_msi(dev); 554 } 555 } 556 557 error = bus_alloc_resources(dev, sc->age_irq_spec, sc->age_irq); 558 if (error != 0) { 559 device_printf(dev, "cannot allocate IRQ resources.\n"); 560 goto fail; 561 } 562 563 /* Get DMA parameters from PCIe device control register. */ 564 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 565 sc->age_flags |= AGE_FLAG_PCIE; 566 burst = pci_read_config(dev, i + 0x08, 2); 567 /* Max read request size. */ 568 sc->age_dma_rd_burst = ((burst >> 12) & 0x07) << 569 DMA_CFG_RD_BURST_SHIFT; 570 /* Max payload size. */ 571 sc->age_dma_wr_burst = ((burst >> 5) & 0x07) << 572 DMA_CFG_WR_BURST_SHIFT; 573 if (bootverbose) { 574 device_printf(dev, "Read request size : %d bytes.\n", 575 128 << ((burst >> 12) & 0x07)); 576 device_printf(dev, "TLP payload size : %d bytes.\n", 577 128 << ((burst >> 5) & 0x07)); 578 } 579 } else { 580 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 581 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 582 } 583 584 /* Create device sysctl node. */ 585 age_sysctl_node(sc); 586 587 if ((error = age_dma_alloc(sc)) != 0) 588 goto fail; 589 590 /* Load station address. */ 591 age_get_macaddr(sc); 592 593 ifp = sc->age_ifp = if_alloc(IFT_ETHER); 594 if_setsoftc(ifp, sc); 595 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 596 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 597 if_setioctlfn(ifp, age_ioctl); 598 if_setstartfn(ifp, age_start); 599 if_setinitfn(ifp, age_init); 600 if_setsendqlen(ifp, AGE_TX_RING_CNT - 1); 601 if_setsendqready(ifp); 602 if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_TSO4); 603 if_sethwassist(ifp, AGE_CSUM_FEATURES | CSUM_TSO); 604 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 605 sc->age_flags |= AGE_FLAG_PMCAP; 606 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0); 607 } 608 if_setcapenable(ifp, if_getcapabilities(ifp)); 609 610 /* Set up MII bus. */ 611 error = mii_attach(dev, &sc->age_miibus, ifp, age_mediachange, 612 age_mediastatus, BMSR_DEFCAPMASK, sc->age_phyaddr, MII_OFFSET_ANY, 613 0); 614 if (error != 0) { 615 device_printf(dev, "attaching PHYs failed\n"); 616 goto fail; 617 } 618 619 ether_ifattach(ifp, sc->age_eaddr); 620 621 /* VLAN capability setup. */ 622 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 623 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 624 if_setcapenable(ifp, if_getcapabilities(ifp)); 625 626 /* Tell the upper layer(s) we support long frames. */ 627 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 628 629 /* Create local taskq. */ 630 sc->age_tq = taskqueue_create_fast("age_taskq", M_WAITOK, 631 taskqueue_thread_enqueue, &sc->age_tq); 632 taskqueue_start_threads(&sc->age_tq, 1, PI_NET, "%s taskq", 633 device_get_nameunit(sc->age_dev)); 634 635 if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 636 msic = AGE_MSIX_MESSAGES; 637 else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 638 msic = AGE_MSI_MESSAGES; 639 else 640 msic = 1; 641 for (i = 0; i < msic; i++) { 642 error = bus_setup_intr(dev, sc->age_irq[i], 643 INTR_TYPE_NET | INTR_MPSAFE, age_intr, NULL, sc, 644 &sc->age_intrhand[i]); 645 if (error != 0) 646 break; 647 } 648 if (error != 0) { 649 device_printf(dev, "could not set up interrupt handler.\n"); 650 taskqueue_free(sc->age_tq); 651 sc->age_tq = NULL; 652 ether_ifdetach(ifp); 653 goto fail; 654 } 655 656 fail: 657 if (error != 0) 658 age_detach(dev); 659 660 return (error); 661 } 662 663 static int 664 age_detach(device_t dev) 665 { 666 struct age_softc *sc; 667 if_t ifp; 668 int i, msic; 669 670 sc = device_get_softc(dev); 671 672 ifp = sc->age_ifp; 673 if (device_is_attached(dev)) { 674 AGE_LOCK(sc); 675 sc->age_flags |= AGE_FLAG_DETACH; 676 age_stop(sc); 677 AGE_UNLOCK(sc); 678 callout_drain(&sc->age_tick_ch); 679 taskqueue_drain(sc->age_tq, &sc->age_int_task); 680 taskqueue_drain(taskqueue_swi, &sc->age_link_task); 681 ether_ifdetach(ifp); 682 } 683 684 if (sc->age_tq != NULL) { 685 taskqueue_drain(sc->age_tq, &sc->age_int_task); 686 taskqueue_free(sc->age_tq); 687 sc->age_tq = NULL; 688 } 689 690 if (sc->age_miibus != NULL) { 691 device_delete_child(dev, sc->age_miibus); 692 sc->age_miibus = NULL; 693 } 694 bus_generic_detach(dev); 695 age_dma_free(sc); 696 697 if (ifp != NULL) { 698 if_free(ifp); 699 sc->age_ifp = NULL; 700 } 701 702 if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 703 msic = AGE_MSIX_MESSAGES; 704 else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 705 msic = AGE_MSI_MESSAGES; 706 else 707 msic = 1; 708 for (i = 0; i < msic; i++) { 709 if (sc->age_intrhand[i] != NULL) { 710 bus_teardown_intr(dev, sc->age_irq[i], 711 sc->age_intrhand[i]); 712 sc->age_intrhand[i] = NULL; 713 } 714 } 715 716 bus_release_resources(dev, sc->age_irq_spec, sc->age_irq); 717 if ((sc->age_flags & (AGE_FLAG_MSI | AGE_FLAG_MSIX)) != 0) 718 pci_release_msi(dev); 719 bus_release_resources(dev, sc->age_res_spec, sc->age_res); 720 mtx_destroy(&sc->age_mtx); 721 722 return (0); 723 } 724 725 static void 726 age_sysctl_node(struct age_softc *sc) 727 { 728 int error; 729 730 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 731 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 732 "stats", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 733 sc, 0, sysctl_age_stats, "I", "Statistics"); 734 735 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 736 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 737 "int_mod", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 738 &sc->age_int_mod, 0, sysctl_hw_age_int_mod, "I", 739 "age interrupt moderation"); 740 741 /* Pull in device tunables. */ 742 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 743 error = resource_int_value(device_get_name(sc->age_dev), 744 device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod); 745 if (error == 0) { 746 if (sc->age_int_mod < AGE_IM_TIMER_MIN || 747 sc->age_int_mod > AGE_IM_TIMER_MAX) { 748 device_printf(sc->age_dev, 749 "int_mod value out of range; using default: %d\n", 750 AGE_IM_TIMER_DEFAULT); 751 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 752 } 753 } 754 755 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 756 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 757 "process_limit", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 758 &sc->age_process_limit, 0, sysctl_hw_age_proc_limit, "I", 759 "max number of Rx events to process"); 760 761 /* Pull in device tunables. */ 762 sc->age_process_limit = AGE_PROC_DEFAULT; 763 error = resource_int_value(device_get_name(sc->age_dev), 764 device_get_unit(sc->age_dev), "process_limit", 765 &sc->age_process_limit); 766 if (error == 0) { 767 if (sc->age_process_limit < AGE_PROC_MIN || 768 sc->age_process_limit > AGE_PROC_MAX) { 769 device_printf(sc->age_dev, 770 "process_limit value out of range; " 771 "using default: %d\n", AGE_PROC_DEFAULT); 772 sc->age_process_limit = AGE_PROC_DEFAULT; 773 } 774 } 775 } 776 777 struct age_dmamap_arg { 778 bus_addr_t age_busaddr; 779 }; 780 781 static void 782 age_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 783 { 784 struct age_dmamap_arg *ctx; 785 786 if (error != 0) 787 return; 788 789 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 790 791 ctx = (struct age_dmamap_arg *)arg; 792 ctx->age_busaddr = segs[0].ds_addr; 793 } 794 795 /* 796 * Attansic L1 controller have single register to specify high 797 * address part of DMA blocks. So all descriptor structures and 798 * DMA memory blocks should have the same high address of given 799 * 4GB address space(i.e. crossing 4GB boundary is not allowed). 800 */ 801 static int 802 age_check_boundary(struct age_softc *sc) 803 { 804 bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end; 805 bus_addr_t cmb_block_end, smb_block_end; 806 807 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 808 tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ; 809 rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ; 810 rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ; 811 cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ; 812 smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ; 813 814 if ((AGE_ADDR_HI(tx_ring_end) != 815 AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) || 816 (AGE_ADDR_HI(rx_ring_end) != 817 AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) || 818 (AGE_ADDR_HI(rr_ring_end) != 819 AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) || 820 (AGE_ADDR_HI(cmb_block_end) != 821 AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) || 822 (AGE_ADDR_HI(smb_block_end) != 823 AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr))) 824 return (EFBIG); 825 826 if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) || 827 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) || 828 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) || 829 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end))) 830 return (EFBIG); 831 832 return (0); 833 } 834 835 static int 836 age_dma_alloc(struct age_softc *sc) 837 { 838 struct age_txdesc *txd; 839 struct age_rxdesc *rxd; 840 bus_addr_t lowaddr; 841 struct age_dmamap_arg ctx; 842 int error, i; 843 844 lowaddr = BUS_SPACE_MAXADDR; 845 846 again: 847 /* Create parent ring/DMA block tag. */ 848 error = bus_dma_tag_create( 849 bus_get_dma_tag(sc->age_dev), /* parent */ 850 1, 0, /* alignment, boundary */ 851 lowaddr, /* lowaddr */ 852 BUS_SPACE_MAXADDR, /* highaddr */ 853 NULL, NULL, /* filter, filterarg */ 854 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 855 0, /* nsegments */ 856 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 857 0, /* flags */ 858 NULL, NULL, /* lockfunc, lockarg */ 859 &sc->age_cdata.age_parent_tag); 860 if (error != 0) { 861 device_printf(sc->age_dev, 862 "could not create parent DMA tag.\n"); 863 goto fail; 864 } 865 866 /* Create tag for Tx ring. */ 867 error = bus_dma_tag_create( 868 sc->age_cdata.age_parent_tag, /* parent */ 869 AGE_TX_RING_ALIGN, 0, /* alignment, boundary */ 870 BUS_SPACE_MAXADDR, /* lowaddr */ 871 BUS_SPACE_MAXADDR, /* highaddr */ 872 NULL, NULL, /* filter, filterarg */ 873 AGE_TX_RING_SZ, /* maxsize */ 874 1, /* nsegments */ 875 AGE_TX_RING_SZ, /* maxsegsize */ 876 0, /* flags */ 877 NULL, NULL, /* lockfunc, lockarg */ 878 &sc->age_cdata.age_tx_ring_tag); 879 if (error != 0) { 880 device_printf(sc->age_dev, 881 "could not create Tx ring DMA tag.\n"); 882 goto fail; 883 } 884 885 /* Create tag for Rx ring. */ 886 error = bus_dma_tag_create( 887 sc->age_cdata.age_parent_tag, /* parent */ 888 AGE_RX_RING_ALIGN, 0, /* alignment, boundary */ 889 BUS_SPACE_MAXADDR, /* lowaddr */ 890 BUS_SPACE_MAXADDR, /* highaddr */ 891 NULL, NULL, /* filter, filterarg */ 892 AGE_RX_RING_SZ, /* maxsize */ 893 1, /* nsegments */ 894 AGE_RX_RING_SZ, /* maxsegsize */ 895 0, /* flags */ 896 NULL, NULL, /* lockfunc, lockarg */ 897 &sc->age_cdata.age_rx_ring_tag); 898 if (error != 0) { 899 device_printf(sc->age_dev, 900 "could not create Rx ring DMA tag.\n"); 901 goto fail; 902 } 903 904 /* Create tag for Rx return ring. */ 905 error = bus_dma_tag_create( 906 sc->age_cdata.age_parent_tag, /* parent */ 907 AGE_RR_RING_ALIGN, 0, /* alignment, boundary */ 908 BUS_SPACE_MAXADDR, /* lowaddr */ 909 BUS_SPACE_MAXADDR, /* highaddr */ 910 NULL, NULL, /* filter, filterarg */ 911 AGE_RR_RING_SZ, /* maxsize */ 912 1, /* nsegments */ 913 AGE_RR_RING_SZ, /* maxsegsize */ 914 0, /* flags */ 915 NULL, NULL, /* lockfunc, lockarg */ 916 &sc->age_cdata.age_rr_ring_tag); 917 if (error != 0) { 918 device_printf(sc->age_dev, 919 "could not create Rx return ring DMA tag.\n"); 920 goto fail; 921 } 922 923 /* Create tag for coalesing message block. */ 924 error = bus_dma_tag_create( 925 sc->age_cdata.age_parent_tag, /* parent */ 926 AGE_CMB_ALIGN, 0, /* alignment, boundary */ 927 BUS_SPACE_MAXADDR, /* lowaddr */ 928 BUS_SPACE_MAXADDR, /* highaddr */ 929 NULL, NULL, /* filter, filterarg */ 930 AGE_CMB_BLOCK_SZ, /* maxsize */ 931 1, /* nsegments */ 932 AGE_CMB_BLOCK_SZ, /* maxsegsize */ 933 0, /* flags */ 934 NULL, NULL, /* lockfunc, lockarg */ 935 &sc->age_cdata.age_cmb_block_tag); 936 if (error != 0) { 937 device_printf(sc->age_dev, 938 "could not create CMB DMA tag.\n"); 939 goto fail; 940 } 941 942 /* Create tag for statistics message block. */ 943 error = bus_dma_tag_create( 944 sc->age_cdata.age_parent_tag, /* parent */ 945 AGE_SMB_ALIGN, 0, /* alignment, boundary */ 946 BUS_SPACE_MAXADDR, /* lowaddr */ 947 BUS_SPACE_MAXADDR, /* highaddr */ 948 NULL, NULL, /* filter, filterarg */ 949 AGE_SMB_BLOCK_SZ, /* maxsize */ 950 1, /* nsegments */ 951 AGE_SMB_BLOCK_SZ, /* maxsegsize */ 952 0, /* flags */ 953 NULL, NULL, /* lockfunc, lockarg */ 954 &sc->age_cdata.age_smb_block_tag); 955 if (error != 0) { 956 device_printf(sc->age_dev, 957 "could not create SMB DMA tag.\n"); 958 goto fail; 959 } 960 961 /* Allocate DMA'able memory and load the DMA map. */ 962 error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag, 963 (void **)&sc->age_rdata.age_tx_ring, 964 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 965 &sc->age_cdata.age_tx_ring_map); 966 if (error != 0) { 967 device_printf(sc->age_dev, 968 "could not allocate DMA'able memory for Tx ring.\n"); 969 goto fail; 970 } 971 ctx.age_busaddr = 0; 972 error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag, 973 sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring, 974 AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0); 975 if (error != 0 || ctx.age_busaddr == 0) { 976 device_printf(sc->age_dev, 977 "could not load DMA'able memory for Tx ring.\n"); 978 goto fail; 979 } 980 sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr; 981 /* Rx ring */ 982 error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag, 983 (void **)&sc->age_rdata.age_rx_ring, 984 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 985 &sc->age_cdata.age_rx_ring_map); 986 if (error != 0) { 987 device_printf(sc->age_dev, 988 "could not allocate DMA'able memory for Rx ring.\n"); 989 goto fail; 990 } 991 ctx.age_busaddr = 0; 992 error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag, 993 sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring, 994 AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0); 995 if (error != 0 || ctx.age_busaddr == 0) { 996 device_printf(sc->age_dev, 997 "could not load DMA'able memory for Rx ring.\n"); 998 goto fail; 999 } 1000 sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr; 1001 /* Rx return ring */ 1002 error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag, 1003 (void **)&sc->age_rdata.age_rr_ring, 1004 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1005 &sc->age_cdata.age_rr_ring_map); 1006 if (error != 0) { 1007 device_printf(sc->age_dev, 1008 "could not allocate DMA'able memory for Rx return ring.\n"); 1009 goto fail; 1010 } 1011 ctx.age_busaddr = 0; 1012 error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag, 1013 sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring, 1014 AGE_RR_RING_SZ, age_dmamap_cb, 1015 &ctx, 0); 1016 if (error != 0 || ctx.age_busaddr == 0) { 1017 device_printf(sc->age_dev, 1018 "could not load DMA'able memory for Rx return ring.\n"); 1019 goto fail; 1020 } 1021 sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr; 1022 /* CMB block */ 1023 error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag, 1024 (void **)&sc->age_rdata.age_cmb_block, 1025 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1026 &sc->age_cdata.age_cmb_block_map); 1027 if (error != 0) { 1028 device_printf(sc->age_dev, 1029 "could not allocate DMA'able memory for CMB block.\n"); 1030 goto fail; 1031 } 1032 ctx.age_busaddr = 0; 1033 error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag, 1034 sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block, 1035 AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1036 if (error != 0 || ctx.age_busaddr == 0) { 1037 device_printf(sc->age_dev, 1038 "could not load DMA'able memory for CMB block.\n"); 1039 goto fail; 1040 } 1041 sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr; 1042 /* SMB block */ 1043 error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag, 1044 (void **)&sc->age_rdata.age_smb_block, 1045 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1046 &sc->age_cdata.age_smb_block_map); 1047 if (error != 0) { 1048 device_printf(sc->age_dev, 1049 "could not allocate DMA'able memory for SMB block.\n"); 1050 goto fail; 1051 } 1052 ctx.age_busaddr = 0; 1053 error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag, 1054 sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block, 1055 AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1056 if (error != 0 || ctx.age_busaddr == 0) { 1057 device_printf(sc->age_dev, 1058 "could not load DMA'able memory for SMB block.\n"); 1059 goto fail; 1060 } 1061 sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr; 1062 1063 /* 1064 * All ring buffer and DMA blocks should have the same 1065 * high address part of 64bit DMA address space. 1066 */ 1067 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1068 (error = age_check_boundary(sc)) != 0) { 1069 device_printf(sc->age_dev, "4GB boundary crossed, " 1070 "switching to 32bit DMA addressing mode.\n"); 1071 age_dma_free(sc); 1072 /* Limit DMA address space to 32bit and try again. */ 1073 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1074 goto again; 1075 } 1076 1077 /* 1078 * Create Tx/Rx buffer parent tag. 1079 * L1 supports full 64bit DMA addressing in Tx/Rx buffers 1080 * so it needs separate parent DMA tag. 1081 * XXX 1082 * It seems enabling 64bit DMA causes data corruption. Limit 1083 * DMA address space to 32bit. 1084 */ 1085 error = bus_dma_tag_create( 1086 bus_get_dma_tag(sc->age_dev), /* parent */ 1087 1, 0, /* alignment, boundary */ 1088 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1089 BUS_SPACE_MAXADDR, /* highaddr */ 1090 NULL, NULL, /* filter, filterarg */ 1091 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1092 0, /* nsegments */ 1093 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1094 0, /* flags */ 1095 NULL, NULL, /* lockfunc, lockarg */ 1096 &sc->age_cdata.age_buffer_tag); 1097 if (error != 0) { 1098 device_printf(sc->age_dev, 1099 "could not create parent buffer DMA tag.\n"); 1100 goto fail; 1101 } 1102 1103 /* Create tag for Tx buffers. */ 1104 error = bus_dma_tag_create( 1105 sc->age_cdata.age_buffer_tag, /* parent */ 1106 1, 0, /* alignment, boundary */ 1107 BUS_SPACE_MAXADDR, /* lowaddr */ 1108 BUS_SPACE_MAXADDR, /* highaddr */ 1109 NULL, NULL, /* filter, filterarg */ 1110 AGE_TSO_MAXSIZE, /* maxsize */ 1111 AGE_MAXTXSEGS, /* nsegments */ 1112 AGE_TSO_MAXSEGSIZE, /* maxsegsize */ 1113 0, /* flags */ 1114 NULL, NULL, /* lockfunc, lockarg */ 1115 &sc->age_cdata.age_tx_tag); 1116 if (error != 0) { 1117 device_printf(sc->age_dev, "could not create Tx DMA tag.\n"); 1118 goto fail; 1119 } 1120 1121 /* Create tag for Rx buffers. */ 1122 error = bus_dma_tag_create( 1123 sc->age_cdata.age_buffer_tag, /* parent */ 1124 AGE_RX_BUF_ALIGN, 0, /* alignment, boundary */ 1125 BUS_SPACE_MAXADDR, /* lowaddr */ 1126 BUS_SPACE_MAXADDR, /* highaddr */ 1127 NULL, NULL, /* filter, filterarg */ 1128 MCLBYTES, /* maxsize */ 1129 1, /* nsegments */ 1130 MCLBYTES, /* maxsegsize */ 1131 0, /* flags */ 1132 NULL, NULL, /* lockfunc, lockarg */ 1133 &sc->age_cdata.age_rx_tag); 1134 if (error != 0) { 1135 device_printf(sc->age_dev, "could not create Rx DMA tag.\n"); 1136 goto fail; 1137 } 1138 1139 /* Create DMA maps for Tx buffers. */ 1140 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1141 txd = &sc->age_cdata.age_txdesc[i]; 1142 txd->tx_m = NULL; 1143 txd->tx_dmamap = NULL; 1144 error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0, 1145 &txd->tx_dmamap); 1146 if (error != 0) { 1147 device_printf(sc->age_dev, 1148 "could not create Tx dmamap.\n"); 1149 goto fail; 1150 } 1151 } 1152 /* Create DMA maps for Rx buffers. */ 1153 if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1154 &sc->age_cdata.age_rx_sparemap)) != 0) { 1155 device_printf(sc->age_dev, 1156 "could not create spare Rx dmamap.\n"); 1157 goto fail; 1158 } 1159 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1160 rxd = &sc->age_cdata.age_rxdesc[i]; 1161 rxd->rx_m = NULL; 1162 rxd->rx_dmamap = NULL; 1163 error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1164 &rxd->rx_dmamap); 1165 if (error != 0) { 1166 device_printf(sc->age_dev, 1167 "could not create Rx dmamap.\n"); 1168 goto fail; 1169 } 1170 } 1171 1172 fail: 1173 return (error); 1174 } 1175 1176 static void 1177 age_dma_free(struct age_softc *sc) 1178 { 1179 struct age_txdesc *txd; 1180 struct age_rxdesc *rxd; 1181 int i; 1182 1183 /* Tx buffers */ 1184 if (sc->age_cdata.age_tx_tag != NULL) { 1185 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1186 txd = &sc->age_cdata.age_txdesc[i]; 1187 if (txd->tx_dmamap != NULL) { 1188 bus_dmamap_destroy(sc->age_cdata.age_tx_tag, 1189 txd->tx_dmamap); 1190 txd->tx_dmamap = NULL; 1191 } 1192 } 1193 bus_dma_tag_destroy(sc->age_cdata.age_tx_tag); 1194 sc->age_cdata.age_tx_tag = NULL; 1195 } 1196 /* Rx buffers */ 1197 if (sc->age_cdata.age_rx_tag != NULL) { 1198 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1199 rxd = &sc->age_cdata.age_rxdesc[i]; 1200 if (rxd->rx_dmamap != NULL) { 1201 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1202 rxd->rx_dmamap); 1203 rxd->rx_dmamap = NULL; 1204 } 1205 } 1206 if (sc->age_cdata.age_rx_sparemap != NULL) { 1207 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1208 sc->age_cdata.age_rx_sparemap); 1209 sc->age_cdata.age_rx_sparemap = NULL; 1210 } 1211 bus_dma_tag_destroy(sc->age_cdata.age_rx_tag); 1212 sc->age_cdata.age_rx_tag = NULL; 1213 } 1214 /* Tx ring. */ 1215 if (sc->age_cdata.age_tx_ring_tag != NULL) { 1216 if (sc->age_rdata.age_tx_ring_paddr != 0) 1217 bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag, 1218 sc->age_cdata.age_tx_ring_map); 1219 if (sc->age_rdata.age_tx_ring != NULL) 1220 bus_dmamem_free(sc->age_cdata.age_tx_ring_tag, 1221 sc->age_rdata.age_tx_ring, 1222 sc->age_cdata.age_tx_ring_map); 1223 sc->age_rdata.age_tx_ring_paddr = 0; 1224 sc->age_rdata.age_tx_ring = NULL; 1225 bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag); 1226 sc->age_cdata.age_tx_ring_tag = NULL; 1227 } 1228 /* Rx ring. */ 1229 if (sc->age_cdata.age_rx_ring_tag != NULL) { 1230 if (sc->age_rdata.age_rx_ring_paddr != 0) 1231 bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag, 1232 sc->age_cdata.age_rx_ring_map); 1233 if (sc->age_rdata.age_rx_ring != NULL) 1234 bus_dmamem_free(sc->age_cdata.age_rx_ring_tag, 1235 sc->age_rdata.age_rx_ring, 1236 sc->age_cdata.age_rx_ring_map); 1237 sc->age_rdata.age_rx_ring_paddr = 0; 1238 sc->age_rdata.age_rx_ring = NULL; 1239 bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag); 1240 sc->age_cdata.age_rx_ring_tag = NULL; 1241 } 1242 /* Rx return ring. */ 1243 if (sc->age_cdata.age_rr_ring_tag != NULL) { 1244 if (sc->age_rdata.age_rr_ring_paddr != 0) 1245 bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag, 1246 sc->age_cdata.age_rr_ring_map); 1247 if (sc->age_rdata.age_rr_ring != NULL) 1248 bus_dmamem_free(sc->age_cdata.age_rr_ring_tag, 1249 sc->age_rdata.age_rr_ring, 1250 sc->age_cdata.age_rr_ring_map); 1251 sc->age_rdata.age_rr_ring_paddr = 0; 1252 sc->age_rdata.age_rr_ring = NULL; 1253 bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag); 1254 sc->age_cdata.age_rr_ring_tag = NULL; 1255 } 1256 /* CMB block */ 1257 if (sc->age_cdata.age_cmb_block_tag != NULL) { 1258 if (sc->age_rdata.age_cmb_block_paddr != 0) 1259 bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag, 1260 sc->age_cdata.age_cmb_block_map); 1261 if (sc->age_rdata.age_cmb_block != NULL) 1262 bus_dmamem_free(sc->age_cdata.age_cmb_block_tag, 1263 sc->age_rdata.age_cmb_block, 1264 sc->age_cdata.age_cmb_block_map); 1265 sc->age_rdata.age_cmb_block_paddr = 0; 1266 sc->age_rdata.age_cmb_block = NULL; 1267 bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag); 1268 sc->age_cdata.age_cmb_block_tag = NULL; 1269 } 1270 /* SMB block */ 1271 if (sc->age_cdata.age_smb_block_tag != NULL) { 1272 if (sc->age_rdata.age_smb_block_paddr != 0) 1273 bus_dmamap_unload(sc->age_cdata.age_smb_block_tag, 1274 sc->age_cdata.age_smb_block_map); 1275 if (sc->age_rdata.age_smb_block != NULL) 1276 bus_dmamem_free(sc->age_cdata.age_smb_block_tag, 1277 sc->age_rdata.age_smb_block, 1278 sc->age_cdata.age_smb_block_map); 1279 sc->age_rdata.age_smb_block_paddr = 0; 1280 sc->age_rdata.age_smb_block = NULL; 1281 bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag); 1282 sc->age_cdata.age_smb_block_tag = NULL; 1283 } 1284 1285 if (sc->age_cdata.age_buffer_tag != NULL) { 1286 bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag); 1287 sc->age_cdata.age_buffer_tag = NULL; 1288 } 1289 if (sc->age_cdata.age_parent_tag != NULL) { 1290 bus_dma_tag_destroy(sc->age_cdata.age_parent_tag); 1291 sc->age_cdata.age_parent_tag = NULL; 1292 } 1293 } 1294 1295 /* 1296 * Make sure the interface is stopped at reboot time. 1297 */ 1298 static int 1299 age_shutdown(device_t dev) 1300 { 1301 1302 return (age_suspend(dev)); 1303 } 1304 1305 static void 1306 age_setwol(struct age_softc *sc) 1307 { 1308 if_t ifp; 1309 struct mii_data *mii; 1310 uint32_t reg, pmcs; 1311 uint16_t pmstat; 1312 int aneg, i, pmc; 1313 1314 AGE_LOCK_ASSERT(sc); 1315 1316 if (pci_find_cap(sc->age_dev, PCIY_PMG, &pmc) != 0) { 1317 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1318 /* 1319 * No PME capability, PHY power down. 1320 * XXX 1321 * Due to an unknown reason powering down PHY resulted 1322 * in unexpected results such as inaccessbility of 1323 * hardware of freshly rebooted system. Disable 1324 * powering down PHY until I got more information for 1325 * Attansic/Atheros PHY hardwares. 1326 */ 1327 #ifdef notyet 1328 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1329 MII_BMCR, BMCR_PDOWN); 1330 #endif 1331 return; 1332 } 1333 1334 ifp = sc->age_ifp; 1335 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 1336 /* 1337 * Note, this driver resets the link speed to 10/100Mbps with 1338 * auto-negotiation but we don't know whether that operation 1339 * would succeed or not as it have no control after powering 1340 * off. If the renegotiation fail WOL may not work. Running 1341 * at 1Gbps will draw more power than 375mA at 3.3V which is 1342 * specified in PCI specification and that would result in 1343 * complete shutdowning power to ethernet controller. 1344 * 1345 * TODO 1346 * Save current negotiated media speed/duplex/flow-control 1347 * to softc and restore the same link again after resuming. 1348 * PHY handling such as power down/resetting to 100Mbps 1349 * may be better handled in suspend method in phy driver. 1350 */ 1351 mii = device_get_softc(sc->age_miibus); 1352 mii_pollstat(mii); 1353 aneg = 0; 1354 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1355 switch IFM_SUBTYPE(mii->mii_media_active) { 1356 case IFM_10_T: 1357 case IFM_100_TX: 1358 goto got_link; 1359 case IFM_1000_T: 1360 aneg++; 1361 default: 1362 break; 1363 } 1364 } 1365 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1366 MII_100T2CR, 0); 1367 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1368 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | 1369 ANAR_10 | ANAR_CSMA); 1370 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1371 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1372 DELAY(1000); 1373 if (aneg != 0) { 1374 /* Poll link state until age(4) get a 10/100 link. */ 1375 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1376 mii_pollstat(mii); 1377 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1378 switch (IFM_SUBTYPE( 1379 mii->mii_media_active)) { 1380 case IFM_10_T: 1381 case IFM_100_TX: 1382 age_mac_config(sc); 1383 goto got_link; 1384 default: 1385 break; 1386 } 1387 } 1388 AGE_UNLOCK(sc); 1389 pause("agelnk", hz); 1390 AGE_LOCK(sc); 1391 } 1392 if (i == MII_ANEGTICKS_GIGE) 1393 device_printf(sc->age_dev, 1394 "establishing link failed, " 1395 "WOL may not work!"); 1396 } 1397 /* 1398 * No link, force MAC to have 100Mbps, full-duplex link. 1399 * This is the last resort and may/may not work. 1400 */ 1401 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1402 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1403 age_mac_config(sc); 1404 } 1405 1406 got_link: 1407 pmcs = 0; 1408 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 1409 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1410 CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs); 1411 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1412 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC); 1413 reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST); 1414 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 1415 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1416 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 1417 reg |= MAC_CFG_RX_ENB; 1418 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1419 } 1420 1421 /* Request PME. */ 1422 pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2); 1423 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1424 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 1425 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1426 pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1427 #ifdef notyet 1428 /* See above for powering down PHY issues. */ 1429 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) { 1430 /* No WOL, PHY power down. */ 1431 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1432 MII_BMCR, BMCR_PDOWN); 1433 } 1434 #endif 1435 } 1436 1437 static int 1438 age_suspend(device_t dev) 1439 { 1440 struct age_softc *sc; 1441 1442 sc = device_get_softc(dev); 1443 1444 AGE_LOCK(sc); 1445 age_stop(sc); 1446 age_setwol(sc); 1447 AGE_UNLOCK(sc); 1448 1449 return (0); 1450 } 1451 1452 static int 1453 age_resume(device_t dev) 1454 { 1455 struct age_softc *sc; 1456 if_t ifp; 1457 1458 sc = device_get_softc(dev); 1459 1460 AGE_LOCK(sc); 1461 age_phy_reset(sc); 1462 ifp = sc->age_ifp; 1463 if ((if_getflags(ifp) & IFF_UP) != 0) 1464 age_init_locked(sc); 1465 1466 AGE_UNLOCK(sc); 1467 1468 return (0); 1469 } 1470 1471 static int 1472 age_encap(struct age_softc *sc, struct mbuf **m_head) 1473 { 1474 struct age_txdesc *txd, *txd_last; 1475 struct tx_desc *desc; 1476 struct mbuf *m; 1477 struct ip *ip; 1478 struct tcphdr *tcp; 1479 bus_dma_segment_t txsegs[AGE_MAXTXSEGS]; 1480 bus_dmamap_t map; 1481 uint32_t cflags, hdrlen, ip_off, poff, vtag; 1482 int error, i, nsegs, prod, si; 1483 1484 AGE_LOCK_ASSERT(sc); 1485 1486 M_ASSERTPKTHDR((*m_head)); 1487 1488 m = *m_head; 1489 ip = NULL; 1490 tcp = NULL; 1491 cflags = vtag = 0; 1492 ip_off = poff = 0; 1493 if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1494 /* 1495 * L1 requires offset of TCP/UDP payload in its Tx 1496 * descriptor to perform hardware Tx checksum offload. 1497 * Additionally, TSO requires IP/TCP header size and 1498 * modification of IP/TCP header in order to make TSO 1499 * engine work. This kind of operation takes many CPU 1500 * cycles on FreeBSD so fast host CPU is needed to get 1501 * smooth TSO performance. 1502 */ 1503 struct ether_header *eh; 1504 1505 if (M_WRITABLE(m) == 0) { 1506 /* Get a writable copy. */ 1507 m = m_dup(*m_head, M_NOWAIT); 1508 /* Release original mbufs. */ 1509 m_freem(*m_head); 1510 if (m == NULL) { 1511 *m_head = NULL; 1512 return (ENOBUFS); 1513 } 1514 *m_head = m; 1515 } 1516 ip_off = sizeof(struct ether_header); 1517 m = m_pullup(m, ip_off); 1518 if (m == NULL) { 1519 *m_head = NULL; 1520 return (ENOBUFS); 1521 } 1522 eh = mtod(m, struct ether_header *); 1523 /* 1524 * Check if hardware VLAN insertion is off. 1525 * Additional check for LLC/SNAP frame? 1526 */ 1527 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1528 ip_off = sizeof(struct ether_vlan_header); 1529 m = m_pullup(m, ip_off); 1530 if (m == NULL) { 1531 *m_head = NULL; 1532 return (ENOBUFS); 1533 } 1534 } 1535 m = m_pullup(m, ip_off + sizeof(struct ip)); 1536 if (m == NULL) { 1537 *m_head = NULL; 1538 return (ENOBUFS); 1539 } 1540 ip = (struct ip *)(mtod(m, char *) + ip_off); 1541 poff = ip_off + (ip->ip_hl << 2); 1542 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1543 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1544 if (m == NULL) { 1545 *m_head = NULL; 1546 return (ENOBUFS); 1547 } 1548 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1549 m = m_pullup(m, poff + (tcp->th_off << 2)); 1550 if (m == NULL) { 1551 *m_head = NULL; 1552 return (ENOBUFS); 1553 } 1554 /* 1555 * L1 requires IP/TCP header size and offset as 1556 * well as TCP pseudo checksum which complicates 1557 * TSO configuration. I guess this comes from the 1558 * adherence to Microsoft NDIS Large Send 1559 * specification which requires insertion of 1560 * pseudo checksum by upper stack. The pseudo 1561 * checksum that NDIS refers to doesn't include 1562 * TCP payload length so age(4) should recompute 1563 * the pseudo checksum here. Hopefully this wouldn't 1564 * be much burden on modern CPUs. 1565 * Reset IP checksum and recompute TCP pseudo 1566 * checksum as NDIS specification said. 1567 */ 1568 ip = (struct ip *)(mtod(m, char *) + ip_off); 1569 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1570 ip->ip_sum = 0; 1571 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1572 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1573 } 1574 *m_head = m; 1575 } 1576 1577 si = prod = sc->age_cdata.age_tx_prod; 1578 txd = &sc->age_cdata.age_txdesc[prod]; 1579 txd_last = txd; 1580 map = txd->tx_dmamap; 1581 1582 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1583 *m_head, txsegs, &nsegs, 0); 1584 if (error == EFBIG) { 1585 m = m_collapse(*m_head, M_NOWAIT, AGE_MAXTXSEGS); 1586 if (m == NULL) { 1587 m_freem(*m_head); 1588 *m_head = NULL; 1589 return (ENOMEM); 1590 } 1591 *m_head = m; 1592 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1593 *m_head, txsegs, &nsegs, 0); 1594 if (error != 0) { 1595 m_freem(*m_head); 1596 *m_head = NULL; 1597 return (error); 1598 } 1599 } else if (error != 0) 1600 return (error); 1601 if (nsegs == 0) { 1602 m_freem(*m_head); 1603 *m_head = NULL; 1604 return (EIO); 1605 } 1606 1607 /* Check descriptor overrun. */ 1608 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1609 bus_dmamap_unload(sc->age_cdata.age_tx_tag, map); 1610 return (ENOBUFS); 1611 } 1612 1613 m = *m_head; 1614 /* Configure VLAN hardware tag insertion. */ 1615 if ((m->m_flags & M_VLANTAG) != 0) { 1616 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1617 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1618 cflags |= AGE_TD_INSERT_VLAN_TAG; 1619 } 1620 1621 desc = NULL; 1622 i = 0; 1623 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1624 /* Request TSO and set MSS. */ 1625 cflags |= AGE_TD_TSO_IPV4; 1626 cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; 1627 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << 1628 AGE_TD_TSO_MSS_SHIFT); 1629 /* Set IP/TCP header size. */ 1630 cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT; 1631 cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT; 1632 /* 1633 * L1 requires the first buffer should only hold IP/TCP 1634 * header data. TCP payload should be handled in other 1635 * descriptors. 1636 */ 1637 hdrlen = poff + (tcp->th_off << 2); 1638 desc = &sc->age_rdata.age_tx_ring[prod]; 1639 desc->addr = htole64(txsegs[0].ds_addr); 1640 desc->len = htole32(AGE_TX_BYTES(hdrlen) | vtag); 1641 desc->flags = htole32(cflags); 1642 sc->age_cdata.age_tx_cnt++; 1643 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1644 if (m->m_len - hdrlen > 0) { 1645 /* Handle remaining payload of the 1st fragment. */ 1646 desc = &sc->age_rdata.age_tx_ring[prod]; 1647 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 1648 desc->len = htole32(AGE_TX_BYTES(m->m_len - hdrlen) | 1649 vtag); 1650 desc->flags = htole32(cflags); 1651 sc->age_cdata.age_tx_cnt++; 1652 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1653 } 1654 /* Handle remaining fragments. */ 1655 i = 1; 1656 } else if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1657 /* Configure Tx IP/TCP/UDP checksum offload. */ 1658 cflags |= AGE_TD_CSUM; 1659 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1660 cflags |= AGE_TD_TCPCSUM; 1661 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1662 cflags |= AGE_TD_UDPCSUM; 1663 /* Set checksum start offset. */ 1664 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1665 /* Set checksum insertion position of TCP/UDP. */ 1666 cflags |= ((poff + m->m_pkthdr.csum_data) << 1667 AGE_TD_CSUM_XSUMOFFSET_SHIFT); 1668 } 1669 for (; i < nsegs; i++) { 1670 desc = &sc->age_rdata.age_tx_ring[prod]; 1671 desc->addr = htole64(txsegs[i].ds_addr); 1672 desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag); 1673 desc->flags = htole32(cflags); 1674 sc->age_cdata.age_tx_cnt++; 1675 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1676 } 1677 /* Update producer index. */ 1678 sc->age_cdata.age_tx_prod = prod; 1679 1680 /* Set EOP on the last descriptor. */ 1681 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1682 desc = &sc->age_rdata.age_tx_ring[prod]; 1683 desc->flags |= htole32(AGE_TD_EOP); 1684 1685 /* Lastly set TSO header and modify IP/TCP header for TSO operation. */ 1686 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1687 desc = &sc->age_rdata.age_tx_ring[si]; 1688 desc->flags |= htole32(AGE_TD_TSO_HDR); 1689 } 1690 1691 /* Swap dmamap of the first and the last. */ 1692 txd = &sc->age_cdata.age_txdesc[prod]; 1693 map = txd_last->tx_dmamap; 1694 txd_last->tx_dmamap = txd->tx_dmamap; 1695 txd->tx_dmamap = map; 1696 txd->tx_m = m; 1697 1698 /* Sync descriptors. */ 1699 bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE); 1700 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 1701 sc->age_cdata.age_tx_ring_map, 1702 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1703 1704 return (0); 1705 } 1706 1707 static void 1708 age_start(if_t ifp) 1709 { 1710 struct age_softc *sc; 1711 1712 sc = if_getsoftc(ifp); 1713 AGE_LOCK(sc); 1714 age_start_locked(ifp); 1715 AGE_UNLOCK(sc); 1716 } 1717 1718 static void 1719 age_start_locked(if_t ifp) 1720 { 1721 struct age_softc *sc; 1722 struct mbuf *m_head; 1723 int enq; 1724 1725 sc = if_getsoftc(ifp); 1726 1727 AGE_LOCK_ASSERT(sc); 1728 1729 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1730 IFF_DRV_RUNNING || (sc->age_flags & AGE_FLAG_LINK) == 0) 1731 return; 1732 1733 for (enq = 0; !if_sendq_empty(ifp); ) { 1734 m_head = if_dequeue(ifp); 1735 if (m_head == NULL) 1736 break; 1737 /* 1738 * Pack the data into the transmit ring. If we 1739 * don't have room, set the OACTIVE flag and wait 1740 * for the NIC to drain the ring. 1741 */ 1742 if (age_encap(sc, &m_head)) { 1743 if (m_head == NULL) 1744 break; 1745 if_sendq_prepend(ifp, m_head); 1746 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1747 break; 1748 } 1749 1750 enq++; 1751 /* 1752 * If there's a BPF listener, bounce a copy of this frame 1753 * to him. 1754 */ 1755 ETHER_BPF_MTAP(ifp, m_head); 1756 } 1757 1758 if (enq > 0) { 1759 /* Update mbox. */ 1760 AGE_COMMIT_MBOX(sc); 1761 /* Set a timeout in case the chip goes out to lunch. */ 1762 sc->age_watchdog_timer = AGE_TX_TIMEOUT; 1763 } 1764 } 1765 1766 static void 1767 age_watchdog(struct age_softc *sc) 1768 { 1769 if_t ifp; 1770 1771 AGE_LOCK_ASSERT(sc); 1772 1773 if (sc->age_watchdog_timer == 0 || --sc->age_watchdog_timer) 1774 return; 1775 1776 ifp = sc->age_ifp; 1777 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1778 if_printf(sc->age_ifp, "watchdog timeout (missed link)\n"); 1779 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1780 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1781 age_init_locked(sc); 1782 return; 1783 } 1784 if (sc->age_cdata.age_tx_cnt == 0) { 1785 if_printf(sc->age_ifp, 1786 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 1787 if (!if_sendq_empty(ifp)) 1788 age_start_locked(ifp); 1789 return; 1790 } 1791 if_printf(sc->age_ifp, "watchdog timeout\n"); 1792 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1793 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1794 age_init_locked(sc); 1795 if (!if_sendq_empty(ifp)) 1796 age_start_locked(ifp); 1797 } 1798 1799 static int 1800 age_ioctl(if_t ifp, u_long cmd, caddr_t data) 1801 { 1802 struct age_softc *sc; 1803 struct ifreq *ifr; 1804 struct mii_data *mii; 1805 uint32_t reg; 1806 int error, mask; 1807 1808 sc = if_getsoftc(ifp); 1809 ifr = (struct ifreq *)data; 1810 error = 0; 1811 switch (cmd) { 1812 case SIOCSIFMTU: 1813 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU) 1814 error = EINVAL; 1815 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 1816 AGE_LOCK(sc); 1817 if_setmtu(ifp, ifr->ifr_mtu); 1818 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1819 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1820 age_init_locked(sc); 1821 } 1822 AGE_UNLOCK(sc); 1823 } 1824 break; 1825 case SIOCSIFFLAGS: 1826 AGE_LOCK(sc); 1827 if ((if_getflags(ifp) & IFF_UP) != 0) { 1828 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1829 if (((if_getflags(ifp) ^ sc->age_if_flags) 1830 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1831 age_rxfilter(sc); 1832 } else { 1833 if ((sc->age_flags & AGE_FLAG_DETACH) == 0) 1834 age_init_locked(sc); 1835 } 1836 } else { 1837 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1838 age_stop(sc); 1839 } 1840 sc->age_if_flags = if_getflags(ifp); 1841 AGE_UNLOCK(sc); 1842 break; 1843 case SIOCADDMULTI: 1844 case SIOCDELMULTI: 1845 AGE_LOCK(sc); 1846 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1847 age_rxfilter(sc); 1848 AGE_UNLOCK(sc); 1849 break; 1850 case SIOCSIFMEDIA: 1851 case SIOCGIFMEDIA: 1852 mii = device_get_softc(sc->age_miibus); 1853 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1854 break; 1855 case SIOCSIFCAP: 1856 AGE_LOCK(sc); 1857 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1858 if ((mask & IFCAP_TXCSUM) != 0 && 1859 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 1860 if_togglecapenable(ifp, IFCAP_TXCSUM); 1861 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 1862 if_sethwassistbits(ifp, AGE_CSUM_FEATURES, 0); 1863 else 1864 if_sethwassistbits(ifp, 0, AGE_CSUM_FEATURES); 1865 } 1866 if ((mask & IFCAP_RXCSUM) != 0 && 1867 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) { 1868 if_togglecapenable(ifp, IFCAP_RXCSUM); 1869 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1870 reg &= ~MAC_CFG_RXCSUM_ENB; 1871 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 1872 reg |= MAC_CFG_RXCSUM_ENB; 1873 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1874 } 1875 if ((mask & IFCAP_TSO4) != 0 && 1876 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 1877 if_togglecapenable(ifp, IFCAP_TSO4); 1878 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) 1879 if_sethwassistbits(ifp, CSUM_TSO, 0); 1880 else 1881 if_sethwassistbits(ifp, 0, CSUM_TSO); 1882 } 1883 1884 if ((mask & IFCAP_WOL_MCAST) != 0 && 1885 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0) 1886 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 1887 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1888 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 1889 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 1890 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1891 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 1892 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 1893 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1894 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 1895 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 1896 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1897 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 1898 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 1899 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 1900 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); 1901 age_rxvlan(sc); 1902 } 1903 AGE_UNLOCK(sc); 1904 VLAN_CAPABILITIES(ifp); 1905 break; 1906 default: 1907 error = ether_ioctl(ifp, cmd, data); 1908 break; 1909 } 1910 1911 return (error); 1912 } 1913 1914 static void 1915 age_mac_config(struct age_softc *sc) 1916 { 1917 struct mii_data *mii; 1918 uint32_t reg; 1919 1920 AGE_LOCK_ASSERT(sc); 1921 1922 mii = device_get_softc(sc->age_miibus); 1923 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1924 reg &= ~MAC_CFG_FULL_DUPLEX; 1925 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1926 reg &= ~MAC_CFG_SPEED_MASK; 1927 /* Reprogram MAC with resolved speed/duplex. */ 1928 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1929 case IFM_10_T: 1930 case IFM_100_TX: 1931 reg |= MAC_CFG_SPEED_10_100; 1932 break; 1933 case IFM_1000_T: 1934 reg |= MAC_CFG_SPEED_1000; 1935 break; 1936 } 1937 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1938 reg |= MAC_CFG_FULL_DUPLEX; 1939 #ifdef notyet 1940 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1941 reg |= MAC_CFG_TX_FC; 1942 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1943 reg |= MAC_CFG_RX_FC; 1944 #endif 1945 } 1946 1947 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1948 } 1949 1950 static void 1951 age_link_task(void *arg, int pending) 1952 { 1953 struct age_softc *sc; 1954 struct mii_data *mii; 1955 if_t ifp; 1956 uint32_t reg; 1957 1958 sc = (struct age_softc *)arg; 1959 1960 AGE_LOCK(sc); 1961 mii = device_get_softc(sc->age_miibus); 1962 ifp = sc->age_ifp; 1963 if (mii == NULL || ifp == NULL || 1964 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 1965 AGE_UNLOCK(sc); 1966 return; 1967 } 1968 1969 sc->age_flags &= ~AGE_FLAG_LINK; 1970 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1971 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1972 case IFM_10_T: 1973 case IFM_100_TX: 1974 case IFM_1000_T: 1975 sc->age_flags |= AGE_FLAG_LINK; 1976 break; 1977 default: 1978 break; 1979 } 1980 } 1981 1982 /* Stop Rx/Tx MACs. */ 1983 age_stop_rxmac(sc); 1984 age_stop_txmac(sc); 1985 1986 /* Program MACs with resolved speed/duplex/flow-control. */ 1987 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 1988 age_mac_config(sc); 1989 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1990 /* Restart DMA engine and Tx/Rx MAC. */ 1991 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 1992 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 1993 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 1994 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1995 } 1996 1997 AGE_UNLOCK(sc); 1998 } 1999 2000 static void 2001 age_stats_update(struct age_softc *sc) 2002 { 2003 struct age_stats *stat; 2004 struct smb *smb; 2005 if_t ifp; 2006 2007 AGE_LOCK_ASSERT(sc); 2008 2009 stat = &sc->age_stat; 2010 2011 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2012 sc->age_cdata.age_smb_block_map, 2013 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2014 2015 smb = sc->age_rdata.age_smb_block; 2016 if (smb->updated == 0) 2017 return; 2018 2019 ifp = sc->age_ifp; 2020 /* Rx stats. */ 2021 stat->rx_frames += smb->rx_frames; 2022 stat->rx_bcast_frames += smb->rx_bcast_frames; 2023 stat->rx_mcast_frames += smb->rx_mcast_frames; 2024 stat->rx_pause_frames += smb->rx_pause_frames; 2025 stat->rx_control_frames += smb->rx_control_frames; 2026 stat->rx_crcerrs += smb->rx_crcerrs; 2027 stat->rx_lenerrs += smb->rx_lenerrs; 2028 stat->rx_bytes += smb->rx_bytes; 2029 stat->rx_runts += smb->rx_runts; 2030 stat->rx_fragments += smb->rx_fragments; 2031 stat->rx_pkts_64 += smb->rx_pkts_64; 2032 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2033 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2034 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2035 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2036 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2037 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2038 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2039 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2040 stat->rx_desc_oflows += smb->rx_desc_oflows; 2041 stat->rx_alignerrs += smb->rx_alignerrs; 2042 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2043 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2044 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2045 2046 /* Tx stats. */ 2047 stat->tx_frames += smb->tx_frames; 2048 stat->tx_bcast_frames += smb->tx_bcast_frames; 2049 stat->tx_mcast_frames += smb->tx_mcast_frames; 2050 stat->tx_pause_frames += smb->tx_pause_frames; 2051 stat->tx_excess_defer += smb->tx_excess_defer; 2052 stat->tx_control_frames += smb->tx_control_frames; 2053 stat->tx_deferred += smb->tx_deferred; 2054 stat->tx_bytes += smb->tx_bytes; 2055 stat->tx_pkts_64 += smb->tx_pkts_64; 2056 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2057 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2058 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2059 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2060 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2061 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2062 stat->tx_single_colls += smb->tx_single_colls; 2063 stat->tx_multi_colls += smb->tx_multi_colls; 2064 stat->tx_late_colls += smb->tx_late_colls; 2065 stat->tx_excess_colls += smb->tx_excess_colls; 2066 stat->tx_underrun += smb->tx_underrun; 2067 stat->tx_desc_underrun += smb->tx_desc_underrun; 2068 stat->tx_lenerrs += smb->tx_lenerrs; 2069 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2070 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2071 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2072 2073 /* Update counters in ifnet. */ 2074 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 2075 2076 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 2077 smb->tx_multi_colls + smb->tx_late_colls + 2078 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 2079 2080 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_excess_colls + 2081 smb->tx_late_colls + smb->tx_underrun + 2082 smb->tx_pkts_truncated); 2083 2084 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 2085 2086 if_inc_counter(ifp, IFCOUNTER_IERRORS, smb->rx_crcerrs + 2087 smb->rx_lenerrs + smb->rx_runts + smb->rx_pkts_truncated + 2088 smb->rx_fifo_oflows + smb->rx_desc_oflows + 2089 smb->rx_alignerrs); 2090 2091 /* Update done, clear. */ 2092 smb->updated = 0; 2093 2094 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2095 sc->age_cdata.age_smb_block_map, 2096 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2097 } 2098 2099 static int 2100 age_intr(void *arg) 2101 { 2102 struct age_softc *sc; 2103 uint32_t status; 2104 2105 sc = (struct age_softc *)arg; 2106 2107 status = CSR_READ_4(sc, AGE_INTR_STATUS); 2108 if (status == 0 || (status & AGE_INTRS) == 0) 2109 return (FILTER_STRAY); 2110 /* Disable interrupts. */ 2111 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 2112 taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2113 2114 return (FILTER_HANDLED); 2115 } 2116 2117 static void 2118 age_int_task(void *arg, int pending) 2119 { 2120 struct age_softc *sc; 2121 if_t ifp; 2122 struct cmb *cmb; 2123 uint32_t status; 2124 2125 sc = (struct age_softc *)arg; 2126 2127 AGE_LOCK(sc); 2128 2129 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2130 sc->age_cdata.age_cmb_block_map, 2131 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2132 cmb = sc->age_rdata.age_cmb_block; 2133 status = le32toh(cmb->intr_status); 2134 if (sc->age_morework != 0) 2135 status |= INTR_CMB_RX; 2136 if ((status & AGE_INTRS) == 0) 2137 goto done; 2138 2139 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 2140 TPD_CONS_SHIFT; 2141 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 2142 RRD_PROD_SHIFT; 2143 /* Let hardware know CMB was served. */ 2144 cmb->intr_status = 0; 2145 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2146 sc->age_cdata.age_cmb_block_map, 2147 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2148 2149 ifp = sc->age_ifp; 2150 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2151 if ((status & INTR_CMB_RX) != 0) 2152 sc->age_morework = age_rxintr(sc, sc->age_rr_prod, 2153 sc->age_process_limit); 2154 if ((status & INTR_CMB_TX) != 0) 2155 age_txintr(sc, sc->age_tpd_cons); 2156 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2157 if ((status & INTR_DMA_RD_TO_RST) != 0) 2158 device_printf(sc->age_dev, 2159 "DMA read error! -- resetting\n"); 2160 if ((status & INTR_DMA_WR_TO_RST) != 0) 2161 device_printf(sc->age_dev, 2162 "DMA write error! -- resetting\n"); 2163 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2164 age_init_locked(sc); 2165 } 2166 if (!if_sendq_empty(ifp)) 2167 age_start_locked(ifp); 2168 if ((status & INTR_SMB) != 0) 2169 age_stats_update(sc); 2170 } 2171 2172 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 2173 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2174 sc->age_cdata.age_cmb_block_map, 2175 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2176 status = le32toh(cmb->intr_status); 2177 if (sc->age_morework != 0 || (status & AGE_INTRS) != 0) { 2178 taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2179 AGE_UNLOCK(sc); 2180 return; 2181 } 2182 2183 done: 2184 /* Re-enable interrupts. */ 2185 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2186 AGE_UNLOCK(sc); 2187 } 2188 2189 static void 2190 age_txintr(struct age_softc *sc, int tpd_cons) 2191 { 2192 if_t ifp; 2193 struct age_txdesc *txd; 2194 int cons, prog; 2195 2196 AGE_LOCK_ASSERT(sc); 2197 2198 ifp = sc->age_ifp; 2199 2200 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2201 sc->age_cdata.age_tx_ring_map, 2202 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2203 2204 /* 2205 * Go through our Tx list and free mbufs for those 2206 * frames which have been transmitted. 2207 */ 2208 cons = sc->age_cdata.age_tx_cons; 2209 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 2210 if (sc->age_cdata.age_tx_cnt <= 0) 2211 break; 2212 prog++; 2213 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2214 sc->age_cdata.age_tx_cnt--; 2215 txd = &sc->age_cdata.age_txdesc[cons]; 2216 /* 2217 * Clear Tx descriptors, it's not required but would 2218 * help debugging in case of Tx issues. 2219 */ 2220 txd->tx_desc->addr = 0; 2221 txd->tx_desc->len = 0; 2222 txd->tx_desc->flags = 0; 2223 2224 if (txd->tx_m == NULL) 2225 continue; 2226 /* Reclaim transmitted mbufs. */ 2227 bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap, 2228 BUS_DMASYNC_POSTWRITE); 2229 bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap); 2230 m_freem(txd->tx_m); 2231 txd->tx_m = NULL; 2232 } 2233 2234 if (prog > 0) { 2235 sc->age_cdata.age_tx_cons = cons; 2236 2237 /* 2238 * Unarm watchdog timer only when there are no pending 2239 * Tx descriptors in queue. 2240 */ 2241 if (sc->age_cdata.age_tx_cnt == 0) 2242 sc->age_watchdog_timer = 0; 2243 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2244 sc->age_cdata.age_tx_ring_map, 2245 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2246 } 2247 } 2248 2249 #ifndef __NO_STRICT_ALIGNMENT 2250 static struct mbuf * 2251 age_fixup_rx(if_t ifp, struct mbuf *m) 2252 { 2253 struct mbuf *n; 2254 int i; 2255 uint16_t *src, *dst; 2256 2257 src = mtod(m, uint16_t *); 2258 dst = src - 3; 2259 2260 if (m->m_next == NULL) { 2261 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2262 *dst++ = *src++; 2263 m->m_data -= 6; 2264 return (m); 2265 } 2266 /* 2267 * Append a new mbuf to received mbuf chain and copy ethernet 2268 * header from the mbuf chain. This can save lots of CPU 2269 * cycles for jumbo frame. 2270 */ 2271 MGETHDR(n, M_NOWAIT, MT_DATA); 2272 if (n == NULL) { 2273 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2274 m_freem(m); 2275 return (NULL); 2276 } 2277 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 2278 m->m_data += ETHER_HDR_LEN; 2279 m->m_len -= ETHER_HDR_LEN; 2280 n->m_len = ETHER_HDR_LEN; 2281 M_MOVE_PKTHDR(n, m); 2282 n->m_next = m; 2283 return (n); 2284 } 2285 #endif 2286 2287 /* Receive a frame. */ 2288 static void 2289 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 2290 { 2291 struct age_rxdesc *rxd; 2292 if_t ifp; 2293 struct mbuf *mp, *m; 2294 uint32_t status, index, vtag; 2295 int count, nsegs; 2296 int rx_cons; 2297 2298 AGE_LOCK_ASSERT(sc); 2299 2300 ifp = sc->age_ifp; 2301 status = le32toh(rxrd->flags); 2302 index = le32toh(rxrd->index); 2303 rx_cons = AGE_RX_CONS(index); 2304 nsegs = AGE_RX_NSEGS(index); 2305 2306 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2307 if ((status & (AGE_RRD_ERROR | AGE_RRD_LENGTH_NOK)) != 0) { 2308 /* 2309 * We want to pass the following frames to upper 2310 * layer regardless of error status of Rx return 2311 * ring. 2312 * 2313 * o IP/TCP/UDP checksum is bad. 2314 * o frame length and protocol specific length 2315 * does not match. 2316 */ 2317 status |= AGE_RRD_IPCSUM_NOK | AGE_RRD_TCP_UDPCSUM_NOK; 2318 if ((status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 2319 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) 2320 return; 2321 } 2322 2323 for (count = 0; count < nsegs; count++, 2324 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 2325 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 2326 mp = rxd->rx_m; 2327 /* Add a new receive buffer to the ring. */ 2328 if (age_newbuf(sc, rxd) != 0) { 2329 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2330 /* Reuse Rx buffers. */ 2331 if (sc->age_cdata.age_rxhead != NULL) 2332 m_freem(sc->age_cdata.age_rxhead); 2333 break; 2334 } 2335 2336 /* 2337 * Assume we've received a full sized frame. 2338 * Actual size is fixed when we encounter the end of 2339 * multi-segmented frame. 2340 */ 2341 mp->m_len = AGE_RX_BUF_SIZE; 2342 2343 /* Chain received mbufs. */ 2344 if (sc->age_cdata.age_rxhead == NULL) { 2345 sc->age_cdata.age_rxhead = mp; 2346 sc->age_cdata.age_rxtail = mp; 2347 } else { 2348 mp->m_flags &= ~M_PKTHDR; 2349 sc->age_cdata.age_rxprev_tail = 2350 sc->age_cdata.age_rxtail; 2351 sc->age_cdata.age_rxtail->m_next = mp; 2352 sc->age_cdata.age_rxtail = mp; 2353 } 2354 2355 if (count == nsegs - 1) { 2356 /* Last desc. for this frame. */ 2357 m = sc->age_cdata.age_rxhead; 2358 m->m_flags |= M_PKTHDR; 2359 /* 2360 * It seems that L1 controller has no way 2361 * to tell hardware to strip CRC bytes. 2362 */ 2363 m->m_pkthdr.len = sc->age_cdata.age_rxlen - 2364 ETHER_CRC_LEN; 2365 if (nsegs > 1) { 2366 /* Set last mbuf size. */ 2367 mp->m_len = sc->age_cdata.age_rxlen - 2368 ((nsegs - 1) * AGE_RX_BUF_SIZE); 2369 /* Remove the CRC bytes in chained mbufs. */ 2370 if (mp->m_len <= ETHER_CRC_LEN) { 2371 sc->age_cdata.age_rxtail = 2372 sc->age_cdata.age_rxprev_tail; 2373 sc->age_cdata.age_rxtail->m_len -= 2374 (ETHER_CRC_LEN - mp->m_len); 2375 sc->age_cdata.age_rxtail->m_next = NULL; 2376 m_freem(mp); 2377 } else { 2378 mp->m_len -= ETHER_CRC_LEN; 2379 } 2380 } else 2381 m->m_len = m->m_pkthdr.len; 2382 m->m_pkthdr.rcvif = ifp; 2383 /* 2384 * Set checksum information. 2385 * It seems that L1 controller can compute partial 2386 * checksum. The partial checksum value can be used 2387 * to accelerate checksum computation for fragmented 2388 * TCP/UDP packets. Upper network stack already 2389 * takes advantage of the partial checksum value in 2390 * IP reassembly stage. But I'm not sure the 2391 * correctness of the partial hardware checksum 2392 * assistance due to lack of data sheet. If it is 2393 * proven to work on L1 I'll enable it. 2394 */ 2395 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 && 2396 (status & AGE_RRD_IPV4) != 0) { 2397 if ((status & AGE_RRD_IPCSUM_NOK) == 0) 2398 m->m_pkthdr.csum_flags |= 2399 CSUM_IP_CHECKED | CSUM_IP_VALID; 2400 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 2401 (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) { 2402 m->m_pkthdr.csum_flags |= 2403 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2404 m->m_pkthdr.csum_data = 0xffff; 2405 } 2406 /* 2407 * Don't mark bad checksum for TCP/UDP frames 2408 * as fragmented frames may always have set 2409 * bad checksummed bit of descriptor status. 2410 */ 2411 } 2412 2413 /* Check for VLAN tagged frames. */ 2414 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 2415 (status & AGE_RRD_VLAN) != 0) { 2416 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 2417 m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag); 2418 m->m_flags |= M_VLANTAG; 2419 } 2420 #ifndef __NO_STRICT_ALIGNMENT 2421 m = age_fixup_rx(ifp, m); 2422 if (m != NULL) 2423 #endif 2424 { 2425 /* Pass it on. */ 2426 AGE_UNLOCK(sc); 2427 if_input(ifp, m); 2428 AGE_LOCK(sc); 2429 } 2430 } 2431 } 2432 2433 /* Reset mbuf chains. */ 2434 AGE_RXCHAIN_RESET(sc); 2435 } 2436 2437 static int 2438 age_rxintr(struct age_softc *sc, int rr_prod, int count) 2439 { 2440 struct rx_rdesc *rxrd; 2441 int rr_cons, nsegs, pktlen, prog; 2442 2443 AGE_LOCK_ASSERT(sc); 2444 2445 rr_cons = sc->age_cdata.age_rr_cons; 2446 if (rr_cons == rr_prod) 2447 return (0); 2448 2449 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2450 sc->age_cdata.age_rr_ring_map, 2451 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2452 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2453 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_POSTWRITE); 2454 2455 for (prog = 0; rr_cons != rr_prod; prog++) { 2456 if (count-- <= 0) 2457 break; 2458 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 2459 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 2460 if (nsegs == 0) 2461 break; 2462 /* 2463 * Check number of segments against received bytes. 2464 * Non-matching value would indicate that hardware 2465 * is still trying to update Rx return descriptors. 2466 * I'm not sure whether this check is really needed. 2467 */ 2468 pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2469 if (nsegs != howmany(pktlen, AGE_RX_BUF_SIZE)) 2470 break; 2471 2472 /* Received a frame. */ 2473 age_rxeof(sc, rxrd); 2474 /* Clear return ring. */ 2475 rxrd->index = 0; 2476 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 2477 sc->age_cdata.age_rx_cons += nsegs; 2478 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2479 } 2480 2481 if (prog > 0) { 2482 /* Update the consumer index. */ 2483 sc->age_cdata.age_rr_cons = rr_cons; 2484 2485 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2486 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE); 2487 /* Sync descriptors. */ 2488 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2489 sc->age_cdata.age_rr_ring_map, 2490 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2491 2492 /* Notify hardware availability of new Rx buffers. */ 2493 AGE_COMMIT_MBOX(sc); 2494 } 2495 2496 return (count > 0 ? 0 : EAGAIN); 2497 } 2498 2499 static void 2500 age_tick(void *arg) 2501 { 2502 struct age_softc *sc; 2503 struct mii_data *mii; 2504 2505 sc = (struct age_softc *)arg; 2506 2507 AGE_LOCK_ASSERT(sc); 2508 2509 mii = device_get_softc(sc->age_miibus); 2510 mii_tick(mii); 2511 age_watchdog(sc); 2512 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2513 } 2514 2515 static void 2516 age_reset(struct age_softc *sc) 2517 { 2518 uint32_t reg; 2519 int i; 2520 2521 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 2522 CSR_READ_4(sc, AGE_MASTER_CFG); 2523 DELAY(1000); 2524 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2525 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2526 break; 2527 DELAY(10); 2528 } 2529 2530 if (i == 0) 2531 device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg); 2532 /* Initialize PCIe module. From Linux. */ 2533 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2534 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2535 } 2536 2537 static void 2538 age_init(void *xsc) 2539 { 2540 struct age_softc *sc; 2541 2542 sc = (struct age_softc *)xsc; 2543 AGE_LOCK(sc); 2544 age_init_locked(sc); 2545 AGE_UNLOCK(sc); 2546 } 2547 2548 static void 2549 age_init_locked(struct age_softc *sc) 2550 { 2551 if_t ifp; 2552 struct mii_data *mii; 2553 uint8_t eaddr[ETHER_ADDR_LEN]; 2554 bus_addr_t paddr; 2555 uint32_t reg, fsize; 2556 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 2557 int error; 2558 2559 AGE_LOCK_ASSERT(sc); 2560 2561 ifp = sc->age_ifp; 2562 mii = device_get_softc(sc->age_miibus); 2563 2564 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2565 return; 2566 2567 /* 2568 * Cancel any pending I/O. 2569 */ 2570 age_stop(sc); 2571 2572 /* 2573 * Reset the chip to a known state. 2574 */ 2575 age_reset(sc); 2576 2577 /* Initialize descriptors. */ 2578 error = age_init_rx_ring(sc); 2579 if (error != 0) { 2580 device_printf(sc->age_dev, "no memory for Rx buffers.\n"); 2581 age_stop(sc); 2582 return; 2583 } 2584 age_init_rr_ring(sc); 2585 age_init_tx_ring(sc); 2586 age_init_cmb_block(sc); 2587 age_init_smb_block(sc); 2588 2589 /* Reprogram the station address. */ 2590 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN); 2591 CSR_WRITE_4(sc, AGE_PAR0, 2592 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2593 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 2594 2595 /* Set descriptor base addresses. */ 2596 paddr = sc->age_rdata.age_tx_ring_paddr; 2597 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 2598 paddr = sc->age_rdata.age_rx_ring_paddr; 2599 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 2600 paddr = sc->age_rdata.age_rr_ring_paddr; 2601 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 2602 paddr = sc->age_rdata.age_tx_ring_paddr; 2603 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 2604 paddr = sc->age_rdata.age_cmb_block_paddr; 2605 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2606 paddr = sc->age_rdata.age_smb_block_paddr; 2607 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2608 /* Set Rx/Rx return descriptor counter. */ 2609 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 2610 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 2611 DESC_RRD_CNT_MASK) | 2612 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 2613 /* Set Tx descriptor counter. */ 2614 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 2615 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 2616 2617 /* Tell hardware that we're ready to load descriptors. */ 2618 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 2619 2620 /* 2621 * Initialize mailbox register. 2622 * Updated producer/consumer index information is exchanged 2623 * through this mailbox register. However Tx producer and 2624 * Rx return consumer/Rx producer are all shared such that 2625 * it's hard to separate code path between Tx and Rx without 2626 * locking. If L1 hardware have a separate mail box register 2627 * for Tx and Rx consumer/producer management we could have 2628 * independent Tx/Rx handler which in turn Rx handler could have 2629 * been run without any locking. 2630 */ 2631 AGE_COMMIT_MBOX(sc); 2632 2633 /* Configure IPG/IFG parameters. */ 2634 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 2635 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 2636 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2637 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2638 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 2639 2640 /* Set parameters for half-duplex media. */ 2641 CSR_WRITE_4(sc, AGE_HDPX_CFG, 2642 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2643 HDPX_CFG_LCOL_MASK) | 2644 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2645 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2646 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2647 HDPX_CFG_ABEBT_MASK) | 2648 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2649 HDPX_CFG_JAMIPG_MASK)); 2650 2651 /* Configure interrupt moderation timer. */ 2652 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 2653 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 2654 reg &= ~MASTER_MTIMER_ENB; 2655 if (AGE_USECS(sc->age_int_mod) == 0) 2656 reg &= ~MASTER_ITIMER_ENB; 2657 else 2658 reg |= MASTER_ITIMER_ENB; 2659 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 2660 if (bootverbose) 2661 device_printf(sc->age_dev, "interrupt moderation is %d us.\n", 2662 sc->age_int_mod); 2663 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 2664 2665 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 2666 if (if_getmtu(ifp) < ETHERMTU) 2667 sc->age_max_frame_size = ETHERMTU; 2668 else 2669 sc->age_max_frame_size = if_getmtu(ifp); 2670 sc->age_max_frame_size += ETHER_HDR_LEN + 2671 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 2672 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 2673 /* Configure jumbo frame. */ 2674 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 2675 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 2676 (((fsize / sizeof(uint64_t)) << 2677 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 2678 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 2679 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 2680 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 2681 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 2682 2683 /* Configure flow-control parameters. From Linux. */ 2684 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 2685 /* 2686 * Magic workaround for old-L1. 2687 * Don't know which hw revision requires this magic. 2688 */ 2689 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2690 /* 2691 * Another magic workaround for flow-control mode 2692 * change. From Linux. 2693 */ 2694 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2695 } 2696 /* 2697 * TODO 2698 * Should understand pause parameter relationships between FIFO 2699 * size and number of Rx descriptors and Rx return descriptors. 2700 * 2701 * Magic parameters came from Linux. 2702 */ 2703 switch (sc->age_chip_rev) { 2704 case 0x8001: 2705 case 0x9001: 2706 case 0x9002: 2707 case 0x9003: 2708 rxf_hi = AGE_RX_RING_CNT / 16; 2709 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 2710 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 2711 rrd_lo = AGE_RR_RING_CNT / 16; 2712 break; 2713 default: 2714 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 2715 rxf_lo = reg / 16; 2716 if (rxf_lo < 192) 2717 rxf_lo = 192; 2718 rxf_hi = (reg * 7) / 8; 2719 if (rxf_hi < rxf_lo) 2720 rxf_hi = rxf_lo + 16; 2721 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 2722 rrd_lo = reg / 8; 2723 rrd_hi = (reg * 7) / 8; 2724 if (rrd_lo < 2) 2725 rrd_lo = 2; 2726 if (rrd_hi < rrd_lo) 2727 rrd_hi = rrd_lo + 3; 2728 break; 2729 } 2730 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 2731 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 2732 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 2733 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 2734 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 2735 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 2736 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 2737 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 2738 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 2739 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 2740 2741 /* Configure RxQ. */ 2742 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2743 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2744 RXQ_CFG_RD_BURST_MASK) | 2745 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 2746 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 2747 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 2748 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 2749 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2750 2751 /* Configure TxQ. */ 2752 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2753 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2754 TXQ_CFG_TPD_BURST_MASK) | 2755 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 2756 TXQ_CFG_TX_FIFO_BURST_MASK) | 2757 ((TXQ_CFG_TPD_FETCH_DEFAULT << 2758 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 2759 TXQ_CFG_ENB); 2760 2761 CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG, 2762 (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) & 2763 TX_JUMBO_TPD_TH_MASK) | 2764 ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) & 2765 TX_JUMBO_TPD_IPG_MASK)); 2766 /* Configure DMA parameters. */ 2767 CSR_WRITE_4(sc, AGE_DMA_CFG, 2768 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 2769 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 2770 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 2771 2772 /* Configure CMB DMA write threshold. */ 2773 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 2774 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 2775 CMB_WR_THRESH_RRD_MASK) | 2776 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 2777 CMB_WR_THRESH_TPD_MASK)); 2778 2779 /* Set CMB/SMB timer and enable them. */ 2780 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 2781 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 2782 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 2783 /* Request SMB updates for every seconds. */ 2784 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 2785 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 2786 2787 /* 2788 * Disable all WOL bits as WOL can interfere normal Rx 2789 * operation. 2790 */ 2791 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 2792 2793 /* 2794 * Configure Tx/Rx MACs. 2795 * - Auto-padding for short frames. 2796 * - Enable CRC generation. 2797 * Start with full-duplex/1000Mbps media. Actual reconfiguration 2798 * of MAC is followed after link establishment. 2799 */ 2800 CSR_WRITE_4(sc, AGE_MAC_CFG, 2801 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 2802 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 2803 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2804 MAC_CFG_PREAMBLE_MASK)); 2805 /* Set up the receive filter. */ 2806 age_rxfilter(sc); 2807 age_rxvlan(sc); 2808 2809 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2810 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 2811 reg |= MAC_CFG_RXCSUM_ENB; 2812 2813 /* Ack all pending interrupts and clear it. */ 2814 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2815 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 2816 2817 /* Finally enable Tx/Rx MAC. */ 2818 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2819 2820 sc->age_flags &= ~AGE_FLAG_LINK; 2821 /* Switch to the current media. */ 2822 mii_mediachg(mii); 2823 2824 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2825 2826 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2827 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2828 } 2829 2830 static void 2831 age_stop(struct age_softc *sc) 2832 { 2833 if_t ifp; 2834 struct age_txdesc *txd; 2835 struct age_rxdesc *rxd; 2836 uint32_t reg; 2837 int i; 2838 2839 AGE_LOCK_ASSERT(sc); 2840 /* 2841 * Mark the interface down and cancel the watchdog timer. 2842 */ 2843 ifp = sc->age_ifp; 2844 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2845 sc->age_flags &= ~AGE_FLAG_LINK; 2846 callout_stop(&sc->age_tick_ch); 2847 sc->age_watchdog_timer = 0; 2848 2849 /* 2850 * Disable interrupts. 2851 */ 2852 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 2853 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 2854 /* Stop CMB/SMB updates. */ 2855 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 2856 /* Stop Rx/Tx MAC. */ 2857 age_stop_rxmac(sc); 2858 age_stop_txmac(sc); 2859 /* Stop DMA. */ 2860 CSR_WRITE_4(sc, AGE_DMA_CFG, 2861 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 2862 /* Stop TxQ/RxQ. */ 2863 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2864 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 2865 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2866 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 2867 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2868 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2869 break; 2870 DELAY(10); 2871 } 2872 if (i == 0) 2873 device_printf(sc->age_dev, 2874 "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg); 2875 2876 /* Reclaim Rx buffers that have been processed. */ 2877 if (sc->age_cdata.age_rxhead != NULL) 2878 m_freem(sc->age_cdata.age_rxhead); 2879 AGE_RXCHAIN_RESET(sc); 2880 /* 2881 * Free RX and TX mbufs still in the queues. 2882 */ 2883 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2884 rxd = &sc->age_cdata.age_rxdesc[i]; 2885 if (rxd->rx_m != NULL) { 2886 bus_dmamap_sync(sc->age_cdata.age_rx_tag, 2887 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2888 bus_dmamap_unload(sc->age_cdata.age_rx_tag, 2889 rxd->rx_dmamap); 2890 m_freem(rxd->rx_m); 2891 rxd->rx_m = NULL; 2892 } 2893 } 2894 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2895 txd = &sc->age_cdata.age_txdesc[i]; 2896 if (txd->tx_m != NULL) { 2897 bus_dmamap_sync(sc->age_cdata.age_tx_tag, 2898 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2899 bus_dmamap_unload(sc->age_cdata.age_tx_tag, 2900 txd->tx_dmamap); 2901 m_freem(txd->tx_m); 2902 txd->tx_m = NULL; 2903 } 2904 } 2905 } 2906 2907 static void 2908 age_stop_txmac(struct age_softc *sc) 2909 { 2910 uint32_t reg; 2911 int i; 2912 2913 AGE_LOCK_ASSERT(sc); 2914 2915 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2916 if ((reg & MAC_CFG_TX_ENB) != 0) { 2917 reg &= ~MAC_CFG_TX_ENB; 2918 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2919 } 2920 /* Stop Tx DMA engine. */ 2921 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2922 if ((reg & DMA_CFG_RD_ENB) != 0) { 2923 reg &= ~DMA_CFG_RD_ENB; 2924 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2925 } 2926 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2927 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2928 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2929 break; 2930 DELAY(10); 2931 } 2932 if (i == 0) 2933 device_printf(sc->age_dev, "stopping TxMAC timeout!\n"); 2934 } 2935 2936 static void 2937 age_stop_rxmac(struct age_softc *sc) 2938 { 2939 uint32_t reg; 2940 int i; 2941 2942 AGE_LOCK_ASSERT(sc); 2943 2944 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2945 if ((reg & MAC_CFG_RX_ENB) != 0) { 2946 reg &= ~MAC_CFG_RX_ENB; 2947 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2948 } 2949 /* Stop Rx DMA engine. */ 2950 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2951 if ((reg & DMA_CFG_WR_ENB) != 0) { 2952 reg &= ~DMA_CFG_WR_ENB; 2953 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2954 } 2955 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2956 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2957 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2958 break; 2959 DELAY(10); 2960 } 2961 if (i == 0) 2962 device_printf(sc->age_dev, "stopping RxMAC timeout!\n"); 2963 } 2964 2965 static void 2966 age_init_tx_ring(struct age_softc *sc) 2967 { 2968 struct age_ring_data *rd; 2969 struct age_txdesc *txd; 2970 int i; 2971 2972 AGE_LOCK_ASSERT(sc); 2973 2974 sc->age_cdata.age_tx_prod = 0; 2975 sc->age_cdata.age_tx_cons = 0; 2976 sc->age_cdata.age_tx_cnt = 0; 2977 2978 rd = &sc->age_rdata; 2979 bzero(rd->age_tx_ring, AGE_TX_RING_SZ); 2980 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2981 txd = &sc->age_cdata.age_txdesc[i]; 2982 txd->tx_desc = &rd->age_tx_ring[i]; 2983 txd->tx_m = NULL; 2984 } 2985 2986 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2987 sc->age_cdata.age_tx_ring_map, 2988 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2989 } 2990 2991 static int 2992 age_init_rx_ring(struct age_softc *sc) 2993 { 2994 struct age_ring_data *rd; 2995 struct age_rxdesc *rxd; 2996 int i; 2997 2998 AGE_LOCK_ASSERT(sc); 2999 3000 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 3001 sc->age_morework = 0; 3002 rd = &sc->age_rdata; 3003 bzero(rd->age_rx_ring, AGE_RX_RING_SZ); 3004 for (i = 0; i < AGE_RX_RING_CNT; i++) { 3005 rxd = &sc->age_cdata.age_rxdesc[i]; 3006 rxd->rx_m = NULL; 3007 rxd->rx_desc = &rd->age_rx_ring[i]; 3008 if (age_newbuf(sc, rxd) != 0) 3009 return (ENOBUFS); 3010 } 3011 3012 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 3013 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE); 3014 3015 return (0); 3016 } 3017 3018 static void 3019 age_init_rr_ring(struct age_softc *sc) 3020 { 3021 struct age_ring_data *rd; 3022 3023 AGE_LOCK_ASSERT(sc); 3024 3025 sc->age_cdata.age_rr_cons = 0; 3026 AGE_RXCHAIN_RESET(sc); 3027 3028 rd = &sc->age_rdata; 3029 bzero(rd->age_rr_ring, AGE_RR_RING_SZ); 3030 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 3031 sc->age_cdata.age_rr_ring_map, 3032 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3033 } 3034 3035 static void 3036 age_init_cmb_block(struct age_softc *sc) 3037 { 3038 struct age_ring_data *rd; 3039 3040 AGE_LOCK_ASSERT(sc); 3041 3042 rd = &sc->age_rdata; 3043 bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ); 3044 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 3045 sc->age_cdata.age_cmb_block_map, 3046 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3047 } 3048 3049 static void 3050 age_init_smb_block(struct age_softc *sc) 3051 { 3052 struct age_ring_data *rd; 3053 3054 AGE_LOCK_ASSERT(sc); 3055 3056 rd = &sc->age_rdata; 3057 bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ); 3058 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 3059 sc->age_cdata.age_smb_block_map, 3060 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3061 } 3062 3063 static int 3064 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd) 3065 { 3066 struct rx_desc *desc; 3067 struct mbuf *m; 3068 bus_dma_segment_t segs[1]; 3069 bus_dmamap_t map; 3070 int nsegs; 3071 3072 AGE_LOCK_ASSERT(sc); 3073 3074 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3075 if (m == NULL) 3076 return (ENOBUFS); 3077 m->m_len = m->m_pkthdr.len = MCLBYTES; 3078 #ifndef __NO_STRICT_ALIGNMENT 3079 m_adj(m, AGE_RX_BUF_ALIGN); 3080 #endif 3081 3082 if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag, 3083 sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3084 m_freem(m); 3085 return (ENOBUFS); 3086 } 3087 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3088 3089 if (rxd->rx_m != NULL) { 3090 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3091 BUS_DMASYNC_POSTREAD); 3092 bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap); 3093 } 3094 map = rxd->rx_dmamap; 3095 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 3096 sc->age_cdata.age_rx_sparemap = map; 3097 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3098 BUS_DMASYNC_PREREAD); 3099 rxd->rx_m = m; 3100 3101 desc = rxd->rx_desc; 3102 desc->addr = htole64(segs[0].ds_addr); 3103 desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) << 3104 AGE_RD_LEN_SHIFT); 3105 return (0); 3106 } 3107 3108 static void 3109 age_rxvlan(struct age_softc *sc) 3110 { 3111 if_t ifp; 3112 uint32_t reg; 3113 3114 AGE_LOCK_ASSERT(sc); 3115 3116 ifp = sc->age_ifp; 3117 reg = CSR_READ_4(sc, AGE_MAC_CFG); 3118 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3119 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 3120 reg |= MAC_CFG_VLAN_TAG_STRIP; 3121 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 3122 } 3123 3124 static u_int 3125 age_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 3126 { 3127 uint32_t *mchash = arg; 3128 uint32_t crc; 3129 3130 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 3131 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3132 3133 return (1); 3134 } 3135 3136 static void 3137 age_rxfilter(struct age_softc *sc) 3138 { 3139 if_t ifp; 3140 uint32_t mchash[2]; 3141 uint32_t rxcfg; 3142 3143 AGE_LOCK_ASSERT(sc); 3144 3145 ifp = sc->age_ifp; 3146 3147 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 3148 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3149 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 3150 rxcfg |= MAC_CFG_BCAST; 3151 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3152 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 3153 rxcfg |= MAC_CFG_PROMISC; 3154 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 3155 rxcfg |= MAC_CFG_ALLMULTI; 3156 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); 3157 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); 3158 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3159 return; 3160 } 3161 3162 /* Program new filter. */ 3163 bzero(mchash, sizeof(mchash)); 3164 if_foreach_llmaddr(ifp, age_hash_maddr, mchash); 3165 3166 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 3167 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 3168 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3169 } 3170 3171 static int 3172 sysctl_age_stats(SYSCTL_HANDLER_ARGS) 3173 { 3174 struct age_softc *sc; 3175 struct age_stats *stats; 3176 int error, result; 3177 3178 result = -1; 3179 error = sysctl_handle_int(oidp, &result, 0, req); 3180 3181 if (error != 0 || req->newptr == NULL) 3182 return (error); 3183 3184 if (result != 1) 3185 return (error); 3186 3187 sc = (struct age_softc *)arg1; 3188 stats = &sc->age_stat; 3189 printf("%s statistics:\n", device_get_nameunit(sc->age_dev)); 3190 printf("Transmit good frames : %ju\n", 3191 (uintmax_t)stats->tx_frames); 3192 printf("Transmit good broadcast frames : %ju\n", 3193 (uintmax_t)stats->tx_bcast_frames); 3194 printf("Transmit good multicast frames : %ju\n", 3195 (uintmax_t)stats->tx_mcast_frames); 3196 printf("Transmit pause control frames : %u\n", 3197 stats->tx_pause_frames); 3198 printf("Transmit control frames : %u\n", 3199 stats->tx_control_frames); 3200 printf("Transmit frames with excessive deferrals : %u\n", 3201 stats->tx_excess_defer); 3202 printf("Transmit deferrals : %u\n", 3203 stats->tx_deferred); 3204 printf("Transmit good octets : %ju\n", 3205 (uintmax_t)stats->tx_bytes); 3206 printf("Transmit good broadcast octets : %ju\n", 3207 (uintmax_t)stats->tx_bcast_bytes); 3208 printf("Transmit good multicast octets : %ju\n", 3209 (uintmax_t)stats->tx_mcast_bytes); 3210 printf("Transmit frames 64 bytes : %ju\n", 3211 (uintmax_t)stats->tx_pkts_64); 3212 printf("Transmit frames 65 to 127 bytes : %ju\n", 3213 (uintmax_t)stats->tx_pkts_65_127); 3214 printf("Transmit frames 128 to 255 bytes : %ju\n", 3215 (uintmax_t)stats->tx_pkts_128_255); 3216 printf("Transmit frames 256 to 511 bytes : %ju\n", 3217 (uintmax_t)stats->tx_pkts_256_511); 3218 printf("Transmit frames 512 to 1024 bytes : %ju\n", 3219 (uintmax_t)stats->tx_pkts_512_1023); 3220 printf("Transmit frames 1024 to 1518 bytes : %ju\n", 3221 (uintmax_t)stats->tx_pkts_1024_1518); 3222 printf("Transmit frames 1519 to MTU bytes : %ju\n", 3223 (uintmax_t)stats->tx_pkts_1519_max); 3224 printf("Transmit single collisions : %u\n", 3225 stats->tx_single_colls); 3226 printf("Transmit multiple collisions : %u\n", 3227 stats->tx_multi_colls); 3228 printf("Transmit late collisions : %u\n", 3229 stats->tx_late_colls); 3230 printf("Transmit abort due to excessive collisions : %u\n", 3231 stats->tx_excess_colls); 3232 printf("Transmit underruns due to FIFO underruns : %u\n", 3233 stats->tx_underrun); 3234 printf("Transmit descriptor write-back errors : %u\n", 3235 stats->tx_desc_underrun); 3236 printf("Transmit frames with length mismatched frame size : %u\n", 3237 stats->tx_lenerrs); 3238 printf("Transmit frames with truncated due to MTU size : %u\n", 3239 stats->tx_lenerrs); 3240 3241 printf("Receive good frames : %ju\n", 3242 (uintmax_t)stats->rx_frames); 3243 printf("Receive good broadcast frames : %ju\n", 3244 (uintmax_t)stats->rx_bcast_frames); 3245 printf("Receive good multicast frames : %ju\n", 3246 (uintmax_t)stats->rx_mcast_frames); 3247 printf("Receive pause control frames : %u\n", 3248 stats->rx_pause_frames); 3249 printf("Receive control frames : %u\n", 3250 stats->rx_control_frames); 3251 printf("Receive CRC errors : %u\n", 3252 stats->rx_crcerrs); 3253 printf("Receive frames with length errors : %u\n", 3254 stats->rx_lenerrs); 3255 printf("Receive good octets : %ju\n", 3256 (uintmax_t)stats->rx_bytes); 3257 printf("Receive good broadcast octets : %ju\n", 3258 (uintmax_t)stats->rx_bcast_bytes); 3259 printf("Receive good multicast octets : %ju\n", 3260 (uintmax_t)stats->rx_mcast_bytes); 3261 printf("Receive frames too short : %u\n", 3262 stats->rx_runts); 3263 printf("Receive fragmented frames : %ju\n", 3264 (uintmax_t)stats->rx_fragments); 3265 printf("Receive frames 64 bytes : %ju\n", 3266 (uintmax_t)stats->rx_pkts_64); 3267 printf("Receive frames 65 to 127 bytes : %ju\n", 3268 (uintmax_t)stats->rx_pkts_65_127); 3269 printf("Receive frames 128 to 255 bytes : %ju\n", 3270 (uintmax_t)stats->rx_pkts_128_255); 3271 printf("Receive frames 256 to 511 bytes : %ju\n", 3272 (uintmax_t)stats->rx_pkts_256_511); 3273 printf("Receive frames 512 to 1024 bytes : %ju\n", 3274 (uintmax_t)stats->rx_pkts_512_1023); 3275 printf("Receive frames 1024 to 1518 bytes : %ju\n", 3276 (uintmax_t)stats->rx_pkts_1024_1518); 3277 printf("Receive frames 1519 to MTU bytes : %ju\n", 3278 (uintmax_t)stats->rx_pkts_1519_max); 3279 printf("Receive frames too long : %ju\n", 3280 (uint64_t)stats->rx_pkts_truncated); 3281 printf("Receive frames with FIFO overflow : %u\n", 3282 stats->rx_fifo_oflows); 3283 printf("Receive frames with return descriptor overflow : %u\n", 3284 stats->rx_desc_oflows); 3285 printf("Receive frames with alignment errors : %u\n", 3286 stats->rx_alignerrs); 3287 printf("Receive frames dropped due to address filtering : %ju\n", 3288 (uint64_t)stats->rx_pkts_filtered); 3289 3290 return (error); 3291 } 3292 3293 static int 3294 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3295 { 3296 int error, value; 3297 3298 if (arg1 == NULL) 3299 return (EINVAL); 3300 value = *(int *)arg1; 3301 error = sysctl_handle_int(oidp, &value, 0, req); 3302 if (error || req->newptr == NULL) 3303 return (error); 3304 if (value < low || value > high) 3305 return (EINVAL); 3306 *(int *)arg1 = value; 3307 3308 return (0); 3309 } 3310 3311 static int 3312 sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS) 3313 { 3314 return (sysctl_int_range(oidp, arg1, arg2, req, 3315 AGE_PROC_MIN, AGE_PROC_MAX)); 3316 } 3317 3318 static int 3319 sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS) 3320 { 3321 3322 return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN, 3323 AGE_IM_TIMER_MAX)); 3324 } 3325