1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008 Stanislav Sedov <[email protected]>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * Driver for Attansic Technology Corp. L2 FastEthernet adapter. 28 * 29 * This driver is heavily based on age(4) Attansic L1 driver by Pyun YongHyeon. 30 */ 31 32 #include <sys/cdefs.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/mbuf.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 #include <sys/module.h> 44 #include <sys/queue.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 #include <sys/taskqueue.h> 49 50 #include <net/bpf.h> 51 #include <net/if.h> 52 #include <net/if_var.h> 53 #include <net/if_arp.h> 54 #include <net/ethernet.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 #include <net/if_vlan_var.h> 59 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/ip.h> 63 #include <netinet/tcp.h> 64 65 #include <dev/mii/mii.h> 66 #include <dev/mii/miivar.h> 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 70 #include <machine/bus.h> 71 72 #include "miibus_if.h" 73 74 #include "if_aereg.h" 75 #include "if_aevar.h" 76 77 /* 78 * Devices supported by this driver. 79 */ 80 static struct ae_dev { 81 uint16_t vendorid; 82 uint16_t deviceid; 83 const char *name; 84 } ae_devs[] = { 85 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L2, 86 "Attansic Technology Corp, L2 FastEthernet" }, 87 }; 88 #define AE_DEVS_COUNT nitems(ae_devs) 89 90 static struct resource_spec ae_res_spec_mem[] = { 91 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 92 { -1, 0, 0 } 93 }; 94 static struct resource_spec ae_res_spec_irq[] = { 95 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 96 { -1, 0, 0 } 97 }; 98 static struct resource_spec ae_res_spec_msi[] = { 99 { SYS_RES_IRQ, 1, RF_ACTIVE }, 100 { -1, 0, 0 } 101 }; 102 103 static int ae_probe(device_t dev); 104 static int ae_attach(device_t dev); 105 static void ae_pcie_init(ae_softc_t *sc); 106 static void ae_phy_reset(ae_softc_t *sc); 107 static void ae_phy_init(ae_softc_t *sc); 108 static int ae_reset(ae_softc_t *sc); 109 static void ae_init(void *arg); 110 static int ae_init_locked(ae_softc_t *sc); 111 static int ae_detach(device_t dev); 112 static int ae_miibus_readreg(device_t dev, int phy, int reg); 113 static int ae_miibus_writereg(device_t dev, int phy, int reg, int val); 114 static void ae_miibus_statchg(device_t dev); 115 static void ae_mediastatus(if_t ifp, struct ifmediareq *ifmr); 116 static int ae_mediachange(if_t ifp); 117 static void ae_retrieve_address(ae_softc_t *sc); 118 static void ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, 119 int error); 120 static int ae_alloc_rings(ae_softc_t *sc); 121 static void ae_dma_free(ae_softc_t *sc); 122 static int ae_shutdown(device_t dev); 123 static int ae_suspend(device_t dev); 124 static void ae_powersave_disable(ae_softc_t *sc); 125 static void ae_powersave_enable(ae_softc_t *sc); 126 static int ae_resume(device_t dev); 127 static unsigned int ae_tx_avail_size(ae_softc_t *sc); 128 static int ae_encap(ae_softc_t *sc, struct mbuf **m_head); 129 static void ae_start(if_t ifp); 130 static void ae_start_locked(if_t ifp); 131 static void ae_link_task(void *arg, int pending); 132 static void ae_stop_rxmac(ae_softc_t *sc); 133 static void ae_stop_txmac(ae_softc_t *sc); 134 static void ae_mac_config(ae_softc_t *sc); 135 static int ae_intr(void *arg); 136 static void ae_int_task(void *arg, int pending); 137 static void ae_tx_intr(ae_softc_t *sc); 138 static void ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd); 139 static void ae_rx_intr(ae_softc_t *sc); 140 static void ae_watchdog(ae_softc_t *sc); 141 static void ae_tick(void *arg); 142 static void ae_rxfilter(ae_softc_t *sc); 143 static void ae_rxvlan(ae_softc_t *sc); 144 static int ae_ioctl(if_t ifp, u_long cmd, caddr_t data); 145 static void ae_stop(ae_softc_t *sc); 146 static int ae_check_eeprom_present(ae_softc_t *sc, int *vpdc); 147 static int ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word); 148 static int ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr); 149 static int ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr); 150 static void ae_update_stats_rx(uint16_t flags, ae_stats_t *stats); 151 static void ae_update_stats_tx(uint16_t flags, ae_stats_t *stats); 152 static void ae_init_tunables(ae_softc_t *sc); 153 154 static device_method_t ae_methods[] = { 155 /* Device interface. */ 156 DEVMETHOD(device_probe, ae_probe), 157 DEVMETHOD(device_attach, ae_attach), 158 DEVMETHOD(device_detach, ae_detach), 159 DEVMETHOD(device_shutdown, ae_shutdown), 160 DEVMETHOD(device_suspend, ae_suspend), 161 DEVMETHOD(device_resume, ae_resume), 162 163 /* MII interface. */ 164 DEVMETHOD(miibus_readreg, ae_miibus_readreg), 165 DEVMETHOD(miibus_writereg, ae_miibus_writereg), 166 DEVMETHOD(miibus_statchg, ae_miibus_statchg), 167 { NULL, NULL } 168 }; 169 static driver_t ae_driver = { 170 "ae", 171 ae_methods, 172 sizeof(ae_softc_t) 173 }; 174 175 DRIVER_MODULE(ae, pci, ae_driver, 0, 0); 176 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, ae, ae_devs, 177 nitems(ae_devs)); 178 DRIVER_MODULE(miibus, ae, miibus_driver, 0, 0); 179 MODULE_DEPEND(ae, pci, 1, 1, 1); 180 MODULE_DEPEND(ae, ether, 1, 1, 1); 181 MODULE_DEPEND(ae, miibus, 1, 1, 1); 182 183 /* 184 * Tunables. 185 */ 186 static int msi_disable = 0; 187 TUNABLE_INT("hw.ae.msi_disable", &msi_disable); 188 189 #define AE_READ_4(sc, reg) \ 190 bus_read_4((sc)->mem[0], (reg)) 191 #define AE_READ_2(sc, reg) \ 192 bus_read_2((sc)->mem[0], (reg)) 193 #define AE_READ_1(sc, reg) \ 194 bus_read_1((sc)->mem[0], (reg)) 195 #define AE_WRITE_4(sc, reg, val) \ 196 bus_write_4((sc)->mem[0], (reg), (val)) 197 #define AE_WRITE_2(sc, reg, val) \ 198 bus_write_2((sc)->mem[0], (reg), (val)) 199 #define AE_WRITE_1(sc, reg, val) \ 200 bus_write_1((sc)->mem[0], (reg), (val)) 201 #define AE_PHY_READ(sc, reg) \ 202 ae_miibus_readreg(sc->dev, 0, reg) 203 #define AE_PHY_WRITE(sc, reg, val) \ 204 ae_miibus_writereg(sc->dev, 0, reg, val) 205 #define AE_CHECK_EADDR_VALID(eaddr) \ 206 ((eaddr[0] == 0 && eaddr[1] == 0) || \ 207 (eaddr[0] == 0xffffffff && eaddr[1] == 0xffff)) 208 #define AE_RXD_VLAN(vtag) \ 209 (((vtag) >> 4) | (((vtag) & 0x07) << 13) | (((vtag) & 0x08) << 9)) 210 #define AE_TXD_VLAN(vtag) \ 211 (((vtag) << 4) | (((vtag) >> 13) & 0x07) | (((vtag) >> 9) & 0x08)) 212 213 static int 214 ae_probe(device_t dev) 215 { 216 uint16_t deviceid, vendorid; 217 int i; 218 219 vendorid = pci_get_vendor(dev); 220 deviceid = pci_get_device(dev); 221 222 /* 223 * Search through the list of supported devs for matching one. 224 */ 225 for (i = 0; i < AE_DEVS_COUNT; i++) { 226 if (vendorid == ae_devs[i].vendorid && 227 deviceid == ae_devs[i].deviceid) { 228 device_set_desc(dev, ae_devs[i].name); 229 return (BUS_PROBE_DEFAULT); 230 } 231 } 232 return (ENXIO); 233 } 234 235 static int 236 ae_attach(device_t dev) 237 { 238 ae_softc_t *sc; 239 if_t ifp; 240 uint8_t chiprev; 241 uint32_t pcirev; 242 int nmsi, pmc; 243 int error; 244 245 sc = device_get_softc(dev); /* Automatically allocated and zeroed 246 on attach. */ 247 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 248 sc->dev = dev; 249 250 /* 251 * Initialize mutexes and tasks. 252 */ 253 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); 254 callout_init_mtx(&sc->tick_ch, &sc->mtx, 0); 255 TASK_INIT(&sc->int_task, 0, ae_int_task, sc); 256 TASK_INIT(&sc->link_task, 0, ae_link_task, sc); 257 258 pci_enable_busmaster(dev); /* Enable bus mastering. */ 259 260 sc->spec_mem = ae_res_spec_mem; 261 262 /* 263 * Allocate memory-mapped registers. 264 */ 265 error = bus_alloc_resources(dev, sc->spec_mem, sc->mem); 266 if (error != 0) { 267 device_printf(dev, "could not allocate memory resources.\n"); 268 sc->spec_mem = NULL; 269 goto fail; 270 } 271 272 /* 273 * Retrieve PCI and chip revisions. 274 */ 275 pcirev = pci_get_revid(dev); 276 chiprev = (AE_READ_4(sc, AE_MASTER_REG) >> AE_MASTER_REVNUM_SHIFT) & 277 AE_MASTER_REVNUM_MASK; 278 if (bootverbose) { 279 device_printf(dev, "pci device revision: %#04x\n", pcirev); 280 device_printf(dev, "chip id: %#02x\n", chiprev); 281 } 282 nmsi = pci_msi_count(dev); 283 if (bootverbose) 284 device_printf(dev, "MSI count: %d.\n", nmsi); 285 286 /* 287 * Allocate interrupt resources. 288 */ 289 if (msi_disable == 0 && nmsi == 1) { 290 error = pci_alloc_msi(dev, &nmsi); 291 if (error == 0) { 292 device_printf(dev, "Using MSI messages.\n"); 293 sc->spec_irq = ae_res_spec_msi; 294 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq); 295 if (error != 0) { 296 device_printf(dev, "MSI allocation failed.\n"); 297 sc->spec_irq = NULL; 298 pci_release_msi(dev); 299 } else { 300 sc->flags |= AE_FLAG_MSI; 301 } 302 } 303 } 304 if (sc->spec_irq == NULL) { 305 sc->spec_irq = ae_res_spec_irq; 306 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq); 307 if (error != 0) { 308 device_printf(dev, "could not allocate IRQ resources.\n"); 309 sc->spec_irq = NULL; 310 goto fail; 311 } 312 } 313 314 ae_init_tunables(sc); 315 316 ae_phy_reset(sc); /* Reset PHY. */ 317 error = ae_reset(sc); /* Reset the controller itself. */ 318 if (error != 0) 319 goto fail; 320 321 ae_pcie_init(sc); 322 323 ae_retrieve_address(sc); /* Load MAC address. */ 324 325 error = ae_alloc_rings(sc); /* Allocate ring buffers. */ 326 if (error != 0) 327 goto fail; 328 329 ifp = sc->ifp = if_alloc(IFT_ETHER); 330 if_setsoftc(ifp, sc); 331 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 332 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 333 if_setioctlfn(ifp, ae_ioctl); 334 if_setstartfn(ifp, ae_start); 335 if_setinitfn(ifp, ae_init); 336 if_setcapabilities(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING); 337 if_sethwassist(ifp, 0); 338 if_setsendqlen(ifp, ifqmaxlen); 339 if_setsendqready(ifp); 340 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 341 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0); 342 sc->flags |= AE_FLAG_PMG; 343 } 344 if_setcapenable(ifp, if_getcapabilities(ifp)); 345 346 /* 347 * Configure and attach MII bus. 348 */ 349 error = mii_attach(dev, &sc->miibus, ifp, ae_mediachange, 350 ae_mediastatus, BMSR_DEFCAPMASK, AE_PHYADDR_DEFAULT, 351 MII_OFFSET_ANY, 0); 352 if (error != 0) { 353 device_printf(dev, "attaching PHYs failed\n"); 354 goto fail; 355 } 356 357 ether_ifattach(ifp, sc->eaddr); 358 /* Tell the upper layer(s) we support long frames. */ 359 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 360 361 /* 362 * Create and run all helper tasks. 363 */ 364 sc->tq = taskqueue_create_fast("ae_taskq", M_WAITOK, 365 taskqueue_thread_enqueue, &sc->tq); 366 if (sc->tq == NULL) { 367 device_printf(dev, "could not create taskqueue.\n"); 368 ether_ifdetach(ifp); 369 error = ENXIO; 370 goto fail; 371 } 372 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 373 device_get_nameunit(sc->dev)); 374 375 /* 376 * Configure interrupt handlers. 377 */ 378 error = bus_setup_intr(dev, sc->irq[0], INTR_TYPE_NET | INTR_MPSAFE, 379 ae_intr, NULL, sc, &sc->intrhand); 380 if (error != 0) { 381 device_printf(dev, "could not set up interrupt handler.\n"); 382 taskqueue_free(sc->tq); 383 sc->tq = NULL; 384 ether_ifdetach(ifp); 385 goto fail; 386 } 387 388 fail: 389 if (error != 0) 390 ae_detach(dev); 391 392 return (error); 393 } 394 395 #define AE_SYSCTL(stx, parent, name, desc, ptr) \ 396 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, name, CTLFLAG_RD, ptr, 0, desc) 397 398 static void 399 ae_init_tunables(ae_softc_t *sc) 400 { 401 struct sysctl_ctx_list *ctx; 402 struct sysctl_oid *root, *stats, *stats_rx, *stats_tx; 403 struct ae_stats *ae_stats; 404 405 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 406 ae_stats = &sc->stats; 407 408 ctx = device_get_sysctl_ctx(sc->dev); 409 root = device_get_sysctl_tree(sc->dev); 410 stats = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(root), OID_AUTO, "stats", 411 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ae statistics"); 412 413 /* 414 * Receiver statistcics. 415 */ 416 stats_rx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx", 417 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 418 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "bcast", 419 "broadcast frames", &ae_stats->rx_bcast); 420 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "mcast", 421 "multicast frames", &ae_stats->rx_mcast); 422 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "pause", 423 "PAUSE frames", &ae_stats->rx_pause); 424 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "control", 425 "control frames", &ae_stats->rx_ctrl); 426 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "crc_errors", 427 "frames with CRC errors", &ae_stats->rx_crcerr); 428 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "code_errors", 429 "frames with invalid opcode", &ae_stats->rx_codeerr); 430 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "runt", 431 "runt frames", &ae_stats->rx_runt); 432 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "frag", 433 "fragmented frames", &ae_stats->rx_frag); 434 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "align_errors", 435 "frames with alignment errors", &ae_stats->rx_align); 436 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "truncated", 437 "frames truncated due to Rx FIFO inderrun", &ae_stats->rx_trunc); 438 439 /* 440 * Receiver statistcics. 441 */ 442 stats_tx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "tx", 443 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 444 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "bcast", 445 "broadcast frames", &ae_stats->tx_bcast); 446 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "mcast", 447 "multicast frames", &ae_stats->tx_mcast); 448 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "pause", 449 "PAUSE frames", &ae_stats->tx_pause); 450 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "control", 451 "control frames", &ae_stats->tx_ctrl); 452 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "defers", 453 "deferrals occuried", &ae_stats->tx_defer); 454 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "exc_defers", 455 "excessive deferrals occuried", &ae_stats->tx_excdefer); 456 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "singlecols", 457 "single collisions occuried", &ae_stats->tx_singlecol); 458 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "multicols", 459 "multiple collisions occuried", &ae_stats->tx_multicol); 460 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "latecols", 461 "late collisions occuried", &ae_stats->tx_latecol); 462 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "aborts", 463 "transmit aborts due collisions", &ae_stats->tx_abortcol); 464 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "underruns", 465 "Tx FIFO underruns", &ae_stats->tx_underrun); 466 } 467 468 static void 469 ae_pcie_init(ae_softc_t *sc) 470 { 471 472 AE_WRITE_4(sc, AE_PCIE_LTSSM_TESTMODE_REG, AE_PCIE_LTSSM_TESTMODE_DEFAULT); 473 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, AE_PCIE_DLL_TX_CTRL_DEFAULT); 474 } 475 476 static void 477 ae_phy_reset(ae_softc_t *sc) 478 { 479 480 AE_WRITE_4(sc, AE_PHY_ENABLE_REG, AE_PHY_ENABLE); 481 DELAY(1000); /* XXX: pause(9) ? */ 482 } 483 484 static int 485 ae_reset(ae_softc_t *sc) 486 { 487 int i; 488 489 /* 490 * Issue a soft reset. 491 */ 492 AE_WRITE_4(sc, AE_MASTER_REG, AE_MASTER_SOFT_RESET); 493 bus_barrier(sc->mem[0], AE_MASTER_REG, 4, 494 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 495 496 /* 497 * Wait for reset to complete. 498 */ 499 for (i = 0; i < AE_RESET_TIMEOUT; i++) { 500 if ((AE_READ_4(sc, AE_MASTER_REG) & AE_MASTER_SOFT_RESET) == 0) 501 break; 502 DELAY(10); 503 } 504 if (i == AE_RESET_TIMEOUT) { 505 device_printf(sc->dev, "reset timeout.\n"); 506 return (ENXIO); 507 } 508 509 /* 510 * Wait for everything to enter idle state. 511 */ 512 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 513 if (AE_READ_4(sc, AE_IDLE_REG) == 0) 514 break; 515 DELAY(100); 516 } 517 if (i == AE_IDLE_TIMEOUT) { 518 device_printf(sc->dev, "could not enter idle state.\n"); 519 return (ENXIO); 520 } 521 return (0); 522 } 523 524 static void 525 ae_init(void *arg) 526 { 527 ae_softc_t *sc; 528 529 sc = (ae_softc_t *)arg; 530 AE_LOCK(sc); 531 ae_init_locked(sc); 532 AE_UNLOCK(sc); 533 } 534 535 static void 536 ae_phy_init(ae_softc_t *sc) 537 { 538 539 /* 540 * Enable link status change interrupt. 541 * XXX magic numbers. 542 */ 543 #ifdef notyet 544 AE_PHY_WRITE(sc, 18, 0xc00); 545 #endif 546 } 547 548 static int 549 ae_init_locked(ae_softc_t *sc) 550 { 551 if_t ifp; 552 struct mii_data *mii; 553 uint8_t eaddr[ETHER_ADDR_LEN]; 554 uint32_t val; 555 bus_addr_t addr; 556 557 AE_LOCK_ASSERT(sc); 558 559 ifp = sc->ifp; 560 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 561 return (0); 562 mii = device_get_softc(sc->miibus); 563 564 ae_stop(sc); 565 ae_reset(sc); 566 ae_pcie_init(sc); /* Initialize PCIE stuff. */ 567 ae_phy_init(sc); 568 ae_powersave_disable(sc); 569 570 /* 571 * Clear and disable interrupts. 572 */ 573 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff); 574 575 /* 576 * Set the MAC address. 577 */ 578 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN); 579 val = eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]; 580 AE_WRITE_4(sc, AE_EADDR0_REG, val); 581 val = eaddr[0] << 8 | eaddr[1]; 582 AE_WRITE_4(sc, AE_EADDR1_REG, val); 583 584 bzero(sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING); 585 bzero(sc->txd_base, AE_TXD_BUFSIZE_DEFAULT); 586 bzero(sc->txs_base, AE_TXS_COUNT_DEFAULT * 4); 587 /* 588 * Set ring buffers base addresses. 589 */ 590 addr = sc->dma_rxd_busaddr; 591 AE_WRITE_4(sc, AE_DESC_ADDR_HI_REG, BUS_ADDR_HI(addr)); 592 AE_WRITE_4(sc, AE_RXD_ADDR_LO_REG, BUS_ADDR_LO(addr)); 593 addr = sc->dma_txd_busaddr; 594 AE_WRITE_4(sc, AE_TXD_ADDR_LO_REG, BUS_ADDR_LO(addr)); 595 addr = sc->dma_txs_busaddr; 596 AE_WRITE_4(sc, AE_TXS_ADDR_LO_REG, BUS_ADDR_LO(addr)); 597 598 /* 599 * Configure ring buffers sizes. 600 */ 601 AE_WRITE_2(sc, AE_RXD_COUNT_REG, AE_RXD_COUNT_DEFAULT); 602 AE_WRITE_2(sc, AE_TXD_BUFSIZE_REG, AE_TXD_BUFSIZE_DEFAULT / 4); 603 AE_WRITE_2(sc, AE_TXS_COUNT_REG, AE_TXS_COUNT_DEFAULT); 604 605 /* 606 * Configure interframe gap parameters. 607 */ 608 val = ((AE_IFG_TXIPG_DEFAULT << AE_IFG_TXIPG_SHIFT) & 609 AE_IFG_TXIPG_MASK) | 610 ((AE_IFG_RXIPG_DEFAULT << AE_IFG_RXIPG_SHIFT) & 611 AE_IFG_RXIPG_MASK) | 612 ((AE_IFG_IPGR1_DEFAULT << AE_IFG_IPGR1_SHIFT) & 613 AE_IFG_IPGR1_MASK) | 614 ((AE_IFG_IPGR2_DEFAULT << AE_IFG_IPGR2_SHIFT) & 615 AE_IFG_IPGR2_MASK); 616 AE_WRITE_4(sc, AE_IFG_REG, val); 617 618 /* 619 * Configure half-duplex operation. 620 */ 621 val = ((AE_HDPX_LCOL_DEFAULT << AE_HDPX_LCOL_SHIFT) & 622 AE_HDPX_LCOL_MASK) | 623 ((AE_HDPX_RETRY_DEFAULT << AE_HDPX_RETRY_SHIFT) & 624 AE_HDPX_RETRY_MASK) | 625 ((AE_HDPX_ABEBT_DEFAULT << AE_HDPX_ABEBT_SHIFT) & 626 AE_HDPX_ABEBT_MASK) | 627 ((AE_HDPX_JAMIPG_DEFAULT << AE_HDPX_JAMIPG_SHIFT) & 628 AE_HDPX_JAMIPG_MASK) | AE_HDPX_EXC_EN; 629 AE_WRITE_4(sc, AE_HDPX_REG, val); 630 631 /* 632 * Configure interrupt moderate timer. 633 */ 634 AE_WRITE_2(sc, AE_IMT_REG, AE_IMT_DEFAULT); 635 val = AE_READ_4(sc, AE_MASTER_REG); 636 val |= AE_MASTER_IMT_EN; 637 AE_WRITE_4(sc, AE_MASTER_REG, val); 638 639 /* 640 * Configure interrupt clearing timer. 641 */ 642 AE_WRITE_2(sc, AE_ICT_REG, AE_ICT_DEFAULT); 643 644 /* 645 * Configure MTU. 646 */ 647 val = if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 648 ETHER_CRC_LEN; 649 AE_WRITE_2(sc, AE_MTU_REG, val); 650 651 /* 652 * Configure cut-through threshold. 653 */ 654 AE_WRITE_4(sc, AE_CUT_THRESH_REG, AE_CUT_THRESH_DEFAULT); 655 656 /* 657 * Configure flow control. 658 */ 659 AE_WRITE_2(sc, AE_FLOW_THRESH_HI_REG, (AE_RXD_COUNT_DEFAULT / 8) * 7); 660 AE_WRITE_2(sc, AE_FLOW_THRESH_LO_REG, (AE_RXD_COUNT_MIN / 8) > 661 (AE_RXD_COUNT_DEFAULT / 12) ? (AE_RXD_COUNT_MIN / 8) : 662 (AE_RXD_COUNT_DEFAULT / 12)); 663 664 /* 665 * Init mailboxes. 666 */ 667 sc->txd_cur = sc->rxd_cur = 0; 668 sc->txs_ack = sc->txd_ack = 0; 669 sc->rxd_cur = 0; 670 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur); 671 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur); 672 673 sc->tx_inproc = 0; /* Number of packets the chip processes now. */ 674 sc->flags |= AE_FLAG_TXAVAIL; /* Free Tx's available. */ 675 676 /* 677 * Enable DMA. 678 */ 679 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN); 680 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN); 681 682 /* 683 * Check if everything is OK. 684 */ 685 val = AE_READ_4(sc, AE_ISR_REG); 686 if ((val & AE_ISR_PHY_LINKDOWN) != 0) { 687 device_printf(sc->dev, "Initialization failed.\n"); 688 return (ENXIO); 689 } 690 691 /* 692 * Clear interrupt status. 693 */ 694 AE_WRITE_4(sc, AE_ISR_REG, 0x3fffffff); 695 AE_WRITE_4(sc, AE_ISR_REG, 0x0); 696 697 /* 698 * Enable interrupts. 699 */ 700 val = AE_READ_4(sc, AE_MASTER_REG); 701 AE_WRITE_4(sc, AE_MASTER_REG, val | AE_MASTER_MANUAL_INT); 702 AE_WRITE_4(sc, AE_IMR_REG, AE_IMR_DEFAULT); 703 704 /* 705 * Disable WOL. 706 */ 707 AE_WRITE_4(sc, AE_WOL_REG, 0); 708 709 /* 710 * Configure MAC. 711 */ 712 val = AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD | 713 AE_MAC_FULL_DUPLEX | AE_MAC_CLK_PHY | 714 AE_MAC_TX_FLOW_EN | AE_MAC_RX_FLOW_EN | 715 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & AE_HALFBUF_MASK) | 716 ((AE_MAC_PREAMBLE_DEFAULT << AE_MAC_PREAMBLE_SHIFT) & 717 AE_MAC_PREAMBLE_MASK); 718 AE_WRITE_4(sc, AE_MAC_REG, val); 719 720 /* 721 * Configure Rx MAC. 722 */ 723 ae_rxfilter(sc); 724 ae_rxvlan(sc); 725 726 /* 727 * Enable Tx/Rx. 728 */ 729 val = AE_READ_4(sc, AE_MAC_REG); 730 AE_WRITE_4(sc, AE_MAC_REG, val | AE_MAC_TX_EN | AE_MAC_RX_EN); 731 732 sc->flags &= ~AE_FLAG_LINK; 733 mii_mediachg(mii); /* Switch to the current media. */ 734 735 callout_reset(&sc->tick_ch, hz, ae_tick, sc); 736 737 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 738 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 739 740 #ifdef AE_DEBUG 741 device_printf(sc->dev, "Initialization complete.\n"); 742 #endif 743 744 return (0); 745 } 746 747 static int 748 ae_detach(device_t dev) 749 { 750 struct ae_softc *sc; 751 if_t ifp; 752 753 sc = device_get_softc(dev); 754 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__)); 755 ifp = sc->ifp; 756 if (device_is_attached(dev)) { 757 AE_LOCK(sc); 758 sc->flags |= AE_FLAG_DETACH; 759 ae_stop(sc); 760 AE_UNLOCK(sc); 761 callout_drain(&sc->tick_ch); 762 taskqueue_drain(sc->tq, &sc->int_task); 763 taskqueue_drain(taskqueue_swi, &sc->link_task); 764 ether_ifdetach(ifp); 765 } 766 if (sc->tq != NULL) { 767 taskqueue_drain(sc->tq, &sc->int_task); 768 taskqueue_free(sc->tq); 769 sc->tq = NULL; 770 } 771 if (sc->miibus != NULL) { 772 device_delete_child(dev, sc->miibus); 773 sc->miibus = NULL; 774 } 775 bus_generic_detach(sc->dev); 776 ae_dma_free(sc); 777 if (sc->intrhand != NULL) { 778 bus_teardown_intr(dev, sc->irq[0], sc->intrhand); 779 sc->intrhand = NULL; 780 } 781 if (ifp != NULL) { 782 if_free(ifp); 783 sc->ifp = NULL; 784 } 785 if (sc->spec_irq != NULL) 786 bus_release_resources(dev, sc->spec_irq, sc->irq); 787 if (sc->spec_mem != NULL) 788 bus_release_resources(dev, sc->spec_mem, sc->mem); 789 if ((sc->flags & AE_FLAG_MSI) != 0) 790 pci_release_msi(dev); 791 mtx_destroy(&sc->mtx); 792 793 return (0); 794 } 795 796 static int 797 ae_miibus_readreg(device_t dev, int phy, int reg) 798 { 799 ae_softc_t *sc; 800 uint32_t val; 801 int i; 802 803 sc = device_get_softc(dev); 804 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 805 806 /* 807 * Locking is done in upper layers. 808 */ 809 810 val = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) | 811 AE_MDIO_START | AE_MDIO_READ | AE_MDIO_SUP_PREAMBLE | 812 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK); 813 AE_WRITE_4(sc, AE_MDIO_REG, val); 814 815 /* 816 * Wait for operation to complete. 817 */ 818 for (i = 0; i < AE_MDIO_TIMEOUT; i++) { 819 DELAY(2); 820 val = AE_READ_4(sc, AE_MDIO_REG); 821 if ((val & (AE_MDIO_START | AE_MDIO_BUSY)) == 0) 822 break; 823 } 824 if (i == AE_MDIO_TIMEOUT) { 825 device_printf(sc->dev, "phy read timeout: %d.\n", reg); 826 return (0); 827 } 828 return ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK); 829 } 830 831 static int 832 ae_miibus_writereg(device_t dev, int phy, int reg, int val) 833 { 834 ae_softc_t *sc; 835 uint32_t aereg; 836 int i; 837 838 sc = device_get_softc(dev); 839 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 840 841 /* 842 * Locking is done in upper layers. 843 */ 844 845 aereg = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) | 846 AE_MDIO_START | AE_MDIO_SUP_PREAMBLE | 847 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK) | 848 ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK); 849 AE_WRITE_4(sc, AE_MDIO_REG, aereg); 850 851 /* 852 * Wait for operation to complete. 853 */ 854 for (i = 0; i < AE_MDIO_TIMEOUT; i++) { 855 DELAY(2); 856 aereg = AE_READ_4(sc, AE_MDIO_REG); 857 if ((aereg & (AE_MDIO_START | AE_MDIO_BUSY)) == 0) 858 break; 859 } 860 if (i == AE_MDIO_TIMEOUT) { 861 device_printf(sc->dev, "phy write timeout: %d.\n", reg); 862 } 863 return (0); 864 } 865 866 static void 867 ae_miibus_statchg(device_t dev) 868 { 869 ae_softc_t *sc; 870 871 sc = device_get_softc(dev); 872 taskqueue_enqueue(taskqueue_swi, &sc->link_task); 873 } 874 875 static void 876 ae_mediastatus(if_t ifp, struct ifmediareq *ifmr) 877 { 878 ae_softc_t *sc; 879 struct mii_data *mii; 880 881 sc = if_getsoftc(ifp); 882 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 883 884 AE_LOCK(sc); 885 mii = device_get_softc(sc->miibus); 886 mii_pollstat(mii); 887 ifmr->ifm_status = mii->mii_media_status; 888 ifmr->ifm_active = mii->mii_media_active; 889 AE_UNLOCK(sc); 890 } 891 892 static int 893 ae_mediachange(if_t ifp) 894 { 895 ae_softc_t *sc; 896 struct mii_data *mii; 897 struct mii_softc *mii_sc; 898 int error; 899 900 /* XXX: check IFF_UP ?? */ 901 sc = if_getsoftc(ifp); 902 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 903 AE_LOCK(sc); 904 mii = device_get_softc(sc->miibus); 905 LIST_FOREACH(mii_sc, &mii->mii_phys, mii_list) 906 PHY_RESET(mii_sc); 907 error = mii_mediachg(mii); 908 AE_UNLOCK(sc); 909 910 return (error); 911 } 912 913 static int 914 ae_check_eeprom_present(ae_softc_t *sc, int *vpdc) 915 { 916 int error; 917 uint32_t val; 918 919 KASSERT(vpdc != NULL, ("[ae, %d]: vpdc is NULL!\n", __LINE__)); 920 921 /* 922 * Not sure why, but Linux does this. 923 */ 924 val = AE_READ_4(sc, AE_SPICTL_REG); 925 if ((val & AE_SPICTL_VPD_EN) != 0) { 926 val &= ~AE_SPICTL_VPD_EN; 927 AE_WRITE_4(sc, AE_SPICTL_REG, val); 928 } 929 error = pci_find_cap(sc->dev, PCIY_VPD, vpdc); 930 return (error); 931 } 932 933 static int 934 ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word) 935 { 936 uint32_t val; 937 int i; 938 939 AE_WRITE_4(sc, AE_VPD_DATA_REG, 0); /* Clear register value. */ 940 941 /* 942 * VPD registers start at offset 0x100. Read them. 943 */ 944 val = 0x100 + reg * 4; 945 AE_WRITE_4(sc, AE_VPD_CAP_REG, (val << AE_VPD_CAP_ADDR_SHIFT) & 946 AE_VPD_CAP_ADDR_MASK); 947 for (i = 0; i < AE_VPD_TIMEOUT; i++) { 948 DELAY(2000); 949 val = AE_READ_4(sc, AE_VPD_CAP_REG); 950 if ((val & AE_VPD_CAP_DONE) != 0) 951 break; 952 } 953 if (i == AE_VPD_TIMEOUT) { 954 device_printf(sc->dev, "timeout reading VPD register %d.\n", 955 reg); 956 return (ETIMEDOUT); 957 } 958 *word = AE_READ_4(sc, AE_VPD_DATA_REG); 959 return (0); 960 } 961 962 static int 963 ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr) 964 { 965 uint32_t word, reg, val; 966 int error; 967 int found; 968 int vpdc; 969 int i; 970 971 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 972 KASSERT(eaddr != NULL, ("[ae, %d]: eaddr is NULL", __LINE__)); 973 974 /* 975 * Check for EEPROM. 976 */ 977 error = ae_check_eeprom_present(sc, &vpdc); 978 if (error != 0) 979 return (error); 980 981 /* 982 * Read the VPD configuration space. 983 * Each register is prefixed with signature, 984 * so we can check if it is valid. 985 */ 986 for (i = 0, found = 0; i < AE_VPD_NREGS; i++) { 987 error = ae_vpd_read_word(sc, i, &word); 988 if (error != 0) 989 break; 990 991 /* 992 * Check signature. 993 */ 994 if ((word & AE_VPD_SIG_MASK) != AE_VPD_SIG) 995 break; 996 reg = word >> AE_VPD_REG_SHIFT; 997 i++; /* Move to the next word. */ 998 999 if (reg != AE_EADDR0_REG && reg != AE_EADDR1_REG) 1000 continue; 1001 1002 error = ae_vpd_read_word(sc, i, &val); 1003 if (error != 0) 1004 break; 1005 if (reg == AE_EADDR0_REG) 1006 eaddr[0] = val; 1007 else 1008 eaddr[1] = val; 1009 found++; 1010 } 1011 1012 if (found < 2) 1013 return (ENOENT); 1014 1015 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */ 1016 if (AE_CHECK_EADDR_VALID(eaddr) != 0) { 1017 if (bootverbose) 1018 device_printf(sc->dev, 1019 "VPD ethernet address registers are invalid.\n"); 1020 return (EINVAL); 1021 } 1022 return (0); 1023 } 1024 1025 static int 1026 ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr) 1027 { 1028 1029 /* 1030 * BIOS is supposed to set this. 1031 */ 1032 eaddr[0] = AE_READ_4(sc, AE_EADDR0_REG); 1033 eaddr[1] = AE_READ_4(sc, AE_EADDR1_REG); 1034 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */ 1035 1036 if (AE_CHECK_EADDR_VALID(eaddr) != 0) { 1037 if (bootverbose) 1038 device_printf(sc->dev, 1039 "Ethernet address registers are invalid.\n"); 1040 return (EINVAL); 1041 } 1042 return (0); 1043 } 1044 1045 static void 1046 ae_retrieve_address(ae_softc_t *sc) 1047 { 1048 uint32_t eaddr[2] = {0, 0}; 1049 int error; 1050 1051 /* 1052 *Check for EEPROM. 1053 */ 1054 error = ae_get_vpd_eaddr(sc, eaddr); 1055 if (error != 0) 1056 error = ae_get_reg_eaddr(sc, eaddr); 1057 if (error != 0) { 1058 if (bootverbose) 1059 device_printf(sc->dev, 1060 "Generating random ethernet address.\n"); 1061 eaddr[0] = arc4random(); 1062 1063 /* 1064 * Set OUI to ASUSTek COMPUTER INC. 1065 */ 1066 sc->eaddr[0] = 0x02; /* U/L bit set. */ 1067 sc->eaddr[1] = 0x1f; 1068 sc->eaddr[2] = 0xc6; 1069 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff; 1070 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff; 1071 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff; 1072 } else { 1073 sc->eaddr[0] = (eaddr[1] >> 8) & 0xff; 1074 sc->eaddr[1] = (eaddr[1] >> 0) & 0xff; 1075 sc->eaddr[2] = (eaddr[0] >> 24) & 0xff; 1076 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff; 1077 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff; 1078 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff; 1079 } 1080 } 1081 1082 static void 1083 ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1084 { 1085 bus_addr_t *addr = arg; 1086 1087 if (error != 0) 1088 return; 1089 KASSERT(nsegs == 1, ("[ae, %d]: %d segments instead of 1!", __LINE__, 1090 nsegs)); 1091 *addr = segs[0].ds_addr; 1092 } 1093 1094 static int 1095 ae_alloc_rings(ae_softc_t *sc) 1096 { 1097 bus_addr_t busaddr; 1098 int error; 1099 1100 /* 1101 * Create parent DMA tag. 1102 */ 1103 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1104 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1105 NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 1106 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 1107 &sc->dma_parent_tag); 1108 if (error != 0) { 1109 device_printf(sc->dev, "could not creare parent DMA tag.\n"); 1110 return (error); 1111 } 1112 1113 /* 1114 * Create DMA tag for TxD. 1115 */ 1116 error = bus_dma_tag_create(sc->dma_parent_tag, 1117 8, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1118 NULL, NULL, AE_TXD_BUFSIZE_DEFAULT, 1, 1119 AE_TXD_BUFSIZE_DEFAULT, 0, NULL, NULL, 1120 &sc->dma_txd_tag); 1121 if (error != 0) { 1122 device_printf(sc->dev, "could not creare TxD DMA tag.\n"); 1123 return (error); 1124 } 1125 1126 /* 1127 * Create DMA tag for TxS. 1128 */ 1129 error = bus_dma_tag_create(sc->dma_parent_tag, 1130 8, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1131 NULL, NULL, AE_TXS_COUNT_DEFAULT * 4, 1, 1132 AE_TXS_COUNT_DEFAULT * 4, 0, NULL, NULL, 1133 &sc->dma_txs_tag); 1134 if (error != 0) { 1135 device_printf(sc->dev, "could not creare TxS DMA tag.\n"); 1136 return (error); 1137 } 1138 1139 /* 1140 * Create DMA tag for RxD. 1141 */ 1142 error = bus_dma_tag_create(sc->dma_parent_tag, 1143 128, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1144 NULL, NULL, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 1, 1145 AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 0, NULL, NULL, 1146 &sc->dma_rxd_tag); 1147 if (error != 0) { 1148 device_printf(sc->dev, "could not creare TxS DMA tag.\n"); 1149 return (error); 1150 } 1151 1152 /* 1153 * Allocate TxD DMA memory. 1154 */ 1155 error = bus_dmamem_alloc(sc->dma_txd_tag, (void **)&sc->txd_base, 1156 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1157 &sc->dma_txd_map); 1158 if (error != 0) { 1159 device_printf(sc->dev, 1160 "could not allocate DMA memory for TxD ring.\n"); 1161 return (error); 1162 } 1163 error = bus_dmamap_load(sc->dma_txd_tag, sc->dma_txd_map, sc->txd_base, 1164 AE_TXD_BUFSIZE_DEFAULT, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1165 if (error != 0 || busaddr == 0) { 1166 device_printf(sc->dev, 1167 "could not load DMA map for TxD ring.\n"); 1168 return (error); 1169 } 1170 sc->dma_txd_busaddr = busaddr; 1171 1172 /* 1173 * Allocate TxS DMA memory. 1174 */ 1175 error = bus_dmamem_alloc(sc->dma_txs_tag, (void **)&sc->txs_base, 1176 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1177 &sc->dma_txs_map); 1178 if (error != 0) { 1179 device_printf(sc->dev, 1180 "could not allocate DMA memory for TxS ring.\n"); 1181 return (error); 1182 } 1183 error = bus_dmamap_load(sc->dma_txs_tag, sc->dma_txs_map, sc->txs_base, 1184 AE_TXS_COUNT_DEFAULT * 4, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1185 if (error != 0 || busaddr == 0) { 1186 device_printf(sc->dev, 1187 "could not load DMA map for TxS ring.\n"); 1188 return (error); 1189 } 1190 sc->dma_txs_busaddr = busaddr; 1191 1192 /* 1193 * Allocate RxD DMA memory. 1194 */ 1195 error = bus_dmamem_alloc(sc->dma_rxd_tag, (void **)&sc->rxd_base_dma, 1196 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1197 &sc->dma_rxd_map); 1198 if (error != 0) { 1199 device_printf(sc->dev, 1200 "could not allocate DMA memory for RxD ring.\n"); 1201 return (error); 1202 } 1203 error = bus_dmamap_load(sc->dma_rxd_tag, sc->dma_rxd_map, 1204 sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 1205 ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1206 if (error != 0 || busaddr == 0) { 1207 device_printf(sc->dev, 1208 "could not load DMA map for RxD ring.\n"); 1209 return (error); 1210 } 1211 sc->dma_rxd_busaddr = busaddr + AE_RXD_PADDING; 1212 sc->rxd_base = (ae_rxd_t *)(sc->rxd_base_dma + AE_RXD_PADDING); 1213 1214 return (0); 1215 } 1216 1217 static void 1218 ae_dma_free(ae_softc_t *sc) 1219 { 1220 1221 if (sc->dma_txd_tag != NULL) { 1222 if (sc->dma_txd_busaddr != 0) 1223 bus_dmamap_unload(sc->dma_txd_tag, sc->dma_txd_map); 1224 if (sc->txd_base != NULL) 1225 bus_dmamem_free(sc->dma_txd_tag, sc->txd_base, 1226 sc->dma_txd_map); 1227 bus_dma_tag_destroy(sc->dma_txd_tag); 1228 sc->dma_txd_tag = NULL; 1229 sc->txd_base = NULL; 1230 sc->dma_txd_busaddr = 0; 1231 } 1232 if (sc->dma_txs_tag != NULL) { 1233 if (sc->dma_txs_busaddr != 0) 1234 bus_dmamap_unload(sc->dma_txs_tag, sc->dma_txs_map); 1235 if (sc->txs_base != NULL) 1236 bus_dmamem_free(sc->dma_txs_tag, sc->txs_base, 1237 sc->dma_txs_map); 1238 bus_dma_tag_destroy(sc->dma_txs_tag); 1239 sc->dma_txs_tag = NULL; 1240 sc->txs_base = NULL; 1241 sc->dma_txs_busaddr = 0; 1242 } 1243 if (sc->dma_rxd_tag != NULL) { 1244 if (sc->dma_rxd_busaddr != 0) 1245 bus_dmamap_unload(sc->dma_rxd_tag, sc->dma_rxd_map); 1246 if (sc->rxd_base_dma != NULL) 1247 bus_dmamem_free(sc->dma_rxd_tag, sc->rxd_base_dma, 1248 sc->dma_rxd_map); 1249 bus_dma_tag_destroy(sc->dma_rxd_tag); 1250 sc->dma_rxd_tag = NULL; 1251 sc->rxd_base_dma = NULL; 1252 sc->dma_rxd_busaddr = 0; 1253 } 1254 if (sc->dma_parent_tag != NULL) { 1255 bus_dma_tag_destroy(sc->dma_parent_tag); 1256 sc->dma_parent_tag = NULL; 1257 } 1258 } 1259 1260 static int 1261 ae_shutdown(device_t dev) 1262 { 1263 ae_softc_t *sc; 1264 int error; 1265 1266 sc = device_get_softc(dev); 1267 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__)); 1268 1269 error = ae_suspend(dev); 1270 AE_LOCK(sc); 1271 ae_powersave_enable(sc); 1272 AE_UNLOCK(sc); 1273 return (error); 1274 } 1275 1276 static void 1277 ae_powersave_disable(ae_softc_t *sc) 1278 { 1279 uint32_t val; 1280 1281 AE_LOCK_ASSERT(sc); 1282 1283 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0); 1284 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA); 1285 if (val & AE_PHY_DBG_POWERSAVE) { 1286 val &= ~AE_PHY_DBG_POWERSAVE; 1287 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, val); 1288 DELAY(1000); 1289 } 1290 } 1291 1292 static void 1293 ae_powersave_enable(ae_softc_t *sc) 1294 { 1295 uint32_t val; 1296 1297 AE_LOCK_ASSERT(sc); 1298 1299 /* 1300 * XXX magic numbers. 1301 */ 1302 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0); 1303 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA); 1304 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, val | 0x1000); 1305 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 2); 1306 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0x3000); 1307 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 3); 1308 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0); 1309 } 1310 1311 static void 1312 ae_pm_init(ae_softc_t *sc) 1313 { 1314 if_t ifp; 1315 uint32_t val; 1316 uint16_t pmstat; 1317 struct mii_data *mii; 1318 int pmc; 1319 1320 AE_LOCK_ASSERT(sc); 1321 1322 ifp = sc->ifp; 1323 if ((sc->flags & AE_FLAG_PMG) == 0) { 1324 /* Disable WOL entirely. */ 1325 AE_WRITE_4(sc, AE_WOL_REG, 0); 1326 return; 1327 } 1328 1329 /* 1330 * Configure WOL if enabled. 1331 */ 1332 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 1333 mii = device_get_softc(sc->miibus); 1334 mii_pollstat(mii); 1335 if ((mii->mii_media_status & IFM_AVALID) != 0 && 1336 (mii->mii_media_status & IFM_ACTIVE) != 0) { 1337 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_MAGIC | \ 1338 AE_WOL_MAGIC_PME); 1339 1340 /* 1341 * Configure MAC. 1342 */ 1343 val = AE_MAC_RX_EN | AE_MAC_CLK_PHY | \ 1344 AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD | \ 1345 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & \ 1346 AE_HALFBUF_MASK) | \ 1347 ((AE_MAC_PREAMBLE_DEFAULT << \ 1348 AE_MAC_PREAMBLE_SHIFT) & AE_MAC_PREAMBLE_MASK) | \ 1349 AE_MAC_BCAST_EN | AE_MAC_MCAST_EN; 1350 if ((IFM_OPTIONS(mii->mii_media_active) & \ 1351 IFM_FDX) != 0) 1352 val |= AE_MAC_FULL_DUPLEX; 1353 AE_WRITE_4(sc, AE_MAC_REG, val); 1354 1355 } else { /* No link. */ 1356 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_LNKCHG | \ 1357 AE_WOL_LNKCHG_PME); 1358 AE_WRITE_4(sc, AE_MAC_REG, 0); 1359 } 1360 } else { 1361 ae_powersave_enable(sc); 1362 } 1363 1364 /* 1365 * PCIE hacks. Magic numbers. 1366 */ 1367 val = AE_READ_4(sc, AE_PCIE_PHYMISC_REG); 1368 val |= AE_PCIE_PHYMISC_FORCE_RCV_DET; 1369 AE_WRITE_4(sc, AE_PCIE_PHYMISC_REG, val); 1370 val = AE_READ_4(sc, AE_PCIE_DLL_TX_CTRL_REG); 1371 val |= AE_PCIE_DLL_TX_CTRL_SEL_NOR_CLK; 1372 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, val); 1373 1374 /* 1375 * Configure PME. 1376 */ 1377 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) { 1378 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1379 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1380 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 1381 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1382 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1383 } 1384 } 1385 1386 static int 1387 ae_suspend(device_t dev) 1388 { 1389 ae_softc_t *sc; 1390 1391 sc = device_get_softc(dev); 1392 1393 AE_LOCK(sc); 1394 ae_stop(sc); 1395 ae_pm_init(sc); 1396 AE_UNLOCK(sc); 1397 1398 return (0); 1399 } 1400 1401 static int 1402 ae_resume(device_t dev) 1403 { 1404 ae_softc_t *sc; 1405 1406 sc = device_get_softc(dev); 1407 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1408 1409 AE_LOCK(sc); 1410 AE_READ_4(sc, AE_WOL_REG); /* Clear WOL status. */ 1411 if ((if_getflags(sc->ifp) & IFF_UP) != 0) 1412 ae_init_locked(sc); 1413 AE_UNLOCK(sc); 1414 1415 return (0); 1416 } 1417 1418 static unsigned int 1419 ae_tx_avail_size(ae_softc_t *sc) 1420 { 1421 unsigned int avail; 1422 1423 if (sc->txd_cur >= sc->txd_ack) 1424 avail = AE_TXD_BUFSIZE_DEFAULT - (sc->txd_cur - sc->txd_ack); 1425 else 1426 avail = sc->txd_ack - sc->txd_cur; 1427 1428 return (avail); 1429 } 1430 1431 static int 1432 ae_encap(ae_softc_t *sc, struct mbuf **m_head) 1433 { 1434 struct mbuf *m0; 1435 ae_txd_t *hdr; 1436 unsigned int to_end; 1437 uint16_t len; 1438 1439 AE_LOCK_ASSERT(sc); 1440 1441 m0 = *m_head; 1442 len = m0->m_pkthdr.len; 1443 1444 if ((sc->flags & AE_FLAG_TXAVAIL) == 0 || 1445 len + sizeof(ae_txd_t) + 3 > ae_tx_avail_size(sc)) { 1446 #ifdef AE_DEBUG 1447 if_printf(sc->ifp, "No free Tx available.\n"); 1448 #endif 1449 return ENOBUFS; 1450 } 1451 1452 hdr = (ae_txd_t *)(sc->txd_base + sc->txd_cur); 1453 bzero(hdr, sizeof(*hdr)); 1454 /* Skip header size. */ 1455 sc->txd_cur = (sc->txd_cur + sizeof(ae_txd_t)) % AE_TXD_BUFSIZE_DEFAULT; 1456 /* Space available to the end of the ring */ 1457 to_end = AE_TXD_BUFSIZE_DEFAULT - sc->txd_cur; 1458 if (to_end >= len) { 1459 m_copydata(m0, 0, len, (caddr_t)(sc->txd_base + sc->txd_cur)); 1460 } else { 1461 m_copydata(m0, 0, to_end, (caddr_t)(sc->txd_base + 1462 sc->txd_cur)); 1463 m_copydata(m0, to_end, len - to_end, (caddr_t)sc->txd_base); 1464 } 1465 1466 /* 1467 * Set TxD flags and parameters. 1468 */ 1469 if ((m0->m_flags & M_VLANTAG) != 0) { 1470 hdr->vlan = htole16(AE_TXD_VLAN(m0->m_pkthdr.ether_vtag)); 1471 hdr->len = htole16(len | AE_TXD_INSERT_VTAG); 1472 } else { 1473 hdr->len = htole16(len); 1474 } 1475 1476 /* 1477 * Set current TxD position and round up to a 4-byte boundary. 1478 */ 1479 sc->txd_cur = ((sc->txd_cur + len + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT; 1480 if (sc->txd_cur == sc->txd_ack) 1481 sc->flags &= ~AE_FLAG_TXAVAIL; 1482 #ifdef AE_DEBUG 1483 if_printf(sc->ifp, "New txd_cur = %d.\n", sc->txd_cur); 1484 #endif 1485 1486 /* 1487 * Update TxS position and check if there are empty TxS available. 1488 */ 1489 sc->txs_base[sc->txs_cur].flags &= ~htole16(AE_TXS_UPDATE); 1490 sc->txs_cur = (sc->txs_cur + 1) % AE_TXS_COUNT_DEFAULT; 1491 if (sc->txs_cur == sc->txs_ack) 1492 sc->flags &= ~AE_FLAG_TXAVAIL; 1493 1494 /* 1495 * Synchronize DMA memory. 1496 */ 1497 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, BUS_DMASYNC_PREREAD | 1498 BUS_DMASYNC_PREWRITE); 1499 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1500 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1501 1502 return (0); 1503 } 1504 1505 static void 1506 ae_start(if_t ifp) 1507 { 1508 ae_softc_t *sc; 1509 1510 sc = if_getsoftc(ifp); 1511 AE_LOCK(sc); 1512 ae_start_locked(ifp); 1513 AE_UNLOCK(sc); 1514 } 1515 1516 static void 1517 ae_start_locked(if_t ifp) 1518 { 1519 ae_softc_t *sc; 1520 unsigned int count; 1521 struct mbuf *m0; 1522 int error; 1523 1524 sc = if_getsoftc(ifp); 1525 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1526 AE_LOCK_ASSERT(sc); 1527 1528 #ifdef AE_DEBUG 1529 if_printf(ifp, "Start called.\n"); 1530 #endif 1531 1532 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1533 IFF_DRV_RUNNING || (sc->flags & AE_FLAG_LINK) == 0) 1534 return; 1535 1536 count = 0; 1537 while (!if_sendq_empty(ifp)) { 1538 m0 = if_dequeue(ifp); 1539 if (m0 == NULL) 1540 break; /* Nothing to do. */ 1541 1542 error = ae_encap(sc, &m0); 1543 if (error != 0) { 1544 if (m0 != NULL) { 1545 if_sendq_prepend(ifp, m0); 1546 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1547 #ifdef AE_DEBUG 1548 if_printf(ifp, "Setting OACTIVE.\n"); 1549 #endif 1550 } 1551 break; 1552 } 1553 count++; 1554 sc->tx_inproc++; 1555 1556 /* Bounce a copy of the frame to BPF. */ 1557 ETHER_BPF_MTAP(ifp, m0); 1558 1559 m_freem(m0); 1560 } 1561 1562 if (count > 0) { /* Something was dequeued. */ 1563 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur / 4); 1564 sc->wd_timer = AE_TX_TIMEOUT; /* Load watchdog. */ 1565 #ifdef AE_DEBUG 1566 if_printf(ifp, "%d packets dequeued.\n", count); 1567 if_printf(ifp, "Tx pos now is %d.\n", sc->txd_cur); 1568 #endif 1569 } 1570 } 1571 1572 static void 1573 ae_link_task(void *arg, int pending) 1574 { 1575 ae_softc_t *sc; 1576 struct mii_data *mii; 1577 if_t ifp; 1578 uint32_t val; 1579 1580 sc = (ae_softc_t *)arg; 1581 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1582 AE_LOCK(sc); 1583 1584 ifp = sc->ifp; 1585 mii = device_get_softc(sc->miibus); 1586 if (mii == NULL || ifp == NULL || 1587 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 1588 AE_UNLOCK(sc); /* XXX: could happen? */ 1589 return; 1590 } 1591 1592 sc->flags &= ~AE_FLAG_LINK; 1593 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 1594 (IFM_AVALID | IFM_ACTIVE)) { 1595 switch(IFM_SUBTYPE(mii->mii_media_active)) { 1596 case IFM_10_T: 1597 case IFM_100_TX: 1598 sc->flags |= AE_FLAG_LINK; 1599 break; 1600 default: 1601 break; 1602 } 1603 } 1604 1605 /* 1606 * Stop Rx/Tx MACs. 1607 */ 1608 ae_stop_rxmac(sc); 1609 ae_stop_txmac(sc); 1610 1611 if ((sc->flags & AE_FLAG_LINK) != 0) { 1612 ae_mac_config(sc); 1613 1614 /* 1615 * Restart DMA engines. 1616 */ 1617 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN); 1618 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN); 1619 1620 /* 1621 * Enable Rx and Tx MACs. 1622 */ 1623 val = AE_READ_4(sc, AE_MAC_REG); 1624 val |= AE_MAC_TX_EN | AE_MAC_RX_EN; 1625 AE_WRITE_4(sc, AE_MAC_REG, val); 1626 } 1627 AE_UNLOCK(sc); 1628 } 1629 1630 static void 1631 ae_stop_rxmac(ae_softc_t *sc) 1632 { 1633 uint32_t val; 1634 int i; 1635 1636 AE_LOCK_ASSERT(sc); 1637 1638 /* 1639 * Stop Rx MAC engine. 1640 */ 1641 val = AE_READ_4(sc, AE_MAC_REG); 1642 if ((val & AE_MAC_RX_EN) != 0) { 1643 val &= ~AE_MAC_RX_EN; 1644 AE_WRITE_4(sc, AE_MAC_REG, val); 1645 } 1646 1647 /* 1648 * Stop Rx DMA engine. 1649 */ 1650 if (AE_READ_1(sc, AE_DMAWRITE_REG) == AE_DMAWRITE_EN) 1651 AE_WRITE_1(sc, AE_DMAWRITE_REG, 0); 1652 1653 /* 1654 * Wait for IDLE state. 1655 */ 1656 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 1657 val = AE_READ_4(sc, AE_IDLE_REG); 1658 if ((val & (AE_IDLE_RXMAC | AE_IDLE_DMAWRITE)) == 0) 1659 break; 1660 DELAY(100); 1661 } 1662 if (i == AE_IDLE_TIMEOUT) 1663 device_printf(sc->dev, "timed out while stopping Rx MAC.\n"); 1664 } 1665 1666 static void 1667 ae_stop_txmac(ae_softc_t *sc) 1668 { 1669 uint32_t val; 1670 int i; 1671 1672 AE_LOCK_ASSERT(sc); 1673 1674 /* 1675 * Stop Tx MAC engine. 1676 */ 1677 val = AE_READ_4(sc, AE_MAC_REG); 1678 if ((val & AE_MAC_TX_EN) != 0) { 1679 val &= ~AE_MAC_TX_EN; 1680 AE_WRITE_4(sc, AE_MAC_REG, val); 1681 } 1682 1683 /* 1684 * Stop Tx DMA engine. 1685 */ 1686 if (AE_READ_1(sc, AE_DMAREAD_REG) == AE_DMAREAD_EN) 1687 AE_WRITE_1(sc, AE_DMAREAD_REG, 0); 1688 1689 /* 1690 * Wait for IDLE state. 1691 */ 1692 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 1693 val = AE_READ_4(sc, AE_IDLE_REG); 1694 if ((val & (AE_IDLE_TXMAC | AE_IDLE_DMAREAD)) == 0) 1695 break; 1696 DELAY(100); 1697 } 1698 if (i == AE_IDLE_TIMEOUT) 1699 device_printf(sc->dev, "timed out while stopping Tx MAC.\n"); 1700 } 1701 1702 static void 1703 ae_mac_config(ae_softc_t *sc) 1704 { 1705 struct mii_data *mii; 1706 uint32_t val; 1707 1708 AE_LOCK_ASSERT(sc); 1709 1710 mii = device_get_softc(sc->miibus); 1711 val = AE_READ_4(sc, AE_MAC_REG); 1712 val &= ~AE_MAC_FULL_DUPLEX; 1713 /* XXX disable AE_MAC_TX_FLOW_EN? */ 1714 1715 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1716 val |= AE_MAC_FULL_DUPLEX; 1717 1718 AE_WRITE_4(sc, AE_MAC_REG, val); 1719 } 1720 1721 static int 1722 ae_intr(void *arg) 1723 { 1724 ae_softc_t *sc; 1725 uint32_t val; 1726 1727 sc = (ae_softc_t *)arg; 1728 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1729 1730 val = AE_READ_4(sc, AE_ISR_REG); 1731 if (val == 0 || (val & AE_IMR_DEFAULT) == 0) 1732 return (FILTER_STRAY); 1733 1734 /* Disable interrupts. */ 1735 AE_WRITE_4(sc, AE_ISR_REG, AE_ISR_DISABLE); 1736 1737 /* Schedule interrupt processing. */ 1738 taskqueue_enqueue(sc->tq, &sc->int_task); 1739 1740 return (FILTER_HANDLED); 1741 } 1742 1743 static void 1744 ae_int_task(void *arg, int pending) 1745 { 1746 ae_softc_t *sc; 1747 if_t ifp; 1748 uint32_t val; 1749 1750 sc = (ae_softc_t *)arg; 1751 1752 AE_LOCK(sc); 1753 1754 ifp = sc->ifp; 1755 1756 val = AE_READ_4(sc, AE_ISR_REG); /* Read interrupt status. */ 1757 if (val == 0) { 1758 AE_UNLOCK(sc); 1759 return; 1760 } 1761 1762 /* 1763 * Clear interrupts and disable them. 1764 */ 1765 AE_WRITE_4(sc, AE_ISR_REG, val | AE_ISR_DISABLE); 1766 1767 #ifdef AE_DEBUG 1768 if_printf(ifp, "Interrupt received: 0x%08x\n", val); 1769 #endif 1770 1771 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1772 if ((val & (AE_ISR_DMAR_TIMEOUT | AE_ISR_DMAW_TIMEOUT | 1773 AE_ISR_PHY_LINKDOWN)) != 0) { 1774 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1775 ae_init_locked(sc); 1776 AE_UNLOCK(sc); 1777 return; 1778 } 1779 if ((val & AE_ISR_TX_EVENT) != 0) 1780 ae_tx_intr(sc); 1781 if ((val & AE_ISR_RX_EVENT) != 0) 1782 ae_rx_intr(sc); 1783 /* 1784 * Re-enable interrupts. 1785 */ 1786 AE_WRITE_4(sc, AE_ISR_REG, 0); 1787 1788 if ((sc->flags & AE_FLAG_TXAVAIL) != 0) { 1789 if (!if_sendq_empty(ifp)) 1790 ae_start_locked(ifp); 1791 } 1792 } 1793 1794 AE_UNLOCK(sc); 1795 } 1796 1797 static void 1798 ae_tx_intr(ae_softc_t *sc) 1799 { 1800 if_t ifp; 1801 ae_txd_t *txd; 1802 ae_txs_t *txs; 1803 uint16_t flags; 1804 1805 AE_LOCK_ASSERT(sc); 1806 1807 ifp = sc->ifp; 1808 1809 #ifdef AE_DEBUG 1810 if_printf(ifp, "Tx interrupt occuried.\n"); 1811 #endif 1812 1813 /* 1814 * Syncronize DMA buffers. 1815 */ 1816 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, 1817 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1818 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1819 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1820 1821 for (;;) { 1822 txs = sc->txs_base + sc->txs_ack; 1823 flags = le16toh(txs->flags); 1824 if ((flags & AE_TXS_UPDATE) == 0) 1825 break; 1826 txs->flags = htole16(flags & ~AE_TXS_UPDATE); 1827 /* Update stats. */ 1828 ae_update_stats_tx(flags, &sc->stats); 1829 1830 /* 1831 * Update TxS position. 1832 */ 1833 sc->txs_ack = (sc->txs_ack + 1) % AE_TXS_COUNT_DEFAULT; 1834 sc->flags |= AE_FLAG_TXAVAIL; 1835 1836 txd = (ae_txd_t *)(sc->txd_base + sc->txd_ack); 1837 if (txs->len != txd->len) 1838 device_printf(sc->dev, "Size mismatch: TxS:%d TxD:%d\n", 1839 le16toh(txs->len), le16toh(txd->len)); 1840 1841 /* 1842 * Move txd ack and align on 4-byte boundary. 1843 */ 1844 sc->txd_ack = ((sc->txd_ack + le16toh(txd->len) + 1845 sizeof(ae_txs_t) + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT; 1846 1847 if ((flags & AE_TXS_SUCCESS) != 0) 1848 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1849 else 1850 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1851 1852 sc->tx_inproc--; 1853 } 1854 1855 if ((sc->flags & AE_FLAG_TXAVAIL) != 0) 1856 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1857 if (sc->tx_inproc < 0) { 1858 if_printf(ifp, "Received stray Tx interrupt(s).\n"); 1859 sc->tx_inproc = 0; 1860 } 1861 1862 if (sc->tx_inproc == 0) 1863 sc->wd_timer = 0; /* Unarm watchdog. */ 1864 1865 /* 1866 * Syncronize DMA buffers. 1867 */ 1868 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, 1869 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1870 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1871 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1872 } 1873 1874 static void 1875 ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd) 1876 { 1877 if_t ifp; 1878 struct mbuf *m; 1879 unsigned int size; 1880 uint16_t flags; 1881 1882 AE_LOCK_ASSERT(sc); 1883 1884 ifp = sc->ifp; 1885 flags = le16toh(rxd->flags); 1886 1887 #ifdef AE_DEBUG 1888 if_printf(ifp, "Rx interrupt occuried.\n"); 1889 #endif 1890 size = le16toh(rxd->len) - ETHER_CRC_LEN; 1891 if (size < (ETHER_MIN_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN)) { 1892 if_printf(ifp, "Runt frame received."); 1893 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1894 return; 1895 } 1896 1897 m = m_devget(&rxd->data[0], size, ETHER_ALIGN, ifp, NULL); 1898 if (m == NULL) { 1899 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1900 return; 1901 } 1902 1903 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 1904 (flags & AE_RXD_HAS_VLAN) != 0) { 1905 m->m_pkthdr.ether_vtag = AE_RXD_VLAN(le16toh(rxd->vlan)); 1906 m->m_flags |= M_VLANTAG; 1907 } 1908 1909 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1910 /* 1911 * Pass it through. 1912 */ 1913 AE_UNLOCK(sc); 1914 if_input(ifp, m); 1915 AE_LOCK(sc); 1916 } 1917 1918 static void 1919 ae_rx_intr(ae_softc_t *sc) 1920 { 1921 ae_rxd_t *rxd; 1922 if_t ifp; 1923 uint16_t flags; 1924 int count; 1925 1926 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 1927 1928 AE_LOCK_ASSERT(sc); 1929 1930 ifp = sc->ifp; 1931 1932 /* 1933 * Syncronize DMA buffers. 1934 */ 1935 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map, 1936 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1937 1938 for (count = 0;; count++) { 1939 rxd = (ae_rxd_t *)(sc->rxd_base + sc->rxd_cur); 1940 flags = le16toh(rxd->flags); 1941 if ((flags & AE_RXD_UPDATE) == 0) 1942 break; 1943 rxd->flags = htole16(flags & ~AE_RXD_UPDATE); 1944 /* Update stats. */ 1945 ae_update_stats_rx(flags, &sc->stats); 1946 1947 /* 1948 * Update position index. 1949 */ 1950 sc->rxd_cur = (sc->rxd_cur + 1) % AE_RXD_COUNT_DEFAULT; 1951 1952 if ((flags & AE_RXD_SUCCESS) != 0) 1953 ae_rxeof(sc, rxd); 1954 else 1955 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1956 } 1957 1958 if (count > 0) { 1959 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map, 1960 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1961 /* 1962 * Update Rx index. 1963 */ 1964 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur); 1965 } 1966 } 1967 1968 static void 1969 ae_watchdog(ae_softc_t *sc) 1970 { 1971 if_t ifp; 1972 1973 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 1974 AE_LOCK_ASSERT(sc); 1975 ifp = sc->ifp; 1976 1977 if (sc->wd_timer == 0 || --sc->wd_timer != 0) 1978 return; /* Noting to do. */ 1979 1980 if ((sc->flags & AE_FLAG_LINK) == 0) 1981 if_printf(ifp, "watchdog timeout (missed link).\n"); 1982 else 1983 if_printf(ifp, "watchdog timeout - resetting.\n"); 1984 1985 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1986 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1987 ae_init_locked(sc); 1988 if (!if_sendq_empty(ifp)) 1989 ae_start_locked(ifp); 1990 } 1991 1992 static void 1993 ae_tick(void *arg) 1994 { 1995 ae_softc_t *sc; 1996 struct mii_data *mii; 1997 1998 sc = (ae_softc_t *)arg; 1999 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 2000 AE_LOCK_ASSERT(sc); 2001 2002 mii = device_get_softc(sc->miibus); 2003 mii_tick(mii); 2004 ae_watchdog(sc); /* Watchdog check. */ 2005 callout_reset(&sc->tick_ch, hz, ae_tick, sc); 2006 } 2007 2008 static void 2009 ae_rxvlan(ae_softc_t *sc) 2010 { 2011 if_t ifp; 2012 uint32_t val; 2013 2014 AE_LOCK_ASSERT(sc); 2015 ifp = sc->ifp; 2016 val = AE_READ_4(sc, AE_MAC_REG); 2017 val &= ~AE_MAC_RMVLAN_EN; 2018 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 2019 val |= AE_MAC_RMVLAN_EN; 2020 AE_WRITE_4(sc, AE_MAC_REG, val); 2021 } 2022 2023 static u_int 2024 ae_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 2025 { 2026 uint32_t crc, *mchash = arg; 2027 2028 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 2029 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2030 2031 return (1); 2032 } 2033 2034 static void 2035 ae_rxfilter(ae_softc_t *sc) 2036 { 2037 if_t ifp; 2038 uint32_t mchash[2]; 2039 uint32_t rxcfg; 2040 2041 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 2042 2043 AE_LOCK_ASSERT(sc); 2044 2045 ifp = sc->ifp; 2046 2047 rxcfg = AE_READ_4(sc, AE_MAC_REG); 2048 rxcfg &= ~(AE_MAC_MCAST_EN | AE_MAC_BCAST_EN | AE_MAC_PROMISC_EN); 2049 2050 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 2051 rxcfg |= AE_MAC_BCAST_EN; 2052 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 2053 rxcfg |= AE_MAC_PROMISC_EN; 2054 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 2055 rxcfg |= AE_MAC_MCAST_EN; 2056 2057 /* 2058 * Wipe old settings. 2059 */ 2060 AE_WRITE_4(sc, AE_REG_MHT0, 0); 2061 AE_WRITE_4(sc, AE_REG_MHT1, 0); 2062 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2063 AE_WRITE_4(sc, AE_REG_MHT0, 0xffffffff); 2064 AE_WRITE_4(sc, AE_REG_MHT1, 0xffffffff); 2065 AE_WRITE_4(sc, AE_MAC_REG, rxcfg); 2066 return; 2067 } 2068 2069 /* 2070 * Load multicast tables. 2071 */ 2072 bzero(mchash, sizeof(mchash)); 2073 if_foreach_llmaddr(ifp, ae_hash_maddr, &mchash); 2074 AE_WRITE_4(sc, AE_REG_MHT0, mchash[0]); 2075 AE_WRITE_4(sc, AE_REG_MHT1, mchash[1]); 2076 AE_WRITE_4(sc, AE_MAC_REG, rxcfg); 2077 } 2078 2079 static int 2080 ae_ioctl(if_t ifp, u_long cmd, caddr_t data) 2081 { 2082 struct ae_softc *sc; 2083 struct ifreq *ifr; 2084 struct mii_data *mii; 2085 int error, mask; 2086 2087 sc = if_getsoftc(ifp); 2088 ifr = (struct ifreq *)data; 2089 error = 0; 2090 2091 switch (cmd) { 2092 case SIOCSIFMTU: 2093 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) 2094 error = EINVAL; 2095 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 2096 AE_LOCK(sc); 2097 if_setmtu(ifp, ifr->ifr_mtu); 2098 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2099 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2100 ae_init_locked(sc); 2101 } 2102 AE_UNLOCK(sc); 2103 } 2104 break; 2105 case SIOCSIFFLAGS: 2106 AE_LOCK(sc); 2107 if ((if_getflags(ifp) & IFF_UP) != 0) { 2108 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2109 if (((if_getflags(ifp) ^ sc->if_flags) 2110 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2111 ae_rxfilter(sc); 2112 } else { 2113 if ((sc->flags & AE_FLAG_DETACH) == 0) 2114 ae_init_locked(sc); 2115 } 2116 } else { 2117 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2118 ae_stop(sc); 2119 } 2120 sc->if_flags = if_getflags(ifp); 2121 AE_UNLOCK(sc); 2122 break; 2123 case SIOCADDMULTI: 2124 case SIOCDELMULTI: 2125 AE_LOCK(sc); 2126 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2127 ae_rxfilter(sc); 2128 AE_UNLOCK(sc); 2129 break; 2130 case SIOCSIFMEDIA: 2131 case SIOCGIFMEDIA: 2132 mii = device_get_softc(sc->miibus); 2133 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2134 break; 2135 case SIOCSIFCAP: 2136 AE_LOCK(sc); 2137 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 2138 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2139 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 2140 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 2141 ae_rxvlan(sc); 2142 } 2143 VLAN_CAPABILITIES(ifp); 2144 AE_UNLOCK(sc); 2145 break; 2146 default: 2147 error = ether_ioctl(ifp, cmd, data); 2148 break; 2149 } 2150 return (error); 2151 } 2152 2153 static void 2154 ae_stop(ae_softc_t *sc) 2155 { 2156 if_t ifp; 2157 int i; 2158 2159 AE_LOCK_ASSERT(sc); 2160 2161 ifp = sc->ifp; 2162 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2163 sc->flags &= ~AE_FLAG_LINK; 2164 sc->wd_timer = 0; /* Cancel watchdog. */ 2165 callout_stop(&sc->tick_ch); 2166 2167 /* 2168 * Clear and disable interrupts. 2169 */ 2170 AE_WRITE_4(sc, AE_IMR_REG, 0); 2171 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff); 2172 2173 /* 2174 * Stop Rx/Tx MACs. 2175 */ 2176 ae_stop_txmac(sc); 2177 ae_stop_rxmac(sc); 2178 2179 /* 2180 * Stop DMA engines. 2181 */ 2182 AE_WRITE_1(sc, AE_DMAREAD_REG, ~AE_DMAREAD_EN); 2183 AE_WRITE_1(sc, AE_DMAWRITE_REG, ~AE_DMAWRITE_EN); 2184 2185 /* 2186 * Wait for everything to enter idle state. 2187 */ 2188 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 2189 if (AE_READ_4(sc, AE_IDLE_REG) == 0) 2190 break; 2191 DELAY(100); 2192 } 2193 if (i == AE_IDLE_TIMEOUT) 2194 device_printf(sc->dev, "could not enter idle state in stop.\n"); 2195 } 2196 2197 static void 2198 ae_update_stats_tx(uint16_t flags, ae_stats_t *stats) 2199 { 2200 2201 if ((flags & AE_TXS_BCAST) != 0) 2202 stats->tx_bcast++; 2203 if ((flags & AE_TXS_MCAST) != 0) 2204 stats->tx_mcast++; 2205 if ((flags & AE_TXS_PAUSE) != 0) 2206 stats->tx_pause++; 2207 if ((flags & AE_TXS_CTRL) != 0) 2208 stats->tx_ctrl++; 2209 if ((flags & AE_TXS_DEFER) != 0) 2210 stats->tx_defer++; 2211 if ((flags & AE_TXS_EXCDEFER) != 0) 2212 stats->tx_excdefer++; 2213 if ((flags & AE_TXS_SINGLECOL) != 0) 2214 stats->tx_singlecol++; 2215 if ((flags & AE_TXS_MULTICOL) != 0) 2216 stats->tx_multicol++; 2217 if ((flags & AE_TXS_LATECOL) != 0) 2218 stats->tx_latecol++; 2219 if ((flags & AE_TXS_ABORTCOL) != 0) 2220 stats->tx_abortcol++; 2221 if ((flags & AE_TXS_UNDERRUN) != 0) 2222 stats->tx_underrun++; 2223 } 2224 2225 static void 2226 ae_update_stats_rx(uint16_t flags, ae_stats_t *stats) 2227 { 2228 2229 if ((flags & AE_RXD_BCAST) != 0) 2230 stats->rx_bcast++; 2231 if ((flags & AE_RXD_MCAST) != 0) 2232 stats->rx_mcast++; 2233 if ((flags & AE_RXD_PAUSE) != 0) 2234 stats->rx_pause++; 2235 if ((flags & AE_RXD_CTRL) != 0) 2236 stats->rx_ctrl++; 2237 if ((flags & AE_RXD_CRCERR) != 0) 2238 stats->rx_crcerr++; 2239 if ((flags & AE_RXD_CODEERR) != 0) 2240 stats->rx_codeerr++; 2241 if ((flags & AE_RXD_RUNT) != 0) 2242 stats->rx_runt++; 2243 if ((flags & AE_RXD_FRAG) != 0) 2244 stats->rx_frag++; 2245 if ((flags & AE_RXD_TRUNC) != 0) 2246 stats->rx_trunc++; 2247 if ((flags & AE_RXD_ALIGN) != 0) 2248 stats->rx_align++; 2249 } 2250