1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008 Stanislav Sedov <[email protected]>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * Driver for Attansic Technology Corp. L2 FastEthernet adapter. 28 * 29 * This driver is heavily based on age(4) Attansic L1 driver by Pyun YongHyeon. 30 */ 31 32 #include <sys/cdefs.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/mbuf.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 #include <sys/module.h> 44 #include <sys/queue.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 #include <sys/taskqueue.h> 49 50 #include <net/bpf.h> 51 #include <net/if.h> 52 #include <net/if_var.h> 53 #include <net/if_arp.h> 54 #include <net/ethernet.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 #include <net/if_vlan_var.h> 59 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/ip.h> 63 #include <netinet/tcp.h> 64 65 #include <dev/mii/mii.h> 66 #include <dev/mii/miivar.h> 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 70 #include <machine/bus.h> 71 72 #include "miibus_if.h" 73 74 #include "if_aereg.h" 75 #include "if_aevar.h" 76 77 /* 78 * Devices supported by this driver. 79 */ 80 static struct ae_dev { 81 uint16_t vendorid; 82 uint16_t deviceid; 83 const char *name; 84 } ae_devs[] = { 85 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L2, 86 "Attansic Technology Corp, L2 FastEthernet" }, 87 }; 88 #define AE_DEVS_COUNT nitems(ae_devs) 89 90 static struct resource_spec ae_res_spec_mem[] = { 91 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 92 { -1, 0, 0 } 93 }; 94 static struct resource_spec ae_res_spec_irq[] = { 95 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 96 { -1, 0, 0 } 97 }; 98 static struct resource_spec ae_res_spec_msi[] = { 99 { SYS_RES_IRQ, 1, RF_ACTIVE }, 100 { -1, 0, 0 } 101 }; 102 103 static int ae_probe(device_t dev); 104 static int ae_attach(device_t dev); 105 static void ae_pcie_init(ae_softc_t *sc); 106 static void ae_phy_reset(ae_softc_t *sc); 107 static void ae_phy_init(ae_softc_t *sc); 108 static int ae_reset(ae_softc_t *sc); 109 static void ae_init(void *arg); 110 static int ae_init_locked(ae_softc_t *sc); 111 static int ae_detach(device_t dev); 112 static int ae_miibus_readreg(device_t dev, int phy, int reg); 113 static int ae_miibus_writereg(device_t dev, int phy, int reg, int val); 114 static void ae_miibus_statchg(device_t dev); 115 static void ae_mediastatus(if_t ifp, struct ifmediareq *ifmr); 116 static int ae_mediachange(if_t ifp); 117 static void ae_retrieve_address(ae_softc_t *sc); 118 static void ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, 119 int error); 120 static int ae_alloc_rings(ae_softc_t *sc); 121 static void ae_dma_free(ae_softc_t *sc); 122 static int ae_shutdown(device_t dev); 123 static int ae_suspend(device_t dev); 124 static void ae_powersave_disable(ae_softc_t *sc); 125 static void ae_powersave_enable(ae_softc_t *sc); 126 static int ae_resume(device_t dev); 127 static unsigned int ae_tx_avail_size(ae_softc_t *sc); 128 static int ae_encap(ae_softc_t *sc, struct mbuf **m_head); 129 static void ae_start(if_t ifp); 130 static void ae_start_locked(if_t ifp); 131 static void ae_link_task(void *arg, int pending); 132 static void ae_stop_rxmac(ae_softc_t *sc); 133 static void ae_stop_txmac(ae_softc_t *sc); 134 static void ae_mac_config(ae_softc_t *sc); 135 static int ae_intr(void *arg); 136 static void ae_int_task(void *arg, int pending); 137 static void ae_tx_intr(ae_softc_t *sc); 138 static void ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd); 139 static void ae_rx_intr(ae_softc_t *sc); 140 static void ae_watchdog(ae_softc_t *sc); 141 static void ae_tick(void *arg); 142 static void ae_rxfilter(ae_softc_t *sc); 143 static void ae_rxvlan(ae_softc_t *sc); 144 static int ae_ioctl(if_t ifp, u_long cmd, caddr_t data); 145 static void ae_stop(ae_softc_t *sc); 146 static int ae_check_eeprom_present(ae_softc_t *sc, int *vpdc); 147 static int ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word); 148 static int ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr); 149 static int ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr); 150 static void ae_update_stats_rx(uint16_t flags, ae_stats_t *stats); 151 static void ae_update_stats_tx(uint16_t flags, ae_stats_t *stats); 152 static void ae_init_tunables(ae_softc_t *sc); 153 154 static device_method_t ae_methods[] = { 155 /* Device interface. */ 156 DEVMETHOD(device_probe, ae_probe), 157 DEVMETHOD(device_attach, ae_attach), 158 DEVMETHOD(device_detach, ae_detach), 159 DEVMETHOD(device_shutdown, ae_shutdown), 160 DEVMETHOD(device_suspend, ae_suspend), 161 DEVMETHOD(device_resume, ae_resume), 162 163 /* MII interface. */ 164 DEVMETHOD(miibus_readreg, ae_miibus_readreg), 165 DEVMETHOD(miibus_writereg, ae_miibus_writereg), 166 DEVMETHOD(miibus_statchg, ae_miibus_statchg), 167 { NULL, NULL } 168 }; 169 static driver_t ae_driver = { 170 "ae", 171 ae_methods, 172 sizeof(ae_softc_t) 173 }; 174 175 DRIVER_MODULE(ae, pci, ae_driver, 0, 0); 176 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, ae, ae_devs, 177 nitems(ae_devs)); 178 DRIVER_MODULE(miibus, ae, miibus_driver, 0, 0); 179 MODULE_DEPEND(ae, pci, 1, 1, 1); 180 MODULE_DEPEND(ae, ether, 1, 1, 1); 181 MODULE_DEPEND(ae, miibus, 1, 1, 1); 182 183 /* 184 * Tunables. 185 */ 186 static int msi_disable = 0; 187 TUNABLE_INT("hw.ae.msi_disable", &msi_disable); 188 189 #define AE_READ_4(sc, reg) \ 190 bus_read_4((sc)->mem[0], (reg)) 191 #define AE_READ_2(sc, reg) \ 192 bus_read_2((sc)->mem[0], (reg)) 193 #define AE_READ_1(sc, reg) \ 194 bus_read_1((sc)->mem[0], (reg)) 195 #define AE_WRITE_4(sc, reg, val) \ 196 bus_write_4((sc)->mem[0], (reg), (val)) 197 #define AE_WRITE_2(sc, reg, val) \ 198 bus_write_2((sc)->mem[0], (reg), (val)) 199 #define AE_WRITE_1(sc, reg, val) \ 200 bus_write_1((sc)->mem[0], (reg), (val)) 201 #define AE_PHY_READ(sc, reg) \ 202 ae_miibus_readreg(sc->dev, 0, reg) 203 #define AE_PHY_WRITE(sc, reg, val) \ 204 ae_miibus_writereg(sc->dev, 0, reg, val) 205 #define AE_CHECK_EADDR_VALID(eaddr) \ 206 ((eaddr[0] == 0 && eaddr[1] == 0) || \ 207 (eaddr[0] == 0xffffffff && eaddr[1] == 0xffff)) 208 #define AE_RXD_VLAN(vtag) \ 209 (((vtag) >> 4) | (((vtag) & 0x07) << 13) | (((vtag) & 0x08) << 9)) 210 #define AE_TXD_VLAN(vtag) \ 211 (((vtag) << 4) | (((vtag) >> 13) & 0x07) | (((vtag) >> 9) & 0x08)) 212 213 static int 214 ae_probe(device_t dev) 215 { 216 uint16_t deviceid, vendorid; 217 int i; 218 219 vendorid = pci_get_vendor(dev); 220 deviceid = pci_get_device(dev); 221 222 /* 223 * Search through the list of supported devs for matching one. 224 */ 225 for (i = 0; i < AE_DEVS_COUNT; i++) { 226 if (vendorid == ae_devs[i].vendorid && 227 deviceid == ae_devs[i].deviceid) { 228 device_set_desc(dev, ae_devs[i].name); 229 return (BUS_PROBE_DEFAULT); 230 } 231 } 232 return (ENXIO); 233 } 234 235 static int 236 ae_attach(device_t dev) 237 { 238 ae_softc_t *sc; 239 if_t ifp; 240 uint8_t chiprev; 241 uint32_t pcirev; 242 int nmsi, pmc; 243 int error; 244 245 sc = device_get_softc(dev); /* Automatically allocated and zeroed 246 on attach. */ 247 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 248 sc->dev = dev; 249 250 /* 251 * Initialize mutexes and tasks. 252 */ 253 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); 254 callout_init_mtx(&sc->tick_ch, &sc->mtx, 0); 255 TASK_INIT(&sc->int_task, 0, ae_int_task, sc); 256 TASK_INIT(&sc->link_task, 0, ae_link_task, sc); 257 258 pci_enable_busmaster(dev); /* Enable bus mastering. */ 259 260 sc->spec_mem = ae_res_spec_mem; 261 262 /* 263 * Allocate memory-mapped registers. 264 */ 265 error = bus_alloc_resources(dev, sc->spec_mem, sc->mem); 266 if (error != 0) { 267 device_printf(dev, "could not allocate memory resources.\n"); 268 sc->spec_mem = NULL; 269 goto fail; 270 } 271 272 /* 273 * Retrieve PCI and chip revisions. 274 */ 275 pcirev = pci_get_revid(dev); 276 chiprev = (AE_READ_4(sc, AE_MASTER_REG) >> AE_MASTER_REVNUM_SHIFT) & 277 AE_MASTER_REVNUM_MASK; 278 if (bootverbose) { 279 device_printf(dev, "pci device revision: %#04x\n", pcirev); 280 device_printf(dev, "chip id: %#02x\n", chiprev); 281 } 282 nmsi = pci_msi_count(dev); 283 if (bootverbose) 284 device_printf(dev, "MSI count: %d.\n", nmsi); 285 286 /* 287 * Allocate interrupt resources. 288 */ 289 if (msi_disable == 0 && nmsi == 1) { 290 error = pci_alloc_msi(dev, &nmsi); 291 if (error == 0) { 292 device_printf(dev, "Using MSI messages.\n"); 293 sc->spec_irq = ae_res_spec_msi; 294 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq); 295 if (error != 0) { 296 device_printf(dev, "MSI allocation failed.\n"); 297 sc->spec_irq = NULL; 298 pci_release_msi(dev); 299 } else { 300 sc->flags |= AE_FLAG_MSI; 301 } 302 } 303 } 304 if (sc->spec_irq == NULL) { 305 sc->spec_irq = ae_res_spec_irq; 306 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq); 307 if (error != 0) { 308 device_printf(dev, "could not allocate IRQ resources.\n"); 309 sc->spec_irq = NULL; 310 goto fail; 311 } 312 } 313 314 ae_init_tunables(sc); 315 316 ae_phy_reset(sc); /* Reset PHY. */ 317 error = ae_reset(sc); /* Reset the controller itself. */ 318 if (error != 0) 319 goto fail; 320 321 ae_pcie_init(sc); 322 323 ae_retrieve_address(sc); /* Load MAC address. */ 324 325 error = ae_alloc_rings(sc); /* Allocate ring buffers. */ 326 if (error != 0) 327 goto fail; 328 329 ifp = sc->ifp = if_alloc(IFT_ETHER); 330 if_setsoftc(ifp, sc); 331 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 332 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 333 if_setioctlfn(ifp, ae_ioctl); 334 if_setstartfn(ifp, ae_start); 335 if_setinitfn(ifp, ae_init); 336 if_setcapabilities(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING); 337 if_sethwassist(ifp, 0); 338 if_setsendqlen(ifp, ifqmaxlen); 339 if_setsendqready(ifp); 340 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 341 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0); 342 sc->flags |= AE_FLAG_PMG; 343 } 344 if_setcapenable(ifp, if_getcapabilities(ifp)); 345 346 /* 347 * Configure and attach MII bus. 348 */ 349 error = mii_attach(dev, &sc->miibus, ifp, ae_mediachange, 350 ae_mediastatus, BMSR_DEFCAPMASK, AE_PHYADDR_DEFAULT, 351 MII_OFFSET_ANY, 0); 352 if (error != 0) { 353 device_printf(dev, "attaching PHYs failed\n"); 354 goto fail; 355 } 356 357 ether_ifattach(ifp, sc->eaddr); 358 /* Tell the upper layer(s) we support long frames. */ 359 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 360 361 /* 362 * Create and run all helper tasks. 363 */ 364 sc->tq = taskqueue_create_fast("ae_taskq", M_WAITOK, 365 taskqueue_thread_enqueue, &sc->tq); 366 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 367 device_get_nameunit(sc->dev)); 368 369 /* 370 * Configure interrupt handlers. 371 */ 372 error = bus_setup_intr(dev, sc->irq[0], INTR_TYPE_NET | INTR_MPSAFE, 373 ae_intr, NULL, sc, &sc->intrhand); 374 if (error != 0) { 375 device_printf(dev, "could not set up interrupt handler.\n"); 376 taskqueue_free(sc->tq); 377 sc->tq = NULL; 378 ether_ifdetach(ifp); 379 goto fail; 380 } 381 382 fail: 383 if (error != 0) 384 ae_detach(dev); 385 386 return (error); 387 } 388 389 #define AE_SYSCTL(stx, parent, name, desc, ptr) \ 390 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, name, CTLFLAG_RD, ptr, 0, desc) 391 392 static void 393 ae_init_tunables(ae_softc_t *sc) 394 { 395 struct sysctl_ctx_list *ctx; 396 struct sysctl_oid *root, *stats, *stats_rx, *stats_tx; 397 struct ae_stats *ae_stats; 398 399 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 400 ae_stats = &sc->stats; 401 402 ctx = device_get_sysctl_ctx(sc->dev); 403 root = device_get_sysctl_tree(sc->dev); 404 stats = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(root), OID_AUTO, "stats", 405 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ae statistics"); 406 407 /* 408 * Receiver statistcics. 409 */ 410 stats_rx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx", 411 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 412 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "bcast", 413 "broadcast frames", &ae_stats->rx_bcast); 414 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "mcast", 415 "multicast frames", &ae_stats->rx_mcast); 416 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "pause", 417 "PAUSE frames", &ae_stats->rx_pause); 418 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "control", 419 "control frames", &ae_stats->rx_ctrl); 420 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "crc_errors", 421 "frames with CRC errors", &ae_stats->rx_crcerr); 422 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "code_errors", 423 "frames with invalid opcode", &ae_stats->rx_codeerr); 424 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "runt", 425 "runt frames", &ae_stats->rx_runt); 426 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "frag", 427 "fragmented frames", &ae_stats->rx_frag); 428 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "align_errors", 429 "frames with alignment errors", &ae_stats->rx_align); 430 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "truncated", 431 "frames truncated due to Rx FIFO inderrun", &ae_stats->rx_trunc); 432 433 /* 434 * Receiver statistcics. 435 */ 436 stats_tx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "tx", 437 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 438 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "bcast", 439 "broadcast frames", &ae_stats->tx_bcast); 440 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "mcast", 441 "multicast frames", &ae_stats->tx_mcast); 442 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "pause", 443 "PAUSE frames", &ae_stats->tx_pause); 444 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "control", 445 "control frames", &ae_stats->tx_ctrl); 446 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "defers", 447 "deferrals occuried", &ae_stats->tx_defer); 448 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "exc_defers", 449 "excessive deferrals occuried", &ae_stats->tx_excdefer); 450 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "singlecols", 451 "single collisions occuried", &ae_stats->tx_singlecol); 452 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "multicols", 453 "multiple collisions occuried", &ae_stats->tx_multicol); 454 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "latecols", 455 "late collisions occuried", &ae_stats->tx_latecol); 456 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "aborts", 457 "transmit aborts due collisions", &ae_stats->tx_abortcol); 458 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "underruns", 459 "Tx FIFO underruns", &ae_stats->tx_underrun); 460 } 461 462 static void 463 ae_pcie_init(ae_softc_t *sc) 464 { 465 466 AE_WRITE_4(sc, AE_PCIE_LTSSM_TESTMODE_REG, AE_PCIE_LTSSM_TESTMODE_DEFAULT); 467 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, AE_PCIE_DLL_TX_CTRL_DEFAULT); 468 } 469 470 static void 471 ae_phy_reset(ae_softc_t *sc) 472 { 473 474 AE_WRITE_4(sc, AE_PHY_ENABLE_REG, AE_PHY_ENABLE); 475 DELAY(1000); /* XXX: pause(9) ? */ 476 } 477 478 static int 479 ae_reset(ae_softc_t *sc) 480 { 481 int i; 482 483 /* 484 * Issue a soft reset. 485 */ 486 AE_WRITE_4(sc, AE_MASTER_REG, AE_MASTER_SOFT_RESET); 487 bus_barrier(sc->mem[0], AE_MASTER_REG, 4, 488 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 489 490 /* 491 * Wait for reset to complete. 492 */ 493 for (i = 0; i < AE_RESET_TIMEOUT; i++) { 494 if ((AE_READ_4(sc, AE_MASTER_REG) & AE_MASTER_SOFT_RESET) == 0) 495 break; 496 DELAY(10); 497 } 498 if (i == AE_RESET_TIMEOUT) { 499 device_printf(sc->dev, "reset timeout.\n"); 500 return (ENXIO); 501 } 502 503 /* 504 * Wait for everything to enter idle state. 505 */ 506 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 507 if (AE_READ_4(sc, AE_IDLE_REG) == 0) 508 break; 509 DELAY(100); 510 } 511 if (i == AE_IDLE_TIMEOUT) { 512 device_printf(sc->dev, "could not enter idle state.\n"); 513 return (ENXIO); 514 } 515 return (0); 516 } 517 518 static void 519 ae_init(void *arg) 520 { 521 ae_softc_t *sc; 522 523 sc = (ae_softc_t *)arg; 524 AE_LOCK(sc); 525 ae_init_locked(sc); 526 AE_UNLOCK(sc); 527 } 528 529 static void 530 ae_phy_init(ae_softc_t *sc) 531 { 532 533 /* 534 * Enable link status change interrupt. 535 * XXX magic numbers. 536 */ 537 #ifdef notyet 538 AE_PHY_WRITE(sc, 18, 0xc00); 539 #endif 540 } 541 542 static int 543 ae_init_locked(ae_softc_t *sc) 544 { 545 if_t ifp; 546 struct mii_data *mii; 547 uint8_t eaddr[ETHER_ADDR_LEN]; 548 uint32_t val; 549 bus_addr_t addr; 550 551 AE_LOCK_ASSERT(sc); 552 553 ifp = sc->ifp; 554 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 555 return (0); 556 mii = device_get_softc(sc->miibus); 557 558 ae_stop(sc); 559 ae_reset(sc); 560 ae_pcie_init(sc); /* Initialize PCIE stuff. */ 561 ae_phy_init(sc); 562 ae_powersave_disable(sc); 563 564 /* 565 * Clear and disable interrupts. 566 */ 567 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff); 568 569 /* 570 * Set the MAC address. 571 */ 572 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN); 573 val = eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]; 574 AE_WRITE_4(sc, AE_EADDR0_REG, val); 575 val = eaddr[0] << 8 | eaddr[1]; 576 AE_WRITE_4(sc, AE_EADDR1_REG, val); 577 578 bzero(sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING); 579 bzero(sc->txd_base, AE_TXD_BUFSIZE_DEFAULT); 580 bzero(sc->txs_base, AE_TXS_COUNT_DEFAULT * 4); 581 /* 582 * Set ring buffers base addresses. 583 */ 584 addr = sc->dma_rxd_busaddr; 585 AE_WRITE_4(sc, AE_DESC_ADDR_HI_REG, BUS_ADDR_HI(addr)); 586 AE_WRITE_4(sc, AE_RXD_ADDR_LO_REG, BUS_ADDR_LO(addr)); 587 addr = sc->dma_txd_busaddr; 588 AE_WRITE_4(sc, AE_TXD_ADDR_LO_REG, BUS_ADDR_LO(addr)); 589 addr = sc->dma_txs_busaddr; 590 AE_WRITE_4(sc, AE_TXS_ADDR_LO_REG, BUS_ADDR_LO(addr)); 591 592 /* 593 * Configure ring buffers sizes. 594 */ 595 AE_WRITE_2(sc, AE_RXD_COUNT_REG, AE_RXD_COUNT_DEFAULT); 596 AE_WRITE_2(sc, AE_TXD_BUFSIZE_REG, AE_TXD_BUFSIZE_DEFAULT / 4); 597 AE_WRITE_2(sc, AE_TXS_COUNT_REG, AE_TXS_COUNT_DEFAULT); 598 599 /* 600 * Configure interframe gap parameters. 601 */ 602 val = ((AE_IFG_TXIPG_DEFAULT << AE_IFG_TXIPG_SHIFT) & 603 AE_IFG_TXIPG_MASK) | 604 ((AE_IFG_RXIPG_DEFAULT << AE_IFG_RXIPG_SHIFT) & 605 AE_IFG_RXIPG_MASK) | 606 ((AE_IFG_IPGR1_DEFAULT << AE_IFG_IPGR1_SHIFT) & 607 AE_IFG_IPGR1_MASK) | 608 ((AE_IFG_IPGR2_DEFAULT << AE_IFG_IPGR2_SHIFT) & 609 AE_IFG_IPGR2_MASK); 610 AE_WRITE_4(sc, AE_IFG_REG, val); 611 612 /* 613 * Configure half-duplex operation. 614 */ 615 val = ((AE_HDPX_LCOL_DEFAULT << AE_HDPX_LCOL_SHIFT) & 616 AE_HDPX_LCOL_MASK) | 617 ((AE_HDPX_RETRY_DEFAULT << AE_HDPX_RETRY_SHIFT) & 618 AE_HDPX_RETRY_MASK) | 619 ((AE_HDPX_ABEBT_DEFAULT << AE_HDPX_ABEBT_SHIFT) & 620 AE_HDPX_ABEBT_MASK) | 621 ((AE_HDPX_JAMIPG_DEFAULT << AE_HDPX_JAMIPG_SHIFT) & 622 AE_HDPX_JAMIPG_MASK) | AE_HDPX_EXC_EN; 623 AE_WRITE_4(sc, AE_HDPX_REG, val); 624 625 /* 626 * Configure interrupt moderate timer. 627 */ 628 AE_WRITE_2(sc, AE_IMT_REG, AE_IMT_DEFAULT); 629 val = AE_READ_4(sc, AE_MASTER_REG); 630 val |= AE_MASTER_IMT_EN; 631 AE_WRITE_4(sc, AE_MASTER_REG, val); 632 633 /* 634 * Configure interrupt clearing timer. 635 */ 636 AE_WRITE_2(sc, AE_ICT_REG, AE_ICT_DEFAULT); 637 638 /* 639 * Configure MTU. 640 */ 641 val = if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 642 ETHER_CRC_LEN; 643 AE_WRITE_2(sc, AE_MTU_REG, val); 644 645 /* 646 * Configure cut-through threshold. 647 */ 648 AE_WRITE_4(sc, AE_CUT_THRESH_REG, AE_CUT_THRESH_DEFAULT); 649 650 /* 651 * Configure flow control. 652 */ 653 AE_WRITE_2(sc, AE_FLOW_THRESH_HI_REG, (AE_RXD_COUNT_DEFAULT / 8) * 7); 654 AE_WRITE_2(sc, AE_FLOW_THRESH_LO_REG, (AE_RXD_COUNT_MIN / 8) > 655 (AE_RXD_COUNT_DEFAULT / 12) ? (AE_RXD_COUNT_MIN / 8) : 656 (AE_RXD_COUNT_DEFAULT / 12)); 657 658 /* 659 * Init mailboxes. 660 */ 661 sc->txd_cur = sc->rxd_cur = 0; 662 sc->txs_ack = sc->txd_ack = 0; 663 sc->rxd_cur = 0; 664 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur); 665 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur); 666 667 sc->tx_inproc = 0; /* Number of packets the chip processes now. */ 668 sc->flags |= AE_FLAG_TXAVAIL; /* Free Tx's available. */ 669 670 /* 671 * Enable DMA. 672 */ 673 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN); 674 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN); 675 676 /* 677 * Check if everything is OK. 678 */ 679 val = AE_READ_4(sc, AE_ISR_REG); 680 if ((val & AE_ISR_PHY_LINKDOWN) != 0) { 681 device_printf(sc->dev, "Initialization failed.\n"); 682 return (ENXIO); 683 } 684 685 /* 686 * Clear interrupt status. 687 */ 688 AE_WRITE_4(sc, AE_ISR_REG, 0x3fffffff); 689 AE_WRITE_4(sc, AE_ISR_REG, 0x0); 690 691 /* 692 * Enable interrupts. 693 */ 694 val = AE_READ_4(sc, AE_MASTER_REG); 695 AE_WRITE_4(sc, AE_MASTER_REG, val | AE_MASTER_MANUAL_INT); 696 AE_WRITE_4(sc, AE_IMR_REG, AE_IMR_DEFAULT); 697 698 /* 699 * Disable WOL. 700 */ 701 AE_WRITE_4(sc, AE_WOL_REG, 0); 702 703 /* 704 * Configure MAC. 705 */ 706 val = AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD | 707 AE_MAC_FULL_DUPLEX | AE_MAC_CLK_PHY | 708 AE_MAC_TX_FLOW_EN | AE_MAC_RX_FLOW_EN | 709 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & AE_HALFBUF_MASK) | 710 ((AE_MAC_PREAMBLE_DEFAULT << AE_MAC_PREAMBLE_SHIFT) & 711 AE_MAC_PREAMBLE_MASK); 712 AE_WRITE_4(sc, AE_MAC_REG, val); 713 714 /* 715 * Configure Rx MAC. 716 */ 717 ae_rxfilter(sc); 718 ae_rxvlan(sc); 719 720 /* 721 * Enable Tx/Rx. 722 */ 723 val = AE_READ_4(sc, AE_MAC_REG); 724 AE_WRITE_4(sc, AE_MAC_REG, val | AE_MAC_TX_EN | AE_MAC_RX_EN); 725 726 sc->flags &= ~AE_FLAG_LINK; 727 mii_mediachg(mii); /* Switch to the current media. */ 728 729 callout_reset(&sc->tick_ch, hz, ae_tick, sc); 730 731 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 732 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 733 734 #ifdef AE_DEBUG 735 device_printf(sc->dev, "Initialization complete.\n"); 736 #endif 737 738 return (0); 739 } 740 741 static int 742 ae_detach(device_t dev) 743 { 744 struct ae_softc *sc; 745 if_t ifp; 746 747 sc = device_get_softc(dev); 748 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__)); 749 ifp = sc->ifp; 750 if (device_is_attached(dev)) { 751 AE_LOCK(sc); 752 sc->flags |= AE_FLAG_DETACH; 753 ae_stop(sc); 754 AE_UNLOCK(sc); 755 callout_drain(&sc->tick_ch); 756 taskqueue_drain(sc->tq, &sc->int_task); 757 taskqueue_drain(taskqueue_swi, &sc->link_task); 758 ether_ifdetach(ifp); 759 } 760 if (sc->tq != NULL) { 761 taskqueue_drain(sc->tq, &sc->int_task); 762 taskqueue_free(sc->tq); 763 sc->tq = NULL; 764 } 765 if (sc->miibus != NULL) { 766 device_delete_child(dev, sc->miibus); 767 sc->miibus = NULL; 768 } 769 bus_generic_detach(sc->dev); 770 ae_dma_free(sc); 771 if (sc->intrhand != NULL) { 772 bus_teardown_intr(dev, sc->irq[0], sc->intrhand); 773 sc->intrhand = NULL; 774 } 775 if (ifp != NULL) { 776 if_free(ifp); 777 sc->ifp = NULL; 778 } 779 if (sc->spec_irq != NULL) 780 bus_release_resources(dev, sc->spec_irq, sc->irq); 781 if (sc->spec_mem != NULL) 782 bus_release_resources(dev, sc->spec_mem, sc->mem); 783 if ((sc->flags & AE_FLAG_MSI) != 0) 784 pci_release_msi(dev); 785 mtx_destroy(&sc->mtx); 786 787 return (0); 788 } 789 790 static int 791 ae_miibus_readreg(device_t dev, int phy, int reg) 792 { 793 ae_softc_t *sc; 794 uint32_t val; 795 int i; 796 797 sc = device_get_softc(dev); 798 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 799 800 /* 801 * Locking is done in upper layers. 802 */ 803 804 val = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) | 805 AE_MDIO_START | AE_MDIO_READ | AE_MDIO_SUP_PREAMBLE | 806 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK); 807 AE_WRITE_4(sc, AE_MDIO_REG, val); 808 809 /* 810 * Wait for operation to complete. 811 */ 812 for (i = 0; i < AE_MDIO_TIMEOUT; i++) { 813 DELAY(2); 814 val = AE_READ_4(sc, AE_MDIO_REG); 815 if ((val & (AE_MDIO_START | AE_MDIO_BUSY)) == 0) 816 break; 817 } 818 if (i == AE_MDIO_TIMEOUT) { 819 device_printf(sc->dev, "phy read timeout: %d.\n", reg); 820 return (0); 821 } 822 return ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK); 823 } 824 825 static int 826 ae_miibus_writereg(device_t dev, int phy, int reg, int val) 827 { 828 ae_softc_t *sc; 829 uint32_t aereg; 830 int i; 831 832 sc = device_get_softc(dev); 833 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 834 835 /* 836 * Locking is done in upper layers. 837 */ 838 839 aereg = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) | 840 AE_MDIO_START | AE_MDIO_SUP_PREAMBLE | 841 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK) | 842 ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK); 843 AE_WRITE_4(sc, AE_MDIO_REG, aereg); 844 845 /* 846 * Wait for operation to complete. 847 */ 848 for (i = 0; i < AE_MDIO_TIMEOUT; i++) { 849 DELAY(2); 850 aereg = AE_READ_4(sc, AE_MDIO_REG); 851 if ((aereg & (AE_MDIO_START | AE_MDIO_BUSY)) == 0) 852 break; 853 } 854 if (i == AE_MDIO_TIMEOUT) { 855 device_printf(sc->dev, "phy write timeout: %d.\n", reg); 856 } 857 return (0); 858 } 859 860 static void 861 ae_miibus_statchg(device_t dev) 862 { 863 ae_softc_t *sc; 864 865 sc = device_get_softc(dev); 866 taskqueue_enqueue(taskqueue_swi, &sc->link_task); 867 } 868 869 static void 870 ae_mediastatus(if_t ifp, struct ifmediareq *ifmr) 871 { 872 ae_softc_t *sc; 873 struct mii_data *mii; 874 875 sc = if_getsoftc(ifp); 876 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 877 878 AE_LOCK(sc); 879 mii = device_get_softc(sc->miibus); 880 mii_pollstat(mii); 881 ifmr->ifm_status = mii->mii_media_status; 882 ifmr->ifm_active = mii->mii_media_active; 883 AE_UNLOCK(sc); 884 } 885 886 static int 887 ae_mediachange(if_t ifp) 888 { 889 ae_softc_t *sc; 890 struct mii_data *mii; 891 struct mii_softc *mii_sc; 892 int error; 893 894 /* XXX: check IFF_UP ?? */ 895 sc = if_getsoftc(ifp); 896 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 897 AE_LOCK(sc); 898 mii = device_get_softc(sc->miibus); 899 LIST_FOREACH(mii_sc, &mii->mii_phys, mii_list) 900 PHY_RESET(mii_sc); 901 error = mii_mediachg(mii); 902 AE_UNLOCK(sc); 903 904 return (error); 905 } 906 907 static int 908 ae_check_eeprom_present(ae_softc_t *sc, int *vpdc) 909 { 910 int error; 911 uint32_t val; 912 913 KASSERT(vpdc != NULL, ("[ae, %d]: vpdc is NULL!\n", __LINE__)); 914 915 /* 916 * Not sure why, but Linux does this. 917 */ 918 val = AE_READ_4(sc, AE_SPICTL_REG); 919 if ((val & AE_SPICTL_VPD_EN) != 0) { 920 val &= ~AE_SPICTL_VPD_EN; 921 AE_WRITE_4(sc, AE_SPICTL_REG, val); 922 } 923 error = pci_find_cap(sc->dev, PCIY_VPD, vpdc); 924 return (error); 925 } 926 927 static int 928 ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word) 929 { 930 uint32_t val; 931 int i; 932 933 AE_WRITE_4(sc, AE_VPD_DATA_REG, 0); /* Clear register value. */ 934 935 /* 936 * VPD registers start at offset 0x100. Read them. 937 */ 938 val = 0x100 + reg * 4; 939 AE_WRITE_4(sc, AE_VPD_CAP_REG, (val << AE_VPD_CAP_ADDR_SHIFT) & 940 AE_VPD_CAP_ADDR_MASK); 941 for (i = 0; i < AE_VPD_TIMEOUT; i++) { 942 DELAY(2000); 943 val = AE_READ_4(sc, AE_VPD_CAP_REG); 944 if ((val & AE_VPD_CAP_DONE) != 0) 945 break; 946 } 947 if (i == AE_VPD_TIMEOUT) { 948 device_printf(sc->dev, "timeout reading VPD register %d.\n", 949 reg); 950 return (ETIMEDOUT); 951 } 952 *word = AE_READ_4(sc, AE_VPD_DATA_REG); 953 return (0); 954 } 955 956 static int 957 ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr) 958 { 959 uint32_t word, reg, val; 960 int error; 961 int found; 962 int vpdc; 963 int i; 964 965 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 966 KASSERT(eaddr != NULL, ("[ae, %d]: eaddr is NULL", __LINE__)); 967 968 /* 969 * Check for EEPROM. 970 */ 971 error = ae_check_eeprom_present(sc, &vpdc); 972 if (error != 0) 973 return (error); 974 975 /* 976 * Read the VPD configuration space. 977 * Each register is prefixed with signature, 978 * so we can check if it is valid. 979 */ 980 for (i = 0, found = 0; i < AE_VPD_NREGS; i++) { 981 error = ae_vpd_read_word(sc, i, &word); 982 if (error != 0) 983 break; 984 985 /* 986 * Check signature. 987 */ 988 if ((word & AE_VPD_SIG_MASK) != AE_VPD_SIG) 989 break; 990 reg = word >> AE_VPD_REG_SHIFT; 991 i++; /* Move to the next word. */ 992 993 if (reg != AE_EADDR0_REG && reg != AE_EADDR1_REG) 994 continue; 995 996 error = ae_vpd_read_word(sc, i, &val); 997 if (error != 0) 998 break; 999 if (reg == AE_EADDR0_REG) 1000 eaddr[0] = val; 1001 else 1002 eaddr[1] = val; 1003 found++; 1004 } 1005 1006 if (found < 2) 1007 return (ENOENT); 1008 1009 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */ 1010 if (AE_CHECK_EADDR_VALID(eaddr) != 0) { 1011 if (bootverbose) 1012 device_printf(sc->dev, 1013 "VPD ethernet address registers are invalid.\n"); 1014 return (EINVAL); 1015 } 1016 return (0); 1017 } 1018 1019 static int 1020 ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr) 1021 { 1022 1023 /* 1024 * BIOS is supposed to set this. 1025 */ 1026 eaddr[0] = AE_READ_4(sc, AE_EADDR0_REG); 1027 eaddr[1] = AE_READ_4(sc, AE_EADDR1_REG); 1028 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */ 1029 1030 if (AE_CHECK_EADDR_VALID(eaddr) != 0) { 1031 if (bootverbose) 1032 device_printf(sc->dev, 1033 "Ethernet address registers are invalid.\n"); 1034 return (EINVAL); 1035 } 1036 return (0); 1037 } 1038 1039 static void 1040 ae_retrieve_address(ae_softc_t *sc) 1041 { 1042 uint32_t eaddr[2] = {0, 0}; 1043 int error; 1044 1045 /* 1046 *Check for EEPROM. 1047 */ 1048 error = ae_get_vpd_eaddr(sc, eaddr); 1049 if (error != 0) 1050 error = ae_get_reg_eaddr(sc, eaddr); 1051 if (error != 0) { 1052 if (bootverbose) 1053 device_printf(sc->dev, 1054 "Generating random ethernet address.\n"); 1055 eaddr[0] = arc4random(); 1056 1057 /* 1058 * Set OUI to ASUSTek COMPUTER INC. 1059 */ 1060 sc->eaddr[0] = 0x02; /* U/L bit set. */ 1061 sc->eaddr[1] = 0x1f; 1062 sc->eaddr[2] = 0xc6; 1063 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff; 1064 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff; 1065 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff; 1066 } else { 1067 sc->eaddr[0] = (eaddr[1] >> 8) & 0xff; 1068 sc->eaddr[1] = (eaddr[1] >> 0) & 0xff; 1069 sc->eaddr[2] = (eaddr[0] >> 24) & 0xff; 1070 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff; 1071 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff; 1072 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff; 1073 } 1074 } 1075 1076 static void 1077 ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1078 { 1079 bus_addr_t *addr = arg; 1080 1081 if (error != 0) 1082 return; 1083 KASSERT(nsegs == 1, ("[ae, %d]: %d segments instead of 1!", __LINE__, 1084 nsegs)); 1085 *addr = segs[0].ds_addr; 1086 } 1087 1088 static int 1089 ae_alloc_rings(ae_softc_t *sc) 1090 { 1091 bus_addr_t busaddr; 1092 int error; 1093 1094 /* 1095 * Create parent DMA tag. 1096 */ 1097 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1098 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1099 NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 1100 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 1101 &sc->dma_parent_tag); 1102 if (error != 0) { 1103 device_printf(sc->dev, "could not creare parent DMA tag.\n"); 1104 return (error); 1105 } 1106 1107 /* 1108 * Create DMA tag for TxD. 1109 */ 1110 error = bus_dma_tag_create(sc->dma_parent_tag, 1111 8, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1112 NULL, NULL, AE_TXD_BUFSIZE_DEFAULT, 1, 1113 AE_TXD_BUFSIZE_DEFAULT, 0, NULL, NULL, 1114 &sc->dma_txd_tag); 1115 if (error != 0) { 1116 device_printf(sc->dev, "could not creare TxD DMA tag.\n"); 1117 return (error); 1118 } 1119 1120 /* 1121 * Create DMA tag for TxS. 1122 */ 1123 error = bus_dma_tag_create(sc->dma_parent_tag, 1124 8, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1125 NULL, NULL, AE_TXS_COUNT_DEFAULT * 4, 1, 1126 AE_TXS_COUNT_DEFAULT * 4, 0, NULL, NULL, 1127 &sc->dma_txs_tag); 1128 if (error != 0) { 1129 device_printf(sc->dev, "could not creare TxS DMA tag.\n"); 1130 return (error); 1131 } 1132 1133 /* 1134 * Create DMA tag for RxD. 1135 */ 1136 error = bus_dma_tag_create(sc->dma_parent_tag, 1137 128, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1138 NULL, NULL, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 1, 1139 AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 0, NULL, NULL, 1140 &sc->dma_rxd_tag); 1141 if (error != 0) { 1142 device_printf(sc->dev, "could not creare TxS DMA tag.\n"); 1143 return (error); 1144 } 1145 1146 /* 1147 * Allocate TxD DMA memory. 1148 */ 1149 error = bus_dmamem_alloc(sc->dma_txd_tag, (void **)&sc->txd_base, 1150 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1151 &sc->dma_txd_map); 1152 if (error != 0) { 1153 device_printf(sc->dev, 1154 "could not allocate DMA memory for TxD ring.\n"); 1155 return (error); 1156 } 1157 error = bus_dmamap_load(sc->dma_txd_tag, sc->dma_txd_map, sc->txd_base, 1158 AE_TXD_BUFSIZE_DEFAULT, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1159 if (error != 0 || busaddr == 0) { 1160 device_printf(sc->dev, 1161 "could not load DMA map for TxD ring.\n"); 1162 return (error); 1163 } 1164 sc->dma_txd_busaddr = busaddr; 1165 1166 /* 1167 * Allocate TxS DMA memory. 1168 */ 1169 error = bus_dmamem_alloc(sc->dma_txs_tag, (void **)&sc->txs_base, 1170 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1171 &sc->dma_txs_map); 1172 if (error != 0) { 1173 device_printf(sc->dev, 1174 "could not allocate DMA memory for TxS ring.\n"); 1175 return (error); 1176 } 1177 error = bus_dmamap_load(sc->dma_txs_tag, sc->dma_txs_map, sc->txs_base, 1178 AE_TXS_COUNT_DEFAULT * 4, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1179 if (error != 0 || busaddr == 0) { 1180 device_printf(sc->dev, 1181 "could not load DMA map for TxS ring.\n"); 1182 return (error); 1183 } 1184 sc->dma_txs_busaddr = busaddr; 1185 1186 /* 1187 * Allocate RxD DMA memory. 1188 */ 1189 error = bus_dmamem_alloc(sc->dma_rxd_tag, (void **)&sc->rxd_base_dma, 1190 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1191 &sc->dma_rxd_map); 1192 if (error != 0) { 1193 device_printf(sc->dev, 1194 "could not allocate DMA memory for RxD ring.\n"); 1195 return (error); 1196 } 1197 error = bus_dmamap_load(sc->dma_rxd_tag, sc->dma_rxd_map, 1198 sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 1199 ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1200 if (error != 0 || busaddr == 0) { 1201 device_printf(sc->dev, 1202 "could not load DMA map for RxD ring.\n"); 1203 return (error); 1204 } 1205 sc->dma_rxd_busaddr = busaddr + AE_RXD_PADDING; 1206 sc->rxd_base = (ae_rxd_t *)(sc->rxd_base_dma + AE_RXD_PADDING); 1207 1208 return (0); 1209 } 1210 1211 static void 1212 ae_dma_free(ae_softc_t *sc) 1213 { 1214 1215 if (sc->dma_txd_tag != NULL) { 1216 if (sc->dma_txd_busaddr != 0) 1217 bus_dmamap_unload(sc->dma_txd_tag, sc->dma_txd_map); 1218 if (sc->txd_base != NULL) 1219 bus_dmamem_free(sc->dma_txd_tag, sc->txd_base, 1220 sc->dma_txd_map); 1221 bus_dma_tag_destroy(sc->dma_txd_tag); 1222 sc->dma_txd_tag = NULL; 1223 sc->txd_base = NULL; 1224 sc->dma_txd_busaddr = 0; 1225 } 1226 if (sc->dma_txs_tag != NULL) { 1227 if (sc->dma_txs_busaddr != 0) 1228 bus_dmamap_unload(sc->dma_txs_tag, sc->dma_txs_map); 1229 if (sc->txs_base != NULL) 1230 bus_dmamem_free(sc->dma_txs_tag, sc->txs_base, 1231 sc->dma_txs_map); 1232 bus_dma_tag_destroy(sc->dma_txs_tag); 1233 sc->dma_txs_tag = NULL; 1234 sc->txs_base = NULL; 1235 sc->dma_txs_busaddr = 0; 1236 } 1237 if (sc->dma_rxd_tag != NULL) { 1238 if (sc->dma_rxd_busaddr != 0) 1239 bus_dmamap_unload(sc->dma_rxd_tag, sc->dma_rxd_map); 1240 if (sc->rxd_base_dma != NULL) 1241 bus_dmamem_free(sc->dma_rxd_tag, sc->rxd_base_dma, 1242 sc->dma_rxd_map); 1243 bus_dma_tag_destroy(sc->dma_rxd_tag); 1244 sc->dma_rxd_tag = NULL; 1245 sc->rxd_base_dma = NULL; 1246 sc->dma_rxd_busaddr = 0; 1247 } 1248 if (sc->dma_parent_tag != NULL) { 1249 bus_dma_tag_destroy(sc->dma_parent_tag); 1250 sc->dma_parent_tag = NULL; 1251 } 1252 } 1253 1254 static int 1255 ae_shutdown(device_t dev) 1256 { 1257 ae_softc_t *sc; 1258 int error; 1259 1260 sc = device_get_softc(dev); 1261 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__)); 1262 1263 error = ae_suspend(dev); 1264 AE_LOCK(sc); 1265 ae_powersave_enable(sc); 1266 AE_UNLOCK(sc); 1267 return (error); 1268 } 1269 1270 static void 1271 ae_powersave_disable(ae_softc_t *sc) 1272 { 1273 uint32_t val; 1274 1275 AE_LOCK_ASSERT(sc); 1276 1277 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0); 1278 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA); 1279 if (val & AE_PHY_DBG_POWERSAVE) { 1280 val &= ~AE_PHY_DBG_POWERSAVE; 1281 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, val); 1282 DELAY(1000); 1283 } 1284 } 1285 1286 static void 1287 ae_powersave_enable(ae_softc_t *sc) 1288 { 1289 uint32_t val; 1290 1291 AE_LOCK_ASSERT(sc); 1292 1293 /* 1294 * XXX magic numbers. 1295 */ 1296 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0); 1297 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA); 1298 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, val | 0x1000); 1299 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 2); 1300 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0x3000); 1301 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 3); 1302 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0); 1303 } 1304 1305 static void 1306 ae_pm_init(ae_softc_t *sc) 1307 { 1308 if_t ifp; 1309 uint32_t val; 1310 uint16_t pmstat; 1311 struct mii_data *mii; 1312 int pmc; 1313 1314 AE_LOCK_ASSERT(sc); 1315 1316 ifp = sc->ifp; 1317 if ((sc->flags & AE_FLAG_PMG) == 0) { 1318 /* Disable WOL entirely. */ 1319 AE_WRITE_4(sc, AE_WOL_REG, 0); 1320 return; 1321 } 1322 1323 /* 1324 * Configure WOL if enabled. 1325 */ 1326 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 1327 mii = device_get_softc(sc->miibus); 1328 mii_pollstat(mii); 1329 if ((mii->mii_media_status & IFM_AVALID) != 0 && 1330 (mii->mii_media_status & IFM_ACTIVE) != 0) { 1331 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_MAGIC | \ 1332 AE_WOL_MAGIC_PME); 1333 1334 /* 1335 * Configure MAC. 1336 */ 1337 val = AE_MAC_RX_EN | AE_MAC_CLK_PHY | \ 1338 AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD | \ 1339 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & \ 1340 AE_HALFBUF_MASK) | \ 1341 ((AE_MAC_PREAMBLE_DEFAULT << \ 1342 AE_MAC_PREAMBLE_SHIFT) & AE_MAC_PREAMBLE_MASK) | \ 1343 AE_MAC_BCAST_EN | AE_MAC_MCAST_EN; 1344 if ((IFM_OPTIONS(mii->mii_media_active) & \ 1345 IFM_FDX) != 0) 1346 val |= AE_MAC_FULL_DUPLEX; 1347 AE_WRITE_4(sc, AE_MAC_REG, val); 1348 1349 } else { /* No link. */ 1350 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_LNKCHG | \ 1351 AE_WOL_LNKCHG_PME); 1352 AE_WRITE_4(sc, AE_MAC_REG, 0); 1353 } 1354 } else { 1355 ae_powersave_enable(sc); 1356 } 1357 1358 /* 1359 * PCIE hacks. Magic numbers. 1360 */ 1361 val = AE_READ_4(sc, AE_PCIE_PHYMISC_REG); 1362 val |= AE_PCIE_PHYMISC_FORCE_RCV_DET; 1363 AE_WRITE_4(sc, AE_PCIE_PHYMISC_REG, val); 1364 val = AE_READ_4(sc, AE_PCIE_DLL_TX_CTRL_REG); 1365 val |= AE_PCIE_DLL_TX_CTRL_SEL_NOR_CLK; 1366 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, val); 1367 1368 /* 1369 * Configure PME. 1370 */ 1371 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) { 1372 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1373 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1374 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 1375 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1376 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1377 } 1378 } 1379 1380 static int 1381 ae_suspend(device_t dev) 1382 { 1383 ae_softc_t *sc; 1384 1385 sc = device_get_softc(dev); 1386 1387 AE_LOCK(sc); 1388 ae_stop(sc); 1389 ae_pm_init(sc); 1390 AE_UNLOCK(sc); 1391 1392 return (0); 1393 } 1394 1395 static int 1396 ae_resume(device_t dev) 1397 { 1398 ae_softc_t *sc; 1399 1400 sc = device_get_softc(dev); 1401 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1402 1403 AE_LOCK(sc); 1404 AE_READ_4(sc, AE_WOL_REG); /* Clear WOL status. */ 1405 if ((if_getflags(sc->ifp) & IFF_UP) != 0) 1406 ae_init_locked(sc); 1407 AE_UNLOCK(sc); 1408 1409 return (0); 1410 } 1411 1412 static unsigned int 1413 ae_tx_avail_size(ae_softc_t *sc) 1414 { 1415 unsigned int avail; 1416 1417 if (sc->txd_cur >= sc->txd_ack) 1418 avail = AE_TXD_BUFSIZE_DEFAULT - (sc->txd_cur - sc->txd_ack); 1419 else 1420 avail = sc->txd_ack - sc->txd_cur; 1421 1422 return (avail); 1423 } 1424 1425 static int 1426 ae_encap(ae_softc_t *sc, struct mbuf **m_head) 1427 { 1428 struct mbuf *m0; 1429 ae_txd_t *hdr; 1430 unsigned int to_end; 1431 uint16_t len; 1432 1433 AE_LOCK_ASSERT(sc); 1434 1435 m0 = *m_head; 1436 len = m0->m_pkthdr.len; 1437 1438 if ((sc->flags & AE_FLAG_TXAVAIL) == 0 || 1439 len + sizeof(ae_txd_t) + 3 > ae_tx_avail_size(sc)) { 1440 #ifdef AE_DEBUG 1441 if_printf(sc->ifp, "No free Tx available.\n"); 1442 #endif 1443 return ENOBUFS; 1444 } 1445 1446 hdr = (ae_txd_t *)(sc->txd_base + sc->txd_cur); 1447 bzero(hdr, sizeof(*hdr)); 1448 /* Skip header size. */ 1449 sc->txd_cur = (sc->txd_cur + sizeof(ae_txd_t)) % AE_TXD_BUFSIZE_DEFAULT; 1450 /* Space available to the end of the ring */ 1451 to_end = AE_TXD_BUFSIZE_DEFAULT - sc->txd_cur; 1452 if (to_end >= len) { 1453 m_copydata(m0, 0, len, (caddr_t)(sc->txd_base + sc->txd_cur)); 1454 } else { 1455 m_copydata(m0, 0, to_end, (caddr_t)(sc->txd_base + 1456 sc->txd_cur)); 1457 m_copydata(m0, to_end, len - to_end, (caddr_t)sc->txd_base); 1458 } 1459 1460 /* 1461 * Set TxD flags and parameters. 1462 */ 1463 if ((m0->m_flags & M_VLANTAG) != 0) { 1464 hdr->vlan = htole16(AE_TXD_VLAN(m0->m_pkthdr.ether_vtag)); 1465 hdr->len = htole16(len | AE_TXD_INSERT_VTAG); 1466 } else { 1467 hdr->len = htole16(len); 1468 } 1469 1470 /* 1471 * Set current TxD position and round up to a 4-byte boundary. 1472 */ 1473 sc->txd_cur = ((sc->txd_cur + len + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT; 1474 if (sc->txd_cur == sc->txd_ack) 1475 sc->flags &= ~AE_FLAG_TXAVAIL; 1476 #ifdef AE_DEBUG 1477 if_printf(sc->ifp, "New txd_cur = %d.\n", sc->txd_cur); 1478 #endif 1479 1480 /* 1481 * Update TxS position and check if there are empty TxS available. 1482 */ 1483 sc->txs_base[sc->txs_cur].flags &= ~htole16(AE_TXS_UPDATE); 1484 sc->txs_cur = (sc->txs_cur + 1) % AE_TXS_COUNT_DEFAULT; 1485 if (sc->txs_cur == sc->txs_ack) 1486 sc->flags &= ~AE_FLAG_TXAVAIL; 1487 1488 /* 1489 * Synchronize DMA memory. 1490 */ 1491 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, BUS_DMASYNC_PREREAD | 1492 BUS_DMASYNC_PREWRITE); 1493 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1494 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1495 1496 return (0); 1497 } 1498 1499 static void 1500 ae_start(if_t ifp) 1501 { 1502 ae_softc_t *sc; 1503 1504 sc = if_getsoftc(ifp); 1505 AE_LOCK(sc); 1506 ae_start_locked(ifp); 1507 AE_UNLOCK(sc); 1508 } 1509 1510 static void 1511 ae_start_locked(if_t ifp) 1512 { 1513 ae_softc_t *sc; 1514 unsigned int count; 1515 struct mbuf *m0; 1516 int error; 1517 1518 sc = if_getsoftc(ifp); 1519 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1520 AE_LOCK_ASSERT(sc); 1521 1522 #ifdef AE_DEBUG 1523 if_printf(ifp, "Start called.\n"); 1524 #endif 1525 1526 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1527 IFF_DRV_RUNNING || (sc->flags & AE_FLAG_LINK) == 0) 1528 return; 1529 1530 count = 0; 1531 while (!if_sendq_empty(ifp)) { 1532 m0 = if_dequeue(ifp); 1533 if (m0 == NULL) 1534 break; /* Nothing to do. */ 1535 1536 error = ae_encap(sc, &m0); 1537 if (error != 0) { 1538 if (m0 != NULL) { 1539 if_sendq_prepend(ifp, m0); 1540 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1541 #ifdef AE_DEBUG 1542 if_printf(ifp, "Setting OACTIVE.\n"); 1543 #endif 1544 } 1545 break; 1546 } 1547 count++; 1548 sc->tx_inproc++; 1549 1550 /* Bounce a copy of the frame to BPF. */ 1551 ETHER_BPF_MTAP(ifp, m0); 1552 1553 m_freem(m0); 1554 } 1555 1556 if (count > 0) { /* Something was dequeued. */ 1557 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur / 4); 1558 sc->wd_timer = AE_TX_TIMEOUT; /* Load watchdog. */ 1559 #ifdef AE_DEBUG 1560 if_printf(ifp, "%d packets dequeued.\n", count); 1561 if_printf(ifp, "Tx pos now is %d.\n", sc->txd_cur); 1562 #endif 1563 } 1564 } 1565 1566 static void 1567 ae_link_task(void *arg, int pending) 1568 { 1569 ae_softc_t *sc; 1570 struct mii_data *mii; 1571 if_t ifp; 1572 uint32_t val; 1573 1574 sc = (ae_softc_t *)arg; 1575 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1576 AE_LOCK(sc); 1577 1578 ifp = sc->ifp; 1579 mii = device_get_softc(sc->miibus); 1580 if (mii == NULL || ifp == NULL || 1581 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 1582 AE_UNLOCK(sc); /* XXX: could happen? */ 1583 return; 1584 } 1585 1586 sc->flags &= ~AE_FLAG_LINK; 1587 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 1588 (IFM_AVALID | IFM_ACTIVE)) { 1589 switch(IFM_SUBTYPE(mii->mii_media_active)) { 1590 case IFM_10_T: 1591 case IFM_100_TX: 1592 sc->flags |= AE_FLAG_LINK; 1593 break; 1594 default: 1595 break; 1596 } 1597 } 1598 1599 /* 1600 * Stop Rx/Tx MACs. 1601 */ 1602 ae_stop_rxmac(sc); 1603 ae_stop_txmac(sc); 1604 1605 if ((sc->flags & AE_FLAG_LINK) != 0) { 1606 ae_mac_config(sc); 1607 1608 /* 1609 * Restart DMA engines. 1610 */ 1611 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN); 1612 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN); 1613 1614 /* 1615 * Enable Rx and Tx MACs. 1616 */ 1617 val = AE_READ_4(sc, AE_MAC_REG); 1618 val |= AE_MAC_TX_EN | AE_MAC_RX_EN; 1619 AE_WRITE_4(sc, AE_MAC_REG, val); 1620 } 1621 AE_UNLOCK(sc); 1622 } 1623 1624 static void 1625 ae_stop_rxmac(ae_softc_t *sc) 1626 { 1627 uint32_t val; 1628 int i; 1629 1630 AE_LOCK_ASSERT(sc); 1631 1632 /* 1633 * Stop Rx MAC engine. 1634 */ 1635 val = AE_READ_4(sc, AE_MAC_REG); 1636 if ((val & AE_MAC_RX_EN) != 0) { 1637 val &= ~AE_MAC_RX_EN; 1638 AE_WRITE_4(sc, AE_MAC_REG, val); 1639 } 1640 1641 /* 1642 * Stop Rx DMA engine. 1643 */ 1644 if (AE_READ_1(sc, AE_DMAWRITE_REG) == AE_DMAWRITE_EN) 1645 AE_WRITE_1(sc, AE_DMAWRITE_REG, 0); 1646 1647 /* 1648 * Wait for IDLE state. 1649 */ 1650 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 1651 val = AE_READ_4(sc, AE_IDLE_REG); 1652 if ((val & (AE_IDLE_RXMAC | AE_IDLE_DMAWRITE)) == 0) 1653 break; 1654 DELAY(100); 1655 } 1656 if (i == AE_IDLE_TIMEOUT) 1657 device_printf(sc->dev, "timed out while stopping Rx MAC.\n"); 1658 } 1659 1660 static void 1661 ae_stop_txmac(ae_softc_t *sc) 1662 { 1663 uint32_t val; 1664 int i; 1665 1666 AE_LOCK_ASSERT(sc); 1667 1668 /* 1669 * Stop Tx MAC engine. 1670 */ 1671 val = AE_READ_4(sc, AE_MAC_REG); 1672 if ((val & AE_MAC_TX_EN) != 0) { 1673 val &= ~AE_MAC_TX_EN; 1674 AE_WRITE_4(sc, AE_MAC_REG, val); 1675 } 1676 1677 /* 1678 * Stop Tx DMA engine. 1679 */ 1680 if (AE_READ_1(sc, AE_DMAREAD_REG) == AE_DMAREAD_EN) 1681 AE_WRITE_1(sc, AE_DMAREAD_REG, 0); 1682 1683 /* 1684 * Wait for IDLE state. 1685 */ 1686 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 1687 val = AE_READ_4(sc, AE_IDLE_REG); 1688 if ((val & (AE_IDLE_TXMAC | AE_IDLE_DMAREAD)) == 0) 1689 break; 1690 DELAY(100); 1691 } 1692 if (i == AE_IDLE_TIMEOUT) 1693 device_printf(sc->dev, "timed out while stopping Tx MAC.\n"); 1694 } 1695 1696 static void 1697 ae_mac_config(ae_softc_t *sc) 1698 { 1699 struct mii_data *mii; 1700 uint32_t val; 1701 1702 AE_LOCK_ASSERT(sc); 1703 1704 mii = device_get_softc(sc->miibus); 1705 val = AE_READ_4(sc, AE_MAC_REG); 1706 val &= ~AE_MAC_FULL_DUPLEX; 1707 /* XXX disable AE_MAC_TX_FLOW_EN? */ 1708 1709 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1710 val |= AE_MAC_FULL_DUPLEX; 1711 1712 AE_WRITE_4(sc, AE_MAC_REG, val); 1713 } 1714 1715 static int 1716 ae_intr(void *arg) 1717 { 1718 ae_softc_t *sc; 1719 uint32_t val; 1720 1721 sc = (ae_softc_t *)arg; 1722 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1723 1724 val = AE_READ_4(sc, AE_ISR_REG); 1725 if (val == 0 || (val & AE_IMR_DEFAULT) == 0) 1726 return (FILTER_STRAY); 1727 1728 /* Disable interrupts. */ 1729 AE_WRITE_4(sc, AE_ISR_REG, AE_ISR_DISABLE); 1730 1731 /* Schedule interrupt processing. */ 1732 taskqueue_enqueue(sc->tq, &sc->int_task); 1733 1734 return (FILTER_HANDLED); 1735 } 1736 1737 static void 1738 ae_int_task(void *arg, int pending) 1739 { 1740 ae_softc_t *sc; 1741 if_t ifp; 1742 uint32_t val; 1743 1744 sc = (ae_softc_t *)arg; 1745 1746 AE_LOCK(sc); 1747 1748 ifp = sc->ifp; 1749 1750 val = AE_READ_4(sc, AE_ISR_REG); /* Read interrupt status. */ 1751 if (val == 0) { 1752 AE_UNLOCK(sc); 1753 return; 1754 } 1755 1756 /* 1757 * Clear interrupts and disable them. 1758 */ 1759 AE_WRITE_4(sc, AE_ISR_REG, val | AE_ISR_DISABLE); 1760 1761 #ifdef AE_DEBUG 1762 if_printf(ifp, "Interrupt received: 0x%08x\n", val); 1763 #endif 1764 1765 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1766 if ((val & (AE_ISR_DMAR_TIMEOUT | AE_ISR_DMAW_TIMEOUT | 1767 AE_ISR_PHY_LINKDOWN)) != 0) { 1768 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1769 ae_init_locked(sc); 1770 AE_UNLOCK(sc); 1771 return; 1772 } 1773 if ((val & AE_ISR_TX_EVENT) != 0) 1774 ae_tx_intr(sc); 1775 if ((val & AE_ISR_RX_EVENT) != 0) 1776 ae_rx_intr(sc); 1777 /* 1778 * Re-enable interrupts. 1779 */ 1780 AE_WRITE_4(sc, AE_ISR_REG, 0); 1781 1782 if ((sc->flags & AE_FLAG_TXAVAIL) != 0) { 1783 if (!if_sendq_empty(ifp)) 1784 ae_start_locked(ifp); 1785 } 1786 } 1787 1788 AE_UNLOCK(sc); 1789 } 1790 1791 static void 1792 ae_tx_intr(ae_softc_t *sc) 1793 { 1794 if_t ifp; 1795 ae_txd_t *txd; 1796 ae_txs_t *txs; 1797 uint16_t flags; 1798 1799 AE_LOCK_ASSERT(sc); 1800 1801 ifp = sc->ifp; 1802 1803 #ifdef AE_DEBUG 1804 if_printf(ifp, "Tx interrupt occuried.\n"); 1805 #endif 1806 1807 /* 1808 * Syncronize DMA buffers. 1809 */ 1810 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, 1811 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1812 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1813 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1814 1815 for (;;) { 1816 txs = sc->txs_base + sc->txs_ack; 1817 flags = le16toh(txs->flags); 1818 if ((flags & AE_TXS_UPDATE) == 0) 1819 break; 1820 txs->flags = htole16(flags & ~AE_TXS_UPDATE); 1821 /* Update stats. */ 1822 ae_update_stats_tx(flags, &sc->stats); 1823 1824 /* 1825 * Update TxS position. 1826 */ 1827 sc->txs_ack = (sc->txs_ack + 1) % AE_TXS_COUNT_DEFAULT; 1828 sc->flags |= AE_FLAG_TXAVAIL; 1829 1830 txd = (ae_txd_t *)(sc->txd_base + sc->txd_ack); 1831 if (txs->len != txd->len) 1832 device_printf(sc->dev, "Size mismatch: TxS:%d TxD:%d\n", 1833 le16toh(txs->len), le16toh(txd->len)); 1834 1835 /* 1836 * Move txd ack and align on 4-byte boundary. 1837 */ 1838 sc->txd_ack = ((sc->txd_ack + le16toh(txd->len) + 1839 sizeof(ae_txs_t) + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT; 1840 1841 if ((flags & AE_TXS_SUCCESS) != 0) 1842 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1843 else 1844 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1845 1846 sc->tx_inproc--; 1847 } 1848 1849 if ((sc->flags & AE_FLAG_TXAVAIL) != 0) 1850 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1851 if (sc->tx_inproc < 0) { 1852 if_printf(ifp, "Received stray Tx interrupt(s).\n"); 1853 sc->tx_inproc = 0; 1854 } 1855 1856 if (sc->tx_inproc == 0) 1857 sc->wd_timer = 0; /* Unarm watchdog. */ 1858 1859 /* 1860 * Syncronize DMA buffers. 1861 */ 1862 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, 1863 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1864 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1865 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1866 } 1867 1868 static void 1869 ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd) 1870 { 1871 if_t ifp; 1872 struct mbuf *m; 1873 unsigned int size; 1874 uint16_t flags; 1875 1876 AE_LOCK_ASSERT(sc); 1877 1878 ifp = sc->ifp; 1879 flags = le16toh(rxd->flags); 1880 1881 #ifdef AE_DEBUG 1882 if_printf(ifp, "Rx interrupt occuried.\n"); 1883 #endif 1884 size = le16toh(rxd->len) - ETHER_CRC_LEN; 1885 if (size < (ETHER_MIN_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN)) { 1886 if_printf(ifp, "Runt frame received."); 1887 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1888 return; 1889 } 1890 1891 m = m_devget(&rxd->data[0], size, ETHER_ALIGN, ifp, NULL); 1892 if (m == NULL) { 1893 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1894 return; 1895 } 1896 1897 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 1898 (flags & AE_RXD_HAS_VLAN) != 0) { 1899 m->m_pkthdr.ether_vtag = AE_RXD_VLAN(le16toh(rxd->vlan)); 1900 m->m_flags |= M_VLANTAG; 1901 } 1902 1903 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1904 /* 1905 * Pass it through. 1906 */ 1907 AE_UNLOCK(sc); 1908 if_input(ifp, m); 1909 AE_LOCK(sc); 1910 } 1911 1912 static void 1913 ae_rx_intr(ae_softc_t *sc) 1914 { 1915 ae_rxd_t *rxd; 1916 if_t ifp; 1917 uint16_t flags; 1918 int count; 1919 1920 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 1921 1922 AE_LOCK_ASSERT(sc); 1923 1924 ifp = sc->ifp; 1925 1926 /* 1927 * Syncronize DMA buffers. 1928 */ 1929 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map, 1930 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1931 1932 for (count = 0;; count++) { 1933 rxd = (ae_rxd_t *)(sc->rxd_base + sc->rxd_cur); 1934 flags = le16toh(rxd->flags); 1935 if ((flags & AE_RXD_UPDATE) == 0) 1936 break; 1937 rxd->flags = htole16(flags & ~AE_RXD_UPDATE); 1938 /* Update stats. */ 1939 ae_update_stats_rx(flags, &sc->stats); 1940 1941 /* 1942 * Update position index. 1943 */ 1944 sc->rxd_cur = (sc->rxd_cur + 1) % AE_RXD_COUNT_DEFAULT; 1945 1946 if ((flags & AE_RXD_SUCCESS) != 0) 1947 ae_rxeof(sc, rxd); 1948 else 1949 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1950 } 1951 1952 if (count > 0) { 1953 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map, 1954 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1955 /* 1956 * Update Rx index. 1957 */ 1958 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur); 1959 } 1960 } 1961 1962 static void 1963 ae_watchdog(ae_softc_t *sc) 1964 { 1965 if_t ifp; 1966 1967 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 1968 AE_LOCK_ASSERT(sc); 1969 ifp = sc->ifp; 1970 1971 if (sc->wd_timer == 0 || --sc->wd_timer != 0) 1972 return; /* Noting to do. */ 1973 1974 if ((sc->flags & AE_FLAG_LINK) == 0) 1975 if_printf(ifp, "watchdog timeout (missed link).\n"); 1976 else 1977 if_printf(ifp, "watchdog timeout - resetting.\n"); 1978 1979 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1980 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1981 ae_init_locked(sc); 1982 if (!if_sendq_empty(ifp)) 1983 ae_start_locked(ifp); 1984 } 1985 1986 static void 1987 ae_tick(void *arg) 1988 { 1989 ae_softc_t *sc; 1990 struct mii_data *mii; 1991 1992 sc = (ae_softc_t *)arg; 1993 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 1994 AE_LOCK_ASSERT(sc); 1995 1996 mii = device_get_softc(sc->miibus); 1997 mii_tick(mii); 1998 ae_watchdog(sc); /* Watchdog check. */ 1999 callout_reset(&sc->tick_ch, hz, ae_tick, sc); 2000 } 2001 2002 static void 2003 ae_rxvlan(ae_softc_t *sc) 2004 { 2005 if_t ifp; 2006 uint32_t val; 2007 2008 AE_LOCK_ASSERT(sc); 2009 ifp = sc->ifp; 2010 val = AE_READ_4(sc, AE_MAC_REG); 2011 val &= ~AE_MAC_RMVLAN_EN; 2012 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 2013 val |= AE_MAC_RMVLAN_EN; 2014 AE_WRITE_4(sc, AE_MAC_REG, val); 2015 } 2016 2017 static u_int 2018 ae_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 2019 { 2020 uint32_t crc, *mchash = arg; 2021 2022 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 2023 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2024 2025 return (1); 2026 } 2027 2028 static void 2029 ae_rxfilter(ae_softc_t *sc) 2030 { 2031 if_t ifp; 2032 uint32_t mchash[2]; 2033 uint32_t rxcfg; 2034 2035 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 2036 2037 AE_LOCK_ASSERT(sc); 2038 2039 ifp = sc->ifp; 2040 2041 rxcfg = AE_READ_4(sc, AE_MAC_REG); 2042 rxcfg &= ~(AE_MAC_MCAST_EN | AE_MAC_BCAST_EN | AE_MAC_PROMISC_EN); 2043 2044 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 2045 rxcfg |= AE_MAC_BCAST_EN; 2046 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 2047 rxcfg |= AE_MAC_PROMISC_EN; 2048 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 2049 rxcfg |= AE_MAC_MCAST_EN; 2050 2051 /* 2052 * Wipe old settings. 2053 */ 2054 AE_WRITE_4(sc, AE_REG_MHT0, 0); 2055 AE_WRITE_4(sc, AE_REG_MHT1, 0); 2056 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2057 AE_WRITE_4(sc, AE_REG_MHT0, 0xffffffff); 2058 AE_WRITE_4(sc, AE_REG_MHT1, 0xffffffff); 2059 AE_WRITE_4(sc, AE_MAC_REG, rxcfg); 2060 return; 2061 } 2062 2063 /* 2064 * Load multicast tables. 2065 */ 2066 bzero(mchash, sizeof(mchash)); 2067 if_foreach_llmaddr(ifp, ae_hash_maddr, &mchash); 2068 AE_WRITE_4(sc, AE_REG_MHT0, mchash[0]); 2069 AE_WRITE_4(sc, AE_REG_MHT1, mchash[1]); 2070 AE_WRITE_4(sc, AE_MAC_REG, rxcfg); 2071 } 2072 2073 static int 2074 ae_ioctl(if_t ifp, u_long cmd, caddr_t data) 2075 { 2076 struct ae_softc *sc; 2077 struct ifreq *ifr; 2078 struct mii_data *mii; 2079 int error, mask; 2080 2081 sc = if_getsoftc(ifp); 2082 ifr = (struct ifreq *)data; 2083 error = 0; 2084 2085 switch (cmd) { 2086 case SIOCSIFMTU: 2087 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) 2088 error = EINVAL; 2089 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 2090 AE_LOCK(sc); 2091 if_setmtu(ifp, ifr->ifr_mtu); 2092 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2093 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2094 ae_init_locked(sc); 2095 } 2096 AE_UNLOCK(sc); 2097 } 2098 break; 2099 case SIOCSIFFLAGS: 2100 AE_LOCK(sc); 2101 if ((if_getflags(ifp) & IFF_UP) != 0) { 2102 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2103 if (((if_getflags(ifp) ^ sc->if_flags) 2104 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2105 ae_rxfilter(sc); 2106 } else { 2107 if ((sc->flags & AE_FLAG_DETACH) == 0) 2108 ae_init_locked(sc); 2109 } 2110 } else { 2111 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2112 ae_stop(sc); 2113 } 2114 sc->if_flags = if_getflags(ifp); 2115 AE_UNLOCK(sc); 2116 break; 2117 case SIOCADDMULTI: 2118 case SIOCDELMULTI: 2119 AE_LOCK(sc); 2120 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2121 ae_rxfilter(sc); 2122 AE_UNLOCK(sc); 2123 break; 2124 case SIOCSIFMEDIA: 2125 case SIOCGIFMEDIA: 2126 mii = device_get_softc(sc->miibus); 2127 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2128 break; 2129 case SIOCSIFCAP: 2130 AE_LOCK(sc); 2131 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 2132 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2133 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 2134 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 2135 ae_rxvlan(sc); 2136 } 2137 VLAN_CAPABILITIES(ifp); 2138 AE_UNLOCK(sc); 2139 break; 2140 default: 2141 error = ether_ioctl(ifp, cmd, data); 2142 break; 2143 } 2144 return (error); 2145 } 2146 2147 static void 2148 ae_stop(ae_softc_t *sc) 2149 { 2150 if_t ifp; 2151 int i; 2152 2153 AE_LOCK_ASSERT(sc); 2154 2155 ifp = sc->ifp; 2156 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2157 sc->flags &= ~AE_FLAG_LINK; 2158 sc->wd_timer = 0; /* Cancel watchdog. */ 2159 callout_stop(&sc->tick_ch); 2160 2161 /* 2162 * Clear and disable interrupts. 2163 */ 2164 AE_WRITE_4(sc, AE_IMR_REG, 0); 2165 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff); 2166 2167 /* 2168 * Stop Rx/Tx MACs. 2169 */ 2170 ae_stop_txmac(sc); 2171 ae_stop_rxmac(sc); 2172 2173 /* 2174 * Stop DMA engines. 2175 */ 2176 AE_WRITE_1(sc, AE_DMAREAD_REG, ~AE_DMAREAD_EN); 2177 AE_WRITE_1(sc, AE_DMAWRITE_REG, ~AE_DMAWRITE_EN); 2178 2179 /* 2180 * Wait for everything to enter idle state. 2181 */ 2182 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 2183 if (AE_READ_4(sc, AE_IDLE_REG) == 0) 2184 break; 2185 DELAY(100); 2186 } 2187 if (i == AE_IDLE_TIMEOUT) 2188 device_printf(sc->dev, "could not enter idle state in stop.\n"); 2189 } 2190 2191 static void 2192 ae_update_stats_tx(uint16_t flags, ae_stats_t *stats) 2193 { 2194 2195 if ((flags & AE_TXS_BCAST) != 0) 2196 stats->tx_bcast++; 2197 if ((flags & AE_TXS_MCAST) != 0) 2198 stats->tx_mcast++; 2199 if ((flags & AE_TXS_PAUSE) != 0) 2200 stats->tx_pause++; 2201 if ((flags & AE_TXS_CTRL) != 0) 2202 stats->tx_ctrl++; 2203 if ((flags & AE_TXS_DEFER) != 0) 2204 stats->tx_defer++; 2205 if ((flags & AE_TXS_EXCDEFER) != 0) 2206 stats->tx_excdefer++; 2207 if ((flags & AE_TXS_SINGLECOL) != 0) 2208 stats->tx_singlecol++; 2209 if ((flags & AE_TXS_MULTICOL) != 0) 2210 stats->tx_multicol++; 2211 if ((flags & AE_TXS_LATECOL) != 0) 2212 stats->tx_latecol++; 2213 if ((flags & AE_TXS_ABORTCOL) != 0) 2214 stats->tx_abortcol++; 2215 if ((flags & AE_TXS_UNDERRUN) != 0) 2216 stats->tx_underrun++; 2217 } 2218 2219 static void 2220 ae_update_stats_rx(uint16_t flags, ae_stats_t *stats) 2221 { 2222 2223 if ((flags & AE_RXD_BCAST) != 0) 2224 stats->rx_bcast++; 2225 if ((flags & AE_RXD_MCAST) != 0) 2226 stats->rx_mcast++; 2227 if ((flags & AE_RXD_PAUSE) != 0) 2228 stats->rx_pause++; 2229 if ((flags & AE_RXD_CTRL) != 0) 2230 stats->rx_ctrl++; 2231 if ((flags & AE_RXD_CRCERR) != 0) 2232 stats->rx_crcerr++; 2233 if ((flags & AE_RXD_CODEERR) != 0) 2234 stats->rx_codeerr++; 2235 if ((flags & AE_RXD_RUNT) != 0) 2236 stats->rx_runt++; 2237 if ((flags & AE_RXD_FRAG) != 0) 2238 stats->rx_frag++; 2239 if ((flags & AE_RXD_TRUNC) != 0) 2240 stats->rx_trunc++; 2241 if ((flags & AE_RXD_ALIGN) != 0) 2242 stats->rx_align++; 2243 } 2244