1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2006 Benno Rice.
5 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
6 * All rights reserved.
7 *
8 * Adapted to Marvell SoC by Semihalf.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1
31 */
32
33 #include <sys/cdefs.h>
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/bus.h>
37 #include <sys/eventhandler.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
40 #include <sys/malloc.h>
41 #include <sys/rman.h>
42 #include <sys/timeet.h>
43 #include <sys/timetc.h>
44 #include <sys/watchdog.h>
45 #include <machine/bus.h>
46 #include <machine/cpu.h>
47 #include <machine/intr.h>
48 #include <machine/machdep.h>
49
50 #include <arm/mv/mvreg.h>
51 #include <arm/mv/mvvar.h>
52
53 #include <dev/ofw/ofw_bus.h>
54 #include <dev/ofw/ofw_bus_subr.h>
55
56 #define INITIAL_TIMECOUNTER (0xffffffff)
57 #define MAX_WATCHDOG_TICKS (0xffffffff)
58
59 #define MV_TMR 0x1
60 #define MV_WDT 0x2
61 #define MV_NONE 0x0
62
63 #define MV_CLOCK_SRC_ARMV7 25000000 /* Timers' 25MHz mode */
64
65 #define WATCHDOG_TIMER_ARMV5 2
66
67 typedef void (*mv_watchdog_enable_t)(void);
68 typedef void (*mv_watchdog_disable_t)(void);
69
70 struct mv_timer_config {
71 enum soc_family soc_family;
72 mv_watchdog_enable_t watchdog_enable;
73 mv_watchdog_disable_t watchdog_disable;
74 unsigned int clock_src;
75 uint32_t bridge_irq_cause;
76 uint32_t irq_timer0_clr;
77 uint32_t irq_timer_wd_clr;
78 };
79
80 struct mv_timer_softc {
81 struct resource * timer_res[2];
82 bus_space_tag_t timer_bst;
83 bus_space_handle_t timer_bsh;
84 struct mtx timer_mtx;
85 struct eventtimer et;
86 boolean_t has_wdt;
87 struct mv_timer_config* config;
88 };
89
90 static struct resource_spec mv_timer_spec[] = {
91 { SYS_RES_MEMORY, 0, RF_ACTIVE },
92 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL },
93 { -1, 0 }
94 };
95
96 /* Interrupt is not required by MV_WDT devices */
97 static struct ofw_compat_data mv_timer_compat[] = {
98 {"marvell,armada-380-timer", MV_NONE },
99 {"marvell,armada-xp-timer", MV_TMR | MV_WDT },
100 {"mrvl,timer", MV_TMR | MV_WDT },
101 {NULL, MV_NONE }
102 };
103
104 static struct mv_timer_softc *timer_softc = NULL;
105 static int timers_initialized = 0;
106
107 static int mv_timer_probe(device_t);
108 static int mv_timer_attach(device_t);
109
110 static int mv_hardclock(void *);
111 static unsigned mv_timer_get_timecount(struct timecounter *);
112
113 static uint32_t mv_get_timer_control(void);
114 static void mv_set_timer_control(uint32_t);
115 static uint32_t mv_get_timer(uint32_t);
116 static void mv_set_timer(uint32_t, uint32_t);
117 static void mv_set_timer_rel(uint32_t, uint32_t);
118 static void mv_watchdog_event(void *, unsigned int, int *);
119 static int mv_timer_start(struct eventtimer *et,
120 sbintime_t first, sbintime_t period);
121 static int mv_timer_stop(struct eventtimer *et);
122 static void mv_setup_timers(void);
123
124 static void mv_watchdog_enable_armv5(void);
125 static void mv_watchdog_enable_armadaxp(void);
126 static void mv_watchdog_disable_armv5(void);
127 static void mv_watchdog_disable_armadaxp(void);
128
129 static void mv_delay(int usec, void* arg);
130
131 static struct mv_timer_config timer_armadaxp_config =
132 {
133 MV_SOC_ARMADA_XP,
134 &mv_watchdog_enable_armadaxp,
135 &mv_watchdog_disable_armadaxp,
136 MV_CLOCK_SRC_ARMV7,
137 BRIDGE_IRQ_CAUSE_ARMADAXP,
138 IRQ_TIMER0_CLR_ARMADAXP,
139 IRQ_TIMER_WD_CLR_ARMADAXP,
140 };
141 static struct mv_timer_config timer_armv5_config =
142 {
143 MV_SOC_ARMV5,
144 &mv_watchdog_enable_armv5,
145 &mv_watchdog_disable_armv5,
146 0,
147 BRIDGE_IRQ_CAUSE,
148 IRQ_TIMER0_CLR,
149 IRQ_TIMER_WD_CLR,
150 };
151
152 static struct ofw_compat_data mv_timer_soc_config[] = {
153 {"marvell,armada-xp-timer", (uintptr_t)&timer_armadaxp_config },
154 {"mrvl,timer", (uintptr_t)&timer_armv5_config },
155 {NULL, (uintptr_t)NULL },
156 };
157
158 static struct timecounter mv_timer_timecounter = {
159 .tc_get_timecount = mv_timer_get_timecount,
160 .tc_name = "CPUTimer1",
161 .tc_frequency = 0, /* This is assigned on the fly in the init sequence */
162 .tc_counter_mask = ~0u,
163 .tc_quality = 1000,
164 };
165
166 static int
mv_timer_probe(device_t dev)167 mv_timer_probe(device_t dev)
168 {
169
170 if (!ofw_bus_status_okay(dev))
171 return (ENXIO);
172
173 if (ofw_bus_search_compatible(dev, mv_timer_compat)->ocd_data == MV_NONE)
174 return (ENXIO);
175
176 device_set_desc(dev, "Marvell CPU Timer");
177 return (0);
178 }
179
180 static int
mv_timer_attach(device_t dev)181 mv_timer_attach(device_t dev)
182 {
183 int error;
184 void *ihl;
185 struct mv_timer_softc *sc;
186 uint32_t irq_cause, irq_mask;
187
188 if (timer_softc != NULL)
189 return (ENXIO);
190
191 sc = (struct mv_timer_softc *)device_get_softc(dev);
192 timer_softc = sc;
193
194 sc->config = (struct mv_timer_config*)
195 ofw_bus_search_compatible(dev, mv_timer_soc_config)->ocd_data;
196
197 if (sc->config->clock_src == 0)
198 sc->config->clock_src = get_tclk();
199
200 error = bus_alloc_resources(dev, mv_timer_spec, sc->timer_res);
201 if (error) {
202 device_printf(dev, "could not allocate resources\n");
203 return (ENXIO);
204 }
205
206 sc->timer_bst = rman_get_bustag(sc->timer_res[0]);
207 sc->timer_bsh = rman_get_bushandle(sc->timer_res[0]);
208
209 sc->has_wdt = ofw_bus_has_prop(dev, "mrvl,has-wdt");
210
211 mtx_init(&timer_softc->timer_mtx, "watchdog", NULL, MTX_DEF);
212
213 if (sc->has_wdt) {
214 if (sc->config->watchdog_disable)
215 sc->config->watchdog_disable();
216 EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0);
217 }
218
219 if (ofw_bus_search_compatible(dev, mv_timer_compat)->ocd_data
220 == MV_WDT) {
221 /* Don't set timers for wdt-only entry. */
222 device_printf(dev, "only watchdog attached\n");
223 return (0);
224 } else if (sc->timer_res[1] == NULL) {
225 device_printf(dev, "no interrupt resource\n");
226 bus_release_resources(dev, mv_timer_spec, sc->timer_res);
227 return (ENXIO);
228 }
229
230 if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK,
231 mv_hardclock, NULL, sc, &ihl) != 0) {
232 bus_release_resources(dev, mv_timer_spec, sc->timer_res);
233 device_printf(dev, "Could not setup interrupt.\n");
234 return (ENXIO);
235 }
236
237 mv_setup_timers();
238 if (sc->config->soc_family != MV_SOC_ARMADA_XP ) {
239 irq_cause = read_cpu_ctrl(sc->config->bridge_irq_cause);
240 irq_cause &= sc->config->irq_timer0_clr;
241
242 write_cpu_ctrl(sc->config->bridge_irq_cause, irq_cause);
243 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
244 irq_mask |= IRQ_TIMER0_MASK;
245 irq_mask &= ~IRQ_TIMER1_MASK;
246 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
247 }
248 sc->et.et_name = "CPUTimer0";
249 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
250 sc->et.et_quality = 1000;
251
252 sc->et.et_frequency = sc->config->clock_src;
253 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
254 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
255 sc->et.et_start = mv_timer_start;
256 sc->et.et_stop = mv_timer_stop;
257 sc->et.et_priv = sc;
258 et_register(&sc->et);
259 mv_timer_timecounter.tc_frequency = sc->config->clock_src;
260 tc_init(&mv_timer_timecounter);
261
262 #ifdef PLATFORM
263 arm_set_delay(mv_delay, NULL);
264 #endif
265 return (0);
266 }
267
268 static int
mv_hardclock(void * arg)269 mv_hardclock(void *arg)
270 {
271 struct mv_timer_softc *sc;
272 uint32_t irq_cause;
273
274 irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);
275 irq_cause &= timer_softc->config->irq_timer0_clr;
276 write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause);
277
278 sc = (struct mv_timer_softc *)arg;
279 if (sc->et.et_active)
280 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
281
282 return (FILTER_HANDLED);
283 }
284
285 static device_method_t mv_timer_methods[] = {
286 DEVMETHOD(device_probe, mv_timer_probe),
287 DEVMETHOD(device_attach, mv_timer_attach),
288 { 0, 0 }
289 };
290
291 static driver_t mv_timer_driver = {
292 "timer",
293 mv_timer_methods,
294 sizeof(struct mv_timer_softc),
295 };
296
297 DRIVER_MODULE(timer_mv, simplebus, mv_timer_driver, 0, 0);
298
299 static unsigned
mv_timer_get_timecount(struct timecounter * tc)300 mv_timer_get_timecount(struct timecounter *tc)
301 {
302
303 return (INITIAL_TIMECOUNTER - mv_get_timer(1));
304 }
305
306 static void
mv_delay(int usec,void * arg)307 mv_delay(int usec, void* arg)
308 {
309 uint32_t val, val_temp;
310 int32_t nticks;
311
312 val = mv_get_timer(1);
313 nticks = ((timer_softc->config->clock_src / 1000000 + 1) * usec);
314
315 while (nticks > 0) {
316 val_temp = mv_get_timer(1);
317 if (val > val_temp)
318 nticks -= (val - val_temp);
319 else
320 nticks -= (val + (INITIAL_TIMECOUNTER - val_temp));
321
322 val = val_temp;
323 }
324 }
325
326 #ifndef PLATFORM
327 void
DELAY(int usec)328 DELAY(int usec)
329 {
330 uint32_t val;
331
332 if (!timers_initialized) {
333 for (; usec > 0; usec--)
334 for (val = 100; val > 0; val--)
335 __asm __volatile("nop" ::: "memory");
336 } else {
337 TSENTER();
338 mv_delay(usec, NULL);
339 TSEXIT();
340 }
341 }
342 #endif
343
344 static uint32_t
mv_get_timer_control(void)345 mv_get_timer_control(void)
346 {
347
348 return (bus_space_read_4(timer_softc->timer_bst,
349 timer_softc->timer_bsh, CPU_TIMER_CONTROL));
350 }
351
352 static void
mv_set_timer_control(uint32_t val)353 mv_set_timer_control(uint32_t val)
354 {
355
356 bus_space_write_4(timer_softc->timer_bst,
357 timer_softc->timer_bsh, CPU_TIMER_CONTROL, val);
358 }
359
360 static uint32_t
mv_get_timer(uint32_t timer)361 mv_get_timer(uint32_t timer)
362 {
363
364 return (bus_space_read_4(timer_softc->timer_bst,
365 timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8));
366 }
367
368 static void
mv_set_timer(uint32_t timer,uint32_t val)369 mv_set_timer(uint32_t timer, uint32_t val)
370 {
371
372 bus_space_write_4(timer_softc->timer_bst,
373 timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8, val);
374 }
375
376 static void
mv_set_timer_rel(uint32_t timer,uint32_t val)377 mv_set_timer_rel(uint32_t timer, uint32_t val)
378 {
379
380 bus_space_write_4(timer_softc->timer_bst,
381 timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val);
382 }
383
384 static void
mv_watchdog_enable_armv5(void)385 mv_watchdog_enable_armv5(void)
386 {
387 uint32_t val, irq_cause, irq_mask;
388
389 irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);
390 irq_cause &= timer_softc->config->irq_timer_wd_clr;
391 write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause);
392
393 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
394 irq_mask |= IRQ_TIMER_WD_MASK;
395 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
396
397 val = read_cpu_ctrl(RSTOUTn_MASK);
398 val |= WD_RST_OUT_EN;
399 write_cpu_ctrl(RSTOUTn_MASK, val);
400
401 val = mv_get_timer_control();
402 val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO;
403 mv_set_timer_control(val);
404 }
405
406 static void
mv_watchdog_enable_armadaxp(void)407 mv_watchdog_enable_armadaxp(void)
408 {
409 uint32_t irq_cause, val;
410
411 irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);
412 irq_cause &= timer_softc->config->irq_timer_wd_clr;
413 write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause);
414
415 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
416 val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
417 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
418
419 val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
420 val &= ~RSTOUTn_MASK_WD;
421 write_cpu_misc(RSTOUTn_MASK_ARMV7, val);
422
423 val = mv_get_timer_control();
424 val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN;
425 mv_set_timer_control(val);
426 }
427
428 static void
mv_watchdog_disable_armv5(void)429 mv_watchdog_disable_armv5(void)
430 {
431 uint32_t val, irq_cause,irq_mask;
432
433 val = mv_get_timer_control();
434 val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);
435 mv_set_timer_control(val);
436
437 val = read_cpu_ctrl(RSTOUTn_MASK);
438 val &= ~WD_RST_OUT_EN;
439 write_cpu_ctrl(RSTOUTn_MASK, val);
440
441 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
442 irq_mask &= ~(IRQ_TIMER_WD_MASK);
443 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
444
445 irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);
446 irq_cause &= timer_softc->config->irq_timer_wd_clr;
447 write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause);
448 }
449
450 static void
mv_watchdog_disable_armadaxp(void)451 mv_watchdog_disable_armadaxp(void)
452 {
453 uint32_t val, irq_cause;
454
455 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
456 val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
457 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
458
459 val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
460 val |= RSTOUTn_MASK_WD;
461 write_cpu_misc(RSTOUTn_MASK_ARMV7, RSTOUTn_MASK_WD);
462
463 irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);
464 irq_cause &= timer_softc->config->irq_timer_wd_clr;
465 write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause);
466
467 val = mv_get_timer_control();
468 val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);
469 mv_set_timer_control(val);
470 }
471
472 /*
473 * Watchdog event handler.
474 */
475 static void
mv_watchdog_event(void * arg,unsigned int cmd,int * error)476 mv_watchdog_event(void *arg, unsigned int cmd, int *error)
477 {
478 uint64_t ns;
479 uint64_t ticks;
480
481 mtx_lock(&timer_softc->timer_mtx);
482 if (cmd == 0) {
483 if (timer_softc->config->watchdog_disable != NULL)
484 timer_softc->config->watchdog_disable();
485 } else {
486 /*
487 * Watchdog timeout is in nanosecs, calculation according to
488 * watchdog(9)
489 */
490 ns = (uint64_t)1 << (cmd & WD_INTERVAL);
491 ticks = (uint64_t)(ns * timer_softc->config->clock_src) / 1000000000;
492 if (ticks > MAX_WATCHDOG_TICKS) {
493 if (timer_softc->config->watchdog_disable != NULL)
494 timer_softc->config->watchdog_disable();
495 } else {
496 mv_set_timer(WATCHDOG_TIMER_ARMV5, ticks);
497 if (timer_softc->config->watchdog_enable != NULL)
498 timer_softc->config->watchdog_enable();
499 *error = 0;
500 }
501 }
502 mtx_unlock(&timer_softc->timer_mtx);
503 }
504
505 static int
mv_timer_start(struct eventtimer * et,sbintime_t first,sbintime_t period)506 mv_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
507 {
508 struct mv_timer_softc *sc;
509 uint32_t val, val1;
510
511 /* Calculate dividers. */
512 sc = (struct mv_timer_softc *)et->et_priv;
513 if (period != 0)
514 val = ((uint32_t)sc->et.et_frequency * period) >> 32;
515 else
516 val = 0;
517 if (first != 0)
518 val1 = ((uint32_t)sc->et.et_frequency * first) >> 32;
519 else
520 val1 = val;
521
522 /* Apply configuration. */
523 mv_set_timer_rel(0, val);
524 mv_set_timer(0, val1);
525 val = mv_get_timer_control();
526 val |= CPU_TIMER0_EN;
527 if (period != 0)
528 val |= CPU_TIMER0_AUTO;
529 else
530 val &= ~CPU_TIMER0_AUTO;
531 mv_set_timer_control(val);
532 return (0);
533 }
534
535 static int
mv_timer_stop(struct eventtimer * et)536 mv_timer_stop(struct eventtimer *et)
537 {
538 uint32_t val;
539
540 val = mv_get_timer_control();
541 val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
542 mv_set_timer_control(val);
543 return (0);
544 }
545
546 static void
mv_setup_timers(void)547 mv_setup_timers(void)
548 {
549 uint32_t val;
550
551 mv_set_timer_rel(1, INITIAL_TIMECOUNTER);
552 mv_set_timer(1, INITIAL_TIMECOUNTER);
553 val = mv_get_timer_control();
554 val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
555 val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO;
556
557 if (timer_softc->config->soc_family == MV_SOC_ARMADA_XP) {
558 /* Enable 25MHz mode */
559 val |= CPU_TIMER0_25MHZ_EN | CPU_TIMER1_25MHZ_EN;
560 }
561
562 mv_set_timer_control(val);
563 timers_initialized = 1;
564 }
565