1 /*-
2 * Copyright (c) 2012 Ganbold Tsagaankhuu <[email protected]>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/bus.h>
31 #include <sys/kernel.h>
32 #include <sys/module.h>
33 #include <sys/malloc.h>
34 #include <sys/rman.h>
35 #include <sys/timeet.h>
36 #include <sys/timetc.h>
37 #include <sys/watchdog.h>
38 #include <machine/bus.h>
39 #include <machine/intr.h>
40 #include <machine/machdep.h>
41
42 #include <dev/ofw/openfirm.h>
43 #include <dev/ofw/ofw_bus.h>
44 #include <dev/ofw/ofw_bus_subr.h>
45
46 #include <dev/extres/clk/clk.h>
47
48 #if defined(__aarch64__)
49 #include "opt_soc.h"
50 #else
51 #include <arm/allwinner/aw_machdep.h>
52 #endif
53
54 /**
55 * Timer registers addr
56 *
57 */
58 #define TIMER_IRQ_EN_REG 0x00
59 #define TIMER_IRQ_ENABLE(x) (1 << x)
60
61 #define TIMER_IRQ_STA_REG 0x04
62 #define TIMER_IRQ_PENDING(x) (1 << x)
63
64 /*
65 * On A10, A13, A20 and A31/A31s 6 timers are available
66 */
67 #define TIMER_CTRL_REG(x) (0x10 + 0x10 * x)
68 #define TIMER_CTRL_START (1 << 0)
69 #define TIMER_CTRL_AUTORELOAD (1 << 1)
70 #define TIMER_CTRL_CLKSRC_MASK (3 << 2)
71 #define TIMER_CTRL_OSC24M (1 << 2)
72 #define TIMER_CTRL_PRESCALAR_MASK (0x7 << 4)
73 #define TIMER_CTRL_PRESCALAR(x) ((x - 1) << 4)
74 #define TIMER_CTRL_MODE_MASK (1 << 7)
75 #define TIMER_CTRL_MODE_SINGLE (1 << 7)
76 #define TIMER_CTRL_MODE_CONTINUOUS (0 << 7)
77 #define TIMER_INTV_REG(x) (0x14 + 0x10 * x)
78 #define TIMER_CURV_REG(x) (0x18 + 0x10 * x)
79
80 /* 64 bit counter, available in A10 and A13 */
81 #define CNT64_CTRL_REG 0xa0
82 #define CNT64_CTRL_RL_EN 0x02 /* read latch enable */
83 #define CNT64_LO_REG 0xa4
84 #define CNT64_HI_REG 0xa8
85
86 #define SYS_TIMER_CLKSRC 24000000 /* clock source */
87
88 enum a10_timer_type {
89 A10_TIMER = 1,
90 A23_TIMER,
91 };
92
93 struct a10_timer_softc {
94 device_t sc_dev;
95 struct resource *res[2];
96 void *sc_ih; /* interrupt handler */
97 uint32_t sc_period;
98 uint64_t timer0_freq;
99 struct eventtimer et;
100 enum a10_timer_type type;
101 };
102
103 #define timer_read_4(sc, reg) \
104 bus_read_4(sc->res[A10_TIMER_MEMRES], reg)
105 #define timer_write_4(sc, reg, val) \
106 bus_write_4(sc->res[A10_TIMER_MEMRES], reg, val)
107
108 static u_int a10_timer_get_timecount(struct timecounter *);
109 #if defined(__arm__)
110 static int a10_timer_timer_start(struct eventtimer *,
111 sbintime_t first, sbintime_t period);
112 static int a10_timer_timer_stop(struct eventtimer *);
113 #endif
114
115 static uint64_t timer_read_counter64(struct a10_timer_softc *sc);
116 #if defined(__arm__)
117 static void a10_timer_eventtimer_setup(struct a10_timer_softc *sc);
118 #endif
119
120 #if defined(__aarch64__)
121 static void a23_timer_timecounter_setup(struct a10_timer_softc *sc);
122 static u_int a23_timer_get_timecount(struct timecounter *tc);
123 #endif
124
125 static int a10_timer_irq(void *);
126 static int a10_timer_probe(device_t);
127 static int a10_timer_attach(device_t);
128
129 #if defined(__arm__)
130 static delay_func a10_timer_delay;
131 #endif
132
133 static struct timecounter a10_timer_timecounter = {
134 .tc_name = "a10_timer timer0",
135 .tc_get_timecount = a10_timer_get_timecount,
136 .tc_counter_mask = ~0u,
137 .tc_frequency = 0,
138 .tc_quality = 1000,
139 };
140
141 #if defined(__aarch64__)
142 static struct timecounter a23_timer_timecounter = {
143 .tc_name = "a10_timer timer0",
144 .tc_get_timecount = a23_timer_get_timecount,
145 .tc_counter_mask = ~0u,
146 .tc_frequency = 0,
147 /* We want it to be selected over the arm generic timecounter */
148 .tc_quality = 2000,
149 };
150 #endif
151
152 #define A10_TIMER_MEMRES 0
153 #define A10_TIMER_IRQRES 1
154
155 static struct resource_spec a10_timer_spec[] = {
156 { SYS_RES_MEMORY, 0, RF_ACTIVE },
157 { SYS_RES_IRQ, 0, RF_ACTIVE },
158 { -1, 0 }
159 };
160
161 static struct ofw_compat_data compat_data[] = {
162 {"allwinner,sun4i-a10-timer", A10_TIMER},
163 #if defined(__aarch64__)
164 {"allwinner,sun8i-a23-timer", A23_TIMER},
165 #endif
166 {NULL, 0},
167 };
168
169 static int
a10_timer_probe(device_t dev)170 a10_timer_probe(device_t dev)
171 {
172 #if defined(__arm__)
173 u_int soc_family;
174 #endif
175
176 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
177 return (ENXIO);
178
179 #if defined(__arm__)
180 /* For SoC >= A10 we have the ARM Timecounter/Eventtimer */
181 soc_family = allwinner_soc_family();
182 if (soc_family != ALLWINNERSOC_SUN4I &&
183 soc_family != ALLWINNERSOC_SUN5I)
184 return (ENXIO);
185 #endif
186
187 device_set_desc(dev, "Allwinner timer");
188 return (BUS_PROBE_DEFAULT);
189 }
190
191 static int
a10_timer_attach(device_t dev)192 a10_timer_attach(device_t dev)
193 {
194 struct a10_timer_softc *sc;
195 clk_t clk;
196 int err;
197
198 sc = device_get_softc(dev);
199 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
200
201 if (bus_alloc_resources(dev, a10_timer_spec, sc->res)) {
202 device_printf(dev, "could not allocate resources\n");
203 return (ENXIO);
204 }
205
206 sc->sc_dev = dev;
207
208 /* Setup and enable the timer interrupt */
209 err = bus_setup_intr(dev, sc->res[A10_TIMER_IRQRES], INTR_TYPE_CLK,
210 a10_timer_irq, NULL, sc, &sc->sc_ih);
211 if (err != 0) {
212 bus_release_resources(dev, a10_timer_spec, sc->res);
213 device_printf(dev, "Unable to setup the clock irq handler, "
214 "err = %d\n", err);
215 return (ENXIO);
216 }
217
218 if (clk_get_by_ofw_index(dev, 0, 0, &clk) != 0)
219 sc->timer0_freq = SYS_TIMER_CLKSRC;
220 else {
221 if (clk_get_freq(clk, &sc->timer0_freq) != 0) {
222 device_printf(dev, "Cannot get clock source frequency\n");
223 return (ENXIO);
224 }
225 }
226
227 #if defined(__arm__)
228 a10_timer_eventtimer_setup(sc);
229 arm_set_delay(a10_timer_delay, sc);
230 a10_timer_timecounter.tc_priv = sc;
231 a10_timer_timecounter.tc_frequency = sc->timer0_freq;
232 tc_init(&a10_timer_timecounter);
233 #elif defined(__aarch64__)
234 a23_timer_timecounter_setup(sc);
235 #endif
236
237 if (bootverbose) {
238 device_printf(sc->sc_dev, "clock: hz=%d stathz = %d\n", hz, stathz);
239
240 device_printf(sc->sc_dev, "event timer clock frequency %ju\n",
241 sc->timer0_freq);
242 device_printf(sc->sc_dev, "timecounter clock frequency %jd\n",
243 a10_timer_timecounter.tc_frequency);
244 }
245
246 return (0);
247 }
248
249 static int
a10_timer_irq(void * arg)250 a10_timer_irq(void *arg)
251 {
252 struct a10_timer_softc *sc;
253 uint32_t val;
254
255 sc = (struct a10_timer_softc *)arg;
256
257 /* Clear interrupt pending bit. */
258 timer_write_4(sc, TIMER_IRQ_STA_REG, TIMER_IRQ_PENDING(0));
259
260 val = timer_read_4(sc, TIMER_CTRL_REG(0));
261
262 /*
263 * Disabled autoreload and sc_period > 0 means
264 * timer_start was called with non NULL first value.
265 * Now we will set periodic timer with the given period
266 * value.
267 */
268 if ((val & (1<<1)) == 0 && sc->sc_period > 0) {
269 /* Update timer */
270 timer_write_4(sc, TIMER_CURV_REG(0), sc->sc_period);
271
272 /* Make periodic and enable */
273 val |= TIMER_CTRL_AUTORELOAD | TIMER_CTRL_START;
274 timer_write_4(sc, TIMER_CTRL_REG(0), val);
275 }
276
277 if (sc->et.et_active)
278 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
279
280 return (FILTER_HANDLED);
281 }
282
283 /*
284 * Event timer function for A10 and A13
285 */
286
287 #if defined(__arm__)
288 static void
a10_timer_eventtimer_setup(struct a10_timer_softc * sc)289 a10_timer_eventtimer_setup(struct a10_timer_softc *sc)
290 {
291 uint32_t val;
292
293 /* Set clock source to OSC24M, 1 pre-division, continuous mode */
294 val = timer_read_4(sc, TIMER_CTRL_REG(0));
295 val &= ~TIMER_CTRL_PRESCALAR_MASK | ~TIMER_CTRL_MODE_MASK | ~TIMER_CTRL_CLKSRC_MASK;
296 val |= TIMER_CTRL_PRESCALAR(1) | TIMER_CTRL_OSC24M;
297 timer_write_4(sc, TIMER_CTRL_REG(0), val);
298
299 /* Enable timer0 */
300 val = timer_read_4(sc, TIMER_IRQ_EN_REG);
301 val |= TIMER_IRQ_ENABLE(0);
302 timer_write_4(sc, TIMER_IRQ_EN_REG, val);
303
304 /* Set desired frequency in event timer and timecounter */
305 sc->et.et_frequency = sc->timer0_freq;
306 sc->et.et_name = "a10_timer Eventtimer";
307 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC;
308 sc->et.et_quality = 1000;
309 sc->et.et_min_period = (0x00000005LLU << 32) / sc->et.et_frequency;
310 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
311 sc->et.et_start = a10_timer_timer_start;
312 sc->et.et_stop = a10_timer_timer_stop;
313 sc->et.et_priv = sc;
314 et_register(&sc->et);
315 }
316
317 static int
a10_timer_timer_start(struct eventtimer * et,sbintime_t first,sbintime_t period)318 a10_timer_timer_start(struct eventtimer *et, sbintime_t first,
319 sbintime_t period)
320 {
321 struct a10_timer_softc *sc;
322 uint32_t count;
323 uint32_t val;
324
325 sc = (struct a10_timer_softc *)et->et_priv;
326
327 if (period != 0)
328 sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32;
329 else
330 sc->sc_period = 0;
331 if (first != 0)
332 count = ((uint32_t)et->et_frequency * first) >> 32;
333 else
334 count = sc->sc_period;
335
336 /* Update timer values */
337 timer_write_4(sc, TIMER_INTV_REG(0), sc->sc_period);
338 timer_write_4(sc, TIMER_CURV_REG(0), count);
339
340 val = timer_read_4(sc, TIMER_CTRL_REG(0));
341 if (period != 0) {
342 /* periodic */
343 val |= TIMER_CTRL_AUTORELOAD;
344 } else {
345 /* oneshot */
346 val &= ~TIMER_CTRL_AUTORELOAD;
347 }
348 /* Enable timer0 */
349 val |= TIMER_IRQ_ENABLE(0);
350 timer_write_4(sc, TIMER_CTRL_REG(0), val);
351
352 return (0);
353 }
354
355 static int
a10_timer_timer_stop(struct eventtimer * et)356 a10_timer_timer_stop(struct eventtimer *et)
357 {
358 struct a10_timer_softc *sc;
359 uint32_t val;
360
361 sc = (struct a10_timer_softc *)et->et_priv;
362
363 /* Disable timer0 */
364 val = timer_read_4(sc, TIMER_CTRL_REG(0));
365 val &= ~TIMER_CTRL_START;
366 timer_write_4(sc, TIMER_CTRL_REG(0), val);
367
368 sc->sc_period = 0;
369
370 return (0);
371 }
372 #endif
373
374 /*
375 * Timecounter functions for A23 and above
376 */
377
378 #if defined(__aarch64__)
379 static void
a23_timer_timecounter_setup(struct a10_timer_softc * sc)380 a23_timer_timecounter_setup(struct a10_timer_softc *sc)
381 {
382 uint32_t val;
383
384 /* Set clock source to OSC24M, 1 pre-division, continuous mode */
385 val = timer_read_4(sc, TIMER_CTRL_REG(0));
386 val &= ~TIMER_CTRL_PRESCALAR_MASK | ~TIMER_CTRL_MODE_MASK | ~TIMER_CTRL_CLKSRC_MASK;
387 val |= TIMER_CTRL_PRESCALAR(1) | TIMER_CTRL_OSC24M;
388 timer_write_4(sc, TIMER_CTRL_REG(0), val);
389
390 /* Set reload value */
391 timer_write_4(sc, TIMER_INTV_REG(0), ~0);
392 val = timer_read_4(sc, TIMER_INTV_REG(0));
393
394 /* Enable timer0 */
395 val = timer_read_4(sc, TIMER_CTRL_REG(0));
396 val |= TIMER_CTRL_AUTORELOAD | TIMER_CTRL_START;
397 timer_write_4(sc, TIMER_CTRL_REG(0), val);
398
399 val = timer_read_4(sc, TIMER_CURV_REG(0));
400
401 a23_timer_timecounter.tc_priv = sc;
402 a23_timer_timecounter.tc_frequency = sc->timer0_freq;
403 tc_init(&a23_timer_timecounter);
404 }
405
406 static u_int
a23_timer_get_timecount(struct timecounter * tc)407 a23_timer_get_timecount(struct timecounter *tc)
408 {
409 struct a10_timer_softc *sc;
410 uint32_t val;
411
412 sc = (struct a10_timer_softc *)tc->tc_priv;
413 if (sc == NULL)
414 return (0);
415
416 val = timer_read_4(sc, TIMER_CURV_REG(0));
417 /* Counter count backwards */
418 return (~0u - val);
419 }
420 #endif
421
422 /*
423 * Timecounter functions for A10 and A13, using the 64 bits counter
424 */
425
426 static uint64_t
timer_read_counter64(struct a10_timer_softc * sc)427 timer_read_counter64(struct a10_timer_softc *sc)
428 {
429 uint32_t lo, hi;
430
431 /* Latch counter, wait for it to be ready to read. */
432 timer_write_4(sc, CNT64_CTRL_REG, CNT64_CTRL_RL_EN);
433 while (timer_read_4(sc, CNT64_CTRL_REG) & CNT64_CTRL_RL_EN)
434 continue;
435
436 hi = timer_read_4(sc, CNT64_HI_REG);
437 lo = timer_read_4(sc, CNT64_LO_REG);
438
439 return (((uint64_t)hi << 32) | lo);
440 }
441
442 #if defined(__arm__)
443 static void
a10_timer_delay(int usec,void * arg)444 a10_timer_delay(int usec, void *arg)
445 {
446 struct a10_timer_softc *sc = arg;
447 uint64_t end, now;
448
449 now = timer_read_counter64(sc);
450 end = now + (sc->timer0_freq / 1000000) * (usec + 1);
451
452 while (now < end)
453 now = timer_read_counter64(sc);
454 }
455 #endif
456
457 static u_int
a10_timer_get_timecount(struct timecounter * tc)458 a10_timer_get_timecount(struct timecounter *tc)
459 {
460
461 if (tc->tc_priv == NULL)
462 return (0);
463
464 return ((u_int)timer_read_counter64(tc->tc_priv));
465 }
466
467 static device_method_t a10_timer_methods[] = {
468 DEVMETHOD(device_probe, a10_timer_probe),
469 DEVMETHOD(device_attach, a10_timer_attach),
470
471 DEVMETHOD_END
472 };
473
474 static driver_t a10_timer_driver = {
475 "a10_timer",
476 a10_timer_methods,
477 sizeof(struct a10_timer_softc),
478 };
479
480 EARLY_DRIVER_MODULE(a10_timer, simplebus, a10_timer_driver, 0, 0,
481 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
482