1 //===-- AMDGPUPALMetadata.cpp - Accumulate and print AMDGPU PAL metadata -===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 ///
11 /// This class has methods called by AMDGPUAsmPrinter to accumulate and print
12 /// the PAL metadata.
13 //
14 //===----------------------------------------------------------------------===//
15 //
16
17 #include "AMDGPUPALMetadata.h"
18 #include "AMDGPUPTNote.h"
19 #include "SIDefines.h"
20 #include "llvm/BinaryFormat/ELF.h"
21 #include "llvm/IR/Constants.h"
22 #include "llvm/IR/Module.h"
23 #include "llvm/Support/AMDGPUMetadata.h"
24 #include "llvm/Support/EndianStream.h"
25
26 using namespace llvm;
27 using namespace llvm::AMDGPU;
28
29 // Read the PAL metadata from IR metadata, where it was put by the frontend.
readFromIR(Module & M)30 void AMDGPUPALMetadata::readFromIR(Module &M) {
31 auto NamedMD = M.getNamedMetadata("amdgpu.pal.metadata.msgpack");
32 if (NamedMD && NamedMD->getNumOperands()) {
33 // This is the new msgpack format for metadata. It is a NamedMD containing
34 // an MDTuple containing an MDString containing the msgpack data.
35 BlobType = ELF::NT_AMDGPU_METADATA;
36 auto MDN = dyn_cast<MDTuple>(NamedMD->getOperand(0));
37 if (MDN && MDN->getNumOperands()) {
38 if (auto MDS = dyn_cast<MDString>(MDN->getOperand(0)))
39 setFromMsgPackBlob(MDS->getString());
40 }
41 return;
42 }
43 BlobType = ELF::NT_AMD_PAL_METADATA;
44 NamedMD = M.getNamedMetadata("amdgpu.pal.metadata");
45 if (!NamedMD || !NamedMD->getNumOperands()) {
46 // Emit msgpack metadata by default
47 BlobType = ELF::NT_AMDGPU_METADATA;
48 return;
49 }
50 // This is the old reg=value pair format for metadata. It is a NamedMD
51 // containing an MDTuple containing a number of MDNodes each of which is an
52 // integer value, and each two integer values forms a key=value pair that we
53 // store as Registers[key]=value in the map.
54 auto Tuple = dyn_cast<MDTuple>(NamedMD->getOperand(0));
55 if (!Tuple)
56 return;
57 for (unsigned I = 0, E = Tuple->getNumOperands() & -2; I != E; I += 2) {
58 auto Key = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I));
59 auto Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I + 1));
60 if (!Key || !Val)
61 continue;
62 setRegister(Key->getZExtValue(), Val->getZExtValue());
63 }
64 }
65
66 // Set PAL metadata from a binary blob from the applicable .note record.
67 // Returns false if bad format. Blob must remain valid for the lifetime of the
68 // Metadata.
setFromBlob(unsigned Type,StringRef Blob)69 bool AMDGPUPALMetadata::setFromBlob(unsigned Type, StringRef Blob) {
70 BlobType = Type;
71 if (Type == ELF::NT_AMD_PAL_METADATA)
72 return setFromLegacyBlob(Blob);
73 return setFromMsgPackBlob(Blob);
74 }
75
76 // Set PAL metadata from legacy (array of key=value pairs) blob.
setFromLegacyBlob(StringRef Blob)77 bool AMDGPUPALMetadata::setFromLegacyBlob(StringRef Blob) {
78 auto Data = reinterpret_cast<const uint32_t *>(Blob.data());
79 for (unsigned I = 0; I != Blob.size() / sizeof(uint32_t) / 2; ++I)
80 setRegister(Data[I * 2], Data[I * 2 + 1]);
81 return true;
82 }
83
84 // Set PAL metadata from msgpack blob.
setFromMsgPackBlob(StringRef Blob)85 bool AMDGPUPALMetadata::setFromMsgPackBlob(StringRef Blob) {
86 return MsgPackDoc.readFromBlob(Blob, /*Multi=*/false);
87 }
88
89 // Given the calling convention, calculate the register number for rsrc1. In
90 // principle the register number could change in future hardware, but we know
91 // it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so
92 // we can use fixed values.
getRsrc1Reg(CallingConv::ID CC)93 static unsigned getRsrc1Reg(CallingConv::ID CC) {
94 switch (CC) {
95 default:
96 return PALMD::R_2E12_COMPUTE_PGM_RSRC1;
97 case CallingConv::AMDGPU_LS:
98 return PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS;
99 case CallingConv::AMDGPU_HS:
100 return PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS;
101 case CallingConv::AMDGPU_ES:
102 return PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES;
103 case CallingConv::AMDGPU_GS:
104 return PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS;
105 case CallingConv::AMDGPU_VS:
106 return PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS;
107 case CallingConv::AMDGPU_PS:
108 return PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS;
109 }
110 }
111
112 // Calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used
113 // with a constant offset to access any non-register shader-specific PAL
114 // metadata key.
getScratchSizeKey(CallingConv::ID CC)115 static unsigned getScratchSizeKey(CallingConv::ID CC) {
116 switch (CC) {
117 case CallingConv::AMDGPU_PS:
118 return PALMD::Key::PS_SCRATCH_SIZE;
119 case CallingConv::AMDGPU_VS:
120 return PALMD::Key::VS_SCRATCH_SIZE;
121 case CallingConv::AMDGPU_GS:
122 return PALMD::Key::GS_SCRATCH_SIZE;
123 case CallingConv::AMDGPU_ES:
124 return PALMD::Key::ES_SCRATCH_SIZE;
125 case CallingConv::AMDGPU_HS:
126 return PALMD::Key::HS_SCRATCH_SIZE;
127 case CallingConv::AMDGPU_LS:
128 return PALMD::Key::LS_SCRATCH_SIZE;
129 default:
130 return PALMD::Key::CS_SCRATCH_SIZE;
131 }
132 }
133
134 // Set the rsrc1 register in the metadata for a particular shader stage.
135 // In fact this ORs the value into any previous setting of the register.
setRsrc1(CallingConv::ID CC,unsigned Val)136 void AMDGPUPALMetadata::setRsrc1(CallingConv::ID CC, unsigned Val) {
137 setRegister(getRsrc1Reg(CC), Val);
138 }
139
140 // Set the rsrc2 register in the metadata for a particular shader stage.
141 // In fact this ORs the value into any previous setting of the register.
setRsrc2(CallingConv::ID CC,unsigned Val)142 void AMDGPUPALMetadata::setRsrc2(CallingConv::ID CC, unsigned Val) {
143 setRegister(getRsrc1Reg(CC) + 1, Val);
144 }
145
146 // Set the SPI_PS_INPUT_ENA register in the metadata.
147 // In fact this ORs the value into any previous setting of the register.
setSpiPsInputEna(unsigned Val)148 void AMDGPUPALMetadata::setSpiPsInputEna(unsigned Val) {
149 setRegister(PALMD::R_A1B3_SPI_PS_INPUT_ENA, Val);
150 }
151
152 // Set the SPI_PS_INPUT_ADDR register in the metadata.
153 // In fact this ORs the value into any previous setting of the register.
setSpiPsInputAddr(unsigned Val)154 void AMDGPUPALMetadata::setSpiPsInputAddr(unsigned Val) {
155 setRegister(PALMD::R_A1B4_SPI_PS_INPUT_ADDR, Val);
156 }
157
158 // Get a register from the metadata, or 0 if not currently set.
getRegister(unsigned Reg)159 unsigned AMDGPUPALMetadata::getRegister(unsigned Reg) {
160 auto Regs = getRegisters();
161 auto It = Regs.find(MsgPackDoc.getNode(Reg));
162 if (It == Regs.end())
163 return 0;
164 auto N = It->second;
165 if (N.getKind() != msgpack::Type::UInt)
166 return 0;
167 return N.getUInt();
168 }
169
170 // Set a register in the metadata.
171 // In fact this ORs the value into any previous setting of the register.
setRegister(unsigned Reg,unsigned Val)172 void AMDGPUPALMetadata::setRegister(unsigned Reg, unsigned Val) {
173 if (!isLegacy()) {
174 // In the new MsgPack format, ignore register numbered >= 0x10000000. It
175 // is a PAL ABI pseudo-register in the old non-MsgPack format.
176 if (Reg >= 0x10000000)
177 return;
178 }
179 auto &N = getRegisters()[MsgPackDoc.getNode(Reg)];
180 if (N.getKind() == msgpack::Type::UInt)
181 Val |= N.getUInt();
182 N = N.getDocument()->getNode(Val);
183 }
184
185 // Set the entry point name for one shader.
setEntryPoint(unsigned CC,StringRef Name)186 void AMDGPUPALMetadata::setEntryPoint(unsigned CC, StringRef Name) {
187 if (isLegacy())
188 return;
189 // Msgpack format.
190 getHwStage(CC)[".entry_point"] = MsgPackDoc.getNode(Name, /*Copy=*/true);
191 }
192
193 // Set the number of used vgprs in the metadata. This is an optional
194 // advisory record for logging etc; wave dispatch actually uses the rsrc1
195 // register for the shader stage to determine the number of vgprs to
196 // allocate.
setNumUsedVgprs(CallingConv::ID CC,unsigned Val)197 void AMDGPUPALMetadata::setNumUsedVgprs(CallingConv::ID CC, unsigned Val) {
198 if (isLegacy()) {
199 // Old non-msgpack format.
200 unsigned NumUsedVgprsKey = getScratchSizeKey(CC) +
201 PALMD::Key::VS_NUM_USED_VGPRS -
202 PALMD::Key::VS_SCRATCH_SIZE;
203 setRegister(NumUsedVgprsKey, Val);
204 return;
205 }
206 // Msgpack format.
207 getHwStage(CC)[".vgpr_count"] = MsgPackDoc.getNode(Val);
208 }
209
210 // Set the number of used agprs in the metadata.
setNumUsedAgprs(CallingConv::ID CC,unsigned Val)211 void AMDGPUPALMetadata::setNumUsedAgprs(CallingConv::ID CC, unsigned Val) {
212 getHwStage(CC)[".agpr_count"] = Val;
213 }
214
215 // Set the number of used sgprs in the metadata. This is an optional advisory
216 // record for logging etc; wave dispatch actually uses the rsrc1 register for
217 // the shader stage to determine the number of sgprs to allocate.
setNumUsedSgprs(CallingConv::ID CC,unsigned Val)218 void AMDGPUPALMetadata::setNumUsedSgprs(CallingConv::ID CC, unsigned Val) {
219 if (isLegacy()) {
220 // Old non-msgpack format.
221 unsigned NumUsedSgprsKey = getScratchSizeKey(CC) +
222 PALMD::Key::VS_NUM_USED_SGPRS -
223 PALMD::Key::VS_SCRATCH_SIZE;
224 setRegister(NumUsedSgprsKey, Val);
225 return;
226 }
227 // Msgpack format.
228 getHwStage(CC)[".sgpr_count"] = MsgPackDoc.getNode(Val);
229 }
230
231 // Set the scratch size in the metadata.
setScratchSize(CallingConv::ID CC,unsigned Val)232 void AMDGPUPALMetadata::setScratchSize(CallingConv::ID CC, unsigned Val) {
233 if (isLegacy()) {
234 // Old non-msgpack format.
235 setRegister(getScratchSizeKey(CC), Val);
236 return;
237 }
238 // Msgpack format.
239 getHwStage(CC)[".scratch_memory_size"] = MsgPackDoc.getNode(Val);
240 }
241
242 // Set the stack frame size of a function in the metadata.
setFunctionScratchSize(StringRef FnName,unsigned Val)243 void AMDGPUPALMetadata::setFunctionScratchSize(StringRef FnName, unsigned Val) {
244 auto Node = getShaderFunction(FnName);
245 Node[".stack_frame_size_in_bytes"] = MsgPackDoc.getNode(Val);
246 Node[".backend_stack_size"] = MsgPackDoc.getNode(Val);
247 }
248
249 // Set the amount of LDS used in bytes in the metadata.
setFunctionLdsSize(StringRef FnName,unsigned Val)250 void AMDGPUPALMetadata::setFunctionLdsSize(StringRef FnName, unsigned Val) {
251 auto Node = getShaderFunction(FnName);
252 Node[".lds_size"] = MsgPackDoc.getNode(Val);
253 }
254
255 // Set the number of used vgprs in the metadata.
setFunctionNumUsedVgprs(StringRef FnName,unsigned Val)256 void AMDGPUPALMetadata::setFunctionNumUsedVgprs(StringRef FnName,
257 unsigned Val) {
258 auto Node = getShaderFunction(FnName);
259 Node[".vgpr_count"] = MsgPackDoc.getNode(Val);
260 }
261
262 // Set the number of used vgprs in the metadata.
setFunctionNumUsedSgprs(StringRef FnName,unsigned Val)263 void AMDGPUPALMetadata::setFunctionNumUsedSgprs(StringRef FnName,
264 unsigned Val) {
265 auto Node = getShaderFunction(FnName);
266 Node[".sgpr_count"] = MsgPackDoc.getNode(Val);
267 }
268
269 // Set the hardware register bit in PAL metadata to enable wave32 on the
270 // shader of the given calling convention.
setWave32(unsigned CC)271 void AMDGPUPALMetadata::setWave32(unsigned CC) {
272 switch (CC) {
273 case CallingConv::AMDGPU_HS:
274 setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_HS_W32_EN(1));
275 break;
276 case CallingConv::AMDGPU_GS:
277 setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_GS_W32_EN(1));
278 break;
279 case CallingConv::AMDGPU_VS:
280 setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_VS_W32_EN(1));
281 break;
282 case CallingConv::AMDGPU_PS:
283 setRegister(PALMD::R_A1B6_SPI_PS_IN_CONTROL, S_0286D8_PS_W32_EN(1));
284 break;
285 case CallingConv::AMDGPU_CS:
286 setRegister(PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR,
287 S_00B800_CS_W32_EN(1));
288 break;
289 }
290 }
291
292 // Convert a register number to name, for display by toString().
293 // Returns nullptr if none.
getRegisterName(unsigned RegNum)294 static const char *getRegisterName(unsigned RegNum) {
295 // Table of registers.
296 static const struct RegInfo {
297 unsigned Num;
298 const char *Name;
299 } RegInfoTable[] = {
300 // Registers that code generation sets/modifies metadata for.
301 {PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS, "SPI_SHADER_PGM_RSRC1_VS"},
302 {PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS + 1, "SPI_SHADER_PGM_RSRC2_VS"},
303 {PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS, "SPI_SHADER_PGM_RSRC1_LS"},
304 {PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS + 1, "SPI_SHADER_PGM_RSRC2_LS"},
305 {PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS, "SPI_SHADER_PGM_RSRC1_HS"},
306 {PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS + 1, "SPI_SHADER_PGM_RSRC2_HS"},
307 {PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES, "SPI_SHADER_PGM_RSRC1_ES"},
308 {PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES + 1, "SPI_SHADER_PGM_RSRC2_ES"},
309 {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS, "SPI_SHADER_PGM_RSRC1_GS"},
310 {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS + 1, "SPI_SHADER_PGM_RSRC2_GS"},
311 {PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR, "COMPUTE_DISPATCH_INITIATOR"},
312 {PALMD::R_2E12_COMPUTE_PGM_RSRC1, "COMPUTE_PGM_RSRC1"},
313 {PALMD::R_2E12_COMPUTE_PGM_RSRC1 + 1, "COMPUTE_PGM_RSRC2"},
314 {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS, "SPI_SHADER_PGM_RSRC1_PS"},
315 {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS + 1, "SPI_SHADER_PGM_RSRC2_PS"},
316 {PALMD::R_A1B3_SPI_PS_INPUT_ENA, "SPI_PS_INPUT_ENA"},
317 {PALMD::R_A1B4_SPI_PS_INPUT_ADDR, "SPI_PS_INPUT_ADDR"},
318 {PALMD::R_A1B6_SPI_PS_IN_CONTROL, "SPI_PS_IN_CONTROL"},
319 {PALMD::R_A2D5_VGT_SHADER_STAGES_EN, "VGT_SHADER_STAGES_EN"},
320
321 // Registers not known to code generation.
322 {0x2c07, "SPI_SHADER_PGM_RSRC3_PS"},
323 {0x2c46, "SPI_SHADER_PGM_RSRC3_VS"},
324 {0x2c87, "SPI_SHADER_PGM_RSRC3_GS"},
325 {0x2cc7, "SPI_SHADER_PGM_RSRC3_ES"},
326 {0x2d07, "SPI_SHADER_PGM_RSRC3_HS"},
327 {0x2d47, "SPI_SHADER_PGM_RSRC3_LS"},
328
329 {0xa1c3, "SPI_SHADER_POS_FORMAT"},
330 {0xa1b1, "SPI_VS_OUT_CONFIG"},
331 {0xa207, "PA_CL_VS_OUT_CNTL"},
332 {0xa204, "PA_CL_CLIP_CNTL"},
333 {0xa206, "PA_CL_VTE_CNTL"},
334 {0xa2f9, "PA_SU_VTX_CNTL"},
335 {0xa293, "PA_SC_MODE_CNTL_1"},
336 {0xa2a1, "VGT_PRIMITIVEID_EN"},
337 {0x2c81, "SPI_SHADER_PGM_RSRC4_GS"},
338 {0x2e18, "COMPUTE_TMPRING_SIZE"},
339 {0xa1b5, "SPI_INTERP_CONTROL_0"},
340 {0xa1ba, "SPI_TMPRING_SIZE"},
341 {0xa1c4, "SPI_SHADER_Z_FORMAT"},
342 {0xa1c5, "SPI_SHADER_COL_FORMAT"},
343 {0xa203, "DB_SHADER_CONTROL"},
344 {0xa08f, "CB_SHADER_MASK"},
345 {0xa191, "SPI_PS_INPUT_CNTL_0"},
346 {0xa192, "SPI_PS_INPUT_CNTL_1"},
347 {0xa193, "SPI_PS_INPUT_CNTL_2"},
348 {0xa194, "SPI_PS_INPUT_CNTL_3"},
349 {0xa195, "SPI_PS_INPUT_CNTL_4"},
350 {0xa196, "SPI_PS_INPUT_CNTL_5"},
351 {0xa197, "SPI_PS_INPUT_CNTL_6"},
352 {0xa198, "SPI_PS_INPUT_CNTL_7"},
353 {0xa199, "SPI_PS_INPUT_CNTL_8"},
354 {0xa19a, "SPI_PS_INPUT_CNTL_9"},
355 {0xa19b, "SPI_PS_INPUT_CNTL_10"},
356 {0xa19c, "SPI_PS_INPUT_CNTL_11"},
357 {0xa19d, "SPI_PS_INPUT_CNTL_12"},
358 {0xa19e, "SPI_PS_INPUT_CNTL_13"},
359 {0xa19f, "SPI_PS_INPUT_CNTL_14"},
360 {0xa1a0, "SPI_PS_INPUT_CNTL_15"},
361 {0xa1a1, "SPI_PS_INPUT_CNTL_16"},
362 {0xa1a2, "SPI_PS_INPUT_CNTL_17"},
363 {0xa1a3, "SPI_PS_INPUT_CNTL_18"},
364 {0xa1a4, "SPI_PS_INPUT_CNTL_19"},
365 {0xa1a5, "SPI_PS_INPUT_CNTL_20"},
366 {0xa1a6, "SPI_PS_INPUT_CNTL_21"},
367 {0xa1a7, "SPI_PS_INPUT_CNTL_22"},
368 {0xa1a8, "SPI_PS_INPUT_CNTL_23"},
369 {0xa1a9, "SPI_PS_INPUT_CNTL_24"},
370 {0xa1aa, "SPI_PS_INPUT_CNTL_25"},
371 {0xa1ab, "SPI_PS_INPUT_CNTL_26"},
372 {0xa1ac, "SPI_PS_INPUT_CNTL_27"},
373 {0xa1ad, "SPI_PS_INPUT_CNTL_28"},
374 {0xa1ae, "SPI_PS_INPUT_CNTL_29"},
375 {0xa1af, "SPI_PS_INPUT_CNTL_30"},
376 {0xa1b0, "SPI_PS_INPUT_CNTL_31"},
377
378 {0xa2ce, "VGT_GS_MAX_VERT_OUT"},
379 {0xa2ab, "VGT_ESGS_RING_ITEMSIZE"},
380 {0xa290, "VGT_GS_MODE"},
381 {0xa291, "VGT_GS_ONCHIP_CNTL"},
382 {0xa2d7, "VGT_GS_VERT_ITEMSIZE"},
383 {0xa2d8, "VGT_GS_VERT_ITEMSIZE_1"},
384 {0xa2d9, "VGT_GS_VERT_ITEMSIZE_2"},
385 {0xa2da, "VGT_GS_VERT_ITEMSIZE_3"},
386 {0xa298, "VGT_GSVS_RING_OFFSET_1"},
387 {0xa299, "VGT_GSVS_RING_OFFSET_2"},
388 {0xa29a, "VGT_GSVS_RING_OFFSET_3"},
389
390 {0xa2e4, "VGT_GS_INSTANCE_CNT"},
391 {0xa297, "VGT_GS_PER_VS"},
392 {0xa29b, "VGT_GS_OUT_PRIM_TYPE"},
393 {0xa2ac, "VGT_GSVS_RING_ITEMSIZE"},
394
395 {0xa2ad, "VGT_REUSE_OFF"},
396 {0xa1b8, "SPI_BARYC_CNTL"},
397
398 {0x2c4c, "SPI_SHADER_USER_DATA_VS_0"},
399 {0x2c4d, "SPI_SHADER_USER_DATA_VS_1"},
400 {0x2c4e, "SPI_SHADER_USER_DATA_VS_2"},
401 {0x2c4f, "SPI_SHADER_USER_DATA_VS_3"},
402 {0x2c50, "SPI_SHADER_USER_DATA_VS_4"},
403 {0x2c51, "SPI_SHADER_USER_DATA_VS_5"},
404 {0x2c52, "SPI_SHADER_USER_DATA_VS_6"},
405 {0x2c53, "SPI_SHADER_USER_DATA_VS_7"},
406 {0x2c54, "SPI_SHADER_USER_DATA_VS_8"},
407 {0x2c55, "SPI_SHADER_USER_DATA_VS_9"},
408 {0x2c56, "SPI_SHADER_USER_DATA_VS_10"},
409 {0x2c57, "SPI_SHADER_USER_DATA_VS_11"},
410 {0x2c58, "SPI_SHADER_USER_DATA_VS_12"},
411 {0x2c59, "SPI_SHADER_USER_DATA_VS_13"},
412 {0x2c5a, "SPI_SHADER_USER_DATA_VS_14"},
413 {0x2c5b, "SPI_SHADER_USER_DATA_VS_15"},
414 {0x2c5c, "SPI_SHADER_USER_DATA_VS_16"},
415 {0x2c5d, "SPI_SHADER_USER_DATA_VS_17"},
416 {0x2c5e, "SPI_SHADER_USER_DATA_VS_18"},
417 {0x2c5f, "SPI_SHADER_USER_DATA_VS_19"},
418 {0x2c60, "SPI_SHADER_USER_DATA_VS_20"},
419 {0x2c61, "SPI_SHADER_USER_DATA_VS_21"},
420 {0x2c62, "SPI_SHADER_USER_DATA_VS_22"},
421 {0x2c63, "SPI_SHADER_USER_DATA_VS_23"},
422 {0x2c64, "SPI_SHADER_USER_DATA_VS_24"},
423 {0x2c65, "SPI_SHADER_USER_DATA_VS_25"},
424 {0x2c66, "SPI_SHADER_USER_DATA_VS_26"},
425 {0x2c67, "SPI_SHADER_USER_DATA_VS_27"},
426 {0x2c68, "SPI_SHADER_USER_DATA_VS_28"},
427 {0x2c69, "SPI_SHADER_USER_DATA_VS_29"},
428 {0x2c6a, "SPI_SHADER_USER_DATA_VS_30"},
429 {0x2c6b, "SPI_SHADER_USER_DATA_VS_31"},
430
431 {0x2c8c, "SPI_SHADER_USER_DATA_GS_0"},
432 {0x2c8d, "SPI_SHADER_USER_DATA_GS_1"},
433 {0x2c8e, "SPI_SHADER_USER_DATA_GS_2"},
434 {0x2c8f, "SPI_SHADER_USER_DATA_GS_3"},
435 {0x2c90, "SPI_SHADER_USER_DATA_GS_4"},
436 {0x2c91, "SPI_SHADER_USER_DATA_GS_5"},
437 {0x2c92, "SPI_SHADER_USER_DATA_GS_6"},
438 {0x2c93, "SPI_SHADER_USER_DATA_GS_7"},
439 {0x2c94, "SPI_SHADER_USER_DATA_GS_8"},
440 {0x2c95, "SPI_SHADER_USER_DATA_GS_9"},
441 {0x2c96, "SPI_SHADER_USER_DATA_GS_10"},
442 {0x2c97, "SPI_SHADER_USER_DATA_GS_11"},
443 {0x2c98, "SPI_SHADER_USER_DATA_GS_12"},
444 {0x2c99, "SPI_SHADER_USER_DATA_GS_13"},
445 {0x2c9a, "SPI_SHADER_USER_DATA_GS_14"},
446 {0x2c9b, "SPI_SHADER_USER_DATA_GS_15"},
447 {0x2c9c, "SPI_SHADER_USER_DATA_GS_16"},
448 {0x2c9d, "SPI_SHADER_USER_DATA_GS_17"},
449 {0x2c9e, "SPI_SHADER_USER_DATA_GS_18"},
450 {0x2c9f, "SPI_SHADER_USER_DATA_GS_19"},
451 {0x2ca0, "SPI_SHADER_USER_DATA_GS_20"},
452 {0x2ca1, "SPI_SHADER_USER_DATA_GS_21"},
453 {0x2ca2, "SPI_SHADER_USER_DATA_GS_22"},
454 {0x2ca3, "SPI_SHADER_USER_DATA_GS_23"},
455 {0x2ca4, "SPI_SHADER_USER_DATA_GS_24"},
456 {0x2ca5, "SPI_SHADER_USER_DATA_GS_25"},
457 {0x2ca6, "SPI_SHADER_USER_DATA_GS_26"},
458 {0x2ca7, "SPI_SHADER_USER_DATA_GS_27"},
459 {0x2ca8, "SPI_SHADER_USER_DATA_GS_28"},
460 {0x2ca9, "SPI_SHADER_USER_DATA_GS_29"},
461 {0x2caa, "SPI_SHADER_USER_DATA_GS_30"},
462 {0x2cab, "SPI_SHADER_USER_DATA_GS_31"},
463
464 {0x2ccc, "SPI_SHADER_USER_DATA_ES_0"},
465 {0x2ccd, "SPI_SHADER_USER_DATA_ES_1"},
466 {0x2cce, "SPI_SHADER_USER_DATA_ES_2"},
467 {0x2ccf, "SPI_SHADER_USER_DATA_ES_3"},
468 {0x2cd0, "SPI_SHADER_USER_DATA_ES_4"},
469 {0x2cd1, "SPI_SHADER_USER_DATA_ES_5"},
470 {0x2cd2, "SPI_SHADER_USER_DATA_ES_6"},
471 {0x2cd3, "SPI_SHADER_USER_DATA_ES_7"},
472 {0x2cd4, "SPI_SHADER_USER_DATA_ES_8"},
473 {0x2cd5, "SPI_SHADER_USER_DATA_ES_9"},
474 {0x2cd6, "SPI_SHADER_USER_DATA_ES_10"},
475 {0x2cd7, "SPI_SHADER_USER_DATA_ES_11"},
476 {0x2cd8, "SPI_SHADER_USER_DATA_ES_12"},
477 {0x2cd9, "SPI_SHADER_USER_DATA_ES_13"},
478 {0x2cda, "SPI_SHADER_USER_DATA_ES_14"},
479 {0x2cdb, "SPI_SHADER_USER_DATA_ES_15"},
480 {0x2cdc, "SPI_SHADER_USER_DATA_ES_16"},
481 {0x2cdd, "SPI_SHADER_USER_DATA_ES_17"},
482 {0x2cde, "SPI_SHADER_USER_DATA_ES_18"},
483 {0x2cdf, "SPI_SHADER_USER_DATA_ES_19"},
484 {0x2ce0, "SPI_SHADER_USER_DATA_ES_20"},
485 {0x2ce1, "SPI_SHADER_USER_DATA_ES_21"},
486 {0x2ce2, "SPI_SHADER_USER_DATA_ES_22"},
487 {0x2ce3, "SPI_SHADER_USER_DATA_ES_23"},
488 {0x2ce4, "SPI_SHADER_USER_DATA_ES_24"},
489 {0x2ce5, "SPI_SHADER_USER_DATA_ES_25"},
490 {0x2ce6, "SPI_SHADER_USER_DATA_ES_26"},
491 {0x2ce7, "SPI_SHADER_USER_DATA_ES_27"},
492 {0x2ce8, "SPI_SHADER_USER_DATA_ES_28"},
493 {0x2ce9, "SPI_SHADER_USER_DATA_ES_29"},
494 {0x2cea, "SPI_SHADER_USER_DATA_ES_30"},
495 {0x2ceb, "SPI_SHADER_USER_DATA_ES_31"},
496
497 {0x2c0c, "SPI_SHADER_USER_DATA_PS_0"},
498 {0x2c0d, "SPI_SHADER_USER_DATA_PS_1"},
499 {0x2c0e, "SPI_SHADER_USER_DATA_PS_2"},
500 {0x2c0f, "SPI_SHADER_USER_DATA_PS_3"},
501 {0x2c10, "SPI_SHADER_USER_DATA_PS_4"},
502 {0x2c11, "SPI_SHADER_USER_DATA_PS_5"},
503 {0x2c12, "SPI_SHADER_USER_DATA_PS_6"},
504 {0x2c13, "SPI_SHADER_USER_DATA_PS_7"},
505 {0x2c14, "SPI_SHADER_USER_DATA_PS_8"},
506 {0x2c15, "SPI_SHADER_USER_DATA_PS_9"},
507 {0x2c16, "SPI_SHADER_USER_DATA_PS_10"},
508 {0x2c17, "SPI_SHADER_USER_DATA_PS_11"},
509 {0x2c18, "SPI_SHADER_USER_DATA_PS_12"},
510 {0x2c19, "SPI_SHADER_USER_DATA_PS_13"},
511 {0x2c1a, "SPI_SHADER_USER_DATA_PS_14"},
512 {0x2c1b, "SPI_SHADER_USER_DATA_PS_15"},
513 {0x2c1c, "SPI_SHADER_USER_DATA_PS_16"},
514 {0x2c1d, "SPI_SHADER_USER_DATA_PS_17"},
515 {0x2c1e, "SPI_SHADER_USER_DATA_PS_18"},
516 {0x2c1f, "SPI_SHADER_USER_DATA_PS_19"},
517 {0x2c20, "SPI_SHADER_USER_DATA_PS_20"},
518 {0x2c21, "SPI_SHADER_USER_DATA_PS_21"},
519 {0x2c22, "SPI_SHADER_USER_DATA_PS_22"},
520 {0x2c23, "SPI_SHADER_USER_DATA_PS_23"},
521 {0x2c24, "SPI_SHADER_USER_DATA_PS_24"},
522 {0x2c25, "SPI_SHADER_USER_DATA_PS_25"},
523 {0x2c26, "SPI_SHADER_USER_DATA_PS_26"},
524 {0x2c27, "SPI_SHADER_USER_DATA_PS_27"},
525 {0x2c28, "SPI_SHADER_USER_DATA_PS_28"},
526 {0x2c29, "SPI_SHADER_USER_DATA_PS_29"},
527 {0x2c2a, "SPI_SHADER_USER_DATA_PS_30"},
528 {0x2c2b, "SPI_SHADER_USER_DATA_PS_31"},
529
530 {0x2e40, "COMPUTE_USER_DATA_0"},
531 {0x2e41, "COMPUTE_USER_DATA_1"},
532 {0x2e42, "COMPUTE_USER_DATA_2"},
533 {0x2e43, "COMPUTE_USER_DATA_3"},
534 {0x2e44, "COMPUTE_USER_DATA_4"},
535 {0x2e45, "COMPUTE_USER_DATA_5"},
536 {0x2e46, "COMPUTE_USER_DATA_6"},
537 {0x2e47, "COMPUTE_USER_DATA_7"},
538 {0x2e48, "COMPUTE_USER_DATA_8"},
539 {0x2e49, "COMPUTE_USER_DATA_9"},
540 {0x2e4a, "COMPUTE_USER_DATA_10"},
541 {0x2e4b, "COMPUTE_USER_DATA_11"},
542 {0x2e4c, "COMPUTE_USER_DATA_12"},
543 {0x2e4d, "COMPUTE_USER_DATA_13"},
544 {0x2e4e, "COMPUTE_USER_DATA_14"},
545 {0x2e4f, "COMPUTE_USER_DATA_15"},
546
547 {0x2e07, "COMPUTE_NUM_THREAD_X"},
548 {0x2e08, "COMPUTE_NUM_THREAD_Y"},
549 {0x2e09, "COMPUTE_NUM_THREAD_Z"},
550 {0xa2db, "VGT_TF_PARAM"},
551 {0xa2d6, "VGT_LS_HS_CONFIG"},
552 {0xa287, "VGT_HOS_MIN_TESS_LEVEL"},
553 {0xa286, "VGT_HOS_MAX_TESS_LEVEL"},
554 {0xa2f8, "PA_SC_AA_CONFIG"},
555 {0xa310, "PA_SC_SHADER_CONTROL"},
556 {0xa313, "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"},
557
558 {0x2d0c, "SPI_SHADER_USER_DATA_HS_0"},
559 {0x2d0d, "SPI_SHADER_USER_DATA_HS_1"},
560 {0x2d0e, "SPI_SHADER_USER_DATA_HS_2"},
561 {0x2d0f, "SPI_SHADER_USER_DATA_HS_3"},
562 {0x2d10, "SPI_SHADER_USER_DATA_HS_4"},
563 {0x2d11, "SPI_SHADER_USER_DATA_HS_5"},
564 {0x2d12, "SPI_SHADER_USER_DATA_HS_6"},
565 {0x2d13, "SPI_SHADER_USER_DATA_HS_7"},
566 {0x2d14, "SPI_SHADER_USER_DATA_HS_8"},
567 {0x2d15, "SPI_SHADER_USER_DATA_HS_9"},
568 {0x2d16, "SPI_SHADER_USER_DATA_HS_10"},
569 {0x2d17, "SPI_SHADER_USER_DATA_HS_11"},
570 {0x2d18, "SPI_SHADER_USER_DATA_HS_12"},
571 {0x2d19, "SPI_SHADER_USER_DATA_HS_13"},
572 {0x2d1a, "SPI_SHADER_USER_DATA_HS_14"},
573 {0x2d1b, "SPI_SHADER_USER_DATA_HS_15"},
574 {0x2d1c, "SPI_SHADER_USER_DATA_HS_16"},
575 {0x2d1d, "SPI_SHADER_USER_DATA_HS_17"},
576 {0x2d1e, "SPI_SHADER_USER_DATA_HS_18"},
577 {0x2d1f, "SPI_SHADER_USER_DATA_HS_19"},
578 {0x2d20, "SPI_SHADER_USER_DATA_HS_20"},
579 {0x2d21, "SPI_SHADER_USER_DATA_HS_21"},
580 {0x2d22, "SPI_SHADER_USER_DATA_HS_22"},
581 {0x2d23, "SPI_SHADER_USER_DATA_HS_23"},
582 {0x2d24, "SPI_SHADER_USER_DATA_HS_24"},
583 {0x2d25, "SPI_SHADER_USER_DATA_HS_25"},
584 {0x2d26, "SPI_SHADER_USER_DATA_HS_26"},
585 {0x2d27, "SPI_SHADER_USER_DATA_HS_27"},
586 {0x2d28, "SPI_SHADER_USER_DATA_HS_28"},
587 {0x2d29, "SPI_SHADER_USER_DATA_HS_29"},
588 {0x2d2a, "SPI_SHADER_USER_DATA_HS_30"},
589 {0x2d2b, "SPI_SHADER_USER_DATA_HS_31"},
590
591 {0x2d4c, "SPI_SHADER_USER_DATA_LS_0"},
592 {0x2d4d, "SPI_SHADER_USER_DATA_LS_1"},
593 {0x2d4e, "SPI_SHADER_USER_DATA_LS_2"},
594 {0x2d4f, "SPI_SHADER_USER_DATA_LS_3"},
595 {0x2d50, "SPI_SHADER_USER_DATA_LS_4"},
596 {0x2d51, "SPI_SHADER_USER_DATA_LS_5"},
597 {0x2d52, "SPI_SHADER_USER_DATA_LS_6"},
598 {0x2d53, "SPI_SHADER_USER_DATA_LS_7"},
599 {0x2d54, "SPI_SHADER_USER_DATA_LS_8"},
600 {0x2d55, "SPI_SHADER_USER_DATA_LS_9"},
601 {0x2d56, "SPI_SHADER_USER_DATA_LS_10"},
602 {0x2d57, "SPI_SHADER_USER_DATA_LS_11"},
603 {0x2d58, "SPI_SHADER_USER_DATA_LS_12"},
604 {0x2d59, "SPI_SHADER_USER_DATA_LS_13"},
605 {0x2d5a, "SPI_SHADER_USER_DATA_LS_14"},
606 {0x2d5b, "SPI_SHADER_USER_DATA_LS_15"},
607
608 {0xa2aa, "IA_MULTI_VGT_PARAM"},
609 {0xa2a5, "VGT_GS_MAX_PRIMS_PER_SUBGROUP"},
610 {0xa2e6, "VGT_STRMOUT_BUFFER_CONFIG"},
611 {0xa2e5, "VGT_STRMOUT_CONFIG"},
612 {0xa2b5, "VGT_STRMOUT_VTX_STRIDE_0"},
613 {0xa2b9, "VGT_STRMOUT_VTX_STRIDE_1"},
614 {0xa2bd, "VGT_STRMOUT_VTX_STRIDE_2"},
615 {0xa2c1, "VGT_STRMOUT_VTX_STRIDE_3"},
616 {0xa316, "VGT_VERTEX_REUSE_BLOCK_CNTL"},
617
618 {0x2e28, "COMPUTE_PGM_RSRC3"},
619 {0x2e2a, "COMPUTE_SHADER_CHKSUM"},
620 {0x2e24, "COMPUTE_USER_ACCUM_0"},
621 {0x2e25, "COMPUTE_USER_ACCUM_1"},
622 {0x2e26, "COMPUTE_USER_ACCUM_2"},
623 {0x2e27, "COMPUTE_USER_ACCUM_3"},
624 {0xa1ff, "GE_MAX_OUTPUT_PER_SUBGROUP"},
625 {0xa2d3, "GE_NGG_SUBGRP_CNTL"},
626 {0xc25f, "GE_STEREO_CNTL"},
627 {0xc262, "GE_USER_VGPR_EN"},
628 {0xc258, "IA_MULTI_VGT_PARAM_PIPED"},
629 {0xa210, "PA_STEREO_CNTL"},
630 {0xa1c2, "SPI_SHADER_IDX_FORMAT"},
631 {0x2c80, "SPI_SHADER_PGM_CHKSUM_GS"},
632 {0x2d00, "SPI_SHADER_PGM_CHKSUM_HS"},
633 {0x2c06, "SPI_SHADER_PGM_CHKSUM_PS"},
634 {0x2c45, "SPI_SHADER_PGM_CHKSUM_VS"},
635 {0x2c88, "SPI_SHADER_PGM_LO_GS"},
636 {0x2cb2, "SPI_SHADER_USER_ACCUM_ESGS_0"},
637 {0x2cb3, "SPI_SHADER_USER_ACCUM_ESGS_1"},
638 {0x2cb4, "SPI_SHADER_USER_ACCUM_ESGS_2"},
639 {0x2cb5, "SPI_SHADER_USER_ACCUM_ESGS_3"},
640 {0x2d32, "SPI_SHADER_USER_ACCUM_LSHS_0"},
641 {0x2d33, "SPI_SHADER_USER_ACCUM_LSHS_1"},
642 {0x2d34, "SPI_SHADER_USER_ACCUM_LSHS_2"},
643 {0x2d35, "SPI_SHADER_USER_ACCUM_LSHS_3"},
644 {0x2c32, "SPI_SHADER_USER_ACCUM_PS_0"},
645 {0x2c33, "SPI_SHADER_USER_ACCUM_PS_1"},
646 {0x2c34, "SPI_SHADER_USER_ACCUM_PS_2"},
647 {0x2c35, "SPI_SHADER_USER_ACCUM_PS_3"},
648 {0x2c72, "SPI_SHADER_USER_ACCUM_VS_0"},
649 {0x2c73, "SPI_SHADER_USER_ACCUM_VS_1"},
650 {0x2c74, "SPI_SHADER_USER_ACCUM_VS_2"},
651 {0x2c75, "SPI_SHADER_USER_ACCUM_VS_3"},
652
653 {0, nullptr}};
654 auto Entry = RegInfoTable;
655 for (; Entry->Num && Entry->Num != RegNum; ++Entry)
656 ;
657 return Entry->Name;
658 }
659
660 // Convert the accumulated PAL metadata into an asm directive.
toString(std::string & String)661 void AMDGPUPALMetadata::toString(std::string &String) {
662 String.clear();
663 if (!BlobType)
664 return;
665 raw_string_ostream Stream(String);
666 if (isLegacy()) {
667 if (MsgPackDoc.getRoot().getKind() == msgpack::Type::Nil)
668 return;
669 // Old linear reg=val format.
670 Stream << '\t' << AMDGPU::PALMD::AssemblerDirective << ' ';
671 auto Regs = getRegisters();
672 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) {
673 if (I != Regs.begin())
674 Stream << ',';
675 unsigned Reg = I->first.getUInt();
676 unsigned Val = I->second.getUInt();
677 Stream << "0x" << Twine::utohexstr(Reg) << ",0x" << Twine::utohexstr(Val);
678 }
679 Stream << '\n';
680 return;
681 }
682
683 // New msgpack-based format -- output as YAML (with unsigned numbers in hex),
684 // but first change the registers map to use names.
685 MsgPackDoc.setHexMode();
686 auto &RegsObj = refRegisters();
687 auto OrigRegs = RegsObj.getMap();
688 RegsObj = MsgPackDoc.getMapNode();
689 for (auto I : OrigRegs) {
690 auto Key = I.first;
691 if (const char *RegName = getRegisterName(Key.getUInt())) {
692 std::string KeyName = Key.toString();
693 KeyName += " (";
694 KeyName += RegName;
695 KeyName += ')';
696 Key = MsgPackDoc.getNode(KeyName, /*Copy=*/true);
697 }
698 RegsObj.getMap()[Key] = I.second;
699 }
700
701 // Output as YAML.
702 Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveBegin << '\n';
703 MsgPackDoc.toYAML(Stream);
704 Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveEnd << '\n';
705
706 // Restore original registers map.
707 RegsObj = OrigRegs;
708 }
709
710 // Convert the accumulated PAL metadata into a binary blob for writing as
711 // a .note record of the specified AMD type. Returns an empty blob if
712 // there is no PAL metadata,
toBlob(unsigned Type,std::string & Blob)713 void AMDGPUPALMetadata::toBlob(unsigned Type, std::string &Blob) {
714 if (Type == ELF::NT_AMD_PAL_METADATA)
715 toLegacyBlob(Blob);
716 else if (Type)
717 toMsgPackBlob(Blob);
718 }
719
toLegacyBlob(std::string & Blob)720 void AMDGPUPALMetadata::toLegacyBlob(std::string &Blob) {
721 Blob.clear();
722 auto Registers = getRegisters();
723 if (Registers.getMap().empty())
724 return;
725 raw_string_ostream OS(Blob);
726 support::endian::Writer EW(OS, llvm::endianness::little);
727 for (auto I : Registers.getMap()) {
728 EW.write(uint32_t(I.first.getUInt()));
729 EW.write(uint32_t(I.second.getUInt()));
730 }
731 }
732
toMsgPackBlob(std::string & Blob)733 void AMDGPUPALMetadata::toMsgPackBlob(std::string &Blob) {
734 Blob.clear();
735 MsgPackDoc.writeToBlob(Blob);
736 }
737
738 // Set PAL metadata from YAML text. Returns false if failed.
setFromString(StringRef S)739 bool AMDGPUPALMetadata::setFromString(StringRef S) {
740 BlobType = ELF::NT_AMDGPU_METADATA;
741 if (!MsgPackDoc.fromYAML(S))
742 return false;
743
744 // In the registers map, some keys may be of the form "0xa191
745 // (SPI_PS_INPUT_CNTL_0)", in which case the YAML input code made it a
746 // string. We need to turn it into a number.
747 auto &RegsObj = refRegisters();
748 auto OrigRegs = RegsObj;
749 RegsObj = MsgPackDoc.getMapNode();
750 Registers = RegsObj.getMap();
751 bool Ok = true;
752 for (auto I : OrigRegs.getMap()) {
753 auto Key = I.first;
754 if (Key.getKind() == msgpack::Type::String) {
755 StringRef S = Key.getString();
756 uint64_t Val;
757 if (S.consumeInteger(0, Val)) {
758 Ok = false;
759 errs() << "Unrecognized PAL metadata register key '" << S << "'\n";
760 continue;
761 }
762 Key = MsgPackDoc.getNode(uint64_t(Val));
763 }
764 Registers.getMap()[Key] = I.second;
765 }
766 return Ok;
767 }
768
769 // Reference (create if necessary) the node for the registers map.
refRegisters()770 msgpack::DocNode &AMDGPUPALMetadata::refRegisters() {
771 auto &N =
772 MsgPackDoc.getRoot()
773 .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")]
774 .getArray(/*Convert=*/true)[0]
775 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".registers")];
776 N.getMap(/*Convert=*/true);
777 return N;
778 }
779
780 // Get (create if necessary) the registers map.
getRegisters()781 msgpack::MapDocNode AMDGPUPALMetadata::getRegisters() {
782 if (Registers.isEmpty())
783 Registers = refRegisters();
784 return Registers.getMap();
785 }
786
787 // Reference (create if necessary) the node for the shader functions map.
refShaderFunctions()788 msgpack::DocNode &AMDGPUPALMetadata::refShaderFunctions() {
789 auto &N =
790 MsgPackDoc.getRoot()
791 .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")]
792 .getArray(/*Convert=*/true)[0]
793 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".shader_functions")];
794 N.getMap(/*Convert=*/true);
795 return N;
796 }
797
798 // Get (create if necessary) the shader functions map.
getShaderFunctions()799 msgpack::MapDocNode AMDGPUPALMetadata::getShaderFunctions() {
800 if (ShaderFunctions.isEmpty())
801 ShaderFunctions = refShaderFunctions();
802 return ShaderFunctions.getMap();
803 }
804
805 // Get (create if necessary) a function in the shader functions map.
getShaderFunction(StringRef Name)806 msgpack::MapDocNode AMDGPUPALMetadata::getShaderFunction(StringRef Name) {
807 auto Functions = getShaderFunctions();
808 return Functions[Name].getMap(/*Convert=*/true);
809 }
810
refComputeRegisters()811 msgpack::DocNode &AMDGPUPALMetadata::refComputeRegisters() {
812 auto &N =
813 MsgPackDoc.getRoot()
814 .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")]
815 .getArray(/*Convert=*/true)[0]
816 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".compute_registers")];
817 N.getMap(/*Convert=*/true);
818 return N;
819 }
820
getComputeRegisters()821 msgpack::MapDocNode AMDGPUPALMetadata::getComputeRegisters() {
822 if (ComputeRegisters.isEmpty())
823 ComputeRegisters = refComputeRegisters();
824 return ComputeRegisters.getMap();
825 }
826
refGraphicsRegisters()827 msgpack::DocNode &AMDGPUPALMetadata::refGraphicsRegisters() {
828 auto &N =
829 MsgPackDoc.getRoot()
830 .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")]
831 .getArray(/*Convert=*/true)[0]
832 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".graphics_registers")];
833 N.getMap(/*Convert=*/true);
834 return N;
835 }
836
getGraphicsRegisters()837 msgpack::MapDocNode AMDGPUPALMetadata::getGraphicsRegisters() {
838 if (GraphicsRegisters.isEmpty())
839 GraphicsRegisters = refGraphicsRegisters();
840 return GraphicsRegisters.getMap();
841 }
842
843 // Return the PAL metadata hardware shader stage name.
getStageName(CallingConv::ID CC)844 static const char *getStageName(CallingConv::ID CC) {
845 switch (CC) {
846 case CallingConv::AMDGPU_PS:
847 return ".ps";
848 case CallingConv::AMDGPU_VS:
849 return ".vs";
850 case CallingConv::AMDGPU_GS:
851 return ".gs";
852 case CallingConv::AMDGPU_ES:
853 return ".es";
854 case CallingConv::AMDGPU_HS:
855 return ".hs";
856 case CallingConv::AMDGPU_LS:
857 return ".ls";
858 case CallingConv::AMDGPU_Gfx:
859 llvm_unreachable("Callable shader has no hardware stage");
860 default:
861 return ".cs";
862 }
863 }
864
refHwStage()865 msgpack::DocNode &AMDGPUPALMetadata::refHwStage() {
866 auto &N =
867 MsgPackDoc.getRoot()
868 .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")]
869 .getArray(/*Convert=*/true)[0]
870 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".hardware_stages")];
871 N.getMap(/*Convert=*/true);
872 return N;
873 }
874
875 // Get (create if necessary) the .hardware_stages entry for the given calling
876 // convention.
getHwStage(unsigned CC)877 msgpack::MapDocNode AMDGPUPALMetadata::getHwStage(unsigned CC) {
878 if (HwStages.isEmpty())
879 HwStages = refHwStage();
880 return HwStages.getMap()[getStageName(CC)].getMap(/*Convert=*/true);
881 }
882
883 // Get .note record vendor name of metadata blob to be emitted.
getVendor() const884 const char *AMDGPUPALMetadata::getVendor() const {
885 return isLegacy() ? ElfNote::NoteNameV2 : ElfNote::NoteNameV3;
886 }
887
888 // Get .note record type of metadata blob to be emitted:
889 // ELF::NT_AMD_PAL_METADATA (legacy key=val format), or
890 // ELF::NT_AMDGPU_METADATA (MsgPack format), or
891 // 0 (no PAL metadata).
getType() const892 unsigned AMDGPUPALMetadata::getType() const {
893 return BlobType;
894 }
895
896 // Return whether the blob type is legacy PAL metadata.
isLegacy() const897 bool AMDGPUPALMetadata::isLegacy() const {
898 return BlobType == ELF::NT_AMD_PAL_METADATA;
899 }
900
901 // Set legacy PAL metadata format.
setLegacy()902 void AMDGPUPALMetadata::setLegacy() {
903 BlobType = ELF::NT_AMD_PAL_METADATA;
904 }
905
906 // Erase all PAL metadata.
reset()907 void AMDGPUPALMetadata::reset() {
908 MsgPackDoc.clear();
909 Registers = MsgPackDoc.getEmptyNode();
910 HwStages = MsgPackDoc.getEmptyNode();
911 ShaderFunctions = MsgPackDoc.getEmptyNode();
912 }
913
getPALVersion(unsigned idx)914 unsigned AMDGPUPALMetadata::getPALVersion(unsigned idx) {
915 assert(idx < 2 &&
916 "illegal index to PAL version - should be 0 (major) or 1 (minor)");
917 if (!VersionChecked) {
918 if (Version.isEmpty()) {
919 auto &M = MsgPackDoc.getRoot().getMap(/*Convert=*/true);
920 auto I = M.find(MsgPackDoc.getNode("amdpal.version"));
921 if (I != M.end())
922 Version = I->second;
923 }
924 VersionChecked = true;
925 }
926 if (Version.isEmpty())
927 // Default to 2.6 if there's no version info
928 return idx ? 6 : 2;
929 return Version.getArray()[idx].getUInt();
930 }
931
getPALMajorVersion()932 unsigned AMDGPUPALMetadata::getPALMajorVersion() { return getPALVersion(0); }
933
getPALMinorVersion()934 unsigned AMDGPUPALMetadata::getPALMinorVersion() { return getPALVersion(1); }
935
936 // Set the field in a given .hardware_stages entry
setHwStage(unsigned CC,StringRef field,unsigned Val)937 void AMDGPUPALMetadata::setHwStage(unsigned CC, StringRef field, unsigned Val) {
938 getHwStage(CC)[field] = Val;
939 }
940
setHwStage(unsigned CC,StringRef field,bool Val)941 void AMDGPUPALMetadata::setHwStage(unsigned CC, StringRef field, bool Val) {
942 getHwStage(CC)[field] = Val;
943 }
944
setComputeRegisters(StringRef field,unsigned Val)945 void AMDGPUPALMetadata::setComputeRegisters(StringRef field, unsigned Val) {
946 getComputeRegisters()[field] = Val;
947 }
948
setComputeRegisters(StringRef field,bool Val)949 void AMDGPUPALMetadata::setComputeRegisters(StringRef field, bool Val) {
950 getComputeRegisters()[field] = Val;
951 }
952
refComputeRegister(StringRef field)953 msgpack::DocNode *AMDGPUPALMetadata::refComputeRegister(StringRef field) {
954 auto M = getComputeRegisters();
955 auto I = M.find(field);
956 return I == M.end() ? nullptr : &I->second;
957 }
958
checkComputeRegisters(StringRef field,unsigned Val)959 bool AMDGPUPALMetadata::checkComputeRegisters(StringRef field, unsigned Val) {
960 if (auto N = refComputeRegister(field))
961 return N->getUInt() == Val;
962 return false;
963 }
964
checkComputeRegisters(StringRef field,bool Val)965 bool AMDGPUPALMetadata::checkComputeRegisters(StringRef field, bool Val) {
966 if (auto N = refComputeRegister(field))
967 return N->getBool() == Val;
968 return false;
969 }
970
setGraphicsRegisters(StringRef field,unsigned Val)971 void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field, unsigned Val) {
972 getGraphicsRegisters()[field] = Val;
973 }
974
setGraphicsRegisters(StringRef field,bool Val)975 void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field, bool Val) {
976 getGraphicsRegisters()[field] = Val;
977 }
978
setGraphicsRegisters(StringRef field1,StringRef field2,unsigned Val)979 void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field1, StringRef field2,
980 unsigned Val) {
981 getGraphicsRegisters()[field1].getMap(true)[field2] = Val;
982 }
983
setGraphicsRegisters(StringRef field1,StringRef field2,bool Val)984 void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field1, StringRef field2,
985 bool Val) {
986 getGraphicsRegisters()[field1].getMap(true)[field2] = Val;
987 }
988