1 /* $NetBSD: fpu_implode.c,v 1.6 2005/12/11 12:18:42 christos Exp $ */
2
3 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 * Copyright (c) 1992, 1993
7 * The Regents of the University of California. All rights reserved.
8 *
9 * This software was developed by the Computer Systems Engineering group
10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
11 * contributed to Berkeley.
12 *
13 * All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Lawrence Berkeley Laboratory.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions
20 * are met:
21 * 1. Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution.
26 * 3. Neither the name of the University nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * SUCH DAMAGE.
41 *
42 * @(#)fpu_implode.c 8.1 (Berkeley) 6/11/93
43 */
44
45 /*
46 * FPU subroutines: `implode' internal format numbers into the machine's
47 * `packed binary' format.
48 */
49
50 #include <sys/cdefs.h>
51 __FBSDID("$FreeBSD$");
52
53 #include <sys/types.h>
54 #include <sys/systm.h>
55
56 #include <machine/fpu.h>
57 #include <machine/ieee.h>
58 #include <machine/ieeefp.h>
59 #include <machine/reg.h>
60
61 #include <powerpc/fpu/fpu_arith.h>
62 #include <powerpc/fpu/fpu_emu.h>
63 #include <powerpc/fpu/fpu_extern.h>
64 #include <powerpc/fpu/fpu_instr.h>
65
66 static int round(struct fpemu *, struct fpn *);
67 static int toinf(struct fpemu *, int);
68
69 /*
70 * Round a number (algorithm from Motorola MC68882 manual, modified for
71 * our internal format). Set inexact exception if rounding is required.
72 * Return true iff we rounded up.
73 *
74 * After rounding, we discard the guard and round bits by shifting right
75 * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky).
76 * This saves effort later.
77 *
78 * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's
79 * responsibility to fix this if necessary.
80 */
81 static int
round(struct fpemu * fe,struct fpn * fp)82 round(struct fpemu *fe, struct fpn *fp)
83 {
84 u_int m0, m1, m2, m3;
85 int gr, s;
86 FPU_DECL_CARRY;
87
88 m0 = fp->fp_mant[0];
89 m1 = fp->fp_mant[1];
90 m2 = fp->fp_mant[2];
91 m3 = fp->fp_mant[3];
92 gr = m3 & 3;
93 s = fp->fp_sticky;
94
95 /* mant >>= FP_NG */
96 m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG));
97 m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG));
98 m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG));
99 m0 >>= FP_NG;
100
101 if ((gr | s) == 0) /* result is exact: no rounding needed */
102 goto rounddown;
103
104 fe->fe_cx |= FPSCR_XX|FPSCR_FI; /* inexact */
105
106 /* Go to rounddown to round down; break to round up. */
107 switch ((fe->fe_fpscr) & FPSCR_RN) {
108 case FP_RN:
109 default:
110 /*
111 * Round only if guard is set (gr & 2). If guard is set,
112 * but round & sticky both clear, then we want to round
113 * but have a tie, so round to even, i.e., add 1 iff odd.
114 */
115 if ((gr & 2) == 0)
116 goto rounddown;
117 if ((gr & 1) || fp->fp_sticky || (m3 & 1))
118 break;
119 goto rounddown;
120
121 case FP_RZ:
122 /* Round towards zero, i.e., down. */
123 goto rounddown;
124
125 case FP_RM:
126 /* Round towards -Inf: up if negative, down if positive. */
127 if (fp->fp_sign)
128 break;
129 goto rounddown;
130
131 case FP_RP:
132 /* Round towards +Inf: up if positive, down otherwise. */
133 if (!fp->fp_sign)
134 break;
135 goto rounddown;
136 }
137
138 /* Bump low bit of mantissa, with carry. */
139 fe->fe_cx |= FPSCR_FR;
140
141 FPU_ADDS(m3, m3, 1);
142 FPU_ADDCS(m2, m2, 0);
143 FPU_ADDCS(m1, m1, 0);
144 FPU_ADDC(m0, m0, 0);
145 fp->fp_mant[0] = m0;
146 fp->fp_mant[1] = m1;
147 fp->fp_mant[2] = m2;
148 fp->fp_mant[3] = m3;
149 return (1);
150
151 rounddown:
152 fp->fp_mant[0] = m0;
153 fp->fp_mant[1] = m1;
154 fp->fp_mant[2] = m2;
155 fp->fp_mant[3] = m3;
156 return (0);
157 }
158
159 /*
160 * For overflow: return true if overflow is to go to +/-Inf, according
161 * to the sign of the overflowing result. If false, overflow is to go
162 * to the largest magnitude value instead.
163 */
164 static int
toinf(struct fpemu * fe,int sign)165 toinf(struct fpemu *fe, int sign)
166 {
167 int inf;
168
169 /* look at rounding direction */
170 switch ((fe->fe_fpscr) & FPSCR_RN) {
171 default:
172 case FP_RN: /* the nearest value is always Inf */
173 inf = 1;
174 break;
175
176 case FP_RZ: /* toward 0 => never towards Inf */
177 inf = 0;
178 break;
179
180 case FP_RP: /* toward +Inf iff positive */
181 inf = sign == 0;
182 break;
183
184 case FP_RM: /* toward -Inf iff negative */
185 inf = sign;
186 break;
187 }
188 if (inf)
189 fe->fe_cx |= FPSCR_OX;
190 return (inf);
191 }
192
193 /*
194 * fpn -> int (int value returned as return value).
195 *
196 * N.B.: this conversion always rounds towards zero (this is a peculiarity
197 * of the SPARC instruction set).
198 */
199 u_int
fpu_ftoi(struct fpemu * fe,struct fpn * fp)200 fpu_ftoi(struct fpemu *fe, struct fpn *fp)
201 {
202 u_int i;
203 int sign, exp;
204
205 sign = fp->fp_sign;
206 switch (fp->fp_class) {
207 case FPC_ZERO:
208 return (0);
209
210 case FPC_NUM:
211 /*
212 * If exp >= 2^32, overflow. Otherwise shift value right
213 * into last mantissa word (this will not exceed 0xffffffff),
214 * shifting any guard and round bits out into the sticky
215 * bit. Then ``round'' towards zero, i.e., just set an
216 * inexact exception if sticky is set (see round()).
217 * If the result is > 0x80000000, or is positive and equals
218 * 0x80000000, overflow; otherwise the last fraction word
219 * is the result.
220 */
221 if ((exp = fp->fp_exp) >= 32)
222 break;
223 /* NB: the following includes exp < 0 cases */
224 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0)
225 fe->fe_cx |= FPSCR_UX;
226 i = fp->fp_mant[3];
227 if (i >= ((u_int)0x80000000 + sign))
228 break;
229 return (sign ? -i : i);
230
231 default: /* Inf, qNaN, sNaN */
232 break;
233 }
234 /* overflow: replace any inexact exception with invalid */
235 fe->fe_cx |= FPSCR_VXCVI;
236 return (0x7fffffff + sign);
237 }
238
239 /*
240 * fpn -> extended int (high bits of int value returned as return value).
241 *
242 * N.B.: this conversion always rounds towards zero (this is a peculiarity
243 * of the SPARC instruction set).
244 */
245 u_int
fpu_ftox(struct fpemu * fe,struct fpn * fp,u_int * res)246 fpu_ftox(struct fpemu *fe, struct fpn *fp, u_int *res)
247 {
248 u_int64_t i;
249 int sign, exp;
250
251 sign = fp->fp_sign;
252 switch (fp->fp_class) {
253 case FPC_ZERO:
254 res[1] = 0;
255 return (0);
256
257 case FPC_NUM:
258 /*
259 * If exp >= 2^64, overflow. Otherwise shift value right
260 * into last mantissa word (this will not exceed 0xffffffffffffffff),
261 * shifting any guard and round bits out into the sticky
262 * bit. Then ``round'' towards zero, i.e., just set an
263 * inexact exception if sticky is set (see round()).
264 * If the result is > 0x8000000000000000, or is positive and equals
265 * 0x8000000000000000, overflow; otherwise the last fraction word
266 * is the result.
267 */
268 if ((exp = fp->fp_exp) >= 64)
269 break;
270 /* NB: the following includes exp < 0 cases */
271 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0)
272 fe->fe_cx |= FPSCR_UX;
273 i = ((u_int64_t)fp->fp_mant[2]<<32)|fp->fp_mant[3];
274 if (i >= ((u_int64_t)0x8000000000000000LL + sign))
275 break;
276 return (sign ? -i : i);
277
278 default: /* Inf, qNaN, sNaN */
279 break;
280 }
281 /* overflow: replace any inexact exception with invalid */
282 fe->fe_cx |= FPSCR_VXCVI;
283 return (0x7fffffffffffffffLL + sign);
284 }
285
286 /*
287 * fpn -> single (32 bit single returned as return value).
288 * We assume <= 29 bits in a single-precision fraction (1.f part).
289 */
290 u_int
fpu_ftos(struct fpemu * fe,struct fpn * fp)291 fpu_ftos(struct fpemu *fe, struct fpn *fp)
292 {
293 u_int sign = fp->fp_sign << 31;
294 int exp;
295
296 #define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */
297 #define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */
298
299 /* Take care of non-numbers first. */
300 if (ISNAN(fp)) {
301 /*
302 * Preserve upper bits of NaN, per SPARC V8 appendix N.
303 * Note that fp->fp_mant[0] has the quiet bit set,
304 * even if it is classified as a signalling NaN.
305 */
306 (void) fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS);
307 exp = SNG_EXP_INFNAN;
308 goto done;
309 }
310 if (ISINF(fp))
311 return (sign | SNG_EXP(SNG_EXP_INFNAN));
312 if (ISZERO(fp))
313 return (sign);
314
315 /*
316 * Normals (including subnormals). Drop all the fraction bits
317 * (including the explicit ``implied'' 1 bit) down into the
318 * single-precision range. If the number is subnormal, move
319 * the ``implied'' 1 into the explicit range as well, and shift
320 * right to introduce leading zeroes. Rounding then acts
321 * differently for normals and subnormals: the largest subnormal
322 * may round to the smallest normal (1.0 x 2^minexp), or may
323 * remain subnormal. In the latter case, signal an underflow
324 * if the result was inexact or if underflow traps are enabled.
325 *
326 * Rounding a normal, on the other hand, always produces another
327 * normal (although either way the result might be too big for
328 * single precision, and cause an overflow). If rounding a
329 * normal produces 2.0 in the fraction, we need not adjust that
330 * fraction at all, since both 1.0 and 2.0 are zero under the
331 * fraction mask.
332 *
333 * Note that the guard and round bits vanish from the number after
334 * rounding.
335 */
336 if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */
337 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */
338 (void) fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp);
339 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(1))
340 return (sign | SNG_EXP(1) | 0);
341 if ((fe->fe_cx & FPSCR_FI) ||
342 (fe->fe_fpscr & FPSCR_UX))
343 fe->fe_cx |= FPSCR_UX;
344 return (sign | SNG_EXP(0) | fp->fp_mant[3]);
345 }
346 /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */
347 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS);
348 #ifdef DIAGNOSTIC
349 if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0)
350 panic("fpu_ftos");
351 #endif
352 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(2))
353 exp++;
354 if (exp >= SNG_EXP_INFNAN) {
355 /* overflow to inf or to max single */
356 if (toinf(fe, sign))
357 return (sign | SNG_EXP(SNG_EXP_INFNAN));
358 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK);
359 }
360 done:
361 /* phew, made it */
362 return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK));
363 }
364
365 /*
366 * fpn -> double (32 bit high-order result returned; 32-bit low order result
367 * left in res[1]). Assumes <= 61 bits in double precision fraction.
368 *
369 * This code mimics fpu_ftos; see it for comments.
370 */
371 u_int
fpu_ftod(struct fpemu * fe,struct fpn * fp,u_int * res)372 fpu_ftod(struct fpemu *fe, struct fpn *fp, u_int *res)
373 {
374 u_int sign = fp->fp_sign << 31;
375 int exp;
376
377 #define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31))
378 #define DBL_MASK (DBL_EXP(1) - 1)
379
380 if (ISNAN(fp)) {
381 (void) fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS);
382 exp = DBL_EXP_INFNAN;
383 goto done;
384 }
385 if (ISINF(fp)) {
386 sign |= DBL_EXP(DBL_EXP_INFNAN);
387 goto zero;
388 }
389 if (ISZERO(fp)) {
390 zero: res[1] = 0;
391 return (sign);
392 }
393
394 if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) {
395 (void) fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp);
396 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) {
397 res[1] = 0;
398 return (sign | DBL_EXP(1) | 0);
399 }
400 if ((fe->fe_cx & FPSCR_FI) ||
401 (fe->fe_fpscr & FPSCR_UX))
402 fe->fe_cx |= FPSCR_UX;
403 exp = 0;
404 goto done;
405 }
406 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS);
407 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(2))
408 exp++;
409 if (exp >= DBL_EXP_INFNAN) {
410 fe->fe_cx |= FPSCR_OX | FPSCR_UX;
411 if (toinf(fe, sign)) {
412 res[1] = 0;
413 return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0);
414 }
415 res[1] = ~0;
416 return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK);
417 }
418 done:
419 res[1] = fp->fp_mant[3];
420 return (sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK));
421 }
422
423 /*
424 * Implode an fpn, writing the result into the given space.
425 */
426 void
fpu_implode(struct fpemu * fe,struct fpn * fp,int type,u_int * space)427 fpu_implode(struct fpemu *fe, struct fpn *fp, int type, u_int *space)
428 {
429
430 switch (type) {
431 case FTYPE_LNG:
432 space[0] = fpu_ftox(fe, fp, space);
433 DPRINTF(FPE_REG, ("fpu_implode: long %x %x\n",
434 space[0], space[1]));
435 break;
436
437 case FTYPE_INT:
438 space[0] = 0;
439 space[1] = fpu_ftoi(fe, fp);
440 DPRINTF(FPE_REG, ("fpu_implode: int %x\n",
441 space[1]));
442 break;
443
444 case FTYPE_SNG:
445 space[0] = fpu_ftos(fe, fp);
446 DPRINTF(FPE_REG, ("fpu_implode: single %x\n",
447 space[0]));
448 break;
449
450 case FTYPE_DBL:
451 space[0] = fpu_ftod(fe, fp, space);
452 DPRINTF(FPE_REG, ("fpu_implode: double %x %x\n",
453 space[0], space[1]));
454 break; break;
455
456 default:
457 panic("fpu_implode: invalid type %d", type);
458 }
459 }
460