1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <[email protected]> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/debugnet.h> 63 #include <net/pfil.h> 64 #include <net/vnet.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_pcb.h> 68 #include <netinet/tcp_lro.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/ip6.h> 73 #include <netinet/tcp.h> 74 #include <netinet/ip_var.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 /* 120 * File organization: 121 * - private structures 122 * - iflib private utility functions 123 * - ifnet functions 124 * - vlan registry and other exported functions 125 * - iflib public core functions 126 * 127 * 128 */ 129 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 130 131 #define IFLIB_RXEOF_MORE (1U << 0) 132 #define IFLIB_RXEOF_EMPTY (2U << 0) 133 134 struct iflib_txq; 135 typedef struct iflib_txq *iflib_txq_t; 136 struct iflib_rxq; 137 typedef struct iflib_rxq *iflib_rxq_t; 138 struct iflib_fl; 139 typedef struct iflib_fl *iflib_fl_t; 140 141 struct iflib_ctx; 142 143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 144 static void iflib_timer(void *arg); 145 static void iflib_tqg_detach(if_ctx_t ctx); 146 147 typedef struct iflib_filter_info { 148 driver_filter_t *ifi_filter; 149 void *ifi_filter_arg; 150 struct grouptask *ifi_task; 151 void *ifi_ctx; 152 } *iflib_filter_info_t; 153 154 struct iflib_ctx { 155 KOBJ_FIELDS; 156 /* 157 * Pointer to hardware driver's softc 158 */ 159 void *ifc_softc; 160 device_t ifc_dev; 161 if_t ifc_ifp; 162 163 cpuset_t ifc_cpus; 164 if_shared_ctx_t ifc_sctx; 165 struct if_softc_ctx ifc_softc_ctx; 166 167 struct sx ifc_ctx_sx; 168 struct mtx ifc_state_mtx; 169 170 iflib_txq_t ifc_txqs; 171 iflib_rxq_t ifc_rxqs; 172 uint32_t ifc_if_flags; 173 uint32_t ifc_flags; 174 uint32_t ifc_max_fl_buf_size; 175 uint32_t ifc_rx_mbuf_sz; 176 177 int ifc_link_state; 178 int ifc_watchdog_events; 179 struct cdev *ifc_led_dev; 180 struct resource *ifc_msix_mem; 181 182 struct if_irq ifc_legacy_irq; 183 struct grouptask ifc_admin_task; 184 struct grouptask ifc_vflr_task; 185 struct iflib_filter_info ifc_filter_info; 186 struct ifmedia ifc_media; 187 struct ifmedia *ifc_mediap; 188 189 struct sysctl_oid *ifc_sysctl_node; 190 uint16_t ifc_sysctl_ntxqs; 191 uint16_t ifc_sysctl_nrxqs; 192 uint16_t ifc_sysctl_qs_eq_override; 193 uint16_t ifc_sysctl_rx_budget; 194 uint16_t ifc_sysctl_tx_abdicate; 195 uint16_t ifc_sysctl_core_offset; 196 #define CORE_OFFSET_UNSPECIFIED 0xffff 197 uint8_t ifc_sysctl_separate_txrx; 198 uint8_t ifc_sysctl_use_logical_cores; 199 bool ifc_cpus_are_physical_cores; 200 201 qidx_t ifc_sysctl_ntxds[8]; 202 qidx_t ifc_sysctl_nrxds[8]; 203 struct if_txrx ifc_txrx; 204 #define isc_txd_encap ifc_txrx.ift_txd_encap 205 #define isc_txd_flush ifc_txrx.ift_txd_flush 206 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 207 #define isc_rxd_available ifc_txrx.ift_rxd_available 208 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 209 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 210 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 211 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 212 eventhandler_tag ifc_vlan_attach_event; 213 eventhandler_tag ifc_vlan_detach_event; 214 struct ether_addr ifc_mac; 215 }; 216 217 void * 218 iflib_get_softc(if_ctx_t ctx) 219 { 220 221 return (ctx->ifc_softc); 222 } 223 224 device_t 225 iflib_get_dev(if_ctx_t ctx) 226 { 227 228 return (ctx->ifc_dev); 229 } 230 231 if_t 232 iflib_get_ifp(if_ctx_t ctx) 233 { 234 235 return (ctx->ifc_ifp); 236 } 237 238 struct ifmedia * 239 iflib_get_media(if_ctx_t ctx) 240 { 241 242 return (ctx->ifc_mediap); 243 } 244 245 uint32_t 246 iflib_get_flags(if_ctx_t ctx) 247 { 248 return (ctx->ifc_flags); 249 } 250 251 void 252 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 253 { 254 255 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 256 } 257 258 if_softc_ctx_t 259 iflib_get_softc_ctx(if_ctx_t ctx) 260 { 261 262 return (&ctx->ifc_softc_ctx); 263 } 264 265 if_shared_ctx_t 266 iflib_get_sctx(if_ctx_t ctx) 267 { 268 269 return (ctx->ifc_sctx); 270 } 271 272 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 273 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 274 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 275 276 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 277 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 278 279 typedef struct iflib_sw_rx_desc_array { 280 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 281 struct mbuf **ifsd_m; /* pkthdr mbufs */ 282 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 283 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 284 } iflib_rxsd_array_t; 285 286 typedef struct iflib_sw_tx_desc_array { 287 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 288 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 289 struct mbuf **ifsd_m; /* pkthdr mbufs */ 290 } if_txsd_vec_t; 291 292 /* magic number that should be high enough for any hardware */ 293 #define IFLIB_MAX_TX_SEGS 128 294 #define IFLIB_RX_COPY_THRESH 128 295 #define IFLIB_MAX_RX_REFRESH 32 296 /* The minimum descriptors per second before we start coalescing */ 297 #define IFLIB_MIN_DESC_SEC 16384 298 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 299 #define IFLIB_QUEUE_IDLE 0 300 #define IFLIB_QUEUE_HUNG 1 301 #define IFLIB_QUEUE_WORKING 2 302 /* maximum number of txqs that can share an rx interrupt */ 303 #define IFLIB_MAX_TX_SHARED_INTR 4 304 305 /* this should really scale with ring size - this is a fairly arbitrary value */ 306 #define TX_BATCH_SIZE 32 307 308 #define IFLIB_RESTART_BUDGET 8 309 310 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 311 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 312 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 313 314 struct iflib_txq { 315 qidx_t ift_in_use; 316 qidx_t ift_cidx; 317 qidx_t ift_cidx_processed; 318 qidx_t ift_pidx; 319 uint8_t ift_gen; 320 uint8_t ift_br_offset; 321 uint16_t ift_npending; 322 uint16_t ift_db_pending; 323 uint16_t ift_rs_pending; 324 /* implicit pad */ 325 uint8_t ift_txd_size[8]; 326 uint64_t ift_processed; 327 uint64_t ift_cleaned; 328 uint64_t ift_cleaned_prev; 329 #if MEMORY_LOGGING 330 uint64_t ift_enqueued; 331 uint64_t ift_dequeued; 332 #endif 333 uint64_t ift_no_tx_dma_setup; 334 uint64_t ift_no_desc_avail; 335 uint64_t ift_mbuf_defrag_failed; 336 uint64_t ift_mbuf_defrag; 337 uint64_t ift_map_failed; 338 uint64_t ift_txd_encap_efbig; 339 uint64_t ift_pullups; 340 uint64_t ift_last_timer_tick; 341 342 struct mtx ift_mtx; 343 struct mtx ift_db_mtx; 344 345 /* constant values */ 346 if_ctx_t ift_ctx; 347 struct ifmp_ring *ift_br; 348 struct grouptask ift_task; 349 qidx_t ift_size; 350 uint16_t ift_id; 351 struct callout ift_timer; 352 #ifdef DEV_NETMAP 353 struct callout ift_netmap_timer; 354 #endif /* DEV_NETMAP */ 355 356 if_txsd_vec_t ift_sds; 357 uint8_t ift_qstatus; 358 uint8_t ift_closed; 359 uint8_t ift_update_freq; 360 struct iflib_filter_info ift_filter_info; 361 bus_dma_tag_t ift_buf_tag; 362 bus_dma_tag_t ift_tso_buf_tag; 363 iflib_dma_info_t ift_ifdi; 364 #define MTX_NAME_LEN 32 365 char ift_mtx_name[MTX_NAME_LEN]; 366 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 367 #ifdef IFLIB_DIAGNOSTICS 368 uint64_t ift_cpu_exec_count[256]; 369 #endif 370 } __aligned(CACHE_LINE_SIZE); 371 372 struct iflib_fl { 373 qidx_t ifl_cidx; 374 qidx_t ifl_pidx; 375 qidx_t ifl_credits; 376 uint8_t ifl_gen; 377 uint8_t ifl_rxd_size; 378 #if MEMORY_LOGGING 379 uint64_t ifl_m_enqueued; 380 uint64_t ifl_m_dequeued; 381 uint64_t ifl_cl_enqueued; 382 uint64_t ifl_cl_dequeued; 383 #endif 384 /* implicit pad */ 385 bitstr_t *ifl_rx_bitmap; 386 qidx_t ifl_fragidx; 387 /* constant */ 388 qidx_t ifl_size; 389 uint16_t ifl_buf_size; 390 uint16_t ifl_cltype; 391 uma_zone_t ifl_zone; 392 iflib_rxsd_array_t ifl_sds; 393 iflib_rxq_t ifl_rxq; 394 uint8_t ifl_id; 395 bus_dma_tag_t ifl_buf_tag; 396 iflib_dma_info_t ifl_ifdi; 397 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 398 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 399 } __aligned(CACHE_LINE_SIZE); 400 401 static inline qidx_t 402 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 403 { 404 qidx_t used; 405 406 if (pidx > cidx) 407 used = pidx - cidx; 408 else if (pidx < cidx) 409 used = size - cidx + pidx; 410 else if (gen == 0 && pidx == cidx) 411 used = 0; 412 else if (gen == 1 && pidx == cidx) 413 used = size; 414 else 415 panic("bad state"); 416 417 return (used); 418 } 419 420 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 421 422 #define IDXDIFF(head, tail, wrap) \ 423 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 424 425 struct iflib_rxq { 426 if_ctx_t ifr_ctx; 427 iflib_fl_t ifr_fl; 428 uint64_t ifr_rx_irq; 429 struct pfil_head *pfil; 430 /* 431 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 432 * the completion queue consumer index. Otherwise it's unused. 433 */ 434 qidx_t ifr_cq_cidx; 435 uint16_t ifr_id; 436 uint8_t ifr_nfl; 437 uint8_t ifr_ntxqirq; 438 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 439 uint8_t ifr_fl_offset; 440 struct lro_ctrl ifr_lc; 441 struct grouptask ifr_task; 442 struct callout ifr_watchdog; 443 struct iflib_filter_info ifr_filter_info; 444 iflib_dma_info_t ifr_ifdi; 445 446 /* dynamically allocate if any drivers need a value substantially larger than this */ 447 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 448 #ifdef IFLIB_DIAGNOSTICS 449 uint64_t ifr_cpu_exec_count[256]; 450 #endif 451 } __aligned(CACHE_LINE_SIZE); 452 453 typedef struct if_rxsd { 454 caddr_t *ifsd_cl; 455 iflib_fl_t ifsd_fl; 456 } *if_rxsd_t; 457 458 /* multiple of word size */ 459 #ifdef __LP64__ 460 #define PKT_INFO_SIZE 6 461 #define RXD_INFO_SIZE 5 462 #define PKT_TYPE uint64_t 463 #else 464 #define PKT_INFO_SIZE 11 465 #define RXD_INFO_SIZE 8 466 #define PKT_TYPE uint32_t 467 #endif 468 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 469 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 470 471 typedef struct if_pkt_info_pad { 472 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 473 } *if_pkt_info_pad_t; 474 typedef struct if_rxd_info_pad { 475 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 476 } *if_rxd_info_pad_t; 477 478 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 479 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 480 481 static inline void 482 pkt_info_zero(if_pkt_info_t pi) 483 { 484 if_pkt_info_pad_t pi_pad; 485 486 pi_pad = (if_pkt_info_pad_t)pi; 487 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 488 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 489 #ifndef __LP64__ 490 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 491 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 492 #endif 493 } 494 495 static device_method_t iflib_pseudo_methods[] = { 496 DEVMETHOD(device_attach, noop_attach), 497 DEVMETHOD(device_detach, iflib_pseudo_detach), 498 DEVMETHOD_END 499 }; 500 501 driver_t iflib_pseudodriver = { 502 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 503 }; 504 505 static inline void 506 rxd_info_zero(if_rxd_info_t ri) 507 { 508 if_rxd_info_pad_t ri_pad; 509 int i; 510 511 ri_pad = (if_rxd_info_pad_t)ri; 512 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 513 ri_pad->rxd_val[i] = 0; 514 ri_pad->rxd_val[i+1] = 0; 515 ri_pad->rxd_val[i+2] = 0; 516 ri_pad->rxd_val[i+3] = 0; 517 } 518 #ifdef __LP64__ 519 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 520 #endif 521 } 522 523 /* 524 * Only allow a single packet to take up most 1/nth of the tx ring 525 */ 526 #define MAX_SINGLE_PACKET_FRACTION 12 527 #define IF_BAD_DMA (bus_addr_t)-1 528 529 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 530 531 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 532 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 533 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 534 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 535 536 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 537 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 538 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 539 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 540 541 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 542 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 543 544 void 545 iflib_set_detach(if_ctx_t ctx) 546 { 547 STATE_LOCK(ctx); 548 ctx->ifc_flags |= IFC_IN_DETACH; 549 STATE_UNLOCK(ctx); 550 } 551 552 /* Our boot-time initialization hook */ 553 static int iflib_module_event_handler(module_t, int, void *); 554 555 static moduledata_t iflib_moduledata = { 556 "iflib", 557 iflib_module_event_handler, 558 NULL 559 }; 560 561 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 562 MODULE_VERSION(iflib, 1); 563 564 MODULE_DEPEND(iflib, pci, 1, 1, 1); 565 MODULE_DEPEND(iflib, ether, 1, 1, 1); 566 567 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 568 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 569 570 #ifndef IFLIB_DEBUG_COUNTERS 571 #ifdef INVARIANTS 572 #define IFLIB_DEBUG_COUNTERS 1 573 #else 574 #define IFLIB_DEBUG_COUNTERS 0 575 #endif /* !INVARIANTS */ 576 #endif 577 578 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 579 "iflib driver parameters"); 580 581 /* 582 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 583 */ 584 static int iflib_min_tx_latency = 0; 585 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 586 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 587 static int iflib_no_tx_batch = 0; 588 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 589 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 590 static int iflib_timer_default = 1000; 591 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW, 592 &iflib_timer_default, 0, "number of ticks between iflib_timer calls"); 593 594 595 #if IFLIB_DEBUG_COUNTERS 596 597 static int iflib_tx_seen; 598 static int iflib_tx_sent; 599 static int iflib_tx_encap; 600 static int iflib_rx_allocs; 601 static int iflib_fl_refills; 602 static int iflib_fl_refills_large; 603 static int iflib_tx_frees; 604 605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 606 &iflib_tx_seen, 0, "# TX mbufs seen"); 607 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 608 &iflib_tx_sent, 0, "# TX mbufs sent"); 609 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 610 &iflib_tx_encap, 0, "# TX mbufs encapped"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 612 &iflib_tx_frees, 0, "# TX frees"); 613 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 614 &iflib_rx_allocs, 0, "# RX allocations"); 615 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 616 &iflib_fl_refills, 0, "# refills"); 617 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 618 &iflib_fl_refills_large, 0, "# large refills"); 619 620 static int iflib_txq_drain_flushing; 621 static int iflib_txq_drain_oactive; 622 static int iflib_txq_drain_notready; 623 624 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 625 &iflib_txq_drain_flushing, 0, "# drain flushes"); 626 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 627 &iflib_txq_drain_oactive, 0, "# drain oactives"); 628 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 629 &iflib_txq_drain_notready, 0, "# drain notready"); 630 631 static int iflib_encap_load_mbuf_fail; 632 static int iflib_encap_pad_mbuf_fail; 633 static int iflib_encap_txq_avail_fail; 634 static int iflib_encap_txd_encap_fail; 635 636 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 637 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 638 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 639 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 640 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 641 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 642 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 643 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 644 645 static int iflib_task_fn_rxs; 646 static int iflib_rx_intr_enables; 647 static int iflib_fast_intrs; 648 static int iflib_rx_unavail; 649 static int iflib_rx_ctx_inactive; 650 static int iflib_rx_if_input; 651 static int iflib_rxd_flush; 652 653 static int iflib_verbose_debug; 654 655 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 656 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 657 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 658 &iflib_rx_intr_enables, 0, "# RX intr enables"); 659 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 660 &iflib_fast_intrs, 0, "# fast_intr calls"); 661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 662 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 664 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 665 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 666 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 667 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 668 &iflib_rxd_flush, 0, "# times rxd_flush called"); 669 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 670 &iflib_verbose_debug, 0, "enable verbose debugging"); 671 672 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 673 static void 674 iflib_debug_reset(void) 675 { 676 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 677 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 678 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 679 iflib_txq_drain_notready = 680 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 681 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 682 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 683 iflib_rx_unavail = 684 iflib_rx_ctx_inactive = iflib_rx_if_input = 685 iflib_rxd_flush = 0; 686 } 687 688 #else 689 #define DBG_COUNTER_INC(name) 690 static void iflib_debug_reset(void) {} 691 #endif 692 693 #define IFLIB_DEBUG 0 694 695 static void iflib_tx_structures_free(if_ctx_t ctx); 696 static void iflib_rx_structures_free(if_ctx_t ctx); 697 static int iflib_queues_alloc(if_ctx_t ctx); 698 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 699 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 700 static int iflib_qset_structures_setup(if_ctx_t ctx); 701 static int iflib_msix_init(if_ctx_t ctx); 702 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 703 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 704 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 705 #ifdef ALTQ 706 static void iflib_altq_if_start(if_t ifp); 707 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 708 #endif 709 static int iflib_register(if_ctx_t); 710 static void iflib_deregister(if_ctx_t); 711 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 712 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 713 static void iflib_init_locked(if_ctx_t ctx); 714 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 715 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 716 static void iflib_ifmp_purge(iflib_txq_t txq); 717 static void _iflib_pre_assert(if_softc_ctx_t scctx); 718 static void iflib_if_init_locked(if_ctx_t ctx); 719 static void iflib_free_intr_mem(if_ctx_t ctx); 720 #ifndef __NO_STRICT_ALIGNMENT 721 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 722 #endif 723 724 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 725 SLIST_HEAD_INITIALIZER(cpu_offsets); 726 struct cpu_offset { 727 SLIST_ENTRY(cpu_offset) entries; 728 cpuset_t set; 729 unsigned int refcount; 730 uint16_t next_cpuid; 731 }; 732 static struct mtx cpu_offset_mtx; 733 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 734 MTX_DEF); 735 736 DEBUGNET_DEFINE(iflib); 737 738 static int 739 iflib_num_rx_descs(if_ctx_t ctx) 740 { 741 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 742 if_shared_ctx_t sctx = ctx->ifc_sctx; 743 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 744 745 return scctx->isc_nrxd[first_rxq]; 746 } 747 748 static int 749 iflib_num_tx_descs(if_ctx_t ctx) 750 { 751 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 752 if_shared_ctx_t sctx = ctx->ifc_sctx; 753 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 754 755 return scctx->isc_ntxd[first_txq]; 756 } 757 758 #ifdef DEV_NETMAP 759 #include <sys/selinfo.h> 760 #include <net/netmap.h> 761 #include <dev/netmap/netmap_kern.h> 762 763 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 764 765 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init); 766 static void iflib_netmap_timer(void *arg); 767 768 /* 769 * device-specific sysctl variables: 770 * 771 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 772 * During regular operations the CRC is stripped, but on some 773 * hardware reception of frames not multiple of 64 is slower, 774 * so using crcstrip=0 helps in benchmarks. 775 * 776 * iflib_rx_miss, iflib_rx_miss_bufs: 777 * count packets that might be missed due to lost interrupts. 778 */ 779 SYSCTL_DECL(_dev_netmap); 780 /* 781 * The xl driver by default strips CRCs and we do not override it. 782 */ 783 784 int iflib_crcstrip = 1; 785 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 786 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 787 788 int iflib_rx_miss, iflib_rx_miss_bufs; 789 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 790 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 791 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 792 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 793 794 /* 795 * Register/unregister. We are already under netmap lock. 796 * Only called on the first register or the last unregister. 797 */ 798 static int 799 iflib_netmap_register(struct netmap_adapter *na, int onoff) 800 { 801 if_t ifp = na->ifp; 802 if_ctx_t ctx = ifp->if_softc; 803 int status; 804 805 CTX_LOCK(ctx); 806 if (!CTX_IS_VF(ctx)) 807 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 808 809 iflib_stop(ctx); 810 811 /* 812 * Enable (or disable) netmap flags, and intercept (or restore) 813 * ifp->if_transmit. This is done once the device has been stopped 814 * to prevent race conditions. Also, this must be done after 815 * calling netmap_disable_all_rings() and before calling 816 * netmap_enable_all_rings(), so that these two functions see the 817 * updated state of the NAF_NETMAP_ON bit. 818 */ 819 if (onoff) { 820 nm_set_native_flags(na); 821 } else { 822 nm_clear_native_flags(na); 823 } 824 825 iflib_init_locked(ctx); 826 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 827 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 828 if (status) 829 nm_clear_native_flags(na); 830 CTX_UNLOCK(ctx); 831 return (status); 832 } 833 834 static int 835 iflib_netmap_config(struct netmap_adapter *na, struct nm_config_info *info) 836 { 837 if_t ifp = na->ifp; 838 if_ctx_t ctx = ifp->if_softc; 839 iflib_rxq_t rxq = &ctx->ifc_rxqs[0]; 840 iflib_fl_t fl = &rxq->ifr_fl[0]; 841 842 info->num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 843 info->num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 844 info->num_tx_descs = iflib_num_tx_descs(ctx); 845 info->num_rx_descs = iflib_num_rx_descs(ctx); 846 info->rx_buf_maxsize = fl->ifl_buf_size; 847 nm_prinf("txr %u rxr %u txd %u rxd %u rbufsz %u", 848 info->num_tx_rings, info->num_rx_rings, info->num_tx_descs, 849 info->num_rx_descs, info->rx_buf_maxsize); 850 851 return 0; 852 } 853 854 static int 855 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init) 856 { 857 struct netmap_adapter *na = kring->na; 858 u_int const lim = kring->nkr_num_slots - 1; 859 struct netmap_ring *ring = kring->ring; 860 bus_dmamap_t *map; 861 struct if_rxd_update iru; 862 if_ctx_t ctx = rxq->ifr_ctx; 863 iflib_fl_t fl = &rxq->ifr_fl[0]; 864 u_int nic_i_first, nic_i; 865 u_int nm_i; 866 int i, n; 867 #if IFLIB_DEBUG_COUNTERS 868 int rf_count = 0; 869 #endif 870 871 /* 872 * This function is used both at initialization and in rxsync. 873 * At initialization we need to prepare (with isc_rxd_refill()) 874 * all the netmap buffers currently owned by the kernel, in 875 * such a way to keep fl->ifl_pidx and kring->nr_hwcur in sync 876 * (except for kring->nkr_hwofs). These may be less than 877 * kring->nkr_num_slots if netmap_reset() was called while 878 * an application using the kring that still owned some 879 * buffers. 880 * At rxsync time, both indexes point to the next buffer to be 881 * refilled. 882 * In any case we publish (with isc_rxd_flush()) up to 883 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod 884 * pointer to overrun the head/cons pointer, although this is 885 * not necessary for some NICs (e.g. vmx). 886 */ 887 if (__predict_false(init)) { 888 n = kring->nkr_num_slots - nm_kr_rxspace(kring); 889 } else { 890 n = kring->rhead - kring->nr_hwcur; 891 if (n == 0) 892 return (0); /* Nothing to do. */ 893 if (n < 0) 894 n += kring->nkr_num_slots; 895 } 896 897 iru_init(&iru, rxq, 0 /* flid */); 898 map = fl->ifl_sds.ifsd_map; 899 nic_i = fl->ifl_pidx; 900 nm_i = netmap_idx_n2k(kring, nic_i); 901 if (__predict_false(init)) { 902 /* 903 * On init/reset, nic_i must be 0, and we must 904 * start to refill from hwtail (see netmap_reset()). 905 */ 906 MPASS(nic_i == 0); 907 MPASS(nm_i == kring->nr_hwtail); 908 } else 909 MPASS(nm_i == kring->nr_hwcur); 910 DBG_COUNTER_INC(fl_refills); 911 while (n > 0) { 912 #if IFLIB_DEBUG_COUNTERS 913 if (++rf_count == 9) 914 DBG_COUNTER_INC(fl_refills_large); 915 #endif 916 nic_i_first = nic_i; 917 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) { 918 struct netmap_slot *slot = &ring->slot[nm_i]; 919 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[i]); 920 921 MPASS(i < IFLIB_MAX_RX_REFRESH); 922 923 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 924 return netmap_ring_reinit(kring); 925 926 fl->ifl_rxd_idxs[i] = nic_i; 927 928 if (__predict_false(init)) { 929 netmap_load_map(na, fl->ifl_buf_tag, 930 map[nic_i], addr); 931 } else if (slot->flags & NS_BUF_CHANGED) { 932 /* buffer has changed, reload map */ 933 netmap_reload_map(na, fl->ifl_buf_tag, 934 map[nic_i], addr); 935 } 936 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i], 937 BUS_DMASYNC_PREREAD); 938 slot->flags &= ~NS_BUF_CHANGED; 939 940 nm_i = nm_next(nm_i, lim); 941 nic_i = nm_next(nic_i, lim); 942 } 943 944 iru.iru_pidx = nic_i_first; 945 iru.iru_count = i; 946 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 947 } 948 fl->ifl_pidx = nic_i; 949 /* 950 * At the end of the loop we must have refilled everything 951 * we could possibly refill. 952 */ 953 MPASS(nm_i == kring->rhead); 954 kring->nr_hwcur = nm_i; 955 956 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 957 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 958 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, 959 nm_prev(nic_i, lim)); 960 DBG_COUNTER_INC(rxd_flush); 961 962 return (0); 963 } 964 965 #define NETMAP_TX_TIMER_US 90 966 967 /* 968 * Reconcile kernel and user view of the transmit ring. 969 * 970 * All information is in the kring. 971 * Userspace wants to send packets up to the one before kring->rhead, 972 * kernel knows kring->nr_hwcur is the first unsent packet. 973 * 974 * Here we push packets out (as many as possible), and possibly 975 * reclaim buffers from previously completed transmission. 976 * 977 * The caller (netmap) guarantees that there is only one instance 978 * running at any time. Any interference with other driver 979 * methods should be handled by the individual drivers. 980 */ 981 static int 982 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 983 { 984 struct netmap_adapter *na = kring->na; 985 if_t ifp = na->ifp; 986 struct netmap_ring *ring = kring->ring; 987 u_int nm_i; /* index into the netmap kring */ 988 u_int nic_i; /* index into the NIC ring */ 989 u_int n; 990 u_int const lim = kring->nkr_num_slots - 1; 991 u_int const head = kring->rhead; 992 struct if_pkt_info pi; 993 int tx_pkts = 0, tx_bytes = 0; 994 995 /* 996 * interrupts on every tx packet are expensive so request 997 * them every half ring, or where NS_REPORT is set 998 */ 999 u_int report_frequency = kring->nkr_num_slots >> 1; 1000 /* device-specific */ 1001 if_ctx_t ctx = ifp->if_softc; 1002 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 1003 1004 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1005 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1006 1007 /* 1008 * First part: process new packets to send. 1009 * nm_i is the current index in the netmap kring, 1010 * nic_i is the corresponding index in the NIC ring. 1011 * 1012 * If we have packets to send (nm_i != head) 1013 * iterate over the netmap ring, fetch length and update 1014 * the corresponding slot in the NIC ring. Some drivers also 1015 * need to update the buffer's physical address in the NIC slot 1016 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 1017 * 1018 * The netmap_reload_map() calls is especially expensive, 1019 * even when (as in this case) the tag is 0, so do only 1020 * when the buffer has actually changed. 1021 * 1022 * If possible do not set the report/intr bit on all slots, 1023 * but only a few times per ring or when NS_REPORT is set. 1024 * 1025 * Finally, on 10G and faster drivers, it might be useful 1026 * to prefetch the next slot and txr entry. 1027 */ 1028 1029 nm_i = kring->nr_hwcur; 1030 if (nm_i != head) { /* we have new packets to send */ 1031 uint32_t pkt_len = 0, seg_idx = 0; 1032 int nic_i_start = -1, flags = 0; 1033 pkt_info_zero(&pi); 1034 pi.ipi_segs = txq->ift_segs; 1035 pi.ipi_qsidx = kring->ring_id; 1036 nic_i = netmap_idx_k2n(kring, nm_i); 1037 1038 __builtin_prefetch(&ring->slot[nm_i]); 1039 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 1040 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 1041 1042 for (n = 0; nm_i != head; n++) { 1043 struct netmap_slot *slot = &ring->slot[nm_i]; 1044 u_int len = slot->len; 1045 uint64_t paddr; 1046 void *addr = PNMB(na, slot, &paddr); 1047 1048 flags |= (slot->flags & NS_REPORT || 1049 nic_i == 0 || nic_i == report_frequency) ? 1050 IPI_TX_INTR : 0; 1051 1052 /* 1053 * If this is the first packet fragment, save the 1054 * index of the first NIC slot for later. 1055 */ 1056 if (nic_i_start < 0) 1057 nic_i_start = nic_i; 1058 1059 pi.ipi_segs[seg_idx].ds_addr = paddr; 1060 pi.ipi_segs[seg_idx].ds_len = len; 1061 if (len) { 1062 pkt_len += len; 1063 seg_idx++; 1064 } 1065 1066 if (!(slot->flags & NS_MOREFRAG)) { 1067 pi.ipi_len = pkt_len; 1068 pi.ipi_nsegs = seg_idx; 1069 pi.ipi_pidx = nic_i_start; 1070 pi.ipi_ndescs = 0; 1071 pi.ipi_flags = flags; 1072 1073 /* Prepare the NIC TX ring. */ 1074 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 1075 DBG_COUNTER_INC(tx_encap); 1076 1077 /* Update transmit counters */ 1078 tx_bytes += pi.ipi_len; 1079 tx_pkts++; 1080 1081 /* Reinit per-packet info for the next one. */ 1082 flags = seg_idx = pkt_len = 0; 1083 nic_i_start = -1; 1084 } 1085 1086 /* prefetch for next round */ 1087 __builtin_prefetch(&ring->slot[nm_i + 1]); 1088 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1089 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1090 1091 NM_CHECK_ADDR_LEN(na, addr, len); 1092 1093 if (slot->flags & NS_BUF_CHANGED) { 1094 /* buffer has changed, reload map */ 1095 netmap_reload_map(na, txq->ift_buf_tag, 1096 txq->ift_sds.ifsd_map[nic_i], addr); 1097 } 1098 /* make sure changes to the buffer are synced */ 1099 bus_dmamap_sync(txq->ift_buf_tag, 1100 txq->ift_sds.ifsd_map[nic_i], 1101 BUS_DMASYNC_PREWRITE); 1102 1103 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED | NS_MOREFRAG); 1104 nm_i = nm_next(nm_i, lim); 1105 nic_i = nm_next(nic_i, lim); 1106 } 1107 kring->nr_hwcur = nm_i; 1108 1109 /* synchronize the NIC ring */ 1110 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1111 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1112 1113 /* (re)start the tx unit up to slot nic_i (excluded) */ 1114 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1115 } 1116 1117 /* 1118 * Second part: reclaim buffers for completed transmissions. 1119 * 1120 * If there are unclaimed buffers, attempt to reclaim them. 1121 * If we don't manage to reclaim them all, and TX IRQs are not in use, 1122 * trigger a per-tx-queue timer to try again later. 1123 */ 1124 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1125 if (iflib_tx_credits_update(ctx, txq)) { 1126 /* some tx completed, increment avail */ 1127 nic_i = txq->ift_cidx_processed; 1128 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1129 } 1130 } 1131 1132 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1133 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1134 callout_reset_sbt_on(&txq->ift_netmap_timer, 1135 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US, 1136 iflib_netmap_timer, txq, 1137 txq->ift_netmap_timer.c_cpu, 0); 1138 } 1139 1140 if_inc_counter(ifp, IFCOUNTER_OBYTES, tx_bytes); 1141 if_inc_counter(ifp, IFCOUNTER_OPACKETS, tx_pkts); 1142 1143 return (0); 1144 } 1145 1146 /* 1147 * Reconcile kernel and user view of the receive ring. 1148 * Same as for the txsync, this routine must be efficient. 1149 * The caller guarantees a single invocations, but races against 1150 * the rest of the driver should be handled here. 1151 * 1152 * On call, kring->rhead is the first packet that userspace wants 1153 * to keep, and kring->rcur is the wakeup point. 1154 * The kernel has previously reported packets up to kring->rtail. 1155 * 1156 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1157 * of whether or not we received an interrupt. 1158 */ 1159 static int 1160 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1161 { 1162 struct netmap_adapter *na = kring->na; 1163 struct netmap_ring *ring = kring->ring; 1164 if_t ifp = na->ifp; 1165 uint32_t nm_i; /* index into the netmap ring */ 1166 uint32_t nic_i; /* index into the NIC ring */ 1167 u_int n; 1168 u_int const lim = kring->nkr_num_slots - 1; 1169 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1170 int i = 0, rx_bytes = 0, rx_pkts = 0; 1171 1172 if_ctx_t ctx = ifp->if_softc; 1173 if_shared_ctx_t sctx = ctx->ifc_sctx; 1174 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1175 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1176 iflib_fl_t fl = &rxq->ifr_fl[0]; 1177 struct if_rxd_info ri; 1178 qidx_t *cidxp; 1179 1180 /* 1181 * netmap only uses free list 0, to avoid out of order consumption 1182 * of receive buffers 1183 */ 1184 1185 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1186 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1187 1188 /* 1189 * First part: import newly received packets. 1190 * 1191 * nm_i is the index of the next free slot in the netmap ring, 1192 * nic_i is the index of the next received packet in the NIC ring 1193 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may 1194 * differ in case if_init() has been called while 1195 * in netmap mode. For the receive ring we have 1196 * 1197 * nic_i = fl->ifl_cidx; 1198 * nm_i = kring->nr_hwtail (previous) 1199 * and 1200 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1201 * 1202 * fl->ifl_cidx is set to 0 on a ring reinit 1203 */ 1204 if (netmap_no_pendintr || force_update) { 1205 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1206 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ; 1207 int crclen = iflib_crcstrip ? 0 : 4; 1208 int error, avail; 1209 1210 /* 1211 * For the free list consumer index, we use the same 1212 * logic as in iflib_rxeof(). 1213 */ 1214 if (have_rxcq) 1215 cidxp = &rxq->ifr_cq_cidx; 1216 else 1217 cidxp = &fl->ifl_cidx; 1218 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1219 rxq->ifr_id, *cidxp, USHRT_MAX); 1220 1221 nic_i = fl->ifl_cidx; 1222 nm_i = netmap_idx_n2k(kring, nic_i); 1223 MPASS(nm_i == kring->nr_hwtail); 1224 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1225 rxd_info_zero(&ri); 1226 ri.iri_frags = rxq->ifr_frags; 1227 ri.iri_qsidx = kring->ring_id; 1228 ri.iri_ifp = ctx->ifc_ifp; 1229 ri.iri_cidx = *cidxp; 1230 1231 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1232 for (i = 0; i < ri.iri_nfrags; i++) { 1233 if (error) { 1234 ring->slot[nm_i].len = 0; 1235 ring->slot[nm_i].flags = 0; 1236 } else { 1237 ring->slot[nm_i].len = ri.iri_frags[i].irf_len; 1238 if (i == (ri.iri_nfrags - 1)) { 1239 ring->slot[nm_i].len -= crclen; 1240 ring->slot[nm_i].flags = 0; 1241 1242 /* Update receive counters */ 1243 rx_bytes += ri.iri_len; 1244 rx_pkts++; 1245 } else 1246 ring->slot[nm_i].flags = NS_MOREFRAG; 1247 } 1248 1249 bus_dmamap_sync(fl->ifl_buf_tag, 1250 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1251 nm_i = nm_next(nm_i, lim); 1252 fl->ifl_cidx = nic_i = nm_next(nic_i, lim); 1253 } 1254 1255 if (have_rxcq) { 1256 *cidxp = ri.iri_cidx; 1257 while (*cidxp >= scctx->isc_nrxd[0]) 1258 *cidxp -= scctx->isc_nrxd[0]; 1259 } 1260 1261 } 1262 if (n) { /* update the state variables */ 1263 if (netmap_no_pendintr && !force_update) { 1264 /* diagnostics */ 1265 iflib_rx_miss ++; 1266 iflib_rx_miss_bufs += n; 1267 } 1268 kring->nr_hwtail = nm_i; 1269 } 1270 kring->nr_kflags &= ~NKR_PENDINTR; 1271 } 1272 /* 1273 * Second part: skip past packets that userspace has released. 1274 * (kring->nr_hwcur to head excluded), 1275 * and make the buffers available for reception. 1276 * As usual nm_i is the index in the netmap ring, 1277 * nic_i is the index in the NIC ring, and 1278 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1279 */ 1280 netmap_fl_refill(rxq, kring, false); 1281 1282 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 1283 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 1284 1285 return (0); 1286 } 1287 1288 static void 1289 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1290 { 1291 if_ctx_t ctx = na->ifp->if_softc; 1292 1293 CTX_LOCK(ctx); 1294 if (onoff) { 1295 IFDI_INTR_ENABLE(ctx); 1296 } else { 1297 IFDI_INTR_DISABLE(ctx); 1298 } 1299 CTX_UNLOCK(ctx); 1300 } 1301 1302 static int 1303 iflib_netmap_attach(if_ctx_t ctx) 1304 { 1305 struct netmap_adapter na; 1306 1307 bzero(&na, sizeof(na)); 1308 1309 na.ifp = ctx->ifc_ifp; 1310 na.na_flags = NAF_BDG_MAYSLEEP | NAF_MOREFRAG; 1311 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1312 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1313 1314 na.num_tx_desc = iflib_num_tx_descs(ctx); 1315 na.num_rx_desc = iflib_num_rx_descs(ctx); 1316 na.nm_txsync = iflib_netmap_txsync; 1317 na.nm_rxsync = iflib_netmap_rxsync; 1318 na.nm_register = iflib_netmap_register; 1319 na.nm_intr = iflib_netmap_intr; 1320 na.nm_config = iflib_netmap_config; 1321 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1322 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1323 return (netmap_attach(&na)); 1324 } 1325 1326 static int 1327 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1328 { 1329 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1330 struct netmap_slot *slot; 1331 1332 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1333 if (slot == NULL) 1334 return (0); 1335 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1336 /* 1337 * In netmap mode, set the map for the packet buffer. 1338 * NOTE: Some drivers (not this one) also need to set 1339 * the physical buffer address in the NIC ring. 1340 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1341 * netmap slot index, si 1342 */ 1343 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1344 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1345 NMB(na, slot + si)); 1346 } 1347 return (1); 1348 } 1349 1350 static int 1351 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1352 { 1353 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1354 struct netmap_kring *kring; 1355 struct netmap_slot *slot; 1356 1357 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1358 if (slot == NULL) 1359 return (0); 1360 kring = na->rx_rings[rxq->ifr_id]; 1361 netmap_fl_refill(rxq, kring, true); 1362 return (1); 1363 } 1364 1365 static void 1366 iflib_netmap_timer(void *arg) 1367 { 1368 iflib_txq_t txq = arg; 1369 if_ctx_t ctx = txq->ift_ctx; 1370 1371 /* 1372 * Wake up the netmap application, to give it a chance to 1373 * call txsync and reclaim more completed TX buffers. 1374 */ 1375 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id); 1376 } 1377 1378 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1379 1380 #else 1381 #define iflib_netmap_txq_init(ctx, txq) (0) 1382 #define iflib_netmap_rxq_init(ctx, rxq) (0) 1383 #define iflib_netmap_detach(ifp) 1384 #define netmap_enable_all_rings(ifp) 1385 #define netmap_disable_all_rings(ifp) 1386 1387 #define iflib_netmap_attach(ctx) (0) 1388 #define netmap_rx_irq(ifp, qid, budget) (0) 1389 #endif 1390 1391 #if defined(__i386__) || defined(__amd64__) 1392 static __inline void 1393 prefetch(void *x) 1394 { 1395 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1396 } 1397 static __inline void 1398 prefetch2cachelines(void *x) 1399 { 1400 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1401 #if (CACHE_LINE_SIZE < 128) 1402 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1403 #endif 1404 } 1405 #else 1406 #define prefetch(x) 1407 #define prefetch2cachelines(x) 1408 #endif 1409 1410 static void 1411 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1412 { 1413 iflib_fl_t fl; 1414 1415 fl = &rxq->ifr_fl[flid]; 1416 iru->iru_paddrs = fl->ifl_bus_addrs; 1417 iru->iru_idxs = fl->ifl_rxd_idxs; 1418 iru->iru_qsidx = rxq->ifr_id; 1419 iru->iru_buf_size = fl->ifl_buf_size; 1420 iru->iru_flidx = fl->ifl_id; 1421 } 1422 1423 static void 1424 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1425 { 1426 if (err) 1427 return; 1428 *(bus_addr_t *) arg = segs[0].ds_addr; 1429 } 1430 1431 int 1432 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1433 { 1434 int err; 1435 device_t dev = ctx->ifc_dev; 1436 1437 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1438 align, 0, /* alignment, bounds */ 1439 BUS_SPACE_MAXADDR, /* lowaddr */ 1440 BUS_SPACE_MAXADDR, /* highaddr */ 1441 NULL, NULL, /* filter, filterarg */ 1442 size, /* maxsize */ 1443 1, /* nsegments */ 1444 size, /* maxsegsize */ 1445 BUS_DMA_ALLOCNOW, /* flags */ 1446 NULL, /* lockfunc */ 1447 NULL, /* lockarg */ 1448 &dma->idi_tag); 1449 if (err) { 1450 device_printf(dev, 1451 "%s: bus_dma_tag_create failed: %d\n", 1452 __func__, err); 1453 goto fail_0; 1454 } 1455 1456 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1457 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1458 if (err) { 1459 device_printf(dev, 1460 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1461 __func__, (uintmax_t)size, err); 1462 goto fail_1; 1463 } 1464 1465 dma->idi_paddr = IF_BAD_DMA; 1466 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1467 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1468 if (err || dma->idi_paddr == IF_BAD_DMA) { 1469 device_printf(dev, 1470 "%s: bus_dmamap_load failed: %d\n", 1471 __func__, err); 1472 goto fail_2; 1473 } 1474 1475 dma->idi_size = size; 1476 return (0); 1477 1478 fail_2: 1479 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1480 fail_1: 1481 bus_dma_tag_destroy(dma->idi_tag); 1482 fail_0: 1483 dma->idi_tag = NULL; 1484 1485 return (err); 1486 } 1487 1488 int 1489 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1490 { 1491 if_shared_ctx_t sctx = ctx->ifc_sctx; 1492 1493 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1494 1495 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1496 } 1497 1498 int 1499 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1500 { 1501 int i, err; 1502 iflib_dma_info_t *dmaiter; 1503 1504 dmaiter = dmalist; 1505 for (i = 0; i < count; i++, dmaiter++) { 1506 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1507 break; 1508 } 1509 if (err) 1510 iflib_dma_free_multi(dmalist, i); 1511 return (err); 1512 } 1513 1514 void 1515 iflib_dma_free(iflib_dma_info_t dma) 1516 { 1517 if (dma->idi_tag == NULL) 1518 return; 1519 if (dma->idi_paddr != IF_BAD_DMA) { 1520 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1521 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1522 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1523 dma->idi_paddr = IF_BAD_DMA; 1524 } 1525 if (dma->idi_vaddr != NULL) { 1526 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1527 dma->idi_vaddr = NULL; 1528 } 1529 bus_dma_tag_destroy(dma->idi_tag); 1530 dma->idi_tag = NULL; 1531 } 1532 1533 void 1534 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1535 { 1536 int i; 1537 iflib_dma_info_t *dmaiter = dmalist; 1538 1539 for (i = 0; i < count; i++, dmaiter++) 1540 iflib_dma_free(*dmaiter); 1541 } 1542 1543 static int 1544 iflib_fast_intr(void *arg) 1545 { 1546 iflib_filter_info_t info = arg; 1547 struct grouptask *gtask = info->ifi_task; 1548 int result; 1549 1550 DBG_COUNTER_INC(fast_intrs); 1551 if (info->ifi_filter != NULL) { 1552 result = info->ifi_filter(info->ifi_filter_arg); 1553 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1554 return (result); 1555 } 1556 1557 GROUPTASK_ENQUEUE(gtask); 1558 return (FILTER_HANDLED); 1559 } 1560 1561 static int 1562 iflib_fast_intr_rxtx(void *arg) 1563 { 1564 iflib_filter_info_t info = arg; 1565 struct grouptask *gtask = info->ifi_task; 1566 if_ctx_t ctx; 1567 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1568 iflib_txq_t txq; 1569 void *sc; 1570 int i, cidx, result; 1571 qidx_t txqid; 1572 bool intr_enable, intr_legacy; 1573 1574 DBG_COUNTER_INC(fast_intrs); 1575 if (info->ifi_filter != NULL) { 1576 result = info->ifi_filter(info->ifi_filter_arg); 1577 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1578 return (result); 1579 } 1580 1581 ctx = rxq->ifr_ctx; 1582 sc = ctx->ifc_softc; 1583 intr_enable = false; 1584 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1585 MPASS(rxq->ifr_ntxqirq); 1586 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1587 txqid = rxq->ifr_txqid[i]; 1588 txq = &ctx->ifc_txqs[txqid]; 1589 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1590 BUS_DMASYNC_POSTREAD); 1591 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1592 if (intr_legacy) 1593 intr_enable = true; 1594 else 1595 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1596 continue; 1597 } 1598 GROUPTASK_ENQUEUE(&txq->ift_task); 1599 } 1600 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1601 cidx = rxq->ifr_cq_cidx; 1602 else 1603 cidx = rxq->ifr_fl[0].ifl_cidx; 1604 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1605 GROUPTASK_ENQUEUE(gtask); 1606 else { 1607 if (intr_legacy) 1608 intr_enable = true; 1609 else 1610 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1611 DBG_COUNTER_INC(rx_intr_enables); 1612 } 1613 if (intr_enable) 1614 IFDI_INTR_ENABLE(ctx); 1615 return (FILTER_HANDLED); 1616 } 1617 1618 static int 1619 iflib_fast_intr_ctx(void *arg) 1620 { 1621 iflib_filter_info_t info = arg; 1622 struct grouptask *gtask = info->ifi_task; 1623 int result; 1624 1625 DBG_COUNTER_INC(fast_intrs); 1626 if (info->ifi_filter != NULL) { 1627 result = info->ifi_filter(info->ifi_filter_arg); 1628 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1629 return (result); 1630 } 1631 1632 GROUPTASK_ENQUEUE(gtask); 1633 return (FILTER_HANDLED); 1634 } 1635 1636 static int 1637 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1638 driver_filter_t filter, driver_intr_t handler, void *arg, 1639 const char *name) 1640 { 1641 struct resource *res; 1642 void *tag = NULL; 1643 device_t dev = ctx->ifc_dev; 1644 int flags, i, rc; 1645 1646 flags = RF_ACTIVE; 1647 if (ctx->ifc_flags & IFC_LEGACY) 1648 flags |= RF_SHAREABLE; 1649 MPASS(rid < 512); 1650 i = rid; 1651 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1652 if (res == NULL) { 1653 device_printf(dev, 1654 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1655 return (ENOMEM); 1656 } 1657 irq->ii_res = res; 1658 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1659 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1660 filter, handler, arg, &tag); 1661 if (rc != 0) { 1662 device_printf(dev, 1663 "failed to setup interrupt for rid %d, name %s: %d\n", 1664 rid, name ? name : "unknown", rc); 1665 return (rc); 1666 } else if (name) 1667 bus_describe_intr(dev, res, tag, "%s", name); 1668 1669 irq->ii_tag = tag; 1670 return (0); 1671 } 1672 1673 /********************************************************************* 1674 * 1675 * Allocate DMA resources for TX buffers as well as memory for the TX 1676 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1677 * iflib_sw_tx_desc_array structure, storing all the information that 1678 * is needed to transmit a packet on the wire. This is called only 1679 * once at attach, setup is done every reset. 1680 * 1681 **********************************************************************/ 1682 static int 1683 iflib_txsd_alloc(iflib_txq_t txq) 1684 { 1685 if_ctx_t ctx = txq->ift_ctx; 1686 if_shared_ctx_t sctx = ctx->ifc_sctx; 1687 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1688 device_t dev = ctx->ifc_dev; 1689 bus_size_t tsomaxsize; 1690 int err, nsegments, ntsosegments; 1691 bool tso; 1692 1693 nsegments = scctx->isc_tx_nsegments; 1694 ntsosegments = scctx->isc_tx_tso_segments_max; 1695 tsomaxsize = scctx->isc_tx_tso_size_max; 1696 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1697 tsomaxsize += sizeof(struct ether_vlan_header); 1698 MPASS(scctx->isc_ntxd[0] > 0); 1699 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1700 MPASS(nsegments > 0); 1701 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1702 MPASS(ntsosegments > 0); 1703 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1704 } 1705 1706 /* 1707 * Set up DMA tags for TX buffers. 1708 */ 1709 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1710 1, 0, /* alignment, bounds */ 1711 BUS_SPACE_MAXADDR, /* lowaddr */ 1712 BUS_SPACE_MAXADDR, /* highaddr */ 1713 NULL, NULL, /* filter, filterarg */ 1714 sctx->isc_tx_maxsize, /* maxsize */ 1715 nsegments, /* nsegments */ 1716 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1717 0, /* flags */ 1718 NULL, /* lockfunc */ 1719 NULL, /* lockfuncarg */ 1720 &txq->ift_buf_tag))) { 1721 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1722 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1723 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1724 goto fail; 1725 } 1726 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1727 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1728 1, 0, /* alignment, bounds */ 1729 BUS_SPACE_MAXADDR, /* lowaddr */ 1730 BUS_SPACE_MAXADDR, /* highaddr */ 1731 NULL, NULL, /* filter, filterarg */ 1732 tsomaxsize, /* maxsize */ 1733 ntsosegments, /* nsegments */ 1734 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1735 0, /* flags */ 1736 NULL, /* lockfunc */ 1737 NULL, /* lockfuncarg */ 1738 &txq->ift_tso_buf_tag))) { 1739 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1740 err); 1741 goto fail; 1742 } 1743 1744 /* Allocate memory for the TX mbuf map. */ 1745 if (!(txq->ift_sds.ifsd_m = 1746 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1747 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1748 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1749 err = ENOMEM; 1750 goto fail; 1751 } 1752 1753 /* 1754 * Create the DMA maps for TX buffers. 1755 */ 1756 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1757 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1758 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1759 device_printf(dev, 1760 "Unable to allocate TX buffer DMA map memory\n"); 1761 err = ENOMEM; 1762 goto fail; 1763 } 1764 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1765 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1766 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1767 device_printf(dev, 1768 "Unable to allocate TSO TX buffer map memory\n"); 1769 err = ENOMEM; 1770 goto fail; 1771 } 1772 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1773 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1774 &txq->ift_sds.ifsd_map[i]); 1775 if (err != 0) { 1776 device_printf(dev, "Unable to create TX DMA map\n"); 1777 goto fail; 1778 } 1779 if (!tso) 1780 continue; 1781 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1782 &txq->ift_sds.ifsd_tso_map[i]); 1783 if (err != 0) { 1784 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1785 goto fail; 1786 } 1787 } 1788 return (0); 1789 fail: 1790 /* We free all, it handles case where we are in the middle */ 1791 iflib_tx_structures_free(ctx); 1792 return (err); 1793 } 1794 1795 static void 1796 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1797 { 1798 bus_dmamap_t map; 1799 1800 if (txq->ift_sds.ifsd_map != NULL) { 1801 map = txq->ift_sds.ifsd_map[i]; 1802 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1803 bus_dmamap_unload(txq->ift_buf_tag, map); 1804 bus_dmamap_destroy(txq->ift_buf_tag, map); 1805 txq->ift_sds.ifsd_map[i] = NULL; 1806 } 1807 1808 if (txq->ift_sds.ifsd_tso_map != NULL) { 1809 map = txq->ift_sds.ifsd_tso_map[i]; 1810 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1811 BUS_DMASYNC_POSTWRITE); 1812 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1813 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1814 txq->ift_sds.ifsd_tso_map[i] = NULL; 1815 } 1816 } 1817 1818 static void 1819 iflib_txq_destroy(iflib_txq_t txq) 1820 { 1821 if_ctx_t ctx = txq->ift_ctx; 1822 1823 for (int i = 0; i < txq->ift_size; i++) 1824 iflib_txsd_destroy(ctx, txq, i); 1825 1826 if (txq->ift_br != NULL) { 1827 ifmp_ring_free(txq->ift_br); 1828 txq->ift_br = NULL; 1829 } 1830 1831 mtx_destroy(&txq->ift_mtx); 1832 1833 if (txq->ift_sds.ifsd_map != NULL) { 1834 free(txq->ift_sds.ifsd_map, M_IFLIB); 1835 txq->ift_sds.ifsd_map = NULL; 1836 } 1837 if (txq->ift_sds.ifsd_tso_map != NULL) { 1838 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1839 txq->ift_sds.ifsd_tso_map = NULL; 1840 } 1841 if (txq->ift_sds.ifsd_m != NULL) { 1842 free(txq->ift_sds.ifsd_m, M_IFLIB); 1843 txq->ift_sds.ifsd_m = NULL; 1844 } 1845 if (txq->ift_buf_tag != NULL) { 1846 bus_dma_tag_destroy(txq->ift_buf_tag); 1847 txq->ift_buf_tag = NULL; 1848 } 1849 if (txq->ift_tso_buf_tag != NULL) { 1850 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1851 txq->ift_tso_buf_tag = NULL; 1852 } 1853 if (txq->ift_ifdi != NULL) { 1854 free(txq->ift_ifdi, M_IFLIB); 1855 } 1856 } 1857 1858 static void 1859 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1860 { 1861 struct mbuf **mp; 1862 1863 mp = &txq->ift_sds.ifsd_m[i]; 1864 if (*mp == NULL) 1865 return; 1866 1867 if (txq->ift_sds.ifsd_map != NULL) { 1868 bus_dmamap_sync(txq->ift_buf_tag, 1869 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1870 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1871 } 1872 if (txq->ift_sds.ifsd_tso_map != NULL) { 1873 bus_dmamap_sync(txq->ift_tso_buf_tag, 1874 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1875 bus_dmamap_unload(txq->ift_tso_buf_tag, 1876 txq->ift_sds.ifsd_tso_map[i]); 1877 } 1878 m_freem(*mp); 1879 DBG_COUNTER_INC(tx_frees); 1880 *mp = NULL; 1881 } 1882 1883 static int 1884 iflib_txq_setup(iflib_txq_t txq) 1885 { 1886 if_ctx_t ctx = txq->ift_ctx; 1887 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1888 if_shared_ctx_t sctx = ctx->ifc_sctx; 1889 iflib_dma_info_t di; 1890 int i; 1891 1892 /* Set number of descriptors available */ 1893 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1894 /* XXX make configurable */ 1895 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1896 1897 /* Reset indices */ 1898 txq->ift_cidx_processed = 0; 1899 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1900 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1901 1902 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1903 bzero((void *)di->idi_vaddr, di->idi_size); 1904 1905 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1906 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1907 bus_dmamap_sync(di->idi_tag, di->idi_map, 1908 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1909 return (0); 1910 } 1911 1912 /********************************************************************* 1913 * 1914 * Allocate DMA resources for RX buffers as well as memory for the RX 1915 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1916 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1917 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1918 * Since we use use one entry in iflib_sw_rx_desc_array per received 1919 * packet, the maximum number of entries we'll need is equal to the 1920 * number of hardware receive descriptors that we've allocated. 1921 * 1922 **********************************************************************/ 1923 static int 1924 iflib_rxsd_alloc(iflib_rxq_t rxq) 1925 { 1926 if_ctx_t ctx = rxq->ifr_ctx; 1927 if_shared_ctx_t sctx = ctx->ifc_sctx; 1928 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1929 device_t dev = ctx->ifc_dev; 1930 iflib_fl_t fl; 1931 int err; 1932 1933 MPASS(scctx->isc_nrxd[0] > 0); 1934 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1935 1936 fl = rxq->ifr_fl; 1937 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1938 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1939 /* Set up DMA tag for RX buffers. */ 1940 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1941 1, 0, /* alignment, bounds */ 1942 BUS_SPACE_MAXADDR, /* lowaddr */ 1943 BUS_SPACE_MAXADDR, /* highaddr */ 1944 NULL, NULL, /* filter, filterarg */ 1945 sctx->isc_rx_maxsize, /* maxsize */ 1946 sctx->isc_rx_nsegments, /* nsegments */ 1947 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1948 0, /* flags */ 1949 NULL, /* lockfunc */ 1950 NULL, /* lockarg */ 1951 &fl->ifl_buf_tag); 1952 if (err) { 1953 device_printf(dev, 1954 "Unable to allocate RX DMA tag: %d\n", err); 1955 goto fail; 1956 } 1957 1958 /* Allocate memory for the RX mbuf map. */ 1959 if (!(fl->ifl_sds.ifsd_m = 1960 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1961 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1962 device_printf(dev, 1963 "Unable to allocate RX mbuf map memory\n"); 1964 err = ENOMEM; 1965 goto fail; 1966 } 1967 1968 /* Allocate memory for the direct RX cluster pointer map. */ 1969 if (!(fl->ifl_sds.ifsd_cl = 1970 (caddr_t *) malloc(sizeof(caddr_t) * 1971 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1972 device_printf(dev, 1973 "Unable to allocate RX cluster map memory\n"); 1974 err = ENOMEM; 1975 goto fail; 1976 } 1977 1978 /* Allocate memory for the RX cluster bus address map. */ 1979 if (!(fl->ifl_sds.ifsd_ba = 1980 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1981 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1982 device_printf(dev, 1983 "Unable to allocate RX bus address map memory\n"); 1984 err = ENOMEM; 1985 goto fail; 1986 } 1987 1988 /* 1989 * Create the DMA maps for RX buffers. 1990 */ 1991 if (!(fl->ifl_sds.ifsd_map = 1992 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1993 device_printf(dev, 1994 "Unable to allocate RX buffer DMA map memory\n"); 1995 err = ENOMEM; 1996 goto fail; 1997 } 1998 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1999 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 2000 &fl->ifl_sds.ifsd_map[i]); 2001 if (err != 0) { 2002 device_printf(dev, "Unable to create RX buffer DMA map\n"); 2003 goto fail; 2004 } 2005 } 2006 } 2007 return (0); 2008 2009 fail: 2010 iflib_rx_structures_free(ctx); 2011 return (err); 2012 } 2013 2014 /* 2015 * Internal service routines 2016 */ 2017 2018 struct rxq_refill_cb_arg { 2019 int error; 2020 bus_dma_segment_t seg; 2021 int nseg; 2022 }; 2023 2024 static void 2025 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2026 { 2027 struct rxq_refill_cb_arg *cb_arg = arg; 2028 2029 cb_arg->error = error; 2030 cb_arg->seg = segs[0]; 2031 cb_arg->nseg = nseg; 2032 } 2033 2034 /** 2035 * iflib_fl_refill - refill an rxq free-buffer list 2036 * @ctx: the iflib context 2037 * @fl: the free list to refill 2038 * @count: the number of new buffers to allocate 2039 * 2040 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 2041 * The caller must assure that @count does not exceed the queue's capacity 2042 * minus one (since we always leave a descriptor unavailable). 2043 */ 2044 static uint8_t 2045 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 2046 { 2047 struct if_rxd_update iru; 2048 struct rxq_refill_cb_arg cb_arg; 2049 struct mbuf *m; 2050 caddr_t cl, *sd_cl; 2051 struct mbuf **sd_m; 2052 bus_dmamap_t *sd_map; 2053 bus_addr_t bus_addr, *sd_ba; 2054 int err, frag_idx, i, idx, n, pidx; 2055 qidx_t credits; 2056 2057 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1); 2058 2059 sd_m = fl->ifl_sds.ifsd_m; 2060 sd_map = fl->ifl_sds.ifsd_map; 2061 sd_cl = fl->ifl_sds.ifsd_cl; 2062 sd_ba = fl->ifl_sds.ifsd_ba; 2063 pidx = fl->ifl_pidx; 2064 idx = pidx; 2065 frag_idx = fl->ifl_fragidx; 2066 credits = fl->ifl_credits; 2067 2068 i = 0; 2069 n = count; 2070 MPASS(n > 0); 2071 MPASS(credits + n <= fl->ifl_size); 2072 2073 if (pidx < fl->ifl_cidx) 2074 MPASS(pidx + n <= fl->ifl_cidx); 2075 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 2076 MPASS(fl->ifl_gen == 0); 2077 if (pidx > fl->ifl_cidx) 2078 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 2079 2080 DBG_COUNTER_INC(fl_refills); 2081 if (n > 8) 2082 DBG_COUNTER_INC(fl_refills_large); 2083 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 2084 while (n-- > 0) { 2085 /* 2086 * We allocate an uninitialized mbuf + cluster, mbuf is 2087 * initialized after rx. 2088 * 2089 * If the cluster is still set then we know a minimum sized 2090 * packet was received 2091 */ 2092 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 2093 &frag_idx); 2094 if (frag_idx < 0) 2095 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2096 MPASS(frag_idx >= 0); 2097 if ((cl = sd_cl[frag_idx]) == NULL) { 2098 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT); 2099 if (__predict_false(cl == NULL)) 2100 break; 2101 2102 cb_arg.error = 0; 2103 MPASS(sd_map != NULL); 2104 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2105 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2106 BUS_DMA_NOWAIT); 2107 if (__predict_false(err != 0 || cb_arg.error)) { 2108 uma_zfree(fl->ifl_zone, cl); 2109 break; 2110 } 2111 2112 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2113 sd_cl[frag_idx] = cl; 2114 #if MEMORY_LOGGING 2115 fl->ifl_cl_enqueued++; 2116 #endif 2117 } else { 2118 bus_addr = sd_ba[frag_idx]; 2119 } 2120 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2121 BUS_DMASYNC_PREREAD); 2122 2123 if (sd_m[frag_idx] == NULL) { 2124 m = m_gethdr(M_NOWAIT, MT_NOINIT); 2125 if (__predict_false(m == NULL)) 2126 break; 2127 sd_m[frag_idx] = m; 2128 } 2129 bit_set(fl->ifl_rx_bitmap, frag_idx); 2130 #if MEMORY_LOGGING 2131 fl->ifl_m_enqueued++; 2132 #endif 2133 2134 DBG_COUNTER_INC(rx_allocs); 2135 fl->ifl_rxd_idxs[i] = frag_idx; 2136 fl->ifl_bus_addrs[i] = bus_addr; 2137 credits++; 2138 i++; 2139 MPASS(credits <= fl->ifl_size); 2140 if (++idx == fl->ifl_size) { 2141 #ifdef INVARIANTS 2142 fl->ifl_gen = 1; 2143 #endif 2144 idx = 0; 2145 } 2146 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2147 iru.iru_pidx = pidx; 2148 iru.iru_count = i; 2149 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2150 fl->ifl_pidx = idx; 2151 fl->ifl_credits = credits; 2152 pidx = idx; 2153 i = 0; 2154 } 2155 } 2156 2157 if (n < count - 1) { 2158 if (i != 0) { 2159 iru.iru_pidx = pidx; 2160 iru.iru_count = i; 2161 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2162 fl->ifl_pidx = idx; 2163 fl->ifl_credits = credits; 2164 } 2165 DBG_COUNTER_INC(rxd_flush); 2166 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2167 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2168 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, 2169 fl->ifl_id, fl->ifl_pidx); 2170 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) { 2171 fl->ifl_fragidx = frag_idx + 1; 2172 if (fl->ifl_fragidx == fl->ifl_size) 2173 fl->ifl_fragidx = 0; 2174 } else { 2175 fl->ifl_fragidx = frag_idx; 2176 } 2177 } 2178 2179 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2180 } 2181 2182 static inline uint8_t 2183 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2184 { 2185 /* 2186 * We leave an unused descriptor to avoid pidx to catch up with cidx. 2187 * This is important as it confuses most NICs. For instance, 2188 * Intel NICs have (per receive ring) RDH and RDT registers, where 2189 * RDH points to the next receive descriptor to be used by the NIC, 2190 * and RDT for the next receive descriptor to be published by the 2191 * driver to the NIC (RDT - 1 is thus the last valid one). 2192 * The condition RDH == RDT means no descriptors are available to 2193 * the NIC, and thus it would be ambiguous if it also meant that 2194 * all the descriptors are available to the NIC. 2195 */ 2196 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2197 #ifdef INVARIANTS 2198 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2199 #endif 2200 2201 MPASS(fl->ifl_credits <= fl->ifl_size); 2202 MPASS(reclaimable == delta); 2203 2204 if (reclaimable > 0) 2205 return (iflib_fl_refill(ctx, fl, reclaimable)); 2206 return (0); 2207 } 2208 2209 uint8_t 2210 iflib_in_detach(if_ctx_t ctx) 2211 { 2212 bool in_detach; 2213 2214 STATE_LOCK(ctx); 2215 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2216 STATE_UNLOCK(ctx); 2217 return (in_detach); 2218 } 2219 2220 static void 2221 iflib_fl_bufs_free(iflib_fl_t fl) 2222 { 2223 iflib_dma_info_t idi = fl->ifl_ifdi; 2224 bus_dmamap_t sd_map; 2225 uint32_t i; 2226 2227 for (i = 0; i < fl->ifl_size; i++) { 2228 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2229 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2230 2231 if (*sd_cl != NULL) { 2232 sd_map = fl->ifl_sds.ifsd_map[i]; 2233 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2234 BUS_DMASYNC_POSTREAD); 2235 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2236 uma_zfree(fl->ifl_zone, *sd_cl); 2237 *sd_cl = NULL; 2238 if (*sd_m != NULL) { 2239 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2240 m_free_raw(*sd_m); 2241 *sd_m = NULL; 2242 } 2243 } else { 2244 MPASS(*sd_m == NULL); 2245 } 2246 #if MEMORY_LOGGING 2247 fl->ifl_m_dequeued++; 2248 fl->ifl_cl_dequeued++; 2249 #endif 2250 } 2251 #ifdef INVARIANTS 2252 for (i = 0; i < fl->ifl_size; i++) { 2253 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2254 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2255 } 2256 #endif 2257 /* 2258 * Reset free list values 2259 */ 2260 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2261 bzero(idi->idi_vaddr, idi->idi_size); 2262 } 2263 2264 /********************************************************************* 2265 * 2266 * Initialize a free list and its buffers. 2267 * 2268 **********************************************************************/ 2269 static int 2270 iflib_fl_setup(iflib_fl_t fl) 2271 { 2272 iflib_rxq_t rxq = fl->ifl_rxq; 2273 if_ctx_t ctx = rxq->ifr_ctx; 2274 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2275 int qidx; 2276 2277 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2278 /* 2279 ** Free current RX buffer structs and their mbufs 2280 */ 2281 iflib_fl_bufs_free(fl); 2282 /* Now replenish the mbufs */ 2283 MPASS(fl->ifl_credits == 0); 2284 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2285 if (scctx->isc_rxd_buf_size[qidx] != 0) 2286 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2287 else 2288 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2289 /* 2290 * ifl_buf_size may be a driver-supplied value, so pull it up 2291 * to the selected mbuf size. 2292 */ 2293 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2294 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2295 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2296 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2297 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2298 2299 /* 2300 * Avoid pre-allocating zillions of clusters to an idle card 2301 * potentially speeding up attach. In any case make sure 2302 * to leave a descriptor unavailable. See the comment in 2303 * iflib_fl_refill_all(). 2304 */ 2305 MPASS(fl->ifl_size > 0); 2306 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1)); 2307 if (min(128, fl->ifl_size - 1) != fl->ifl_credits) 2308 return (ENOBUFS); 2309 /* 2310 * handle failure 2311 */ 2312 MPASS(rxq != NULL); 2313 MPASS(fl->ifl_ifdi != NULL); 2314 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2315 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2316 return (0); 2317 } 2318 2319 /********************************************************************* 2320 * 2321 * Free receive ring data structures 2322 * 2323 **********************************************************************/ 2324 static void 2325 iflib_rx_sds_free(iflib_rxq_t rxq) 2326 { 2327 iflib_fl_t fl; 2328 int i, j; 2329 2330 if (rxq->ifr_fl != NULL) { 2331 for (i = 0; i < rxq->ifr_nfl; i++) { 2332 fl = &rxq->ifr_fl[i]; 2333 if (fl->ifl_buf_tag != NULL) { 2334 if (fl->ifl_sds.ifsd_map != NULL) { 2335 for (j = 0; j < fl->ifl_size; j++) { 2336 bus_dmamap_sync( 2337 fl->ifl_buf_tag, 2338 fl->ifl_sds.ifsd_map[j], 2339 BUS_DMASYNC_POSTREAD); 2340 bus_dmamap_unload( 2341 fl->ifl_buf_tag, 2342 fl->ifl_sds.ifsd_map[j]); 2343 bus_dmamap_destroy( 2344 fl->ifl_buf_tag, 2345 fl->ifl_sds.ifsd_map[j]); 2346 } 2347 } 2348 bus_dma_tag_destroy(fl->ifl_buf_tag); 2349 fl->ifl_buf_tag = NULL; 2350 } 2351 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2352 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2353 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2354 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2355 free(fl->ifl_rx_bitmap, M_IFLIB); 2356 fl->ifl_sds.ifsd_m = NULL; 2357 fl->ifl_sds.ifsd_cl = NULL; 2358 fl->ifl_sds.ifsd_ba = NULL; 2359 fl->ifl_sds.ifsd_map = NULL; 2360 fl->ifl_rx_bitmap = NULL; 2361 } 2362 free(rxq->ifr_fl, M_IFLIB); 2363 rxq->ifr_fl = NULL; 2364 free(rxq->ifr_ifdi, M_IFLIB); 2365 rxq->ifr_ifdi = NULL; 2366 rxq->ifr_cq_cidx = 0; 2367 } 2368 } 2369 2370 /* 2371 * Timer routine 2372 */ 2373 static void 2374 iflib_timer(void *arg) 2375 { 2376 iflib_txq_t txq = arg; 2377 if_ctx_t ctx = txq->ift_ctx; 2378 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2379 uint64_t this_tick = ticks; 2380 2381 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2382 return; 2383 2384 /* 2385 ** Check on the state of the TX queue(s), this 2386 ** can be done without the lock because its RO 2387 ** and the HUNG state will be static if set. 2388 */ 2389 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) { 2390 txq->ift_last_timer_tick = this_tick; 2391 IFDI_TIMER(ctx, txq->ift_id); 2392 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2393 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2394 (sctx->isc_pause_frames == 0))) 2395 goto hung; 2396 2397 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2398 ifmp_ring_is_stalled(txq->ift_br)) { 2399 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, 2400 ("queue can't be marked as hung if interface is down")); 2401 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2402 } 2403 txq->ift_cleaned_prev = txq->ift_cleaned; 2404 } 2405 /* handle any laggards */ 2406 if (txq->ift_db_pending) 2407 GROUPTASK_ENQUEUE(&txq->ift_task); 2408 2409 sctx->isc_pause_frames = 0; 2410 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2411 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, 2412 txq, txq->ift_timer.c_cpu); 2413 return; 2414 2415 hung: 2416 device_printf(ctx->ifc_dev, 2417 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2418 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2419 STATE_LOCK(ctx); 2420 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2421 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2422 iflib_admin_intr_deferred(ctx); 2423 STATE_UNLOCK(ctx); 2424 } 2425 2426 static uint16_t 2427 iflib_get_mbuf_size_for(unsigned int size) 2428 { 2429 2430 if (size <= MCLBYTES) 2431 return (MCLBYTES); 2432 else 2433 return (MJUMPAGESIZE); 2434 } 2435 2436 static void 2437 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2438 { 2439 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2440 2441 /* 2442 * XXX don't set the max_frame_size to larger 2443 * than the hardware can handle 2444 */ 2445 ctx->ifc_rx_mbuf_sz = 2446 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2447 } 2448 2449 uint32_t 2450 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2451 { 2452 2453 return (ctx->ifc_rx_mbuf_sz); 2454 } 2455 2456 static void 2457 iflib_init_locked(if_ctx_t ctx) 2458 { 2459 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2460 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2461 if_t ifp = ctx->ifc_ifp; 2462 iflib_fl_t fl; 2463 iflib_txq_t txq; 2464 iflib_rxq_t rxq; 2465 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2466 2467 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2468 IFDI_INTR_DISABLE(ctx); 2469 2470 /* 2471 * See iflib_stop(). Useful in case iflib_init_locked() is 2472 * called without first calling iflib_stop(). 2473 */ 2474 netmap_disable_all_rings(ifp); 2475 2476 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2477 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2478 /* Set hardware offload abilities */ 2479 if_clearhwassist(ifp); 2480 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2481 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2482 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2483 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2484 if (if_getcapenable(ifp) & IFCAP_TSO4) 2485 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2486 if (if_getcapenable(ifp) & IFCAP_TSO6) 2487 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2488 2489 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2490 CALLOUT_LOCK(txq); 2491 callout_stop(&txq->ift_timer); 2492 #ifdef DEV_NETMAP 2493 callout_stop(&txq->ift_netmap_timer); 2494 #endif /* DEV_NETMAP */ 2495 CALLOUT_UNLOCK(txq); 2496 iflib_netmap_txq_init(ctx, txq); 2497 } 2498 2499 /* 2500 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2501 * that drivers can use the value when setting up the hardware receive 2502 * buffers. 2503 */ 2504 iflib_calc_rx_mbuf_sz(ctx); 2505 2506 #ifdef INVARIANTS 2507 i = if_getdrvflags(ifp); 2508 #endif 2509 IFDI_INIT(ctx); 2510 MPASS(if_getdrvflags(ifp) == i); 2511 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2512 if (iflib_netmap_rxq_init(ctx, rxq) > 0) { 2513 /* This rxq is in netmap mode. Skip normal init. */ 2514 continue; 2515 } 2516 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2517 if (iflib_fl_setup(fl)) { 2518 device_printf(ctx->ifc_dev, 2519 "setting up free list %d failed - " 2520 "check cluster settings\n", j); 2521 goto done; 2522 } 2523 } 2524 } 2525 done: 2526 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2527 IFDI_INTR_ENABLE(ctx); 2528 txq = ctx->ifc_txqs; 2529 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2530 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 2531 txq->ift_timer.c_cpu); 2532 2533 /* Re-enable txsync/rxsync. */ 2534 netmap_enable_all_rings(ifp); 2535 } 2536 2537 static int 2538 iflib_media_change(if_t ifp) 2539 { 2540 if_ctx_t ctx = if_getsoftc(ifp); 2541 int err; 2542 2543 CTX_LOCK(ctx); 2544 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2545 iflib_if_init_locked(ctx); 2546 CTX_UNLOCK(ctx); 2547 return (err); 2548 } 2549 2550 static void 2551 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2552 { 2553 if_ctx_t ctx = if_getsoftc(ifp); 2554 2555 CTX_LOCK(ctx); 2556 IFDI_UPDATE_ADMIN_STATUS(ctx); 2557 IFDI_MEDIA_STATUS(ctx, ifmr); 2558 CTX_UNLOCK(ctx); 2559 } 2560 2561 void 2562 iflib_stop(if_ctx_t ctx) 2563 { 2564 iflib_txq_t txq = ctx->ifc_txqs; 2565 iflib_rxq_t rxq = ctx->ifc_rxqs; 2566 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2567 if_shared_ctx_t sctx = ctx->ifc_sctx; 2568 iflib_dma_info_t di; 2569 iflib_fl_t fl; 2570 int i, j; 2571 2572 /* Tell the stack that the interface is no longer active */ 2573 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2574 2575 IFDI_INTR_DISABLE(ctx); 2576 DELAY(1000); 2577 IFDI_STOP(ctx); 2578 DELAY(1000); 2579 2580 /* 2581 * Stop any pending txsync/rxsync and prevent new ones 2582 * form starting. Processes blocked in poll() will get 2583 * POLLERR. 2584 */ 2585 netmap_disable_all_rings(ctx->ifc_ifp); 2586 2587 iflib_debug_reset(); 2588 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2589 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2590 /* make sure all transmitters have completed before proceeding XXX */ 2591 2592 CALLOUT_LOCK(txq); 2593 callout_stop(&txq->ift_timer); 2594 #ifdef DEV_NETMAP 2595 callout_stop(&txq->ift_netmap_timer); 2596 #endif /* DEV_NETMAP */ 2597 CALLOUT_UNLOCK(txq); 2598 2599 /* clean any enqueued buffers */ 2600 iflib_ifmp_purge(txq); 2601 /* Free any existing tx buffers. */ 2602 for (j = 0; j < txq->ift_size; j++) { 2603 iflib_txsd_free(ctx, txq, j); 2604 } 2605 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2606 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2607 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2608 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2609 txq->ift_pullups = 0; 2610 ifmp_ring_reset_stats(txq->ift_br); 2611 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2612 bzero((void *)di->idi_vaddr, di->idi_size); 2613 } 2614 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2615 gtaskqueue_drain(rxq->ifr_task.gt_taskqueue, 2616 &rxq->ifr_task.gt_task); 2617 2618 rxq->ifr_cq_cidx = 0; 2619 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2620 bzero((void *)di->idi_vaddr, di->idi_size); 2621 /* also resets the free lists pidx/cidx */ 2622 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2623 iflib_fl_bufs_free(fl); 2624 } 2625 } 2626 2627 static inline caddr_t 2628 calc_next_rxd(iflib_fl_t fl, int cidx) 2629 { 2630 qidx_t size; 2631 int nrxd; 2632 caddr_t start, end, cur, next; 2633 2634 nrxd = fl->ifl_size; 2635 size = fl->ifl_rxd_size; 2636 start = fl->ifl_ifdi->idi_vaddr; 2637 2638 if (__predict_false(size == 0)) 2639 return (start); 2640 cur = start + size*cidx; 2641 end = start + size*nrxd; 2642 next = CACHE_PTR_NEXT(cur); 2643 return (next < end ? next : start); 2644 } 2645 2646 static inline void 2647 prefetch_pkts(iflib_fl_t fl, int cidx) 2648 { 2649 int nextptr; 2650 int nrxd = fl->ifl_size; 2651 caddr_t next_rxd; 2652 2653 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2654 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2655 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2656 next_rxd = calc_next_rxd(fl, cidx); 2657 prefetch(next_rxd); 2658 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2659 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2660 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2661 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2662 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2663 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2664 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2665 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2666 } 2667 2668 static struct mbuf * 2669 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2670 int *pf_rv, if_rxd_info_t ri) 2671 { 2672 bus_dmamap_t map; 2673 iflib_fl_t fl; 2674 caddr_t payload; 2675 struct mbuf *m; 2676 int flid, cidx, len, next; 2677 2678 map = NULL; 2679 flid = irf->irf_flid; 2680 cidx = irf->irf_idx; 2681 fl = &rxq->ifr_fl[flid]; 2682 sd->ifsd_fl = fl; 2683 m = fl->ifl_sds.ifsd_m[cidx]; 2684 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2685 fl->ifl_credits--; 2686 #if MEMORY_LOGGING 2687 fl->ifl_m_dequeued++; 2688 #endif 2689 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2690 prefetch_pkts(fl, cidx); 2691 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2692 prefetch(&fl->ifl_sds.ifsd_map[next]); 2693 map = fl->ifl_sds.ifsd_map[cidx]; 2694 2695 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2696 2697 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2698 irf->irf_len != 0) { 2699 payload = *sd->ifsd_cl; 2700 payload += ri->iri_pad; 2701 len = ri->iri_len - ri->iri_pad; 2702 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2703 len | PFIL_MEMPTR | PFIL_IN, NULL); 2704 switch (*pf_rv) { 2705 case PFIL_DROPPED: 2706 case PFIL_CONSUMED: 2707 /* 2708 * The filter ate it. Everything is recycled. 2709 */ 2710 m = NULL; 2711 unload = 0; 2712 break; 2713 case PFIL_REALLOCED: 2714 /* 2715 * The filter copied it. Everything is recycled. 2716 */ 2717 m = pfil_mem2mbuf(payload); 2718 unload = 0; 2719 break; 2720 case PFIL_PASS: 2721 /* 2722 * Filter said it was OK, so receive like 2723 * normal 2724 */ 2725 fl->ifl_sds.ifsd_m[cidx] = NULL; 2726 break; 2727 default: 2728 MPASS(0); 2729 } 2730 } else { 2731 fl->ifl_sds.ifsd_m[cidx] = NULL; 2732 if (pf_rv != NULL) 2733 *pf_rv = PFIL_PASS; 2734 } 2735 2736 if (unload && irf->irf_len != 0) 2737 bus_dmamap_unload(fl->ifl_buf_tag, map); 2738 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2739 if (__predict_false(fl->ifl_cidx == 0)) 2740 fl->ifl_gen = 0; 2741 bit_clear(fl->ifl_rx_bitmap, cidx); 2742 return (m); 2743 } 2744 2745 static struct mbuf * 2746 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2747 { 2748 struct mbuf *m, *mh, *mt; 2749 caddr_t cl; 2750 int *pf_rv_ptr, flags, i, padlen; 2751 bool consumed; 2752 2753 i = 0; 2754 mh = NULL; 2755 consumed = false; 2756 *pf_rv = PFIL_PASS; 2757 pf_rv_ptr = pf_rv; 2758 do { 2759 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2760 pf_rv_ptr, ri); 2761 2762 MPASS(*sd->ifsd_cl != NULL); 2763 2764 /* 2765 * Exclude zero-length frags & frags from 2766 * packets the filter has consumed or dropped 2767 */ 2768 if (ri->iri_frags[i].irf_len == 0 || consumed || 2769 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2770 if (mh == NULL) { 2771 /* everything saved here */ 2772 consumed = true; 2773 pf_rv_ptr = NULL; 2774 continue; 2775 } 2776 /* XXX we can save the cluster here, but not the mbuf */ 2777 m_init(m, M_NOWAIT, MT_DATA, 0); 2778 m_free(m); 2779 continue; 2780 } 2781 if (mh == NULL) { 2782 flags = M_PKTHDR|M_EXT; 2783 mh = mt = m; 2784 padlen = ri->iri_pad; 2785 } else { 2786 flags = M_EXT; 2787 mt->m_next = m; 2788 mt = m; 2789 /* assuming padding is only on the first fragment */ 2790 padlen = 0; 2791 } 2792 cl = *sd->ifsd_cl; 2793 *sd->ifsd_cl = NULL; 2794 2795 /* Can these two be made one ? */ 2796 m_init(m, M_NOWAIT, MT_DATA, flags); 2797 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2798 /* 2799 * These must follow m_init and m_cljset 2800 */ 2801 m->m_data += padlen; 2802 ri->iri_len -= padlen; 2803 m->m_len = ri->iri_frags[i].irf_len; 2804 } while (++i < ri->iri_nfrags); 2805 2806 return (mh); 2807 } 2808 2809 /* 2810 * Process one software descriptor 2811 */ 2812 static struct mbuf * 2813 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2814 { 2815 struct if_rxsd sd; 2816 struct mbuf *m; 2817 int pf_rv; 2818 2819 /* should I merge this back in now that the two paths are basically duplicated? */ 2820 if (ri->iri_nfrags == 1 && 2821 ri->iri_frags[0].irf_len != 0 && 2822 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2823 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2824 &pf_rv, ri); 2825 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2826 return (m); 2827 if (pf_rv == PFIL_PASS) { 2828 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2829 #ifndef __NO_STRICT_ALIGNMENT 2830 if (!IP_ALIGNED(m)) 2831 m->m_data += 2; 2832 #endif 2833 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2834 m->m_len = ri->iri_frags[0].irf_len; 2835 } 2836 } else { 2837 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2838 if (m == NULL) 2839 return (NULL); 2840 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2841 return (m); 2842 } 2843 m->m_pkthdr.len = ri->iri_len; 2844 m->m_pkthdr.rcvif = ri->iri_ifp; 2845 m->m_flags |= ri->iri_flags; 2846 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2847 m->m_pkthdr.flowid = ri->iri_flowid; 2848 M_HASHTYPE_SET(m, ri->iri_rsstype); 2849 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2850 m->m_pkthdr.csum_data = ri->iri_csum_data; 2851 return (m); 2852 } 2853 2854 #if defined(INET6) || defined(INET) 2855 static void 2856 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2857 { 2858 CURVNET_SET(lc->ifp->if_vnet); 2859 #if defined(INET6) 2860 *v6 = V_ip6_forwarding; 2861 #endif 2862 #if defined(INET) 2863 *v4 = V_ipforwarding; 2864 #endif 2865 CURVNET_RESTORE(); 2866 } 2867 2868 /* 2869 * Returns true if it's possible this packet could be LROed. 2870 * if it returns false, it is guaranteed that tcp_lro_rx() 2871 * would not return zero. 2872 */ 2873 static bool 2874 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2875 { 2876 struct ether_header *eh; 2877 2878 eh = mtod(m, struct ether_header *); 2879 switch (eh->ether_type) { 2880 #if defined(INET6) 2881 case htons(ETHERTYPE_IPV6): 2882 return (!v6_forwarding); 2883 #endif 2884 #if defined (INET) 2885 case htons(ETHERTYPE_IP): 2886 return (!v4_forwarding); 2887 #endif 2888 } 2889 2890 return false; 2891 } 2892 #else 2893 static void 2894 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2895 { 2896 } 2897 #endif 2898 2899 static void 2900 _task_fn_rx_watchdog(void *context) 2901 { 2902 iflib_rxq_t rxq = context; 2903 2904 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2905 } 2906 2907 static uint8_t 2908 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2909 { 2910 if_t ifp; 2911 if_ctx_t ctx = rxq->ifr_ctx; 2912 if_shared_ctx_t sctx = ctx->ifc_sctx; 2913 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2914 int avail, i; 2915 qidx_t *cidxp; 2916 struct if_rxd_info ri; 2917 int err, budget_left, rx_bytes, rx_pkts; 2918 iflib_fl_t fl; 2919 int lro_enabled; 2920 bool v4_forwarding, v6_forwarding, lro_possible; 2921 uint8_t retval = 0; 2922 2923 /* 2924 * XXX early demux data packets so that if_input processing only handles 2925 * acks in interrupt context 2926 */ 2927 struct mbuf *m, *mh, *mt, *mf; 2928 2929 NET_EPOCH_ASSERT(); 2930 2931 lro_possible = v4_forwarding = v6_forwarding = false; 2932 ifp = ctx->ifc_ifp; 2933 mh = mt = NULL; 2934 MPASS(budget > 0); 2935 rx_pkts = rx_bytes = 0; 2936 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2937 cidxp = &rxq->ifr_cq_cidx; 2938 else 2939 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2940 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2941 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2942 retval |= iflib_fl_refill_all(ctx, fl); 2943 DBG_COUNTER_INC(rx_unavail); 2944 return (retval); 2945 } 2946 2947 /* pfil needs the vnet to be set */ 2948 CURVNET_SET_QUIET(ifp->if_vnet); 2949 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2950 if (__predict_false(!CTX_ACTIVE(ctx))) { 2951 DBG_COUNTER_INC(rx_ctx_inactive); 2952 break; 2953 } 2954 /* 2955 * Reset client set fields to their default values 2956 */ 2957 rxd_info_zero(&ri); 2958 ri.iri_qsidx = rxq->ifr_id; 2959 ri.iri_cidx = *cidxp; 2960 ri.iri_ifp = ifp; 2961 ri.iri_frags = rxq->ifr_frags; 2962 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2963 2964 if (err) 2965 goto err; 2966 rx_pkts += 1; 2967 rx_bytes += ri.iri_len; 2968 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2969 *cidxp = ri.iri_cidx; 2970 /* Update our consumer index */ 2971 /* XXX NB: shurd - check if this is still safe */ 2972 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2973 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2974 /* was this only a completion queue message? */ 2975 if (__predict_false(ri.iri_nfrags == 0)) 2976 continue; 2977 } 2978 MPASS(ri.iri_nfrags != 0); 2979 MPASS(ri.iri_len != 0); 2980 2981 /* will advance the cidx on the corresponding free lists */ 2982 m = iflib_rxd_pkt_get(rxq, &ri); 2983 avail--; 2984 budget_left--; 2985 if (avail == 0 && budget_left) 2986 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2987 2988 if (__predict_false(m == NULL)) 2989 continue; 2990 2991 /* imm_pkt: -- cxgb */ 2992 if (mh == NULL) 2993 mh = mt = m; 2994 else { 2995 mt->m_nextpkt = m; 2996 mt = m; 2997 } 2998 } 2999 CURVNET_RESTORE(); 3000 /* make sure that we can refill faster than drain */ 3001 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 3002 retval |= iflib_fl_refill_all(ctx, fl); 3003 3004 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 3005 if (lro_enabled) 3006 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 3007 mt = mf = NULL; 3008 while (mh != NULL) { 3009 m = mh; 3010 mh = mh->m_nextpkt; 3011 m->m_nextpkt = NULL; 3012 #ifndef __NO_STRICT_ALIGNMENT 3013 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 3014 continue; 3015 #endif 3016 #if defined(INET6) || defined(INET) 3017 if (lro_enabled) { 3018 if (!lro_possible) { 3019 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 3020 if (lro_possible && mf != NULL) { 3021 ifp->if_input(ifp, mf); 3022 DBG_COUNTER_INC(rx_if_input); 3023 mt = mf = NULL; 3024 } 3025 } 3026 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 3027 (CSUM_L4_CALC|CSUM_L4_VALID)) { 3028 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 3029 continue; 3030 } 3031 } 3032 #endif 3033 if (lro_possible) { 3034 ifp->if_input(ifp, m); 3035 DBG_COUNTER_INC(rx_if_input); 3036 continue; 3037 } 3038 3039 if (mf == NULL) 3040 mf = m; 3041 if (mt != NULL) 3042 mt->m_nextpkt = m; 3043 mt = m; 3044 } 3045 if (mf != NULL) { 3046 ifp->if_input(ifp, mf); 3047 DBG_COUNTER_INC(rx_if_input); 3048 } 3049 3050 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 3051 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 3052 3053 /* 3054 * Flush any outstanding LRO work 3055 */ 3056 #if defined(INET6) || defined(INET) 3057 tcp_lro_flush_all(&rxq->ifr_lc); 3058 #endif 3059 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 3060 retval |= IFLIB_RXEOF_MORE; 3061 return (retval); 3062 err: 3063 STATE_LOCK(ctx); 3064 ctx->ifc_flags |= IFC_DO_RESET; 3065 iflib_admin_intr_deferred(ctx); 3066 STATE_UNLOCK(ctx); 3067 return (0); 3068 } 3069 3070 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 3071 static inline qidx_t 3072 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 3073 { 3074 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3075 qidx_t minthresh = txq->ift_size / 8; 3076 if (in_use > 4*minthresh) 3077 return (notify_count); 3078 if (in_use > 2*minthresh) 3079 return (notify_count >> 1); 3080 if (in_use > minthresh) 3081 return (notify_count >> 3); 3082 return (0); 3083 } 3084 3085 static inline qidx_t 3086 txq_max_rs_deferred(iflib_txq_t txq) 3087 { 3088 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3089 qidx_t minthresh = txq->ift_size / 8; 3090 if (txq->ift_in_use > 4*minthresh) 3091 return (notify_count); 3092 if (txq->ift_in_use > 2*minthresh) 3093 return (notify_count >> 1); 3094 if (txq->ift_in_use > minthresh) 3095 return (notify_count >> 2); 3096 return (2); 3097 } 3098 3099 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 3100 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 3101 3102 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 3103 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 3104 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 3105 3106 /* forward compatibility for cxgb */ 3107 #define FIRST_QSET(ctx) 0 3108 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 3109 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 3110 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 3111 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 3112 3113 /* XXX we should be setting this to something other than zero */ 3114 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 3115 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 3116 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 3117 3118 static inline bool 3119 iflib_txd_db_check(iflib_txq_t txq, int ring) 3120 { 3121 if_ctx_t ctx = txq->ift_ctx; 3122 qidx_t dbval, max; 3123 3124 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use); 3125 3126 /* force || threshold exceeded || at the edge of the ring */ 3127 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx) + 2)) { 3128 3129 /* 3130 * 'npending' is used if the card's doorbell is in terms of the number of descriptors 3131 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the 3132 * producer index explicitly (INTC). 3133 */ 3134 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 3135 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3136 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3137 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 3138 3139 /* 3140 * Absent bugs there are zero packets pending so reset pending counts to zero. 3141 */ 3142 txq->ift_db_pending = txq->ift_npending = 0; 3143 return (true); 3144 } 3145 return (false); 3146 } 3147 3148 #ifdef PKT_DEBUG 3149 static void 3150 print_pkt(if_pkt_info_t pi) 3151 { 3152 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 3153 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 3154 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 3155 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 3156 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 3157 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 3158 } 3159 #endif 3160 3161 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3162 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3163 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3164 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3165 3166 static int 3167 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3168 { 3169 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3170 struct ether_vlan_header *eh; 3171 struct mbuf *m; 3172 3173 m = *mp; 3174 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3175 M_WRITABLE(m) == 0) { 3176 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3177 return (ENOMEM); 3178 } else { 3179 m_freem(*mp); 3180 DBG_COUNTER_INC(tx_frees); 3181 *mp = m; 3182 } 3183 } 3184 3185 /* 3186 * Determine where frame payload starts. 3187 * Jump over vlan headers if already present, 3188 * helpful for QinQ too. 3189 */ 3190 if (__predict_false(m->m_len < sizeof(*eh))) { 3191 txq->ift_pullups++; 3192 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3193 return (ENOMEM); 3194 } 3195 eh = mtod(m, struct ether_vlan_header *); 3196 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3197 pi->ipi_etype = ntohs(eh->evl_proto); 3198 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3199 } else { 3200 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3201 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3202 } 3203 3204 switch (pi->ipi_etype) { 3205 #ifdef INET 3206 case ETHERTYPE_IP: 3207 { 3208 struct mbuf *n; 3209 struct ip *ip = NULL; 3210 struct tcphdr *th = NULL; 3211 int minthlen; 3212 3213 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3214 if (__predict_false(m->m_len < minthlen)) { 3215 /* 3216 * if this code bloat is causing too much of a hit 3217 * move it to a separate function and mark it noinline 3218 */ 3219 if (m->m_len == pi->ipi_ehdrlen) { 3220 n = m->m_next; 3221 MPASS(n); 3222 if (n->m_len >= sizeof(*ip)) { 3223 ip = (struct ip *)n->m_data; 3224 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3225 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3226 } else { 3227 txq->ift_pullups++; 3228 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3229 return (ENOMEM); 3230 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3231 } 3232 } else { 3233 txq->ift_pullups++; 3234 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3235 return (ENOMEM); 3236 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3237 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3238 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3239 } 3240 } else { 3241 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3242 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3243 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3244 } 3245 pi->ipi_ip_hlen = ip->ip_hl << 2; 3246 pi->ipi_ipproto = ip->ip_p; 3247 pi->ipi_flags |= IPI_TX_IPV4; 3248 3249 /* TCP checksum offload may require TCP header length */ 3250 if (IS_TX_OFFLOAD4(pi)) { 3251 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3252 if (__predict_false(th == NULL)) { 3253 txq->ift_pullups++; 3254 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3255 return (ENOMEM); 3256 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3257 } 3258 pi->ipi_tcp_hflags = th->th_flags; 3259 pi->ipi_tcp_hlen = th->th_off << 2; 3260 pi->ipi_tcp_seq = th->th_seq; 3261 } 3262 if (IS_TSO4(pi)) { 3263 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3264 return (ENXIO); 3265 /* 3266 * TSO always requires hardware checksum offload. 3267 */ 3268 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3269 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3270 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3271 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3272 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3273 ip->ip_sum = 0; 3274 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3275 } 3276 } 3277 } 3278 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3279 ip->ip_sum = 0; 3280 3281 break; 3282 } 3283 #endif 3284 #ifdef INET6 3285 case ETHERTYPE_IPV6: 3286 { 3287 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3288 struct tcphdr *th; 3289 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3290 3291 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3292 txq->ift_pullups++; 3293 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3294 return (ENOMEM); 3295 } 3296 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3297 3298 /* XXX-BZ this will go badly in case of ext hdrs. */ 3299 pi->ipi_ipproto = ip6->ip6_nxt; 3300 pi->ipi_flags |= IPI_TX_IPV6; 3301 3302 /* TCP checksum offload may require TCP header length */ 3303 if (IS_TX_OFFLOAD6(pi)) { 3304 if (pi->ipi_ipproto == IPPROTO_TCP) { 3305 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3306 txq->ift_pullups++; 3307 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3308 return (ENOMEM); 3309 } 3310 pi->ipi_tcp_hflags = th->th_flags; 3311 pi->ipi_tcp_hlen = th->th_off << 2; 3312 pi->ipi_tcp_seq = th->th_seq; 3313 } 3314 if (IS_TSO6(pi)) { 3315 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3316 return (ENXIO); 3317 /* 3318 * TSO always requires hardware checksum offload. 3319 */ 3320 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3321 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3322 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3323 } 3324 } 3325 break; 3326 } 3327 #endif 3328 default: 3329 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3330 pi->ipi_ip_hlen = 0; 3331 break; 3332 } 3333 *mp = m; 3334 3335 return (0); 3336 } 3337 3338 /* 3339 * If dodgy hardware rejects the scatter gather chain we've handed it 3340 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3341 * m_defrag'd mbufs 3342 */ 3343 static __noinline struct mbuf * 3344 iflib_remove_mbuf(iflib_txq_t txq) 3345 { 3346 int ntxd, pidx; 3347 struct mbuf *m, **ifsd_m; 3348 3349 ifsd_m = txq->ift_sds.ifsd_m; 3350 ntxd = txq->ift_size; 3351 pidx = txq->ift_pidx & (ntxd - 1); 3352 ifsd_m = txq->ift_sds.ifsd_m; 3353 m = ifsd_m[pidx]; 3354 ifsd_m[pidx] = NULL; 3355 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3356 if (txq->ift_sds.ifsd_tso_map != NULL) 3357 bus_dmamap_unload(txq->ift_tso_buf_tag, 3358 txq->ift_sds.ifsd_tso_map[pidx]); 3359 #if MEMORY_LOGGING 3360 txq->ift_dequeued++; 3361 #endif 3362 return (m); 3363 } 3364 3365 static inline caddr_t 3366 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3367 { 3368 qidx_t size; 3369 int ntxd; 3370 caddr_t start, end, cur, next; 3371 3372 ntxd = txq->ift_size; 3373 size = txq->ift_txd_size[qid]; 3374 start = txq->ift_ifdi[qid].idi_vaddr; 3375 3376 if (__predict_false(size == 0)) 3377 return (start); 3378 cur = start + size*cidx; 3379 end = start + size*ntxd; 3380 next = CACHE_PTR_NEXT(cur); 3381 return (next < end ? next : start); 3382 } 3383 3384 /* 3385 * Pad an mbuf to ensure a minimum ethernet frame size. 3386 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3387 */ 3388 static __noinline int 3389 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3390 { 3391 /* 3392 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3393 * and ARP message is the smallest common payload I can think of 3394 */ 3395 static char pad[18]; /* just zeros */ 3396 int n; 3397 struct mbuf *new_head; 3398 3399 if (!M_WRITABLE(*m_head)) { 3400 new_head = m_dup(*m_head, M_NOWAIT); 3401 if (new_head == NULL) { 3402 m_freem(*m_head); 3403 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3404 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3405 DBG_COUNTER_INC(tx_frees); 3406 return ENOMEM; 3407 } 3408 m_freem(*m_head); 3409 *m_head = new_head; 3410 } 3411 3412 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3413 n > 0; n -= sizeof(pad)) 3414 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3415 break; 3416 3417 if (n > 0) { 3418 m_freem(*m_head); 3419 device_printf(dev, "cannot pad short frame\n"); 3420 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3421 DBG_COUNTER_INC(tx_frees); 3422 return (ENOBUFS); 3423 } 3424 3425 return 0; 3426 } 3427 3428 static int 3429 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3430 { 3431 if_ctx_t ctx; 3432 if_shared_ctx_t sctx; 3433 if_softc_ctx_t scctx; 3434 bus_dma_tag_t buf_tag; 3435 bus_dma_segment_t *segs; 3436 struct mbuf *m_head, **ifsd_m; 3437 void *next_txd; 3438 bus_dmamap_t map; 3439 struct if_pkt_info pi; 3440 int remap = 0; 3441 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3442 3443 ctx = txq->ift_ctx; 3444 sctx = ctx->ifc_sctx; 3445 scctx = &ctx->ifc_softc_ctx; 3446 segs = txq->ift_segs; 3447 ntxd = txq->ift_size; 3448 m_head = *m_headp; 3449 map = NULL; 3450 3451 /* 3452 * If we're doing TSO the next descriptor to clean may be quite far ahead 3453 */ 3454 cidx = txq->ift_cidx; 3455 pidx = txq->ift_pidx; 3456 if (ctx->ifc_flags & IFC_PREFETCH) { 3457 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3458 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3459 next_txd = calc_next_txd(txq, cidx, 0); 3460 prefetch(next_txd); 3461 } 3462 3463 /* prefetch the next cache line of mbuf pointers and flags */ 3464 prefetch(&txq->ift_sds.ifsd_m[next]); 3465 prefetch(&txq->ift_sds.ifsd_map[next]); 3466 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3467 } 3468 map = txq->ift_sds.ifsd_map[pidx]; 3469 ifsd_m = txq->ift_sds.ifsd_m; 3470 3471 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3472 buf_tag = txq->ift_tso_buf_tag; 3473 max_segs = scctx->isc_tx_tso_segments_max; 3474 map = txq->ift_sds.ifsd_tso_map[pidx]; 3475 MPASS(buf_tag != NULL); 3476 MPASS(max_segs > 0); 3477 } else { 3478 buf_tag = txq->ift_buf_tag; 3479 max_segs = scctx->isc_tx_nsegments; 3480 map = txq->ift_sds.ifsd_map[pidx]; 3481 } 3482 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3483 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3484 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3485 if (err) { 3486 DBG_COUNTER_INC(encap_txd_encap_fail); 3487 return err; 3488 } 3489 } 3490 m_head = *m_headp; 3491 3492 pkt_info_zero(&pi); 3493 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3494 pi.ipi_pidx = pidx; 3495 pi.ipi_qsidx = txq->ift_id; 3496 pi.ipi_len = m_head->m_pkthdr.len; 3497 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3498 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3499 3500 /* deliberate bitwise OR to make one condition */ 3501 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3502 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3503 DBG_COUNTER_INC(encap_txd_encap_fail); 3504 return (err); 3505 } 3506 m_head = *m_headp; 3507 } 3508 3509 retry: 3510 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3511 BUS_DMA_NOWAIT); 3512 defrag: 3513 if (__predict_false(err)) { 3514 switch (err) { 3515 case EFBIG: 3516 /* try collapse once and defrag once */ 3517 if (remap == 0) { 3518 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3519 /* try defrag if collapsing fails */ 3520 if (m_head == NULL) 3521 remap++; 3522 } 3523 if (remap == 1) { 3524 txq->ift_mbuf_defrag++; 3525 m_head = m_defrag(*m_headp, M_NOWAIT); 3526 } 3527 /* 3528 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3529 * failed to map an mbuf that was run through m_defrag 3530 */ 3531 MPASS(remap <= 1); 3532 if (__predict_false(m_head == NULL || remap > 1)) 3533 goto defrag_failed; 3534 remap++; 3535 *m_headp = m_head; 3536 goto retry; 3537 break; 3538 case ENOMEM: 3539 txq->ift_no_tx_dma_setup++; 3540 break; 3541 default: 3542 txq->ift_no_tx_dma_setup++; 3543 m_freem(*m_headp); 3544 DBG_COUNTER_INC(tx_frees); 3545 *m_headp = NULL; 3546 break; 3547 } 3548 txq->ift_map_failed++; 3549 DBG_COUNTER_INC(encap_load_mbuf_fail); 3550 DBG_COUNTER_INC(encap_txd_encap_fail); 3551 return (err); 3552 } 3553 ifsd_m[pidx] = m_head; 3554 /* 3555 * XXX assumes a 1 to 1 relationship between segments and 3556 * descriptors - this does not hold true on all drivers, e.g. 3557 * cxgb 3558 */ 3559 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3560 txq->ift_no_desc_avail++; 3561 bus_dmamap_unload(buf_tag, map); 3562 DBG_COUNTER_INC(encap_txq_avail_fail); 3563 DBG_COUNTER_INC(encap_txd_encap_fail); 3564 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3565 GROUPTASK_ENQUEUE(&txq->ift_task); 3566 return (ENOBUFS); 3567 } 3568 /* 3569 * On Intel cards we can greatly reduce the number of TX interrupts 3570 * we see by only setting report status on every Nth descriptor. 3571 * However, this also means that the driver will need to keep track 3572 * of the descriptors that RS was set on to check them for the DD bit. 3573 */ 3574 txq->ift_rs_pending += nsegs + 1; 3575 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3576 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3577 pi.ipi_flags |= IPI_TX_INTR; 3578 txq->ift_rs_pending = 0; 3579 } 3580 3581 pi.ipi_segs = segs; 3582 pi.ipi_nsegs = nsegs; 3583 3584 MPASS(pidx >= 0 && pidx < txq->ift_size); 3585 #ifdef PKT_DEBUG 3586 print_pkt(&pi); 3587 #endif 3588 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3589 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3590 DBG_COUNTER_INC(tx_encap); 3591 MPASS(pi.ipi_new_pidx < txq->ift_size); 3592 3593 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3594 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3595 ndesc += txq->ift_size; 3596 txq->ift_gen = 1; 3597 } 3598 /* 3599 * drivers can need as many as 3600 * two sentinels 3601 */ 3602 MPASS(ndesc <= pi.ipi_nsegs + 2); 3603 MPASS(pi.ipi_new_pidx != pidx); 3604 MPASS(ndesc > 0); 3605 txq->ift_in_use += ndesc; 3606 txq->ift_db_pending += ndesc; 3607 3608 /* 3609 * We update the last software descriptor again here because there may 3610 * be a sentinel and/or there may be more mbufs than segments 3611 */ 3612 txq->ift_pidx = pi.ipi_new_pidx; 3613 txq->ift_npending += pi.ipi_ndescs; 3614 } else { 3615 *m_headp = m_head = iflib_remove_mbuf(txq); 3616 if (err == EFBIG) { 3617 txq->ift_txd_encap_efbig++; 3618 if (remap < 2) { 3619 remap = 1; 3620 goto defrag; 3621 } 3622 } 3623 goto defrag_failed; 3624 } 3625 /* 3626 * err can't possibly be non-zero here, so we don't neet to test it 3627 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3628 */ 3629 return (err); 3630 3631 defrag_failed: 3632 txq->ift_mbuf_defrag_failed++; 3633 txq->ift_map_failed++; 3634 m_freem(*m_headp); 3635 DBG_COUNTER_INC(tx_frees); 3636 *m_headp = NULL; 3637 DBG_COUNTER_INC(encap_txd_encap_fail); 3638 return (ENOMEM); 3639 } 3640 3641 static void 3642 iflib_tx_desc_free(iflib_txq_t txq, int n) 3643 { 3644 uint32_t qsize, cidx, mask, gen; 3645 struct mbuf *m, **ifsd_m; 3646 bool do_prefetch; 3647 3648 cidx = txq->ift_cidx; 3649 gen = txq->ift_gen; 3650 qsize = txq->ift_size; 3651 mask = qsize-1; 3652 ifsd_m = txq->ift_sds.ifsd_m; 3653 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3654 3655 while (n-- > 0) { 3656 if (do_prefetch) { 3657 prefetch(ifsd_m[(cidx + 3) & mask]); 3658 prefetch(ifsd_m[(cidx + 4) & mask]); 3659 } 3660 if ((m = ifsd_m[cidx]) != NULL) { 3661 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3662 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3663 bus_dmamap_sync(txq->ift_tso_buf_tag, 3664 txq->ift_sds.ifsd_tso_map[cidx], 3665 BUS_DMASYNC_POSTWRITE); 3666 bus_dmamap_unload(txq->ift_tso_buf_tag, 3667 txq->ift_sds.ifsd_tso_map[cidx]); 3668 } else { 3669 bus_dmamap_sync(txq->ift_buf_tag, 3670 txq->ift_sds.ifsd_map[cidx], 3671 BUS_DMASYNC_POSTWRITE); 3672 bus_dmamap_unload(txq->ift_buf_tag, 3673 txq->ift_sds.ifsd_map[cidx]); 3674 } 3675 /* XXX we don't support any drivers that batch packets yet */ 3676 MPASS(m->m_nextpkt == NULL); 3677 m_freem(m); 3678 ifsd_m[cidx] = NULL; 3679 #if MEMORY_LOGGING 3680 txq->ift_dequeued++; 3681 #endif 3682 DBG_COUNTER_INC(tx_frees); 3683 } 3684 if (__predict_false(++cidx == qsize)) { 3685 cidx = 0; 3686 gen = 0; 3687 } 3688 } 3689 txq->ift_cidx = cidx; 3690 txq->ift_gen = gen; 3691 } 3692 3693 static __inline int 3694 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3695 { 3696 int reclaim; 3697 if_ctx_t ctx = txq->ift_ctx; 3698 3699 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3700 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3701 3702 /* 3703 * Need a rate-limiting check so that this isn't called every time 3704 */ 3705 iflib_tx_credits_update(ctx, txq); 3706 reclaim = DESC_RECLAIMABLE(txq); 3707 3708 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3709 #ifdef INVARIANTS 3710 if (iflib_verbose_debug) { 3711 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3712 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3713 reclaim, thresh); 3714 } 3715 #endif 3716 return (0); 3717 } 3718 iflib_tx_desc_free(txq, reclaim); 3719 txq->ift_cleaned += reclaim; 3720 txq->ift_in_use -= reclaim; 3721 3722 return (reclaim); 3723 } 3724 3725 static struct mbuf ** 3726 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3727 { 3728 int next, size; 3729 struct mbuf **items; 3730 3731 size = r->size; 3732 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3733 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3734 3735 prefetch(items[(cidx + offset) & (size-1)]); 3736 if (remaining > 1) { 3737 prefetch2cachelines(&items[next]); 3738 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3739 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3740 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3741 } 3742 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3743 } 3744 3745 static void 3746 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3747 { 3748 3749 ifmp_ring_check_drainage(txq->ift_br, budget); 3750 } 3751 3752 static uint32_t 3753 iflib_txq_can_drain(struct ifmp_ring *r) 3754 { 3755 iflib_txq_t txq = r->cookie; 3756 if_ctx_t ctx = txq->ift_ctx; 3757 3758 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3759 return (1); 3760 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3761 BUS_DMASYNC_POSTREAD); 3762 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3763 false)); 3764 } 3765 3766 static uint32_t 3767 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3768 { 3769 iflib_txq_t txq = r->cookie; 3770 if_ctx_t ctx = txq->ift_ctx; 3771 if_t ifp = ctx->ifc_ifp; 3772 struct mbuf *m, **mp; 3773 int avail, bytes_sent, skipped, count, err, i; 3774 int mcast_sent, pkt_sent, reclaimed; 3775 bool do_prefetch, rang, ring; 3776 3777 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3778 !LINK_ACTIVE(ctx))) { 3779 DBG_COUNTER_INC(txq_drain_notready); 3780 return (0); 3781 } 3782 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3783 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending); 3784 avail = IDXDIFF(pidx, cidx, r->size); 3785 3786 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3787 /* 3788 * The driver is unloading so we need to free all pending packets. 3789 */ 3790 DBG_COUNTER_INC(txq_drain_flushing); 3791 for (i = 0; i < avail; i++) { 3792 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3793 m_freem(r->items[(cidx + i) & (r->size-1)]); 3794 r->items[(cidx + i) & (r->size-1)] = NULL; 3795 } 3796 return (avail); 3797 } 3798 3799 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3800 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3801 CALLOUT_LOCK(txq); 3802 callout_stop(&txq->ift_timer); 3803 CALLOUT_UNLOCK(txq); 3804 DBG_COUNTER_INC(txq_drain_oactive); 3805 return (0); 3806 } 3807 3808 /* 3809 * If we've reclaimed any packets this queue cannot be hung. 3810 */ 3811 if (reclaimed) 3812 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3813 skipped = mcast_sent = bytes_sent = pkt_sent = 0; 3814 count = MIN(avail, TX_BATCH_SIZE); 3815 #ifdef INVARIANTS 3816 if (iflib_verbose_debug) 3817 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3818 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3819 #endif 3820 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3821 err = 0; 3822 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx) + 2; i++) { 3823 int rem = do_prefetch ? count - i : 0; 3824 3825 mp = _ring_peek_one(r, cidx, i, rem); 3826 MPASS(mp != NULL && *mp != NULL); 3827 3828 /* 3829 * Completion interrupts will use the address of the txq 3830 * as a sentinel to enqueue _something_ in order to acquire 3831 * the lock on the mp_ring (there's no direct lock call). 3832 * We obviously whave to check for these sentinel cases 3833 * and skip them. 3834 */ 3835 if (__predict_false(*mp == (struct mbuf *)txq)) { 3836 skipped++; 3837 continue; 3838 } 3839 err = iflib_encap(txq, mp); 3840 if (__predict_false(err)) { 3841 /* no room - bail out */ 3842 if (err == ENOBUFS) 3843 break; 3844 skipped++; 3845 /* we can't send this packet - skip it */ 3846 continue; 3847 } 3848 pkt_sent++; 3849 m = *mp; 3850 DBG_COUNTER_INC(tx_sent); 3851 bytes_sent += m->m_pkthdr.len; 3852 mcast_sent += !!(m->m_flags & M_MCAST); 3853 3854 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3855 break; 3856 ETHER_BPF_MTAP(ifp, m); 3857 rang = iflib_txd_db_check(txq, false); 3858 } 3859 3860 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3861 ring = rang ? false : (iflib_min_tx_latency | err); 3862 iflib_txd_db_check(txq, ring); 3863 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3864 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3865 if (mcast_sent) 3866 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3867 #ifdef INVARIANTS 3868 if (iflib_verbose_debug) 3869 printf("consumed=%d\n", skipped + pkt_sent); 3870 #endif 3871 return (skipped + pkt_sent); 3872 } 3873 3874 static uint32_t 3875 iflib_txq_drain_always(struct ifmp_ring *r) 3876 { 3877 return (1); 3878 } 3879 3880 static uint32_t 3881 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3882 { 3883 int i, avail; 3884 struct mbuf **mp; 3885 iflib_txq_t txq; 3886 3887 txq = r->cookie; 3888 3889 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3890 CALLOUT_LOCK(txq); 3891 callout_stop(&txq->ift_timer); 3892 CALLOUT_UNLOCK(txq); 3893 3894 avail = IDXDIFF(pidx, cidx, r->size); 3895 for (i = 0; i < avail; i++) { 3896 mp = _ring_peek_one(r, cidx, i, avail - i); 3897 if (__predict_false(*mp == (struct mbuf *)txq)) 3898 continue; 3899 m_freem(*mp); 3900 DBG_COUNTER_INC(tx_frees); 3901 } 3902 MPASS(ifmp_ring_is_stalled(r) == 0); 3903 return (avail); 3904 } 3905 3906 static void 3907 iflib_ifmp_purge(iflib_txq_t txq) 3908 { 3909 struct ifmp_ring *r; 3910 3911 r = txq->ift_br; 3912 r->drain = iflib_txq_drain_free; 3913 r->can_drain = iflib_txq_drain_always; 3914 3915 ifmp_ring_check_drainage(r, r->size); 3916 3917 r->drain = iflib_txq_drain; 3918 r->can_drain = iflib_txq_can_drain; 3919 } 3920 3921 static void 3922 _task_fn_tx(void *context) 3923 { 3924 iflib_txq_t txq = context; 3925 if_ctx_t ctx = txq->ift_ctx; 3926 if_t ifp = ctx->ifc_ifp; 3927 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3928 3929 #ifdef IFLIB_DIAGNOSTICS 3930 txq->ift_cpu_exec_count[curcpu]++; 3931 #endif 3932 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 3933 return; 3934 #ifdef DEV_NETMAP 3935 if ((if_getcapenable(ifp) & IFCAP_NETMAP) && 3936 netmap_tx_irq(ifp, txq->ift_id)) 3937 goto skip_ifmp; 3938 #endif 3939 #ifdef ALTQ 3940 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3941 iflib_altq_if_start(ifp); 3942 #endif 3943 if (txq->ift_db_pending) 3944 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3945 else if (!abdicate) 3946 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3947 /* 3948 * When abdicating, we always need to check drainage, not just when we don't enqueue 3949 */ 3950 if (abdicate) 3951 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3952 #ifdef DEV_NETMAP 3953 skip_ifmp: 3954 #endif 3955 if (ctx->ifc_flags & IFC_LEGACY) 3956 IFDI_INTR_ENABLE(ctx); 3957 else 3958 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3959 } 3960 3961 static void 3962 _task_fn_rx(void *context) 3963 { 3964 iflib_rxq_t rxq = context; 3965 if_ctx_t ctx = rxq->ifr_ctx; 3966 uint8_t more; 3967 uint16_t budget; 3968 #ifdef DEV_NETMAP 3969 u_int work = 0; 3970 int nmirq; 3971 #endif 3972 3973 #ifdef IFLIB_DIAGNOSTICS 3974 rxq->ifr_cpu_exec_count[curcpu]++; 3975 #endif 3976 DBG_COUNTER_INC(task_fn_rxs); 3977 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3978 return; 3979 #ifdef DEV_NETMAP 3980 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 3981 if (nmirq != NM_IRQ_PASS) { 3982 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 3983 goto skip_rxeof; 3984 } 3985 #endif 3986 budget = ctx->ifc_sysctl_rx_budget; 3987 if (budget == 0) 3988 budget = 16; /* XXX */ 3989 more = iflib_rxeof(rxq, budget); 3990 #ifdef DEV_NETMAP 3991 skip_rxeof: 3992 #endif 3993 if ((more & IFLIB_RXEOF_MORE) == 0) { 3994 if (ctx->ifc_flags & IFC_LEGACY) 3995 IFDI_INTR_ENABLE(ctx); 3996 else 3997 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3998 DBG_COUNTER_INC(rx_intr_enables); 3999 } 4000 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4001 return; 4002 4003 if (more & IFLIB_RXEOF_MORE) 4004 GROUPTASK_ENQUEUE(&rxq->ifr_task); 4005 else if (more & IFLIB_RXEOF_EMPTY) 4006 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 4007 } 4008 4009 static void 4010 _task_fn_admin(void *context) 4011 { 4012 if_ctx_t ctx = context; 4013 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 4014 iflib_txq_t txq; 4015 int i; 4016 bool oactive, running, do_reset, do_watchdog, in_detach; 4017 4018 STATE_LOCK(ctx); 4019 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 4020 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 4021 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 4022 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 4023 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 4024 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 4025 STATE_UNLOCK(ctx); 4026 4027 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4028 return; 4029 if (in_detach) 4030 return; 4031 4032 CTX_LOCK(ctx); 4033 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4034 CALLOUT_LOCK(txq); 4035 callout_stop(&txq->ift_timer); 4036 CALLOUT_UNLOCK(txq); 4037 } 4038 if (do_watchdog) { 4039 ctx->ifc_watchdog_events++; 4040 IFDI_WATCHDOG_RESET(ctx); 4041 } 4042 IFDI_UPDATE_ADMIN_STATUS(ctx); 4043 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4044 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 4045 txq->ift_timer.c_cpu); 4046 } 4047 IFDI_LINK_INTR_ENABLE(ctx); 4048 if (do_reset) 4049 iflib_if_init_locked(ctx); 4050 CTX_UNLOCK(ctx); 4051 4052 if (LINK_ACTIVE(ctx) == 0) 4053 return; 4054 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 4055 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4056 } 4057 4058 static void 4059 _task_fn_iov(void *context) 4060 { 4061 if_ctx_t ctx = context; 4062 4063 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 4064 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4065 return; 4066 4067 CTX_LOCK(ctx); 4068 IFDI_VFLR_HANDLE(ctx); 4069 CTX_UNLOCK(ctx); 4070 } 4071 4072 static int 4073 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4074 { 4075 int err; 4076 if_int_delay_info_t info; 4077 if_ctx_t ctx; 4078 4079 info = (if_int_delay_info_t)arg1; 4080 ctx = info->iidi_ctx; 4081 info->iidi_req = req; 4082 info->iidi_oidp = oidp; 4083 CTX_LOCK(ctx); 4084 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 4085 CTX_UNLOCK(ctx); 4086 return (err); 4087 } 4088 4089 /********************************************************************* 4090 * 4091 * IFNET FUNCTIONS 4092 * 4093 **********************************************************************/ 4094 4095 static void 4096 iflib_if_init_locked(if_ctx_t ctx) 4097 { 4098 iflib_stop(ctx); 4099 iflib_init_locked(ctx); 4100 } 4101 4102 static void 4103 iflib_if_init(void *arg) 4104 { 4105 if_ctx_t ctx = arg; 4106 4107 CTX_LOCK(ctx); 4108 iflib_if_init_locked(ctx); 4109 CTX_UNLOCK(ctx); 4110 } 4111 4112 static int 4113 iflib_if_transmit(if_t ifp, struct mbuf *m) 4114 { 4115 if_ctx_t ctx = if_getsoftc(ifp); 4116 4117 iflib_txq_t txq; 4118 int err, qidx; 4119 int abdicate = ctx->ifc_sysctl_tx_abdicate; 4120 4121 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 4122 DBG_COUNTER_INC(tx_frees); 4123 m_freem(m); 4124 return (ENETDOWN); 4125 } 4126 4127 MPASS(m->m_nextpkt == NULL); 4128 /* ALTQ-enabled interfaces always use queue 0. */ 4129 qidx = 0; 4130 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 4131 qidx = QIDX(ctx, m); 4132 /* 4133 * XXX calculate buf_ring based on flowid (divvy up bits?) 4134 */ 4135 txq = &ctx->ifc_txqs[qidx]; 4136 4137 #ifdef DRIVER_BACKPRESSURE 4138 if (txq->ift_closed) { 4139 while (m != NULL) { 4140 next = m->m_nextpkt; 4141 m->m_nextpkt = NULL; 4142 m_freem(m); 4143 DBG_COUNTER_INC(tx_frees); 4144 m = next; 4145 } 4146 return (ENOBUFS); 4147 } 4148 #endif 4149 #ifdef notyet 4150 qidx = count = 0; 4151 mp = marr; 4152 next = m; 4153 do { 4154 count++; 4155 next = next->m_nextpkt; 4156 } while (next != NULL); 4157 4158 if (count > nitems(marr)) 4159 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4160 /* XXX check nextpkt */ 4161 m_freem(m); 4162 /* XXX simplify for now */ 4163 DBG_COUNTER_INC(tx_frees); 4164 return (ENOBUFS); 4165 } 4166 for (next = m, i = 0; next != NULL; i++) { 4167 mp[i] = next; 4168 next = next->m_nextpkt; 4169 mp[i]->m_nextpkt = NULL; 4170 } 4171 #endif 4172 DBG_COUNTER_INC(tx_seen); 4173 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4174 4175 if (abdicate) 4176 GROUPTASK_ENQUEUE(&txq->ift_task); 4177 if (err) { 4178 if (!abdicate) 4179 GROUPTASK_ENQUEUE(&txq->ift_task); 4180 /* support forthcoming later */ 4181 #ifdef DRIVER_BACKPRESSURE 4182 txq->ift_closed = TRUE; 4183 #endif 4184 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4185 m_freem(m); 4186 DBG_COUNTER_INC(tx_frees); 4187 } 4188 4189 return (err); 4190 } 4191 4192 #ifdef ALTQ 4193 /* 4194 * The overall approach to integrating iflib with ALTQ is to continue to use 4195 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4196 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4197 * is redundant/unnecessary, but doing so minimizes the amount of 4198 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4199 * redundantly queueing to an intermediate mp_ring is swamped by the 4200 * performance limitations inherent in using ALTQ. 4201 * 4202 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4203 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4204 * given interface. If ALTQ is enabled for an interface, then all 4205 * transmitted packets for that interface will be submitted to the ALTQ 4206 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4207 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4208 * update stats that the iflib machinery handles, and which is sensitve to 4209 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4210 * will be installed as the start routine for use by ALTQ facilities that 4211 * need to trigger queue drains on a scheduled basis. 4212 * 4213 */ 4214 static void 4215 iflib_altq_if_start(if_t ifp) 4216 { 4217 struct ifaltq *ifq = &ifp->if_snd; 4218 struct mbuf *m; 4219 4220 IFQ_LOCK(ifq); 4221 IFQ_DEQUEUE_NOLOCK(ifq, m); 4222 while (m != NULL) { 4223 iflib_if_transmit(ifp, m); 4224 IFQ_DEQUEUE_NOLOCK(ifq, m); 4225 } 4226 IFQ_UNLOCK(ifq); 4227 } 4228 4229 static int 4230 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4231 { 4232 int err; 4233 4234 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4235 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4236 if (err == 0) 4237 iflib_altq_if_start(ifp); 4238 } else 4239 err = iflib_if_transmit(ifp, m); 4240 4241 return (err); 4242 } 4243 #endif /* ALTQ */ 4244 4245 static void 4246 iflib_if_qflush(if_t ifp) 4247 { 4248 if_ctx_t ctx = if_getsoftc(ifp); 4249 iflib_txq_t txq = ctx->ifc_txqs; 4250 int i; 4251 4252 STATE_LOCK(ctx); 4253 ctx->ifc_flags |= IFC_QFLUSH; 4254 STATE_UNLOCK(ctx); 4255 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4256 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4257 iflib_txq_check_drain(txq, 0); 4258 STATE_LOCK(ctx); 4259 ctx->ifc_flags &= ~IFC_QFLUSH; 4260 STATE_UNLOCK(ctx); 4261 4262 /* 4263 * When ALTQ is enabled, this will also take care of purging the 4264 * ALTQ queue(s). 4265 */ 4266 if_qflush(ifp); 4267 } 4268 4269 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4270 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4271 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4272 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_MEXTPG) 4273 4274 static int 4275 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4276 { 4277 if_ctx_t ctx = if_getsoftc(ifp); 4278 struct ifreq *ifr = (struct ifreq *)data; 4279 #if defined(INET) || defined(INET6) 4280 struct ifaddr *ifa = (struct ifaddr *)data; 4281 #endif 4282 bool avoid_reset = false; 4283 int err = 0, reinit = 0, bits; 4284 4285 switch (command) { 4286 case SIOCSIFADDR: 4287 #ifdef INET 4288 if (ifa->ifa_addr->sa_family == AF_INET) 4289 avoid_reset = true; 4290 #endif 4291 #ifdef INET6 4292 if (ifa->ifa_addr->sa_family == AF_INET6) 4293 avoid_reset = true; 4294 #endif 4295 /* 4296 ** Calling init results in link renegotiation, 4297 ** so we avoid doing it when possible. 4298 */ 4299 if (avoid_reset) { 4300 if_setflagbits(ifp, IFF_UP,0); 4301 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4302 reinit = 1; 4303 #ifdef INET 4304 if (!(if_getflags(ifp) & IFF_NOARP)) 4305 arp_ifinit(ifp, ifa); 4306 #endif 4307 } else 4308 err = ether_ioctl(ifp, command, data); 4309 break; 4310 case SIOCSIFMTU: 4311 CTX_LOCK(ctx); 4312 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4313 CTX_UNLOCK(ctx); 4314 break; 4315 } 4316 bits = if_getdrvflags(ifp); 4317 /* stop the driver and free any clusters before proceeding */ 4318 iflib_stop(ctx); 4319 4320 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4321 STATE_LOCK(ctx); 4322 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4323 ctx->ifc_flags |= IFC_MULTISEG; 4324 else 4325 ctx->ifc_flags &= ~IFC_MULTISEG; 4326 STATE_UNLOCK(ctx); 4327 err = if_setmtu(ifp, ifr->ifr_mtu); 4328 } 4329 iflib_init_locked(ctx); 4330 STATE_LOCK(ctx); 4331 if_setdrvflags(ifp, bits); 4332 STATE_UNLOCK(ctx); 4333 CTX_UNLOCK(ctx); 4334 break; 4335 case SIOCSIFFLAGS: 4336 CTX_LOCK(ctx); 4337 if (if_getflags(ifp) & IFF_UP) { 4338 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4339 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4340 (IFF_PROMISC | IFF_ALLMULTI)) { 4341 CTX_UNLOCK(ctx); 4342 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4343 CTX_LOCK(ctx); 4344 } 4345 } else 4346 reinit = 1; 4347 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4348 iflib_stop(ctx); 4349 } 4350 ctx->ifc_if_flags = if_getflags(ifp); 4351 CTX_UNLOCK(ctx); 4352 break; 4353 case SIOCADDMULTI: 4354 case SIOCDELMULTI: 4355 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4356 CTX_LOCK(ctx); 4357 IFDI_INTR_DISABLE(ctx); 4358 IFDI_MULTI_SET(ctx); 4359 IFDI_INTR_ENABLE(ctx); 4360 CTX_UNLOCK(ctx); 4361 } 4362 break; 4363 case SIOCSIFMEDIA: 4364 CTX_LOCK(ctx); 4365 IFDI_MEDIA_SET(ctx); 4366 CTX_UNLOCK(ctx); 4367 /* FALLTHROUGH */ 4368 case SIOCGIFMEDIA: 4369 case SIOCGIFXMEDIA: 4370 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4371 break; 4372 case SIOCGI2C: 4373 { 4374 struct ifi2creq i2c; 4375 4376 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4377 if (err != 0) 4378 break; 4379 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4380 err = EINVAL; 4381 break; 4382 } 4383 if (i2c.len > sizeof(i2c.data)) { 4384 err = EINVAL; 4385 break; 4386 } 4387 4388 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4389 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4390 sizeof(i2c)); 4391 break; 4392 } 4393 case SIOCSIFCAP: 4394 { 4395 int mask, setmask, oldmask; 4396 4397 oldmask = if_getcapenable(ifp); 4398 mask = ifr->ifr_reqcap ^ oldmask; 4399 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_MEXTPG; 4400 setmask = 0; 4401 #ifdef TCP_OFFLOAD 4402 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4403 #endif 4404 setmask |= (mask & IFCAP_FLAGS); 4405 setmask |= (mask & IFCAP_WOL); 4406 4407 /* 4408 * If any RX csum has changed, change all the ones that 4409 * are supported by the driver. 4410 */ 4411 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4412 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4413 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4414 } 4415 4416 /* 4417 * want to ensure that traffic has stopped before we change any of the flags 4418 */ 4419 if (setmask) { 4420 CTX_LOCK(ctx); 4421 bits = if_getdrvflags(ifp); 4422 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4423 iflib_stop(ctx); 4424 STATE_LOCK(ctx); 4425 if_togglecapenable(ifp, setmask); 4426 STATE_UNLOCK(ctx); 4427 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4428 iflib_init_locked(ctx); 4429 STATE_LOCK(ctx); 4430 if_setdrvflags(ifp, bits); 4431 STATE_UNLOCK(ctx); 4432 CTX_UNLOCK(ctx); 4433 } 4434 if_vlancap(ifp); 4435 break; 4436 } 4437 case SIOCGPRIVATE_0: 4438 case SIOCSDRVSPEC: 4439 case SIOCGDRVSPEC: 4440 CTX_LOCK(ctx); 4441 err = IFDI_PRIV_IOCTL(ctx, command, data); 4442 CTX_UNLOCK(ctx); 4443 break; 4444 default: 4445 err = ether_ioctl(ifp, command, data); 4446 break; 4447 } 4448 if (reinit) 4449 iflib_if_init(ctx); 4450 return (err); 4451 } 4452 4453 static uint64_t 4454 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4455 { 4456 if_ctx_t ctx = if_getsoftc(ifp); 4457 4458 return (IFDI_GET_COUNTER(ctx, cnt)); 4459 } 4460 4461 /********************************************************************* 4462 * 4463 * OTHER FUNCTIONS EXPORTED TO THE STACK 4464 * 4465 **********************************************************************/ 4466 4467 static void 4468 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4469 { 4470 if_ctx_t ctx = if_getsoftc(ifp); 4471 4472 if ((void *)ctx != arg) 4473 return; 4474 4475 if ((vtag == 0) || (vtag > 4095)) 4476 return; 4477 4478 if (iflib_in_detach(ctx)) 4479 return; 4480 4481 CTX_LOCK(ctx); 4482 /* Driver may need all untagged packets to be flushed */ 4483 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4484 iflib_stop(ctx); 4485 IFDI_VLAN_REGISTER(ctx, vtag); 4486 /* Re-init to load the changes, if required */ 4487 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4488 iflib_init_locked(ctx); 4489 CTX_UNLOCK(ctx); 4490 } 4491 4492 static void 4493 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4494 { 4495 if_ctx_t ctx = if_getsoftc(ifp); 4496 4497 if ((void *)ctx != arg) 4498 return; 4499 4500 if ((vtag == 0) || (vtag > 4095)) 4501 return; 4502 4503 CTX_LOCK(ctx); 4504 /* Driver may need all tagged packets to be flushed */ 4505 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4506 iflib_stop(ctx); 4507 IFDI_VLAN_UNREGISTER(ctx, vtag); 4508 /* Re-init to load the changes, if required */ 4509 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4510 iflib_init_locked(ctx); 4511 CTX_UNLOCK(ctx); 4512 } 4513 4514 static void 4515 iflib_led_func(void *arg, int onoff) 4516 { 4517 if_ctx_t ctx = arg; 4518 4519 CTX_LOCK(ctx); 4520 IFDI_LED_FUNC(ctx, onoff); 4521 CTX_UNLOCK(ctx); 4522 } 4523 4524 /********************************************************************* 4525 * 4526 * BUS FUNCTION DEFINITIONS 4527 * 4528 **********************************************************************/ 4529 4530 int 4531 iflib_device_probe(device_t dev) 4532 { 4533 const pci_vendor_info_t *ent; 4534 if_shared_ctx_t sctx; 4535 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4536 uint16_t pci_vendor_id; 4537 4538 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4539 return (ENOTSUP); 4540 4541 pci_vendor_id = pci_get_vendor(dev); 4542 pci_device_id = pci_get_device(dev); 4543 pci_subvendor_id = pci_get_subvendor(dev); 4544 pci_subdevice_id = pci_get_subdevice(dev); 4545 pci_rev_id = pci_get_revid(dev); 4546 if (sctx->isc_parse_devinfo != NULL) 4547 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4548 4549 ent = sctx->isc_vendor_info; 4550 while (ent->pvi_vendor_id != 0) { 4551 if (pci_vendor_id != ent->pvi_vendor_id) { 4552 ent++; 4553 continue; 4554 } 4555 if ((pci_device_id == ent->pvi_device_id) && 4556 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4557 (ent->pvi_subvendor_id == 0)) && 4558 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4559 (ent->pvi_subdevice_id == 0)) && 4560 ((pci_rev_id == ent->pvi_rev_id) || 4561 (ent->pvi_rev_id == 0))) { 4562 device_set_desc_copy(dev, ent->pvi_name); 4563 /* this needs to be changed to zero if the bus probing code 4564 * ever stops re-probing on best match because the sctx 4565 * may have its values over written by register calls 4566 * in subsequent probes 4567 */ 4568 return (BUS_PROBE_DEFAULT); 4569 } 4570 ent++; 4571 } 4572 return (ENXIO); 4573 } 4574 4575 int 4576 iflib_device_probe_vendor(device_t dev) 4577 { 4578 int probe; 4579 4580 probe = iflib_device_probe(dev); 4581 if (probe == BUS_PROBE_DEFAULT) 4582 return (BUS_PROBE_VENDOR); 4583 else 4584 return (probe); 4585 } 4586 4587 static void 4588 iflib_reset_qvalues(if_ctx_t ctx) 4589 { 4590 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4591 if_shared_ctx_t sctx = ctx->ifc_sctx; 4592 device_t dev = ctx->ifc_dev; 4593 int i; 4594 4595 if (ctx->ifc_sysctl_ntxqs != 0) 4596 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4597 if (ctx->ifc_sysctl_nrxqs != 0) 4598 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4599 4600 for (i = 0; i < sctx->isc_ntxqs; i++) { 4601 if (ctx->ifc_sysctl_ntxds[i] != 0) 4602 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4603 else 4604 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4605 } 4606 4607 for (i = 0; i < sctx->isc_nrxqs; i++) { 4608 if (ctx->ifc_sysctl_nrxds[i] != 0) 4609 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4610 else 4611 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4612 } 4613 4614 for (i = 0; i < sctx->isc_nrxqs; i++) { 4615 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4616 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4617 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4618 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4619 } 4620 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4621 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4622 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4623 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4624 } 4625 if (!powerof2(scctx->isc_nrxd[i])) { 4626 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4627 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4628 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4629 } 4630 } 4631 4632 for (i = 0; i < sctx->isc_ntxqs; i++) { 4633 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4634 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4635 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4636 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4637 } 4638 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4639 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4640 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4641 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4642 } 4643 if (!powerof2(scctx->isc_ntxd[i])) { 4644 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4645 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4646 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4647 } 4648 } 4649 } 4650 4651 static void 4652 iflib_add_pfil(if_ctx_t ctx) 4653 { 4654 struct pfil_head *pfil; 4655 struct pfil_head_args pa; 4656 iflib_rxq_t rxq; 4657 int i; 4658 4659 pa.pa_version = PFIL_VERSION; 4660 pa.pa_flags = PFIL_IN; 4661 pa.pa_type = PFIL_TYPE_ETHERNET; 4662 pa.pa_headname = ctx->ifc_ifp->if_xname; 4663 pfil = pfil_head_register(&pa); 4664 4665 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4666 rxq->pfil = pfil; 4667 } 4668 } 4669 4670 static void 4671 iflib_rem_pfil(if_ctx_t ctx) 4672 { 4673 struct pfil_head *pfil; 4674 iflib_rxq_t rxq; 4675 int i; 4676 4677 rxq = ctx->ifc_rxqs; 4678 pfil = rxq->pfil; 4679 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4680 rxq->pfil = NULL; 4681 } 4682 pfil_head_unregister(pfil); 4683 } 4684 4685 4686 /* 4687 * Advance forward by n members of the cpuset ctx->ifc_cpus starting from 4688 * cpuid and wrapping as necessary. 4689 */ 4690 static unsigned int 4691 cpuid_advance(if_ctx_t ctx, unsigned int cpuid, unsigned int n) 4692 { 4693 unsigned int first_valid; 4694 unsigned int last_valid; 4695 4696 /* cpuid should always be in the valid set */ 4697 MPASS(CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4698 4699 /* valid set should never be empty */ 4700 MPASS(!CPU_EMPTY(&ctx->ifc_cpus)); 4701 4702 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 4703 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 4704 n = n % CPU_COUNT(&ctx->ifc_cpus); 4705 while (n > 0) { 4706 do { 4707 cpuid++; 4708 if (cpuid > last_valid) 4709 cpuid = first_valid; 4710 } while (!CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4711 n--; 4712 } 4713 4714 return (cpuid); 4715 } 4716 4717 #if defined(SMP) && defined(SCHED_ULE) 4718 extern struct cpu_group *cpu_top; /* CPU topology */ 4719 4720 static int 4721 find_child_with_core(int cpu, struct cpu_group *grp) 4722 { 4723 int i; 4724 4725 if (grp->cg_children == 0) 4726 return -1; 4727 4728 MPASS(grp->cg_child); 4729 for (i = 0; i < grp->cg_children; i++) { 4730 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 4731 return i; 4732 } 4733 4734 return -1; 4735 } 4736 4737 4738 /* 4739 * Find an L2 neighbor of the given CPU or return -1 if none found. This 4740 * does not distinguish among multiple L2 neighbors if the given CPU has 4741 * more than one (it will always return the same result in that case). 4742 */ 4743 static int 4744 find_l2_neighbor(int cpu) 4745 { 4746 struct cpu_group *grp; 4747 int i; 4748 4749 grp = cpu_top; 4750 if (grp == NULL) 4751 return -1; 4752 4753 /* 4754 * Find the smallest CPU group that contains the given core. 4755 */ 4756 i = 0; 4757 while ((i = find_child_with_core(cpu, grp)) != -1) { 4758 /* 4759 * If the smallest group containing the given CPU has less 4760 * than two members, we conclude the given CPU has no 4761 * L2 neighbor. 4762 */ 4763 if (grp->cg_child[i].cg_count <= 1) 4764 return (-1); 4765 grp = &grp->cg_child[i]; 4766 } 4767 4768 /* Must share L2. */ 4769 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 4770 return -1; 4771 4772 /* 4773 * Select the first member of the set that isn't the reference 4774 * CPU, which at this point is guaranteed to exist. 4775 */ 4776 for (i = 0; i < CPU_SETSIZE; i++) { 4777 if (CPU_ISSET(i, &grp->cg_mask) && i != cpu) 4778 return (i); 4779 } 4780 4781 /* Should never be reached */ 4782 return (-1); 4783 } 4784 4785 #else 4786 static int 4787 find_l2_neighbor(int cpu) 4788 { 4789 4790 return (-1); 4791 } 4792 #endif 4793 4794 /* 4795 * CPU mapping behaviors 4796 * --------------------- 4797 * 'separate txrx' refers to the separate_txrx sysctl 4798 * 'use logical' refers to the use_logical_cores sysctl 4799 * 'INTR CPUS' indicates whether bus_get_cpus(INTR_CPUS) succeeded 4800 * 4801 * separate use INTR 4802 * txrx logical CPUS result 4803 * ---------- --------- ------ ------------------------------------------------ 4804 * - - X RX and TX queues mapped to consecutive physical 4805 * cores with RX/TX pairs on same core and excess 4806 * of either following 4807 * - X X RX and TX queues mapped to consecutive cores 4808 * of any type with RX/TX pairs on same core and 4809 * excess of either following 4810 * X - X RX and TX queues mapped to consecutive physical 4811 * cores; all RX then all TX 4812 * X X X RX queues mapped to consecutive physical cores 4813 * first, then TX queues mapped to L2 neighbor of 4814 * the corresponding RX queue if one exists, 4815 * otherwise to consecutive physical cores 4816 * - n/a - RX and TX queues mapped to consecutive cores of 4817 * any type with RX/TX pairs on same core and excess 4818 * of either following 4819 * X n/a - RX and TX queues mapped to consecutive cores of 4820 * any type; all RX then all TX 4821 */ 4822 static unsigned int 4823 get_cpuid_for_queue(if_ctx_t ctx, unsigned int base_cpuid, unsigned int qid, 4824 bool is_tx) 4825 { 4826 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4827 unsigned int core_index; 4828 4829 if (ctx->ifc_sysctl_separate_txrx) { 4830 /* 4831 * When using separate CPUs for TX and RX, the assignment 4832 * will always be of a consecutive CPU out of the set of 4833 * context CPUs, except for the specific case where the 4834 * context CPUs are phsyical cores, the use of logical cores 4835 * has been enabled, the assignment is for TX, the TX qid 4836 * corresponds to an RX qid, and the CPU assigned to the 4837 * corresponding RX queue has an L2 neighbor. 4838 */ 4839 if (ctx->ifc_sysctl_use_logical_cores && 4840 ctx->ifc_cpus_are_physical_cores && 4841 is_tx && qid < scctx->isc_nrxqsets) { 4842 int l2_neighbor; 4843 unsigned int rx_cpuid; 4844 4845 rx_cpuid = cpuid_advance(ctx, base_cpuid, qid); 4846 l2_neighbor = find_l2_neighbor(rx_cpuid); 4847 if (l2_neighbor != -1) { 4848 return (l2_neighbor); 4849 } 4850 /* 4851 * ... else fall through to the normal 4852 * consecutive-after-RX assignment scheme. 4853 * 4854 * Note that we are assuming that all RX queue CPUs 4855 * have an L2 neighbor, or all do not. If a mixed 4856 * scenario is possible, we will have to keep track 4857 * separately of how many queues prior to this one 4858 * were not able to be assigned to an L2 neighbor. 4859 */ 4860 } 4861 if (is_tx) 4862 core_index = scctx->isc_nrxqsets + qid; 4863 else 4864 core_index = qid; 4865 } else { 4866 core_index = qid; 4867 } 4868 4869 return (cpuid_advance(ctx, base_cpuid, core_index)); 4870 } 4871 4872 static uint16_t 4873 get_ctx_core_offset(if_ctx_t ctx) 4874 { 4875 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4876 struct cpu_offset *op; 4877 cpuset_t assigned_cpus; 4878 unsigned int cores_consumed; 4879 unsigned int base_cpuid = ctx->ifc_sysctl_core_offset; 4880 unsigned int first_valid; 4881 unsigned int last_valid; 4882 unsigned int i; 4883 4884 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 4885 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 4886 4887 if (base_cpuid != CORE_OFFSET_UNSPECIFIED) { 4888 /* 4889 * Align the user-chosen base CPU ID to the next valid CPU 4890 * for this device. If the chosen base CPU ID is smaller 4891 * than the first valid CPU or larger than the last valid 4892 * CPU, we assume the user does not know what the valid 4893 * range is for this device and is thinking in terms of a 4894 * zero-based reference frame, and so we shift the given 4895 * value into the valid range (and wrap accordingly) so the 4896 * intent is translated to the proper frame of reference. 4897 * If the base CPU ID is within the valid first/last, but 4898 * does not correspond to a valid CPU, it is advanced to the 4899 * next valid CPU (wrapping if necessary). 4900 */ 4901 if (base_cpuid < first_valid || base_cpuid > last_valid) { 4902 /* shift from zero-based to first_valid-based */ 4903 base_cpuid += first_valid; 4904 /* wrap to range [first_valid, last_valid] */ 4905 base_cpuid = (base_cpuid - first_valid) % 4906 (last_valid - first_valid + 1); 4907 } 4908 if (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) { 4909 /* 4910 * base_cpuid is in [first_valid, last_valid], but 4911 * not a member of the valid set. In this case, 4912 * there will always be a member of the valid set 4913 * with a CPU ID that is greater than base_cpuid, 4914 * and we simply advance to it. 4915 */ 4916 while (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) 4917 base_cpuid++; 4918 } 4919 return (base_cpuid); 4920 } 4921 4922 /* 4923 * Determine how many cores will be consumed by performing the CPU 4924 * assignments and counting how many of the assigned CPUs correspond 4925 * to CPUs in the set of context CPUs. This is done using the CPU 4926 * ID first_valid as the base CPU ID, as the base CPU must be within 4927 * the set of context CPUs. 4928 * 4929 * Note not all assigned CPUs will be in the set of context CPUs 4930 * when separate CPUs are being allocated to TX and RX queues, 4931 * assignment to logical cores has been enabled, the set of context 4932 * CPUs contains only physical CPUs, and TX queues are mapped to L2 4933 * neighbors of CPUs that RX queues have been mapped to - in this 4934 * case we do only want to count how many CPUs in the set of context 4935 * CPUs have been consumed, as that determines the next CPU in that 4936 * set to start allocating at for the next device for which 4937 * core_offset is not set. 4938 */ 4939 CPU_ZERO(&assigned_cpus); 4940 for (i = 0; i < scctx->isc_ntxqsets; i++) 4941 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, true), 4942 &assigned_cpus); 4943 for (i = 0; i < scctx->isc_nrxqsets; i++) 4944 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, false), 4945 &assigned_cpus); 4946 CPU_AND(&assigned_cpus, &ctx->ifc_cpus); 4947 cores_consumed = CPU_COUNT(&assigned_cpus); 4948 4949 mtx_lock(&cpu_offset_mtx); 4950 SLIST_FOREACH(op, &cpu_offsets, entries) { 4951 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4952 base_cpuid = op->next_cpuid; 4953 op->next_cpuid = cpuid_advance(ctx, op->next_cpuid, 4954 cores_consumed); 4955 MPASS(op->refcount < UINT_MAX); 4956 op->refcount++; 4957 break; 4958 } 4959 } 4960 if (base_cpuid == CORE_OFFSET_UNSPECIFIED) { 4961 base_cpuid = first_valid; 4962 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4963 M_NOWAIT | M_ZERO); 4964 if (op == NULL) { 4965 device_printf(ctx->ifc_dev, 4966 "allocation for cpu offset failed.\n"); 4967 } else { 4968 op->next_cpuid = cpuid_advance(ctx, base_cpuid, 4969 cores_consumed); 4970 op->refcount = 1; 4971 CPU_COPY(&ctx->ifc_cpus, &op->set); 4972 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 4973 } 4974 } 4975 mtx_unlock(&cpu_offset_mtx); 4976 4977 return (base_cpuid); 4978 } 4979 4980 static void 4981 unref_ctx_core_offset(if_ctx_t ctx) 4982 { 4983 struct cpu_offset *op, *top; 4984 4985 mtx_lock(&cpu_offset_mtx); 4986 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 4987 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4988 MPASS(op->refcount > 0); 4989 op->refcount--; 4990 if (op->refcount == 0) { 4991 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 4992 free(op, M_IFLIB); 4993 } 4994 break; 4995 } 4996 } 4997 mtx_unlock(&cpu_offset_mtx); 4998 } 4999 5000 int 5001 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 5002 { 5003 if_ctx_t ctx; 5004 if_t ifp; 5005 if_softc_ctx_t scctx; 5006 kobjop_desc_t kobj_desc; 5007 kobj_method_t *kobj_method; 5008 int err, msix, rid; 5009 int num_txd, num_rxd; 5010 5011 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 5012 5013 if (sc == NULL) { 5014 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 5015 device_set_softc(dev, ctx); 5016 ctx->ifc_flags |= IFC_SC_ALLOCATED; 5017 } 5018 5019 ctx->ifc_sctx = sctx; 5020 ctx->ifc_dev = dev; 5021 ctx->ifc_softc = sc; 5022 5023 if ((err = iflib_register(ctx)) != 0) { 5024 device_printf(dev, "iflib_register failed %d\n", err); 5025 goto fail_ctx_free; 5026 } 5027 iflib_add_device_sysctl_pre(ctx); 5028 5029 scctx = &ctx->ifc_softc_ctx; 5030 ifp = ctx->ifc_ifp; 5031 5032 iflib_reset_qvalues(ctx); 5033 CTX_LOCK(ctx); 5034 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5035 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5036 goto fail_unlock; 5037 } 5038 _iflib_pre_assert(scctx); 5039 ctx->ifc_txrx = *scctx->isc_txrx; 5040 5041 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 5042 ctx->ifc_mediap = scctx->isc_media; 5043 5044 #ifdef INVARIANTS 5045 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5046 MPASS(scctx->isc_tx_csum_flags); 5047 #endif 5048 5049 if_setcapabilities(ifp, 5050 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_MEXTPG); 5051 if_setcapenable(ifp, 5052 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_MEXTPG); 5053 5054 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5055 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5056 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5057 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5058 5059 num_txd = iflib_num_tx_descs(ctx); 5060 num_rxd = iflib_num_rx_descs(ctx); 5061 5062 /* XXX change for per-queue sizes */ 5063 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5064 num_txd, num_rxd); 5065 5066 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5067 scctx->isc_tx_nsegments = max(1, num_txd / 5068 MAX_SINGLE_PACKET_FRACTION); 5069 if (scctx->isc_tx_tso_segments_max > num_txd / 5070 MAX_SINGLE_PACKET_FRACTION) 5071 scctx->isc_tx_tso_segments_max = max(1, 5072 num_txd / MAX_SINGLE_PACKET_FRACTION); 5073 5074 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5075 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5076 /* 5077 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5078 * but some MACs do. 5079 */ 5080 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5081 IP_MAXPACKET)); 5082 /* 5083 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5084 * into account. In the worst case, each of these calls will 5085 * add another mbuf and, thus, the requirement for another DMA 5086 * segment. So for best performance, it doesn't make sense to 5087 * advertize a maximum of TSO segments that typically will 5088 * require defragmentation in iflib_encap(). 5089 */ 5090 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5091 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5092 } 5093 if (scctx->isc_rss_table_size == 0) 5094 scctx->isc_rss_table_size = 64; 5095 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 5096 5097 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5098 /* XXX format name */ 5099 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 5100 NULL, NULL, "admin"); 5101 5102 /* Set up cpu set. If it fails, use the set of all CPUs. */ 5103 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 5104 device_printf(dev, "Unable to fetch CPU list\n"); 5105 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 5106 ctx->ifc_cpus_are_physical_cores = false; 5107 } else 5108 ctx->ifc_cpus_are_physical_cores = true; 5109 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 5110 5111 /* 5112 ** Now set up MSI or MSI-X, should return us the number of supported 5113 ** vectors (will be 1 for a legacy interrupt and MSI). 5114 */ 5115 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 5116 msix = scctx->isc_vectors; 5117 } else if (scctx->isc_msix_bar != 0) 5118 /* 5119 * The simple fact that isc_msix_bar is not 0 does not mean we 5120 * we have a good value there that is known to work. 5121 */ 5122 msix = iflib_msix_init(ctx); 5123 else { 5124 scctx->isc_vectors = 1; 5125 scctx->isc_ntxqsets = 1; 5126 scctx->isc_nrxqsets = 1; 5127 scctx->isc_intr = IFLIB_INTR_LEGACY; 5128 msix = 0; 5129 } 5130 /* Get memory for the station queues */ 5131 if ((err = iflib_queues_alloc(ctx))) { 5132 device_printf(dev, "Unable to allocate queue memory\n"); 5133 goto fail_intr_free; 5134 } 5135 5136 if ((err = iflib_qset_structures_setup(ctx))) 5137 goto fail_queues; 5138 5139 /* 5140 * Now that we know how many queues there are, get the core offset. 5141 */ 5142 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 5143 5144 if (msix > 1) { 5145 /* 5146 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 5147 * aren't the default NULL implementation. 5148 */ 5149 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 5150 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5151 kobj_desc); 5152 if (kobj_method == &kobj_desc->deflt) { 5153 device_printf(dev, 5154 "MSI-X requires ifdi_rx_queue_intr_enable method"); 5155 err = EOPNOTSUPP; 5156 goto fail_queues; 5157 } 5158 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 5159 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5160 kobj_desc); 5161 if (kobj_method == &kobj_desc->deflt) { 5162 device_printf(dev, 5163 "MSI-X requires ifdi_tx_queue_intr_enable method"); 5164 err = EOPNOTSUPP; 5165 goto fail_queues; 5166 } 5167 5168 /* 5169 * Assign the MSI-X vectors. 5170 * Note that the default NULL ifdi_msix_intr_assign method will 5171 * fail here, too. 5172 */ 5173 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 5174 if (err != 0) { 5175 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 5176 err); 5177 goto fail_queues; 5178 } 5179 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 5180 rid = 0; 5181 if (scctx->isc_intr == IFLIB_INTR_MSI) { 5182 MPASS(msix == 1); 5183 rid = 1; 5184 } 5185 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 5186 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 5187 goto fail_queues; 5188 } 5189 } else { 5190 device_printf(dev, 5191 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 5192 err = ENODEV; 5193 goto fail_queues; 5194 } 5195 5196 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5197 5198 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5199 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5200 goto fail_detach; 5201 } 5202 5203 /* 5204 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5205 * This must appear after the call to ether_ifattach() because 5206 * ether_ifattach() sets if_hdrlen to the default value. 5207 */ 5208 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5209 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5210 5211 if ((err = iflib_netmap_attach(ctx))) { 5212 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 5213 goto fail_detach; 5214 } 5215 *ctxp = ctx; 5216 5217 DEBUGNET_SET(ctx->ifc_ifp, iflib); 5218 5219 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5220 iflib_add_device_sysctl_post(ctx); 5221 iflib_add_pfil(ctx); 5222 ctx->ifc_flags |= IFC_INIT_DONE; 5223 CTX_UNLOCK(ctx); 5224 5225 return (0); 5226 5227 fail_detach: 5228 ether_ifdetach(ctx->ifc_ifp); 5229 fail_queues: 5230 iflib_tqg_detach(ctx); 5231 iflib_tx_structures_free(ctx); 5232 iflib_rx_structures_free(ctx); 5233 IFDI_DETACH(ctx); 5234 IFDI_QUEUES_FREE(ctx); 5235 fail_intr_free: 5236 iflib_free_intr_mem(ctx); 5237 fail_unlock: 5238 CTX_UNLOCK(ctx); 5239 iflib_deregister(ctx); 5240 fail_ctx_free: 5241 device_set_softc(ctx->ifc_dev, NULL); 5242 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5243 free(ctx->ifc_softc, M_IFLIB); 5244 free(ctx, M_IFLIB); 5245 return (err); 5246 } 5247 5248 int 5249 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 5250 struct iflib_cloneattach_ctx *clctx) 5251 { 5252 int num_txd, num_rxd; 5253 int err; 5254 if_ctx_t ctx; 5255 if_t ifp; 5256 if_softc_ctx_t scctx; 5257 int i; 5258 void *sc; 5259 5260 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 5261 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 5262 ctx->ifc_flags |= IFC_SC_ALLOCATED; 5263 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 5264 ctx->ifc_flags |= IFC_PSEUDO; 5265 5266 ctx->ifc_sctx = sctx; 5267 ctx->ifc_softc = sc; 5268 ctx->ifc_dev = dev; 5269 5270 if ((err = iflib_register(ctx)) != 0) { 5271 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 5272 goto fail_ctx_free; 5273 } 5274 iflib_add_device_sysctl_pre(ctx); 5275 5276 scctx = &ctx->ifc_softc_ctx; 5277 ifp = ctx->ifc_ifp; 5278 5279 iflib_reset_qvalues(ctx); 5280 CTX_LOCK(ctx); 5281 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5282 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5283 goto fail_unlock; 5284 } 5285 if (sctx->isc_flags & IFLIB_GEN_MAC) 5286 ether_gen_addr(ifp, &ctx->ifc_mac); 5287 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 5288 clctx->cc_params)) != 0) { 5289 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 5290 goto fail_unlock; 5291 } 5292 #ifdef INVARIANTS 5293 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5294 MPASS(scctx->isc_tx_csum_flags); 5295 #endif 5296 5297 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 5298 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 5299 5300 ifp->if_flags |= IFF_NOGROUP; 5301 if (sctx->isc_flags & IFLIB_PSEUDO) { 5302 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 5303 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 5304 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) { 5305 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5306 } else { 5307 if_attach(ctx->ifc_ifp); 5308 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t)); 5309 } 5310 5311 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5312 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5313 goto fail_detach; 5314 } 5315 *ctxp = ctx; 5316 5317 /* 5318 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5319 * This must appear after the call to ether_ifattach() because 5320 * ether_ifattach() sets if_hdrlen to the default value. 5321 */ 5322 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5323 if_setifheaderlen(ifp, 5324 sizeof(struct ether_vlan_header)); 5325 5326 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5327 iflib_add_device_sysctl_post(ctx); 5328 ctx->ifc_flags |= IFC_INIT_DONE; 5329 CTX_UNLOCK(ctx); 5330 return (0); 5331 } 5332 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 5333 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 5334 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 5335 5336 _iflib_pre_assert(scctx); 5337 ctx->ifc_txrx = *scctx->isc_txrx; 5338 5339 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5340 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5341 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5342 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5343 5344 num_txd = iflib_num_tx_descs(ctx); 5345 num_rxd = iflib_num_rx_descs(ctx); 5346 5347 /* XXX change for per-queue sizes */ 5348 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5349 num_txd, num_rxd); 5350 5351 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5352 scctx->isc_tx_nsegments = max(1, num_txd / 5353 MAX_SINGLE_PACKET_FRACTION); 5354 if (scctx->isc_tx_tso_segments_max > num_txd / 5355 MAX_SINGLE_PACKET_FRACTION) 5356 scctx->isc_tx_tso_segments_max = max(1, 5357 num_txd / MAX_SINGLE_PACKET_FRACTION); 5358 5359 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5360 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5361 /* 5362 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5363 * but some MACs do. 5364 */ 5365 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5366 IP_MAXPACKET)); 5367 /* 5368 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5369 * into account. In the worst case, each of these calls will 5370 * add another mbuf and, thus, the requirement for another DMA 5371 * segment. So for best performance, it doesn't make sense to 5372 * advertize a maximum of TSO segments that typically will 5373 * require defragmentation in iflib_encap(). 5374 */ 5375 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5376 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5377 } 5378 if (scctx->isc_rss_table_size == 0) 5379 scctx->isc_rss_table_size = 64; 5380 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 5381 5382 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5383 /* XXX format name */ 5384 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 5385 NULL, NULL, "admin"); 5386 5387 /* XXX --- can support > 1 -- but keep it simple for now */ 5388 scctx->isc_intr = IFLIB_INTR_LEGACY; 5389 5390 /* Get memory for the station queues */ 5391 if ((err = iflib_queues_alloc(ctx))) { 5392 device_printf(dev, "Unable to allocate queue memory\n"); 5393 goto fail_iflib_detach; 5394 } 5395 5396 if ((err = iflib_qset_structures_setup(ctx))) { 5397 device_printf(dev, "qset structure setup failed %d\n", err); 5398 goto fail_queues; 5399 } 5400 5401 /* 5402 * XXX What if anything do we want to do about interrupts? 5403 */ 5404 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5405 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5406 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5407 goto fail_detach; 5408 } 5409 5410 /* 5411 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5412 * This must appear after the call to ether_ifattach() because 5413 * ether_ifattach() sets if_hdrlen to the default value. 5414 */ 5415 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5416 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5417 5418 /* XXX handle more than one queue */ 5419 for (i = 0; i < scctx->isc_nrxqsets; i++) 5420 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 5421 5422 *ctxp = ctx; 5423 5424 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5425 iflib_add_device_sysctl_post(ctx); 5426 ctx->ifc_flags |= IFC_INIT_DONE; 5427 CTX_UNLOCK(ctx); 5428 5429 return (0); 5430 fail_detach: 5431 ether_ifdetach(ctx->ifc_ifp); 5432 fail_queues: 5433 iflib_tqg_detach(ctx); 5434 iflib_tx_structures_free(ctx); 5435 iflib_rx_structures_free(ctx); 5436 fail_iflib_detach: 5437 IFDI_DETACH(ctx); 5438 IFDI_QUEUES_FREE(ctx); 5439 fail_unlock: 5440 CTX_UNLOCK(ctx); 5441 iflib_deregister(ctx); 5442 fail_ctx_free: 5443 free(ctx->ifc_softc, M_IFLIB); 5444 free(ctx, M_IFLIB); 5445 return (err); 5446 } 5447 5448 int 5449 iflib_pseudo_deregister(if_ctx_t ctx) 5450 { 5451 if_t ifp = ctx->ifc_ifp; 5452 if_shared_ctx_t sctx = ctx->ifc_sctx; 5453 5454 /* Unregister VLAN event handlers early */ 5455 iflib_unregister_vlan_handlers(ctx); 5456 5457 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5458 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) { 5459 bpfdetach(ifp); 5460 if_detach(ifp); 5461 } else { 5462 ether_ifdetach(ifp); 5463 } 5464 5465 iflib_tqg_detach(ctx); 5466 iflib_tx_structures_free(ctx); 5467 iflib_rx_structures_free(ctx); 5468 IFDI_DETACH(ctx); 5469 IFDI_QUEUES_FREE(ctx); 5470 5471 iflib_deregister(ctx); 5472 5473 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5474 free(ctx->ifc_softc, M_IFLIB); 5475 free(ctx, M_IFLIB); 5476 return (0); 5477 } 5478 5479 int 5480 iflib_device_attach(device_t dev) 5481 { 5482 if_ctx_t ctx; 5483 if_shared_ctx_t sctx; 5484 5485 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5486 return (ENOTSUP); 5487 5488 pci_enable_busmaster(dev); 5489 5490 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5491 } 5492 5493 int 5494 iflib_device_deregister(if_ctx_t ctx) 5495 { 5496 if_t ifp = ctx->ifc_ifp; 5497 device_t dev = ctx->ifc_dev; 5498 5499 /* Make sure VLANS are not using driver */ 5500 if (if_vlantrunkinuse(ifp)) { 5501 device_printf(dev, "Vlan in use, detach first\n"); 5502 return (EBUSY); 5503 } 5504 #ifdef PCI_IOV 5505 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5506 device_printf(dev, "SR-IOV in use; detach first.\n"); 5507 return (EBUSY); 5508 } 5509 #endif 5510 5511 STATE_LOCK(ctx); 5512 ctx->ifc_flags |= IFC_IN_DETACH; 5513 STATE_UNLOCK(ctx); 5514 5515 /* Unregister VLAN handlers before calling iflib_stop() */ 5516 iflib_unregister_vlan_handlers(ctx); 5517 5518 iflib_netmap_detach(ifp); 5519 ether_ifdetach(ifp); 5520 5521 CTX_LOCK(ctx); 5522 iflib_stop(ctx); 5523 CTX_UNLOCK(ctx); 5524 5525 iflib_rem_pfil(ctx); 5526 if (ctx->ifc_led_dev != NULL) 5527 led_destroy(ctx->ifc_led_dev); 5528 5529 iflib_tqg_detach(ctx); 5530 iflib_tx_structures_free(ctx); 5531 iflib_rx_structures_free(ctx); 5532 5533 CTX_LOCK(ctx); 5534 IFDI_DETACH(ctx); 5535 IFDI_QUEUES_FREE(ctx); 5536 CTX_UNLOCK(ctx); 5537 5538 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5539 iflib_free_intr_mem(ctx); 5540 5541 bus_generic_detach(dev); 5542 5543 iflib_deregister(ctx); 5544 5545 device_set_softc(ctx->ifc_dev, NULL); 5546 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5547 free(ctx->ifc_softc, M_IFLIB); 5548 unref_ctx_core_offset(ctx); 5549 free(ctx, M_IFLIB); 5550 return (0); 5551 } 5552 5553 static void 5554 iflib_tqg_detach(if_ctx_t ctx) 5555 { 5556 iflib_txq_t txq; 5557 iflib_rxq_t rxq; 5558 int i; 5559 struct taskqgroup *tqg; 5560 5561 /* XXX drain any dependent tasks */ 5562 tqg = qgroup_if_io_tqg; 5563 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5564 callout_drain(&txq->ift_timer); 5565 #ifdef DEV_NETMAP 5566 callout_drain(&txq->ift_netmap_timer); 5567 #endif /* DEV_NETMAP */ 5568 if (txq->ift_task.gt_uniq != NULL) 5569 taskqgroup_detach(tqg, &txq->ift_task); 5570 } 5571 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5572 if (rxq->ifr_task.gt_uniq != NULL) 5573 taskqgroup_detach(tqg, &rxq->ifr_task); 5574 } 5575 tqg = qgroup_if_config_tqg; 5576 if (ctx->ifc_admin_task.gt_uniq != NULL) 5577 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5578 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5579 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5580 } 5581 5582 static void 5583 iflib_free_intr_mem(if_ctx_t ctx) 5584 { 5585 5586 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5587 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5588 } 5589 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5590 pci_release_msi(ctx->ifc_dev); 5591 } 5592 if (ctx->ifc_msix_mem != NULL) { 5593 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5594 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5595 ctx->ifc_msix_mem = NULL; 5596 } 5597 } 5598 5599 int 5600 iflib_device_detach(device_t dev) 5601 { 5602 if_ctx_t ctx = device_get_softc(dev); 5603 5604 return (iflib_device_deregister(ctx)); 5605 } 5606 5607 int 5608 iflib_device_suspend(device_t dev) 5609 { 5610 if_ctx_t ctx = device_get_softc(dev); 5611 5612 CTX_LOCK(ctx); 5613 IFDI_SUSPEND(ctx); 5614 CTX_UNLOCK(ctx); 5615 5616 return bus_generic_suspend(dev); 5617 } 5618 int 5619 iflib_device_shutdown(device_t dev) 5620 { 5621 if_ctx_t ctx = device_get_softc(dev); 5622 5623 CTX_LOCK(ctx); 5624 IFDI_SHUTDOWN(ctx); 5625 CTX_UNLOCK(ctx); 5626 5627 return bus_generic_suspend(dev); 5628 } 5629 5630 int 5631 iflib_device_resume(device_t dev) 5632 { 5633 if_ctx_t ctx = device_get_softc(dev); 5634 iflib_txq_t txq = ctx->ifc_txqs; 5635 5636 CTX_LOCK(ctx); 5637 IFDI_RESUME(ctx); 5638 iflib_if_init_locked(ctx); 5639 CTX_UNLOCK(ctx); 5640 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5641 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5642 5643 return (bus_generic_resume(dev)); 5644 } 5645 5646 int 5647 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5648 { 5649 int error; 5650 if_ctx_t ctx = device_get_softc(dev); 5651 5652 CTX_LOCK(ctx); 5653 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5654 CTX_UNLOCK(ctx); 5655 5656 return (error); 5657 } 5658 5659 void 5660 iflib_device_iov_uninit(device_t dev) 5661 { 5662 if_ctx_t ctx = device_get_softc(dev); 5663 5664 CTX_LOCK(ctx); 5665 IFDI_IOV_UNINIT(ctx); 5666 CTX_UNLOCK(ctx); 5667 } 5668 5669 int 5670 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5671 { 5672 int error; 5673 if_ctx_t ctx = device_get_softc(dev); 5674 5675 CTX_LOCK(ctx); 5676 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5677 CTX_UNLOCK(ctx); 5678 5679 return (error); 5680 } 5681 5682 /********************************************************************* 5683 * 5684 * MODULE FUNCTION DEFINITIONS 5685 * 5686 **********************************************************************/ 5687 5688 /* 5689 * - Start a fast taskqueue thread for each core 5690 * - Start a taskqueue for control operations 5691 */ 5692 static int 5693 iflib_module_init(void) 5694 { 5695 iflib_timer_default = hz / 2; 5696 return (0); 5697 } 5698 5699 static int 5700 iflib_module_event_handler(module_t mod, int what, void *arg) 5701 { 5702 int err; 5703 5704 switch (what) { 5705 case MOD_LOAD: 5706 if ((err = iflib_module_init()) != 0) 5707 return (err); 5708 break; 5709 case MOD_UNLOAD: 5710 return (EBUSY); 5711 default: 5712 return (EOPNOTSUPP); 5713 } 5714 5715 return (0); 5716 } 5717 5718 /********************************************************************* 5719 * 5720 * PUBLIC FUNCTION DEFINITIONS 5721 * ordered as in iflib.h 5722 * 5723 **********************************************************************/ 5724 5725 static void 5726 _iflib_assert(if_shared_ctx_t sctx) 5727 { 5728 int i; 5729 5730 MPASS(sctx->isc_tx_maxsize); 5731 MPASS(sctx->isc_tx_maxsegsize); 5732 5733 MPASS(sctx->isc_rx_maxsize); 5734 MPASS(sctx->isc_rx_nsegments); 5735 MPASS(sctx->isc_rx_maxsegsize); 5736 5737 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5738 for (i = 0; i < sctx->isc_nrxqs; i++) { 5739 MPASS(sctx->isc_nrxd_min[i]); 5740 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5741 MPASS(sctx->isc_nrxd_max[i]); 5742 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5743 MPASS(sctx->isc_nrxd_default[i]); 5744 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5745 } 5746 5747 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5748 for (i = 0; i < sctx->isc_ntxqs; i++) { 5749 MPASS(sctx->isc_ntxd_min[i]); 5750 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5751 MPASS(sctx->isc_ntxd_max[i]); 5752 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5753 MPASS(sctx->isc_ntxd_default[i]); 5754 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5755 } 5756 } 5757 5758 static void 5759 _iflib_pre_assert(if_softc_ctx_t scctx) 5760 { 5761 5762 MPASS(scctx->isc_txrx->ift_txd_encap); 5763 MPASS(scctx->isc_txrx->ift_txd_flush); 5764 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5765 MPASS(scctx->isc_txrx->ift_rxd_available); 5766 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5767 MPASS(scctx->isc_txrx->ift_rxd_refill); 5768 MPASS(scctx->isc_txrx->ift_rxd_flush); 5769 } 5770 5771 static int 5772 iflib_register(if_ctx_t ctx) 5773 { 5774 if_shared_ctx_t sctx = ctx->ifc_sctx; 5775 driver_t *driver = sctx->isc_driver; 5776 device_t dev = ctx->ifc_dev; 5777 if_t ifp; 5778 u_char type; 5779 int iflags; 5780 5781 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0) 5782 _iflib_assert(sctx); 5783 5784 CTX_LOCK_INIT(ctx); 5785 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5786 if (sctx->isc_flags & IFLIB_PSEUDO) { 5787 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) 5788 type = IFT_ETHER; 5789 else 5790 type = IFT_PPP; 5791 } else 5792 type = IFT_ETHER; 5793 ifp = ctx->ifc_ifp = if_alloc(type); 5794 if (ifp == NULL) { 5795 device_printf(dev, "can not allocate ifnet structure\n"); 5796 return (ENOMEM); 5797 } 5798 5799 /* 5800 * Initialize our context's device specific methods 5801 */ 5802 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5803 kobj_class_compile((kobj_class_t) driver); 5804 5805 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5806 if_setsoftc(ifp, ctx); 5807 if_setdev(ifp, dev); 5808 if_setinitfn(ifp, iflib_if_init); 5809 if_setioctlfn(ifp, iflib_if_ioctl); 5810 #ifdef ALTQ 5811 if_setstartfn(ifp, iflib_altq_if_start); 5812 if_settransmitfn(ifp, iflib_altq_if_transmit); 5813 if_setsendqready(ifp); 5814 #else 5815 if_settransmitfn(ifp, iflib_if_transmit); 5816 #endif 5817 if_setqflushfn(ifp, iflib_if_qflush); 5818 iflags = IFF_MULTICAST | IFF_KNOWSEPOCH; 5819 5820 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5821 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) 5822 iflags |= IFF_POINTOPOINT; 5823 else 5824 iflags |= IFF_BROADCAST | IFF_SIMPLEX; 5825 if_setflags(ifp, iflags); 5826 ctx->ifc_vlan_attach_event = 5827 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5828 EVENTHANDLER_PRI_FIRST); 5829 ctx->ifc_vlan_detach_event = 5830 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5831 EVENTHANDLER_PRI_FIRST); 5832 5833 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5834 ctx->ifc_mediap = &ctx->ifc_media; 5835 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5836 iflib_media_change, iflib_media_status); 5837 } 5838 return (0); 5839 } 5840 5841 static void 5842 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5843 { 5844 /* Unregister VLAN events */ 5845 if (ctx->ifc_vlan_attach_event != NULL) { 5846 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5847 ctx->ifc_vlan_attach_event = NULL; 5848 } 5849 if (ctx->ifc_vlan_detach_event != NULL) { 5850 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5851 ctx->ifc_vlan_detach_event = NULL; 5852 } 5853 5854 } 5855 5856 static void 5857 iflib_deregister(if_ctx_t ctx) 5858 { 5859 if_t ifp = ctx->ifc_ifp; 5860 5861 /* Remove all media */ 5862 ifmedia_removeall(&ctx->ifc_media); 5863 5864 /* Ensure that VLAN event handlers are unregistered */ 5865 iflib_unregister_vlan_handlers(ctx); 5866 5867 /* Release kobject reference */ 5868 kobj_delete((kobj_t) ctx, NULL); 5869 5870 /* Free the ifnet structure */ 5871 if_free(ifp); 5872 5873 STATE_LOCK_DESTROY(ctx); 5874 5875 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5876 CTX_LOCK_DESTROY(ctx); 5877 } 5878 5879 static int 5880 iflib_queues_alloc(if_ctx_t ctx) 5881 { 5882 if_shared_ctx_t sctx = ctx->ifc_sctx; 5883 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5884 device_t dev = ctx->ifc_dev; 5885 int nrxqsets = scctx->isc_nrxqsets; 5886 int ntxqsets = scctx->isc_ntxqsets; 5887 iflib_txq_t txq; 5888 iflib_rxq_t rxq; 5889 iflib_fl_t fl = NULL; 5890 int i, j, cpu, err, txconf, rxconf; 5891 iflib_dma_info_t ifdip; 5892 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5893 uint32_t *txqsizes = scctx->isc_txqsizes; 5894 uint8_t nrxqs = sctx->isc_nrxqs; 5895 uint8_t ntxqs = sctx->isc_ntxqs; 5896 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5897 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0); 5898 caddr_t *vaddrs; 5899 uint64_t *paddrs; 5900 5901 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5902 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5903 KASSERT(nrxqs >= fl_offset + nfree_lists, 5904 ("there must be at least a rxq for each free list")); 5905 5906 /* Allocate the TX ring struct memory */ 5907 if (!(ctx->ifc_txqs = 5908 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5909 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5910 device_printf(dev, "Unable to allocate TX ring memory\n"); 5911 err = ENOMEM; 5912 goto fail; 5913 } 5914 5915 /* Now allocate the RX */ 5916 if (!(ctx->ifc_rxqs = 5917 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5918 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5919 device_printf(dev, "Unable to allocate RX ring memory\n"); 5920 err = ENOMEM; 5921 goto rx_fail; 5922 } 5923 5924 txq = ctx->ifc_txqs; 5925 rxq = ctx->ifc_rxqs; 5926 5927 /* 5928 * XXX handle allocation failure 5929 */ 5930 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5931 /* Set up some basics */ 5932 5933 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5934 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5935 device_printf(dev, 5936 "Unable to allocate TX DMA info memory\n"); 5937 err = ENOMEM; 5938 goto err_tx_desc; 5939 } 5940 txq->ift_ifdi = ifdip; 5941 for (j = 0; j < ntxqs; j++, ifdip++) { 5942 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5943 device_printf(dev, 5944 "Unable to allocate TX descriptors\n"); 5945 err = ENOMEM; 5946 goto err_tx_desc; 5947 } 5948 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5949 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5950 } 5951 txq->ift_ctx = ctx; 5952 txq->ift_id = i; 5953 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5954 txq->ift_br_offset = 1; 5955 } else { 5956 txq->ift_br_offset = 0; 5957 } 5958 5959 if (iflib_txsd_alloc(txq)) { 5960 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5961 err = ENOMEM; 5962 goto err_tx_desc; 5963 } 5964 5965 /* Initialize the TX lock */ 5966 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5967 device_get_nameunit(dev), txq->ift_id); 5968 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5969 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5970 txq->ift_timer.c_cpu = cpu; 5971 #ifdef DEV_NETMAP 5972 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0); 5973 txq->ift_netmap_timer.c_cpu = cpu; 5974 #endif /* DEV_NETMAP */ 5975 5976 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5977 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5978 if (err) { 5979 /* XXX free any allocated rings */ 5980 device_printf(dev, "Unable to allocate buf_ring\n"); 5981 goto err_tx_desc; 5982 } 5983 } 5984 5985 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5986 /* Set up some basics */ 5987 callout_init(&rxq->ifr_watchdog, 1); 5988 5989 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5990 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5991 device_printf(dev, 5992 "Unable to allocate RX DMA info memory\n"); 5993 err = ENOMEM; 5994 goto err_tx_desc; 5995 } 5996 5997 rxq->ifr_ifdi = ifdip; 5998 /* XXX this needs to be changed if #rx queues != #tx queues */ 5999 rxq->ifr_ntxqirq = 1; 6000 rxq->ifr_txqid[0] = i; 6001 for (j = 0; j < nrxqs; j++, ifdip++) { 6002 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 6003 device_printf(dev, 6004 "Unable to allocate RX descriptors\n"); 6005 err = ENOMEM; 6006 goto err_tx_desc; 6007 } 6008 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 6009 } 6010 rxq->ifr_ctx = ctx; 6011 rxq->ifr_id = i; 6012 rxq->ifr_fl_offset = fl_offset; 6013 rxq->ifr_nfl = nfree_lists; 6014 if (!(fl = 6015 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 6016 device_printf(dev, "Unable to allocate free list memory\n"); 6017 err = ENOMEM; 6018 goto err_tx_desc; 6019 } 6020 rxq->ifr_fl = fl; 6021 for (j = 0; j < nfree_lists; j++) { 6022 fl[j].ifl_rxq = rxq; 6023 fl[j].ifl_id = j; 6024 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 6025 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 6026 } 6027 /* Allocate receive buffers for the ring */ 6028 if (iflib_rxsd_alloc(rxq)) { 6029 device_printf(dev, 6030 "Critical Failure setting up receive buffers\n"); 6031 err = ENOMEM; 6032 goto err_rx_desc; 6033 } 6034 6035 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 6036 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 6037 M_WAITOK); 6038 } 6039 6040 /* TXQs */ 6041 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 6042 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 6043 for (i = 0; i < ntxqsets; i++) { 6044 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 6045 6046 for (j = 0; j < ntxqs; j++, di++) { 6047 vaddrs[i*ntxqs + j] = di->idi_vaddr; 6048 paddrs[i*ntxqs + j] = di->idi_paddr; 6049 } 6050 } 6051 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 6052 device_printf(ctx->ifc_dev, 6053 "Unable to allocate device TX queue\n"); 6054 iflib_tx_structures_free(ctx); 6055 free(vaddrs, M_IFLIB); 6056 free(paddrs, M_IFLIB); 6057 goto err_rx_desc; 6058 } 6059 free(vaddrs, M_IFLIB); 6060 free(paddrs, M_IFLIB); 6061 6062 /* RXQs */ 6063 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 6064 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 6065 for (i = 0; i < nrxqsets; i++) { 6066 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 6067 6068 for (j = 0; j < nrxqs; j++, di++) { 6069 vaddrs[i*nrxqs + j] = di->idi_vaddr; 6070 paddrs[i*nrxqs + j] = di->idi_paddr; 6071 } 6072 } 6073 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 6074 device_printf(ctx->ifc_dev, 6075 "Unable to allocate device RX queue\n"); 6076 iflib_tx_structures_free(ctx); 6077 free(vaddrs, M_IFLIB); 6078 free(paddrs, M_IFLIB); 6079 goto err_rx_desc; 6080 } 6081 free(vaddrs, M_IFLIB); 6082 free(paddrs, M_IFLIB); 6083 6084 return (0); 6085 6086 /* XXX handle allocation failure changes */ 6087 err_rx_desc: 6088 err_tx_desc: 6089 rx_fail: 6090 if (ctx->ifc_rxqs != NULL) 6091 free(ctx->ifc_rxqs, M_IFLIB); 6092 ctx->ifc_rxqs = NULL; 6093 if (ctx->ifc_txqs != NULL) 6094 free(ctx->ifc_txqs, M_IFLIB); 6095 ctx->ifc_txqs = NULL; 6096 fail: 6097 return (err); 6098 } 6099 6100 static int 6101 iflib_tx_structures_setup(if_ctx_t ctx) 6102 { 6103 iflib_txq_t txq = ctx->ifc_txqs; 6104 int i; 6105 6106 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 6107 iflib_txq_setup(txq); 6108 6109 return (0); 6110 } 6111 6112 static void 6113 iflib_tx_structures_free(if_ctx_t ctx) 6114 { 6115 iflib_txq_t txq = ctx->ifc_txqs; 6116 if_shared_ctx_t sctx = ctx->ifc_sctx; 6117 int i, j; 6118 6119 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 6120 for (j = 0; j < sctx->isc_ntxqs; j++) 6121 iflib_dma_free(&txq->ift_ifdi[j]); 6122 iflib_txq_destroy(txq); 6123 } 6124 free(ctx->ifc_txqs, M_IFLIB); 6125 ctx->ifc_txqs = NULL; 6126 } 6127 6128 /********************************************************************* 6129 * 6130 * Initialize all receive rings. 6131 * 6132 **********************************************************************/ 6133 static int 6134 iflib_rx_structures_setup(if_ctx_t ctx) 6135 { 6136 iflib_rxq_t rxq = ctx->ifc_rxqs; 6137 int q; 6138 #if defined(INET6) || defined(INET) 6139 int err, i; 6140 #endif 6141 6142 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 6143 #if defined(INET6) || defined(INET) 6144 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) { 6145 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 6146 TCP_LRO_ENTRIES, min(1024, 6147 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 6148 if (err != 0) { 6149 device_printf(ctx->ifc_dev, 6150 "LRO Initialization failed!\n"); 6151 goto fail; 6152 } 6153 } 6154 #endif 6155 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 6156 } 6157 return (0); 6158 #if defined(INET6) || defined(INET) 6159 fail: 6160 /* 6161 * Free LRO resources allocated so far, we will only handle 6162 * the rings that completed, the failing case will have 6163 * cleaned up for itself. 'q' failed, so its the terminus. 6164 */ 6165 rxq = ctx->ifc_rxqs; 6166 for (i = 0; i < q; ++i, rxq++) { 6167 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 6168 tcp_lro_free(&rxq->ifr_lc); 6169 } 6170 return (err); 6171 #endif 6172 } 6173 6174 /********************************************************************* 6175 * 6176 * Free all receive rings. 6177 * 6178 **********************************************************************/ 6179 static void 6180 iflib_rx_structures_free(if_ctx_t ctx) 6181 { 6182 iflib_rxq_t rxq = ctx->ifc_rxqs; 6183 if_shared_ctx_t sctx = ctx->ifc_sctx; 6184 int i, j; 6185 6186 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 6187 for (j = 0; j < sctx->isc_nrxqs; j++) 6188 iflib_dma_free(&rxq->ifr_ifdi[j]); 6189 iflib_rx_sds_free(rxq); 6190 #if defined(INET6) || defined(INET) 6191 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 6192 tcp_lro_free(&rxq->ifr_lc); 6193 #endif 6194 } 6195 free(ctx->ifc_rxqs, M_IFLIB); 6196 ctx->ifc_rxqs = NULL; 6197 } 6198 6199 static int 6200 iflib_qset_structures_setup(if_ctx_t ctx) 6201 { 6202 int err; 6203 6204 /* 6205 * It is expected that the caller takes care of freeing queues if this 6206 * fails. 6207 */ 6208 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 6209 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 6210 return (err); 6211 } 6212 6213 if ((err = iflib_rx_structures_setup(ctx)) != 0) 6214 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 6215 6216 return (err); 6217 } 6218 6219 int 6220 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 6221 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 6222 { 6223 6224 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 6225 } 6226 6227 /* Just to avoid copy/paste */ 6228 static inline int 6229 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6230 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 6231 const char *name) 6232 { 6233 device_t dev; 6234 unsigned int base_cpuid, cpuid; 6235 int err; 6236 6237 dev = ctx->ifc_dev; 6238 base_cpuid = ctx->ifc_sysctl_core_offset; 6239 cpuid = get_cpuid_for_queue(ctx, base_cpuid, qid, type == IFLIB_INTR_TX); 6240 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, 6241 irq ? irq->ii_res : NULL, name); 6242 if (err) { 6243 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 6244 return (err); 6245 } 6246 #ifdef notyet 6247 if (cpuid > ctx->ifc_cpuid_highest) 6248 ctx->ifc_cpuid_highest = cpuid; 6249 #endif 6250 return (0); 6251 } 6252 6253 int 6254 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 6255 iflib_intr_type_t type, driver_filter_t *filter, 6256 void *filter_arg, int qid, const char *name) 6257 { 6258 device_t dev; 6259 struct grouptask *gtask; 6260 struct taskqgroup *tqg; 6261 iflib_filter_info_t info; 6262 gtask_fn_t *fn; 6263 int tqrid, err; 6264 driver_filter_t *intr_fast; 6265 void *q; 6266 6267 info = &ctx->ifc_filter_info; 6268 tqrid = rid; 6269 6270 switch (type) { 6271 /* XXX merge tx/rx for netmap? */ 6272 case IFLIB_INTR_TX: 6273 q = &ctx->ifc_txqs[qid]; 6274 info = &ctx->ifc_txqs[qid].ift_filter_info; 6275 gtask = &ctx->ifc_txqs[qid].ift_task; 6276 tqg = qgroup_if_io_tqg; 6277 fn = _task_fn_tx; 6278 intr_fast = iflib_fast_intr; 6279 GROUPTASK_INIT(gtask, 0, fn, q); 6280 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 6281 break; 6282 case IFLIB_INTR_RX: 6283 q = &ctx->ifc_rxqs[qid]; 6284 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6285 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6286 tqg = qgroup_if_io_tqg; 6287 fn = _task_fn_rx; 6288 intr_fast = iflib_fast_intr; 6289 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6290 break; 6291 case IFLIB_INTR_RXTX: 6292 q = &ctx->ifc_rxqs[qid]; 6293 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6294 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6295 tqg = qgroup_if_io_tqg; 6296 fn = _task_fn_rx; 6297 intr_fast = iflib_fast_intr_rxtx; 6298 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6299 break; 6300 case IFLIB_INTR_ADMIN: 6301 q = ctx; 6302 tqrid = -1; 6303 info = &ctx->ifc_filter_info; 6304 gtask = &ctx->ifc_admin_task; 6305 tqg = qgroup_if_config_tqg; 6306 fn = _task_fn_admin; 6307 intr_fast = iflib_fast_intr_ctx; 6308 break; 6309 default: 6310 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6311 __func__); 6312 return (EINVAL); 6313 } 6314 6315 info->ifi_filter = filter; 6316 info->ifi_filter_arg = filter_arg; 6317 info->ifi_task = gtask; 6318 info->ifi_ctx = q; 6319 6320 dev = ctx->ifc_dev; 6321 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6322 if (err != 0) { 6323 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6324 return (err); 6325 } 6326 if (type == IFLIB_INTR_ADMIN) 6327 return (0); 6328 6329 if (tqrid != -1) { 6330 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 6331 name); 6332 if (err) 6333 return (err); 6334 } else { 6335 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6336 } 6337 6338 return (0); 6339 } 6340 6341 void 6342 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 6343 { 6344 device_t dev; 6345 struct grouptask *gtask; 6346 struct taskqgroup *tqg; 6347 gtask_fn_t *fn; 6348 void *q; 6349 int err; 6350 6351 switch (type) { 6352 case IFLIB_INTR_TX: 6353 q = &ctx->ifc_txqs[qid]; 6354 gtask = &ctx->ifc_txqs[qid].ift_task; 6355 tqg = qgroup_if_io_tqg; 6356 fn = _task_fn_tx; 6357 GROUPTASK_INIT(gtask, 0, fn, q); 6358 break; 6359 case IFLIB_INTR_RX: 6360 q = &ctx->ifc_rxqs[qid]; 6361 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6362 tqg = qgroup_if_io_tqg; 6363 fn = _task_fn_rx; 6364 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6365 break; 6366 case IFLIB_INTR_IOV: 6367 q = ctx; 6368 gtask = &ctx->ifc_vflr_task; 6369 tqg = qgroup_if_config_tqg; 6370 fn = _task_fn_iov; 6371 GROUPTASK_INIT(gtask, 0, fn, q); 6372 break; 6373 default: 6374 panic("unknown net intr type"); 6375 } 6376 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, name); 6377 if (err) { 6378 dev = ctx->ifc_dev; 6379 taskqgroup_attach(tqg, gtask, q, dev, irq ? irq->ii_res : NULL, 6380 name); 6381 } 6382 } 6383 6384 void 6385 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6386 { 6387 6388 if (irq->ii_tag) 6389 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6390 6391 if (irq->ii_res) 6392 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6393 rman_get_rid(irq->ii_res), irq->ii_res); 6394 } 6395 6396 static int 6397 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6398 { 6399 iflib_txq_t txq = ctx->ifc_txqs; 6400 iflib_rxq_t rxq = ctx->ifc_rxqs; 6401 if_irq_t irq = &ctx->ifc_legacy_irq; 6402 iflib_filter_info_t info; 6403 device_t dev; 6404 struct grouptask *gtask; 6405 struct resource *res; 6406 struct taskqgroup *tqg; 6407 void *q; 6408 int err, tqrid; 6409 bool rx_only; 6410 6411 q = &ctx->ifc_rxqs[0]; 6412 info = &rxq[0].ifr_filter_info; 6413 gtask = &rxq[0].ifr_task; 6414 tqg = qgroup_if_io_tqg; 6415 tqrid = *rid; 6416 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6417 6418 ctx->ifc_flags |= IFC_LEGACY; 6419 info->ifi_filter = filter; 6420 info->ifi_filter_arg = filter_arg; 6421 info->ifi_task = gtask; 6422 info->ifi_ctx = rx_only ? ctx : q; 6423 6424 dev = ctx->ifc_dev; 6425 /* We allocate a single interrupt resource */ 6426 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6427 iflib_fast_intr_rxtx, NULL, info, name); 6428 if (err != 0) 6429 return (err); 6430 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q); 6431 res = irq->ii_res; 6432 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6433 6434 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6435 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6436 "tx"); 6437 return (0); 6438 } 6439 6440 void 6441 iflib_led_create(if_ctx_t ctx) 6442 { 6443 6444 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6445 device_get_nameunit(ctx->ifc_dev)); 6446 } 6447 6448 void 6449 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6450 { 6451 6452 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6453 } 6454 6455 void 6456 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6457 { 6458 6459 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6460 } 6461 6462 void 6463 iflib_admin_intr_deferred(if_ctx_t ctx) 6464 { 6465 6466 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL); 6467 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6468 } 6469 6470 void 6471 iflib_iov_intr_deferred(if_ctx_t ctx) 6472 { 6473 6474 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6475 } 6476 6477 void 6478 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6479 { 6480 6481 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6482 name); 6483 } 6484 6485 void 6486 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6487 const char *name) 6488 { 6489 6490 GROUPTASK_INIT(gtask, 0, fn, ctx); 6491 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6492 name); 6493 } 6494 6495 void 6496 iflib_config_gtask_deinit(struct grouptask *gtask) 6497 { 6498 6499 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6500 } 6501 6502 void 6503 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6504 { 6505 if_t ifp = ctx->ifc_ifp; 6506 iflib_txq_t txq = ctx->ifc_txqs; 6507 6508 if_setbaudrate(ifp, baudrate); 6509 if (baudrate >= IF_Gbps(10)) { 6510 STATE_LOCK(ctx); 6511 ctx->ifc_flags |= IFC_PREFETCH; 6512 STATE_UNLOCK(ctx); 6513 } 6514 /* If link down, disable watchdog */ 6515 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6516 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6517 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6518 } 6519 ctx->ifc_link_state = link_state; 6520 if_link_state_change(ifp, link_state); 6521 } 6522 6523 static int 6524 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6525 { 6526 int credits; 6527 #ifdef INVARIANTS 6528 int credits_pre = txq->ift_cidx_processed; 6529 #endif 6530 6531 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6532 BUS_DMASYNC_POSTREAD); 6533 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6534 return (0); 6535 6536 txq->ift_processed += credits; 6537 txq->ift_cidx_processed += credits; 6538 6539 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6540 if (txq->ift_cidx_processed >= txq->ift_size) 6541 txq->ift_cidx_processed -= txq->ift_size; 6542 return (credits); 6543 } 6544 6545 static int 6546 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6547 { 6548 iflib_fl_t fl; 6549 u_int i; 6550 6551 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6552 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6553 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6554 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6555 budget)); 6556 } 6557 6558 void 6559 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6560 const char *description, if_int_delay_info_t info, 6561 int offset, int value) 6562 { 6563 info->iidi_ctx = ctx; 6564 info->iidi_offset = offset; 6565 info->iidi_value = value; 6566 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6567 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6568 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6569 info, 0, iflib_sysctl_int_delay, "I", description); 6570 } 6571 6572 struct sx * 6573 iflib_ctx_lock_get(if_ctx_t ctx) 6574 { 6575 6576 return (&ctx->ifc_ctx_sx); 6577 } 6578 6579 static int 6580 iflib_msix_init(if_ctx_t ctx) 6581 { 6582 device_t dev = ctx->ifc_dev; 6583 if_shared_ctx_t sctx = ctx->ifc_sctx; 6584 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6585 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6586 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6587 6588 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6589 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6590 6591 if (bootverbose) 6592 device_printf(dev, "msix_init qsets capped at %d\n", 6593 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6594 6595 /* Override by tuneable */ 6596 if (scctx->isc_disable_msix) 6597 goto msi; 6598 6599 /* First try MSI-X */ 6600 if ((msgs = pci_msix_count(dev)) == 0) { 6601 if (bootverbose) 6602 device_printf(dev, "MSI-X not supported or disabled\n"); 6603 goto msi; 6604 } 6605 6606 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6607 /* 6608 * bar == -1 => "trust me I know what I'm doing" 6609 * Some drivers are for hardware that is so shoddily 6610 * documented that no one knows which bars are which 6611 * so the developer has to map all bars. This hack 6612 * allows shoddy garbage to use MSI-X in this framework. 6613 */ 6614 if (bar != -1) { 6615 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6616 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6617 if (ctx->ifc_msix_mem == NULL) { 6618 device_printf(dev, "Unable to map MSI-X table\n"); 6619 goto msi; 6620 } 6621 } 6622 6623 admincnt = sctx->isc_admin_intrcnt; 6624 #if IFLIB_DEBUG 6625 /* use only 1 qset in debug mode */ 6626 queuemsgs = min(msgs - admincnt, 1); 6627 #else 6628 queuemsgs = msgs - admincnt; 6629 #endif 6630 #ifdef RSS 6631 queues = imin(queuemsgs, rss_getnumbuckets()); 6632 #else 6633 queues = queuemsgs; 6634 #endif 6635 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6636 if (bootverbose) 6637 device_printf(dev, 6638 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6639 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6640 #ifdef RSS 6641 /* If we're doing RSS, clamp at the number of RSS buckets */ 6642 if (queues > rss_getnumbuckets()) 6643 queues = rss_getnumbuckets(); 6644 #endif 6645 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6646 rx_queues = iflib_num_rx_queues; 6647 else 6648 rx_queues = queues; 6649 6650 if (rx_queues > scctx->isc_nrxqsets) 6651 rx_queues = scctx->isc_nrxqsets; 6652 6653 /* 6654 * We want this to be all logical CPUs by default 6655 */ 6656 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6657 tx_queues = iflib_num_tx_queues; 6658 else 6659 tx_queues = mp_ncpus; 6660 6661 if (tx_queues > scctx->isc_ntxqsets) 6662 tx_queues = scctx->isc_ntxqsets; 6663 6664 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6665 #ifdef INVARIANTS 6666 if (tx_queues != rx_queues) 6667 device_printf(dev, 6668 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6669 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6670 #endif 6671 tx_queues = min(rx_queues, tx_queues); 6672 rx_queues = min(rx_queues, tx_queues); 6673 } 6674 6675 vectors = rx_queues + admincnt; 6676 if (msgs < vectors) { 6677 device_printf(dev, 6678 "insufficient number of MSI-X vectors " 6679 "(supported %d, need %d)\n", msgs, vectors); 6680 goto msi; 6681 } 6682 6683 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6684 tx_queues); 6685 msgs = vectors; 6686 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6687 if (vectors != msgs) { 6688 device_printf(dev, 6689 "Unable to allocate sufficient MSI-X vectors " 6690 "(got %d, need %d)\n", vectors, msgs); 6691 pci_release_msi(dev); 6692 if (bar != -1) { 6693 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6694 ctx->ifc_msix_mem); 6695 ctx->ifc_msix_mem = NULL; 6696 } 6697 goto msi; 6698 } 6699 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6700 vectors); 6701 scctx->isc_vectors = vectors; 6702 scctx->isc_nrxqsets = rx_queues; 6703 scctx->isc_ntxqsets = tx_queues; 6704 scctx->isc_intr = IFLIB_INTR_MSIX; 6705 6706 return (vectors); 6707 } else { 6708 device_printf(dev, 6709 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6710 err); 6711 if (bar != -1) { 6712 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6713 ctx->ifc_msix_mem); 6714 ctx->ifc_msix_mem = NULL; 6715 } 6716 } 6717 6718 msi: 6719 vectors = pci_msi_count(dev); 6720 scctx->isc_nrxqsets = 1; 6721 scctx->isc_ntxqsets = 1; 6722 scctx->isc_vectors = vectors; 6723 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6724 device_printf(dev,"Using an MSI interrupt\n"); 6725 scctx->isc_intr = IFLIB_INTR_MSI; 6726 } else { 6727 scctx->isc_vectors = 1; 6728 device_printf(dev,"Using a Legacy interrupt\n"); 6729 scctx->isc_intr = IFLIB_INTR_LEGACY; 6730 } 6731 6732 return (vectors); 6733 } 6734 6735 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6736 6737 static int 6738 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6739 { 6740 int rc; 6741 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6742 struct sbuf *sb; 6743 const char *ring_state = "UNKNOWN"; 6744 6745 /* XXX needed ? */ 6746 rc = sysctl_wire_old_buffer(req, 0); 6747 MPASS(rc == 0); 6748 if (rc != 0) 6749 return (rc); 6750 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6751 MPASS(sb != NULL); 6752 if (sb == NULL) 6753 return (ENOMEM); 6754 if (state[3] <= 3) 6755 ring_state = ring_states[state[3]]; 6756 6757 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6758 state[0], state[1], state[2], ring_state); 6759 rc = sbuf_finish(sb); 6760 sbuf_delete(sb); 6761 return(rc); 6762 } 6763 6764 enum iflib_ndesc_handler { 6765 IFLIB_NTXD_HANDLER, 6766 IFLIB_NRXD_HANDLER, 6767 }; 6768 6769 static int 6770 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6771 { 6772 if_ctx_t ctx = (void *)arg1; 6773 enum iflib_ndesc_handler type = arg2; 6774 char buf[256] = {0}; 6775 qidx_t *ndesc; 6776 char *p, *next; 6777 int nqs, rc, i; 6778 6779 nqs = 8; 6780 switch(type) { 6781 case IFLIB_NTXD_HANDLER: 6782 ndesc = ctx->ifc_sysctl_ntxds; 6783 if (ctx->ifc_sctx) 6784 nqs = ctx->ifc_sctx->isc_ntxqs; 6785 break; 6786 case IFLIB_NRXD_HANDLER: 6787 ndesc = ctx->ifc_sysctl_nrxds; 6788 if (ctx->ifc_sctx) 6789 nqs = ctx->ifc_sctx->isc_nrxqs; 6790 break; 6791 default: 6792 printf("%s: unhandled type\n", __func__); 6793 return (EINVAL); 6794 } 6795 if (nqs == 0) 6796 nqs = 8; 6797 6798 for (i=0; i<8; i++) { 6799 if (i >= nqs) 6800 break; 6801 if (i) 6802 strcat(buf, ","); 6803 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6804 } 6805 6806 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6807 if (rc || req->newptr == NULL) 6808 return rc; 6809 6810 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6811 i++, p = strsep(&next, " ,")) { 6812 ndesc[i] = strtoul(p, NULL, 10); 6813 } 6814 6815 return(rc); 6816 } 6817 6818 #define NAME_BUFLEN 32 6819 static void 6820 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6821 { 6822 device_t dev = iflib_get_dev(ctx); 6823 struct sysctl_oid_list *child, *oid_list; 6824 struct sysctl_ctx_list *ctx_list; 6825 struct sysctl_oid *node; 6826 6827 ctx_list = device_get_sysctl_ctx(dev); 6828 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6829 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6830 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields"); 6831 oid_list = SYSCTL_CHILDREN(node); 6832 6833 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6834 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6835 "driver version"); 6836 6837 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6838 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6839 "# of txqs to use, 0 => use default #"); 6840 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6841 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6842 "# of rxqs to use, 0 => use default #"); 6843 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6844 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6845 "permit #txq != #rxq"); 6846 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6847 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6848 "disable MSI-X (default 0)"); 6849 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6850 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6851 "set the RX budget"); 6852 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6853 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6854 "cause TX to abdicate instead of running to completion"); 6855 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6856 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6857 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6858 "offset to start using cores at"); 6859 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6860 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6861 "use separate cores for TX and RX"); 6862 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "use_logical_cores", 6863 CTLFLAG_RDTUN, &ctx->ifc_sysctl_use_logical_cores, 0, 6864 "try to make use of logical cores for TX and RX"); 6865 6866 /* XXX change for per-queue sizes */ 6867 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6868 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6869 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 6870 "list of # of TX descriptors to use, 0 = use default #"); 6871 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6872 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6873 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 6874 "list of # of RX descriptors to use, 0 = use default #"); 6875 } 6876 6877 static void 6878 iflib_add_device_sysctl_post(if_ctx_t ctx) 6879 { 6880 if_shared_ctx_t sctx = ctx->ifc_sctx; 6881 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6882 device_t dev = iflib_get_dev(ctx); 6883 struct sysctl_oid_list *child; 6884 struct sysctl_ctx_list *ctx_list; 6885 iflib_fl_t fl; 6886 iflib_txq_t txq; 6887 iflib_rxq_t rxq; 6888 int i, j; 6889 char namebuf[NAME_BUFLEN]; 6890 char *qfmt; 6891 struct sysctl_oid *queue_node, *fl_node, *node; 6892 struct sysctl_oid_list *queue_list, *fl_list; 6893 ctx_list = device_get_sysctl_ctx(dev); 6894 6895 node = ctx->ifc_sysctl_node; 6896 child = SYSCTL_CHILDREN(node); 6897 6898 if (scctx->isc_ntxqsets > 100) 6899 qfmt = "txq%03d"; 6900 else if (scctx->isc_ntxqsets > 10) 6901 qfmt = "txq%02d"; 6902 else 6903 qfmt = "txq%d"; 6904 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6905 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6906 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6907 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6908 queue_list = SYSCTL_CHILDREN(queue_node); 6909 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 6910 CTLFLAG_RD, 6911 &txq->ift_task.gt_cpu, 0, "cpu this queue is bound to"); 6912 #if MEMORY_LOGGING 6913 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6914 CTLFLAG_RD, 6915 &txq->ift_dequeued, "total mbufs freed"); 6916 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6917 CTLFLAG_RD, 6918 &txq->ift_enqueued, "total mbufs enqueued"); 6919 #endif 6920 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6921 CTLFLAG_RD, 6922 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6923 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6924 CTLFLAG_RD, 6925 &txq->ift_pullups, "# of times m_pullup was called"); 6926 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6927 CTLFLAG_RD, 6928 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6929 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6930 CTLFLAG_RD, 6931 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6932 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6933 CTLFLAG_RD, 6934 &txq->ift_map_failed, "# of times DMA map failed"); 6935 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6936 CTLFLAG_RD, 6937 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6938 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6939 CTLFLAG_RD, 6940 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6941 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6942 CTLFLAG_RD, 6943 &txq->ift_pidx, 1, "Producer Index"); 6944 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6945 CTLFLAG_RD, 6946 &txq->ift_cidx, 1, "Consumer Index"); 6947 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6948 CTLFLAG_RD, 6949 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6950 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6951 CTLFLAG_RD, 6952 &txq->ift_in_use, 1, "descriptors in use"); 6953 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6954 CTLFLAG_RD, 6955 &txq->ift_processed, "descriptors procesed for clean"); 6956 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6957 CTLFLAG_RD, 6958 &txq->ift_cleaned, "total cleaned"); 6959 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6960 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 6961 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 6962 mp_ring_state_handler, "A", "soft ring state"); 6963 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6964 CTLFLAG_RD, &txq->ift_br->enqueues, 6965 "# of enqueues to the mp_ring for this queue"); 6966 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6967 CTLFLAG_RD, &txq->ift_br->drops, 6968 "# of drops in the mp_ring for this queue"); 6969 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6970 CTLFLAG_RD, &txq->ift_br->starts, 6971 "# of normal consumer starts in the mp_ring for this queue"); 6972 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6973 CTLFLAG_RD, &txq->ift_br->stalls, 6974 "# of consumer stalls in the mp_ring for this queue"); 6975 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6976 CTLFLAG_RD, &txq->ift_br->restarts, 6977 "# of consumer restarts in the mp_ring for this queue"); 6978 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6979 CTLFLAG_RD, &txq->ift_br->abdications, 6980 "# of consumer abdications in the mp_ring for this queue"); 6981 } 6982 6983 if (scctx->isc_nrxqsets > 100) 6984 qfmt = "rxq%03d"; 6985 else if (scctx->isc_nrxqsets > 10) 6986 qfmt = "rxq%02d"; 6987 else 6988 qfmt = "rxq%d"; 6989 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6990 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6991 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6992 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6993 queue_list = SYSCTL_CHILDREN(queue_node); 6994 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 6995 CTLFLAG_RD, 6996 &rxq->ifr_task.gt_cpu, 0, "cpu this queue is bound to"); 6997 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6998 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6999 CTLFLAG_RD, 7000 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 7001 } 7002 7003 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 7004 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 7005 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 7006 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name"); 7007 fl_list = SYSCTL_CHILDREN(fl_node); 7008 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 7009 CTLFLAG_RD, 7010 &fl->ifl_pidx, 1, "Producer Index"); 7011 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 7012 CTLFLAG_RD, 7013 &fl->ifl_cidx, 1, "Consumer Index"); 7014 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 7015 CTLFLAG_RD, 7016 &fl->ifl_credits, 1, "credits available"); 7017 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 7018 CTLFLAG_RD, 7019 &fl->ifl_buf_size, 1, "buffer size"); 7020 #if MEMORY_LOGGING 7021 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 7022 CTLFLAG_RD, 7023 &fl->ifl_m_enqueued, "mbufs allocated"); 7024 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 7025 CTLFLAG_RD, 7026 &fl->ifl_m_dequeued, "mbufs freed"); 7027 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 7028 CTLFLAG_RD, 7029 &fl->ifl_cl_enqueued, "clusters allocated"); 7030 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 7031 CTLFLAG_RD, 7032 &fl->ifl_cl_dequeued, "clusters freed"); 7033 #endif 7034 } 7035 } 7036 7037 } 7038 7039 void 7040 iflib_request_reset(if_ctx_t ctx) 7041 { 7042 7043 STATE_LOCK(ctx); 7044 ctx->ifc_flags |= IFC_DO_RESET; 7045 STATE_UNLOCK(ctx); 7046 } 7047 7048 #ifndef __NO_STRICT_ALIGNMENT 7049 static struct mbuf * 7050 iflib_fixup_rx(struct mbuf *m) 7051 { 7052 struct mbuf *n; 7053 7054 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 7055 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 7056 m->m_data += ETHER_HDR_LEN; 7057 n = m; 7058 } else { 7059 MGETHDR(n, M_NOWAIT, MT_DATA); 7060 if (n == NULL) { 7061 m_freem(m); 7062 return (NULL); 7063 } 7064 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 7065 m->m_data += ETHER_HDR_LEN; 7066 m->m_len -= ETHER_HDR_LEN; 7067 n->m_len = ETHER_HDR_LEN; 7068 M_MOVE_PKTHDR(n, m); 7069 n->m_next = m; 7070 } 7071 return (n); 7072 } 7073 #endif 7074 7075 #ifdef DEBUGNET 7076 static void 7077 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 7078 { 7079 if_ctx_t ctx; 7080 7081 ctx = if_getsoftc(ifp); 7082 CTX_LOCK(ctx); 7083 *nrxr = NRXQSETS(ctx); 7084 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 7085 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 7086 CTX_UNLOCK(ctx); 7087 } 7088 7089 static void 7090 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 7091 { 7092 if_ctx_t ctx; 7093 if_softc_ctx_t scctx; 7094 iflib_fl_t fl; 7095 iflib_rxq_t rxq; 7096 int i, j; 7097 7098 ctx = if_getsoftc(ifp); 7099 scctx = &ctx->ifc_softc_ctx; 7100 7101 switch (event) { 7102 case DEBUGNET_START: 7103 for (i = 0; i < scctx->isc_nrxqsets; i++) { 7104 rxq = &ctx->ifc_rxqs[i]; 7105 for (j = 0; j < rxq->ifr_nfl; j++) { 7106 fl = rxq->ifr_fl; 7107 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 7108 } 7109 } 7110 iflib_no_tx_batch = 1; 7111 break; 7112 default: 7113 break; 7114 } 7115 } 7116 7117 static int 7118 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 7119 { 7120 if_ctx_t ctx; 7121 iflib_txq_t txq; 7122 int error; 7123 7124 ctx = if_getsoftc(ifp); 7125 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7126 IFF_DRV_RUNNING) 7127 return (EBUSY); 7128 7129 txq = &ctx->ifc_txqs[0]; 7130 error = iflib_encap(txq, &m); 7131 if (error == 0) 7132 (void)iflib_txd_db_check(txq, true); 7133 return (error); 7134 } 7135 7136 static int 7137 iflib_debugnet_poll(if_t ifp, int count) 7138 { 7139 struct epoch_tracker et; 7140 if_ctx_t ctx; 7141 if_softc_ctx_t scctx; 7142 iflib_txq_t txq; 7143 int i; 7144 7145 ctx = if_getsoftc(ifp); 7146 scctx = &ctx->ifc_softc_ctx; 7147 7148 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7149 IFF_DRV_RUNNING) 7150 return (EBUSY); 7151 7152 txq = &ctx->ifc_txqs[0]; 7153 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 7154 7155 NET_EPOCH_ENTER(et); 7156 for (i = 0; i < scctx->isc_nrxqsets; i++) 7157 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 7158 NET_EPOCH_EXIT(et); 7159 return (0); 7160 } 7161 #endif /* DEBUGNET */ 7162